URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/rtl
- from Rev 106 to Rev 111
- ↔ Reverse comparison
Rev 106 → Rev 111
/verilog/omsp_frontend.v
80,7 → 80,7
nmi_evt, // Non-maskable interrupt event |
pc_sw, // Program counter software value |
pc_sw_wr, // Program counter software write |
puc, // Main system reset |
puc_rst, // Main system reset |
wdt_irq // Watchdog-timer interrupt |
); |
|
124,12 → 124,12
input nmi_evt; // Non-maskable interrupt event |
input [15:0] pc_sw; // Program counter software value |
input pc_sw_wr; // Program counter software write |
input puc; // Main system reset |
input puc_rst; // Main system reset |
input wdt_irq; // Watchdog-timer interrupt |
|
|
//============================================================================= |
// 0) UTILITY FUNCTIONS |
// 1) UTILITY FUNCTIONS |
//============================================================================= |
|
// 16 bits one-hot decoder |
152,9 → 152,44
|
|
//============================================================================= |
// 1) FRONTEND STATE MACHINE |
// 2) Parameter definitions |
//============================================================================= |
|
// |
// 2.1) Instruction State machine definitons |
//------------------------------------------- |
|
parameter I_IRQ_FETCH = `I_IRQ_FETCH; |
parameter I_IRQ_DONE = `I_IRQ_DONE; |
parameter I_DEC = `I_DEC; // New instruction ready for decode |
parameter I_EXT1 = `I_EXT1; // 1st Extension word |
parameter I_EXT2 = `I_EXT2; // 2nd Extension word |
parameter I_IDLE = `I_IDLE; // CPU is in IDLE mode |
|
// |
// 2.2) Execution State machine definitons |
//------------------------------------------- |
|
parameter E_IRQ_0 = `E_IRQ_0; |
parameter E_IRQ_1 = `E_IRQ_1; |
parameter E_IRQ_2 = `E_IRQ_2; |
parameter E_IRQ_3 = `E_IRQ_3; |
parameter E_IRQ_4 = `E_IRQ_4; |
parameter E_SRC_AD = `E_SRC_AD; |
parameter E_SRC_RD = `E_SRC_RD; |
parameter E_SRC_WR = `E_SRC_WR; |
parameter E_DST_AD = `E_DST_AD; |
parameter E_DST_RD = `E_DST_RD; |
parameter E_DST_WR = `E_DST_WR; |
parameter E_EXEC = `E_EXEC; |
parameter E_JUMP = `E_JUMP; |
parameter E_IDLE = `E_IDLE; |
|
|
//============================================================================= |
// 3) FRONTEND STATE MACHINE |
//============================================================================= |
|
// The wire "conv" is used as state bits to calculate the next response |
reg [2:0] i_state; |
reg [2:0] i_state_nxt; |
167,20 → 202,12
reg [15:0] sconst_nxt; |
reg [3:0] e_state_nxt; |
|
// State machine definitons |
parameter I_IRQ_FETCH = 3'h0; |
parameter I_IRQ_DONE = 3'h1; |
parameter I_DEC = 3'h2; // New instruction ready for decode |
parameter I_EXT1 = 3'h3; // 1st Extension word |
parameter I_EXT2 = 3'h4; // 2nd Extension word |
parameter I_IDLE = 3'h5; // CPU is in IDLE mode |
|
// CPU on/off through the debug interface or cpu_en port |
wire cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s; |
|
// States Transitions |
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or |
exec_done or irq_detect or cpuoff or cpu_halt_cmd or e_state) |
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or |
irq_detect or cpuoff or cpu_halt_cmd or e_state) |
case(i_state) |
I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH : |
(~cpuoff & ~cpu_halt_cmd) ? I_DEC : I_IDLE; |
188,9 → 215,9
I_IRQ_DONE : i_state_nxt = I_DEC; |
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH : |
(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE : |
cpu_halt_cmd & (e_state==`E_IDLE) ? I_IDLE : |
cpu_halt_cmd & (e_state==E_IDLE) ? I_IDLE : |
pc_sw_wr ? I_DEC : |
~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state |
~exec_done & ~(e_state==E_IDLE) ? I_DEC : // Wait in decode state |
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed |
I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH : |
pc_sw_wr ? I_DEC : |
200,30 → 227,30
endcase |
|
// State machine |
always @(posedge mclk or posedge puc) |
if (puc) i_state <= I_IRQ_FETCH; |
else i_state <= i_state_nxt; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) i_state <= I_IRQ_FETCH; |
else i_state <= i_state_nxt; |
|
// Utility signals |
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))); |
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==E_IDLE))); |
wire decode = decode_noirq | irq_detect; |
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE); |
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==E_IDLE))) & ~(e_state_nxt==E_IDLE); |
|
// Debug interface cpu status |
reg dbg_halt_st; |
always @(posedge mclk or posedge puc) |
if (puc) dbg_halt_st <= 1'b0; |
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE); |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) dbg_halt_st <= 1'b0; |
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE); |
|
|
//============================================================================= |
// 2) INTERRUPT HANDLING |
// 4) INTERRUPT HANDLING |
//============================================================================= |
|
// Detect nmi interrupt |
reg inst_nmi; |
always @(posedge mclk or posedge puc) |
if (puc) inst_nmi <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_nmi <= 1'b0; |
else if (nmi_evt) inst_nmi <= 1'b1; |
else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0; |
|
230,8 → 257,8
|
// Detect reset interrupt |
reg inst_irq_rst; |
always @(posedge mclk or posedge puc) |
if (puc) inst_irq_rst <= 1'b1; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_irq_rst <= 1'b1; |
else if (exec_done) inst_irq_rst <= 1'b0; |
|
// Detect other interrupts |
239,8 → 266,8
|
// Select interrupt vector |
reg [3:0] irq_num; |
always @(posedge mclk or posedge puc) |
if (puc) irq_num <= 4'hf; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) irq_num <= 4'hf; |
else if (irq_detect) irq_num <= inst_nmi ? 4'he : |
irq[13] ? 4'hd : |
irq[12] ? 4'hc : |
266,11 → 293,11
|
|
//============================================================================= |
// 3) FETCH INSTRUCTION |
// 5) FETCH INSTRUCTION |
//============================================================================= |
|
// |
// 3.1) PROGRAM COUNTER & MEMORY INTERFACE |
// 5.1) PROGRAM COUNTER & MEMORY INTERFACE |
//----------------------------------------- |
|
// Program counter |
282,15 → 309,15
(i_state==I_IRQ_FETCH) ? irq_addr : |
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr; |
|
always @(posedge mclk or posedge puc) |
if (puc) pc <= 16'h0000; |
else pc <= pc_nxt; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) pc <= 16'h0000; |
else pc <= pc_nxt; |
|
// Check if ROM has been busy in order to retry ROM access |
reg pmem_busy; |
always @(posedge mclk or posedge puc) |
if (puc) pmem_busy <= 1'b0; |
else pmem_busy <= fe_pmem_wait; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) pmem_busy <= 1'b0; |
else pmem_busy <= fe_pmem_wait; |
|
// Memory interface |
wire [15:0] mab = pc_nxt; |
298,7 → 325,7
|
|
// |
// 3.2) INSTRUCTION REGISTER |
// 5.2) INSTRUCTION REGISTER |
//-------------------------------- |
|
// Instruction register |
321,8 → 348,8
|
// Store source extension word |
reg [15:0] inst_sext; |
always @(posedge mclk or posedge puc) |
if (puc) inst_sext <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_sext <= 16'h0000; |
else if (decode & is_const) inst_sext <= sconst_nxt; |
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0}; |
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt; |
333,8 → 360,8
|
// Store destination extension word |
reg [15:0] inst_dext; |
always @(posedge mclk or posedge puc) |
if (puc) inst_dext <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_dext <= 16'h0000; |
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt; |
else if (i_state==I_EXT2) inst_dext <= ext_nxt; |
|
343,11 → 370,11
|
|
//============================================================================= |
// 4) DECODE INSTRUCTION |
// 6) DECODE INSTRUCTION |
//============================================================================= |
|
// |
// 4.1) OPCODE: INSTRUCTION TYPE |
// 6.1) OPCODE: INSTRUCTION TYPE |
//---------------------------------------- |
// Instructions type is encoded in a one hot fashion as following: |
// |
360,12 → 387,12
(ir[15:13]==3'b001), |
(ir[15:13]==3'b000)} & {3{~irq_detect}}; |
|
always @(posedge mclk or posedge puc) |
if (puc) inst_type <= 3'b000; |
else if (decode) inst_type <= inst_type_nxt; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_type <= 3'b000; |
else if (decode) inst_type <= inst_type_nxt; |
|
// |
// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC |
// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC |
//---------------------------------------- |
// Instructions are encoded in a one hot fashion as following: |
// |
381,12 → 408,12
reg [7:0] inst_so; |
wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}}); |
|
always @(posedge mclk or posedge puc) |
if (puc) inst_so <= 8'h00; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_so <= 8'h00; |
else if (decode) inst_so <= inst_so_nxt; |
|
// |
// 4.3) OPCODE: CONDITIONAL JUMP |
// 6.3) OPCODE: CONDITIONAL JUMP |
//-------------------------------- |
// Instructions are encoded in a one hot fashion as following: |
// |
400,8 → 427,8
// 8'b10000000: JMP |
|
reg [2:0] inst_jmp_bin; |
always @(posedge mclk or posedge puc) |
if (puc) inst_jmp_bin <= 3'h0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_jmp_bin <= 3'h0; |
else if (decode) inst_jmp_bin <= ir[12:10]; |
|
wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}}; |
408,7 → 435,7
|
|
// |
// 4.4) OPCODE: TWO-OPERAND ARITHMETIC |
// 6.4) OPCODE: TWO-OPERAND ARITHMETIC |
//------------------------------------- |
// Instructions are encoded in a one hot fashion as following: |
// |
429,19 → 456,19
wire [11:0] inst_to_nxt = inst_to_1hot[15:4]; |
|
reg inst_mov; |
always @(posedge mclk or posedge puc) |
if (puc) inst_mov <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_mov <= 1'b0; |
else if (decode) inst_mov <= inst_to_nxt[`MOV]; |
|
|
// |
// 4.5) SOURCE AND DESTINATION REGISTERS |
// 6.5) SOURCE AND DESTINATION REGISTERS |
//--------------------------------------- |
|
// Destination register |
reg [3:0] inst_dest_bin; |
always @(posedge mclk or posedge puc) |
if (puc) inst_dest_bin <= 4'h0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_dest_bin <= 4'h0; |
else if (decode) inst_dest_bin <= ir[3:0]; |
|
wire [15:0] inst_dest = dbg_halt_st ? one_hot16(dbg_reg_sel) : |
454,8 → 481,8
|
// Source register |
reg [3:0] inst_src_bin; |
always @(posedge mclk or posedge puc) |
if (puc) inst_src_bin <= 4'h0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_src_bin <= 4'h0; |
else if (decode) inst_src_bin <= ir[11:8]; |
|
wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) : |
465,7 → 492,7
|
|
// |
// 4.6) SOURCE ADDRESSING MODES |
// 6.6) SOURCE ADDRESSING MODES |
//-------------------------------- |
// Source addressing modes are encoded in a one hot fashion as following: |
// |
523,8 → 550,8
assign is_const = |inst_as_nxt[12:7]; |
|
reg [7:0] inst_as; |
always @(posedge mclk or posedge puc) |
if (puc) inst_as <= 8'h00; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_as <= 8'h00; |
else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]}; |
|
|
547,7 → 574,7
|
|
// |
// 4.7) DESTINATION ADDRESSING MODES |
// 6.7) DESTINATION ADDRESSING MODES |
//----------------------------------- |
// Destination addressing modes are encoded in a one hot fashion as following: |
// |
582,31 → 609,31
end |
|
reg [7:0] inst_ad; |
always @(posedge mclk or posedge puc) |
if (puc) inst_ad <= 8'h00; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_ad <= 8'h00; |
else if (decode) inst_ad <= inst_ad_nxt; |
|
|
// |
// 4.8) REMAINING INSTRUCTION DECODING |
// 6.8) REMAINING INSTRUCTION DECODING |
//------------------------------------- |
|
// Operation size |
reg inst_bw; |
always @(posedge mclk or posedge puc) |
if (puc) inst_bw <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_bw <= 1'b0; |
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd; |
|
// Extended instruction size |
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} + |
{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])}; |
always @(posedge mclk or posedge puc) |
if (puc) inst_sz <= 2'b00; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_sz <= 2'b00; |
else if (decode) inst_sz <= inst_sz_nxt; |
|
|
//============================================================================= |
// 5) EXECUTION-UNIT STATE MACHINE |
// 7) EXECUTION-UNIT STATE MACHINE |
//============================================================================= |
|
// State machine registers |
626,37 → 653,37
wire inst_branch = (inst_ad_nxt[`DIR] & (ir[3:0]==4'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI]; |
|
reg exec_jmp; |
always @(posedge mclk or posedge puc) |
if (puc) exec_jmp <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) exec_jmp <= 1'b0; |
else if (inst_branch & decode) exec_jmp <= 1'b1; |
else if (e_state==`E_JUMP) exec_jmp <= 1'b0; |
else if (e_state==E_JUMP) exec_jmp <= 1'b0; |
|
reg exec_dst_wr; |
always @(posedge mclk or posedge puc) |
if (puc) exec_dst_wr <= 1'b0; |
else if (e_state==`E_DST_RD) exec_dst_wr <= 1'b1; |
else if (e_state==`E_DST_WR) exec_dst_wr <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) exec_dst_wr <= 1'b0; |
else if (e_state==E_DST_RD) exec_dst_wr <= 1'b1; |
else if (e_state==E_DST_WR) exec_dst_wr <= 1'b0; |
|
reg exec_src_wr; |
always @(posedge mclk or posedge puc) |
if (puc) exec_src_wr <= 1'b0; |
else if (inst_type[`INST_SO] & (e_state==`E_SRC_RD)) exec_src_wr <= 1'b1; |
else if ((e_state==`E_SRC_WR) || (e_state==`E_DST_WR)) exec_src_wr <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) exec_src_wr <= 1'b0; |
else if (inst_type[`INST_SO] & (e_state==E_SRC_RD)) exec_src_wr <= 1'b1; |
else if ((e_state==E_SRC_WR) || (e_state==E_DST_WR)) exec_src_wr <= 1'b0; |
|
reg exec_dext_rdy; |
always @(posedge mclk or posedge puc) |
if (puc) exec_dext_rdy <= 1'b0; |
else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0; |
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) exec_dext_rdy <= 1'b0; |
else if (e_state==E_DST_RD) exec_dext_rdy <= 1'b0; |
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1; |
|
// Execution first state |
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 : |
cpu_halt_cmd | (i_state==I_IDLE) ? `E_IDLE : |
cpuoff ? `E_IDLE : |
src_acalc_pre ? `E_SRC_AD : |
src_rd_pre ? `E_SRC_RD : |
dst_acalc_pre ? `E_DST_AD : |
dst_rd_pre ? `E_DST_RD : `E_EXEC; |
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? E_IRQ_0 : |
cpu_halt_cmd | (i_state==I_IDLE) ? E_IDLE : |
cpuoff ? E_IDLE : |
src_acalc_pre ? E_SRC_AD : |
src_rd_pre ? E_SRC_RD : |
dst_acalc_pre ? E_DST_AD : |
dst_rd_pre ? E_DST_RD : E_EXEC; |
|
|
// State machine |
667,36 → 694,36
inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr or |
e_first_state or exec_src_wr) |
case(e_state) |
`E_IDLE : e_state_nxt = e_first_state; |
`E_IRQ_0 : e_state_nxt = `E_IRQ_1; |
`E_IRQ_1 : e_state_nxt = `E_IRQ_2; |
`E_IRQ_2 : e_state_nxt = `E_IRQ_3; |
`E_IRQ_3 : e_state_nxt = `E_IRQ_4; |
`E_IRQ_4 : e_state_nxt = `E_EXEC; |
E_IDLE : e_state_nxt = e_first_state; |
E_IRQ_0 : e_state_nxt = E_IRQ_1; |
E_IRQ_1 : e_state_nxt = E_IRQ_2; |
E_IRQ_2 : e_state_nxt = E_IRQ_3; |
E_IRQ_3 : e_state_nxt = E_IRQ_4; |
E_IRQ_4 : e_state_nxt = E_EXEC; |
|
`E_SRC_AD : e_state_nxt = inst_sext_rdy ? `E_SRC_RD : `E_SRC_AD; |
E_SRC_AD : e_state_nxt = inst_sext_rdy ? E_SRC_RD : E_SRC_AD; |
|
`E_SRC_RD : e_state_nxt = dst_acalc ? `E_DST_AD : |
dst_rd ? `E_DST_RD : `E_EXEC; |
E_SRC_RD : e_state_nxt = dst_acalc ? E_DST_AD : |
dst_rd ? E_DST_RD : E_EXEC; |
|
`E_DST_AD : e_state_nxt = (inst_dext_rdy | |
exec_dext_rdy) ? `E_DST_RD : `E_DST_AD; |
E_DST_AD : e_state_nxt = (inst_dext_rdy | |
exec_dext_rdy) ? E_DST_RD : E_DST_AD; |
|
`E_DST_RD : e_state_nxt = `E_EXEC; |
E_DST_RD : e_state_nxt = E_EXEC; |
|
`E_EXEC : e_state_nxt = exec_dst_wr ? `E_DST_WR : |
exec_jmp ? `E_JUMP : |
exec_src_wr ? `E_SRC_WR : e_first_state; |
E_EXEC : e_state_nxt = exec_dst_wr ? E_DST_WR : |
exec_jmp ? E_JUMP : |
exec_src_wr ? E_SRC_WR : e_first_state; |
|
`E_JUMP : e_state_nxt = e_first_state; |
`E_DST_WR : e_state_nxt = exec_jmp ? `E_JUMP : e_first_state; |
`E_SRC_WR : e_state_nxt = e_first_state; |
default : e_state_nxt = `E_IRQ_0; |
E_JUMP : e_state_nxt = e_first_state; |
E_DST_WR : e_state_nxt = exec_jmp ? E_JUMP : e_first_state; |
E_SRC_WR : e_state_nxt = e_first_state; |
default : e_state_nxt = E_IRQ_0; |
endcase |
|
// State machine |
always @(posedge mclk or posedge puc) |
if (puc) e_state <= `E_IRQ_1; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) e_state <= E_IRQ_1; |
else e_state <= e_state_nxt; |
|
|
703,17 → 730,17
// Frontend State machine control signals |
//---------------------------------------- |
|
wire exec_done = exec_jmp ? (e_state==`E_JUMP) : |
exec_dst_wr ? (e_state==`E_DST_WR) : |
exec_src_wr ? (e_state==`E_SRC_WR) : (e_state==`E_EXEC); |
wire exec_done = exec_jmp ? (e_state==E_JUMP) : |
exec_dst_wr ? (e_state==E_DST_WR) : |
exec_src_wr ? (e_state==E_SRC_WR) : (e_state==E_EXEC); |
|
|
//============================================================================= |
// 6) EXECUTION-UNIT STATE CONTROL |
// 8) EXECUTION-UNIT STATE CONTROL |
//============================================================================= |
|
// |
// 6.1) ALU CONTROL SIGNALS |
// 8.1) ALU CONTROL SIGNALS |
//------------------------------------- |
// |
// 12'b000000000001: Enable ALU source inverter |
769,8 → 796,8
|
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT]; |
|
always @(posedge mclk or posedge puc) |
if (puc) inst_alu <= 12'h000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_alu <= 12'h000; |
else if (decode) inst_alu <= {exec_no_wr, |
alu_shift, |
alu_stat_f, |
/verilog/omsp_alu.v
92,9 → 92,9
|
reg [4:0] Z; |
begin |
Z = {1'b0,X}+{1'b0,Y}+C; |
if (Z<10) bcd_add = Z; |
else bcd_add = Z+6; |
Z = {1'b0,X}+{1'b0,Y}+{4'b0,C}; |
if (Z<5'd10) bcd_add = Z; |
else bcd_add = Z+5'd6; |
end |
|
endfunction |
204,13 → 204,13
inst_so[`SWPB] | |
inst_so[`SXT]); |
|
wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) | |
({16{inst_alu[`ALU_OR]}} & alu_or) | |
({16{inst_alu[`ALU_XOR]}} & alu_xor) | |
({16{inst_alu[`ALU_SHIFT]}} & alu_shift) | |
({16{inst_so[`SWPB]}} & alu_swpb) | |
({16{inst_so[`SXT]}} & alu_sxt) | |
({16{alu_short_thro}} & op_src_in); |
wire [16:0] alu_short = ({17{inst_alu[`ALU_AND]}} & alu_and) | |
({17{inst_alu[`ALU_OR]}} & alu_or) | |
({17{inst_alu[`ALU_XOR]}} & alu_xor) | |
({17{inst_alu[`ALU_SHIFT]}} & alu_shift) | |
({17{inst_so[`SWPB]}} & alu_swpb) | |
({17{inst_so[`SXT]}} & alu_sxt) | |
({17{alu_short_thro}} & op_src_in); |
|
|
// ALU output mux |
/verilog/omsp_register_file.v
61,7 → 61,7
inst_src, // Register source selection |
mclk, // Main system clock |
pc, // Program counter |
puc, // Main system reset |
puc_rst, // Main system reset |
reg_dest_val, // Selected register destination value |
reg_dest_wr, // Write selected register destination |
reg_pc_call, // Trigger PC update for a CALL instruction |
93,7 → 93,7
input [15:0] inst_src; // Register source selection |
input mclk; // Main system clock |
input [15:0] pc; // Program counter |
input puc; // Main system reset |
input puc_rst; // Main system reset |
input [15:0] reg_dest_val; // Selected register destination value |
input reg_dest_wr; // Write selected register destination |
input reg_pc_call; // Trigger PC update for a CALL instruction |
139,8 → 139,8
wire r1_wr = inst_dest[1] & reg_dest_wr; |
wire r1_inc = inst_src_in[1] & reg_incr; |
|
always @(posedge mclk or posedge puc) |
if (puc) r1 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r1 <= 16'h0000; |
else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe; |
else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe; |
else if (r1_inc) r1 <= reg_incr_val & 16'hfffe; |
166,8 → 166,8
r2_wr ? reg_dest_val_in[8] : r2[8]; // V |
|
|
always @(posedge mclk or posedge puc) |
if (puc) r2 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r2 <= 16'h0000; |
else if (reg_sr_clr) r2 <= 16'h0000; |
else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c}; |
|
184,8 → 184,8
wire r3_wr = inst_dest[3] & reg_dest_wr; |
wire r3_inc = inst_src_in[3] & reg_incr; |
|
always @(posedge mclk or posedge puc) |
if (puc) r3 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r3 <= 16'h0000; |
else if (r3_wr) r3 <= reg_dest_val_in; |
else if (r3_inc) r3 <= reg_incr_val; |
|
198,8 → 198,8
reg [15:0] r4; |
wire r4_wr = inst_dest[4] & reg_dest_wr; |
wire r4_inc = inst_src_in[4] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r4 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r4 <= 16'h0000; |
else if (r4_wr) r4 <= reg_dest_val_in; |
else if (r4_inc) r4 <= reg_incr_val; |
|
207,8 → 207,8
reg [15:0] r5; |
wire r5_wr = inst_dest[5] & reg_dest_wr; |
wire r5_inc = inst_src_in[5] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r5 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r5 <= 16'h0000; |
else if (r5_wr) r5 <= reg_dest_val_in; |
else if (r5_inc) r5 <= reg_incr_val; |
|
216,8 → 216,8
reg [15:0] r6; |
wire r6_wr = inst_dest[6] & reg_dest_wr; |
wire r6_inc = inst_src_in[6] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r6 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r6 <= 16'h0000; |
else if (r6_wr) r6 <= reg_dest_val_in; |
else if (r6_inc) r6 <= reg_incr_val; |
|
225,8 → 225,8
reg [15:0] r7; |
wire r7_wr = inst_dest[7] & reg_dest_wr; |
wire r7_inc = inst_src_in[7] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r7 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r7 <= 16'h0000; |
else if (r7_wr) r7 <= reg_dest_val_in; |
else if (r7_inc) r7 <= reg_incr_val; |
|
234,8 → 234,8
reg [15:0] r8; |
wire r8_wr = inst_dest[8] & reg_dest_wr; |
wire r8_inc = inst_src_in[8] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r8 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r8 <= 16'h0000; |
else if (r8_wr) r8 <= reg_dest_val_in; |
else if (r8_inc) r8 <= reg_incr_val; |
|
243,8 → 243,8
reg [15:0] r9; |
wire r9_wr = inst_dest[9] & reg_dest_wr; |
wire r9_inc = inst_src_in[9] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r9 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r9 <= 16'h0000; |
else if (r9_wr) r9 <= reg_dest_val_in; |
else if (r9_inc) r9 <= reg_incr_val; |
|
252,8 → 252,8
reg [15:0] r10; |
wire r10_wr = inst_dest[10] & reg_dest_wr; |
wire r10_inc = inst_src_in[10] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r10 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r10 <= 16'h0000; |
else if (r10_wr) r10 <= reg_dest_val_in; |
else if (r10_inc) r10 <= reg_incr_val; |
|
261,8 → 261,8
reg [15:0] r11; |
wire r11_wr = inst_dest[11] & reg_dest_wr; |
wire r11_inc = inst_src_in[11] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r11 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r11 <= 16'h0000; |
else if (r11_wr) r11 <= reg_dest_val_in; |
else if (r11_inc) r11 <= reg_incr_val; |
|
270,8 → 270,8
reg [15:0] r12; |
wire r12_wr = inst_dest[12] & reg_dest_wr; |
wire r12_inc = inst_src_in[12] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r12 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r12 <= 16'h0000; |
else if (r12_wr) r12 <= reg_dest_val_in; |
else if (r12_inc) r12 <= reg_incr_val; |
|
279,8 → 279,8
reg [15:0] r13; |
wire r13_wr = inst_dest[13] & reg_dest_wr; |
wire r13_inc = inst_src_in[13] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r13 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r13 <= 16'h0000; |
else if (r13_wr) r13 <= reg_dest_val_in; |
else if (r13_inc) r13 <= reg_incr_val; |
|
288,8 → 288,8
reg [15:0] r14; |
wire r14_wr = inst_dest[14] & reg_dest_wr; |
wire r14_inc = inst_src_in[14] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r14 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r14 <= 16'h0000; |
else if (r14_wr) r14 <= reg_dest_val_in; |
else if (r14_inc) r14 <= reg_incr_val; |
|
297,8 → 297,8
reg [15:0] r15; |
wire r15_wr = inst_dest[15] & reg_dest_wr; |
wire r15_inc = inst_src_in[15] & reg_incr; |
always @(posedge mclk or posedge puc) |
if (puc) r15 <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) r15 <= 16'h0000; |
else if (r15_wr) r15 <= reg_dest_val_in; |
else if (r15_inc) r15 <= reg_incr_val; |
|
/verilog/periph/template_periph_8b.v
52,7 → 52,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
62,11 → 62,11
// INPUTs |
//========= |
input mclk; // Main system clock |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
73,18 → 73,28
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter CNTRL1 = 9'h090; |
parameter CNTRL2 = 9'h091; |
parameter CNTRL3 = 9'h092; |
parameter CNTRL4 = 9'h093; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0090; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 2; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] CNTRL1 = 'h0, |
CNTRL2 = 'h1, |
CNTRL3 = 'h2, |
CNTRL4 = 'h3; |
|
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter CNTRL1_D = (256'h1 << (CNTRL1 /2)); |
parameter CNTRL2_D = (256'h1 << (CNTRL2 /2)); |
parameter CNTRL3_D = (256'h1 << (CNTRL3 /2)); |
parameter CNTRL4_D = (256'h1 << (CNTRL4 /2)); |
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1), |
CNTRL2_D = (BASE_REG << CNTRL2), |
CNTRL3_D = (BASE_REG << CNTRL3), |
CNTRL4_D = (BASE_REG << CNTRL4); |
|
|
//============================================================================ |
91,26 → 101,27
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; |
|
// Register address decode |
reg [255:0] reg_dec; |
always @(per_addr) |
case (per_addr) |
(CNTRL1 /2): reg_dec = CNTRL1_D; |
(CNTRL2 /2): reg_dec = CNTRL2_D; |
(CNTRL3 /2): reg_dec = CNTRL3_D; |
(CNTRL4 /2): reg_dec = CNTRL4_D; |
default : reg_dec = {256{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) | |
(CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) | |
(CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) | |
(CNTRL4_D & {DEC_SZ{(reg_addr==(CNTRL4 >>1))}}); |
|
// Read/Write probes |
wire reg_lo_write = per_we[0] & per_en; |
wire reg_hi_write = per_we[1] & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_lo_write = per_we[0] & reg_sel; |
wire reg_hi_write = per_we[1] & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; |
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; |
wire [255:0] reg_rd = reg_dec & {256{reg_read}}; |
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; |
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
121,11 → 132,11
//----------------- |
reg [7:0] cntrl1; |
|
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1/2] : reg_lo_wr[CNTRL1/2]; |
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0]; |
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1]; |
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl1 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl1 <= 8'h00; |
else if (cntrl1_wr) cntrl1 <= cntrl1_nxt; |
|
|
133,11 → 144,11
//----------------- |
reg [7:0] cntrl2; |
|
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2/2] : reg_lo_wr[CNTRL2/2]; |
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0]; |
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2]; |
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl2 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl2 <= 8'h00; |
else if (cntrl2_wr) cntrl2 <= cntrl2_nxt; |
|
|
145,11 → 156,11
//----------------- |
reg [7:0] cntrl3; |
|
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3/2] : reg_lo_wr[CNTRL3/2]; |
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0]; |
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3]; |
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl3 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl3 <= 8'h00; |
else if (cntrl3_wr) cntrl3 <= cntrl3_nxt; |
|
|
157,11 → 168,11
//----------------- |
reg [7:0] cntrl4; |
|
wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4/2] : reg_lo_wr[CNTRL4/2]; |
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0]; |
wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4]; |
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl4 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl4 <= 8'h00; |
else if (cntrl4_wr) cntrl4 <= cntrl4_nxt; |
|
|
171,10 → 182,10
//============================================================================ |
|
// Data output mux |
wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1/2]}})} << (8 & {4{CNTRL1[0]}}); |
wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2/2]}})} << (8 & {4{CNTRL2[0]}}); |
wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3/2]}})} << (8 & {4{CNTRL3[0]}}); |
wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[CNTRL4/2]}})} << (8 & {4{CNTRL4[0]}}); |
wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}}); |
wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}}); |
wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}}); |
wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[CNTRL4]}})} << (8 & {4{CNTRL4[0]}}); |
|
wire [15:0] per_dout = cntrl1_rd | |
cntrl2_rd | |
/verilog/periph/omsp_gpio.v
73,7 → 73,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// PARAMETERs |
119,11 → 119,11
input [7:0] p4_din; // Port 4 data input |
input [7:0] p5_din; // Port 5 data input |
input [7:0] p6_din; // Port 6 data input |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
131,77 → 131,86
//============================================================================= |
|
// Masks |
parameter P1_EN_MSK = {8{P1_EN[0]}}; |
parameter P2_EN_MSK = {8{P2_EN[0]}}; |
parameter P3_EN_MSK = {8{P3_EN[0]}}; |
parameter P4_EN_MSK = {8{P4_EN[0]}}; |
parameter P5_EN_MSK = {8{P5_EN[0]}}; |
parameter P6_EN_MSK = {8{P6_EN[0]}}; |
parameter P1_EN_MSK = {8{P1_EN[0]}}; |
parameter P2_EN_MSK = {8{P2_EN[0]}}; |
parameter P3_EN_MSK = {8{P3_EN[0]}}; |
parameter P4_EN_MSK = {8{P4_EN[0]}}; |
parameter P5_EN_MSK = {8{P5_EN[0]}}; |
parameter P6_EN_MSK = {8{P6_EN[0]}}; |
|
// Register addresses |
parameter P1IN = 9'h020; // Port 1 |
parameter P1OUT = 9'h021; |
parameter P1DIR = 9'h022; |
parameter P1IFG = 9'h023; |
parameter P1IES = 9'h024; |
parameter P1IE = 9'h025; |
parameter P1SEL = 9'h026; |
parameter P2IN = 9'h028; // Port 2 |
parameter P2OUT = 9'h029; |
parameter P2DIR = 9'h02A; |
parameter P2IFG = 9'h02B; |
parameter P2IES = 9'h02C; |
parameter P2IE = 9'h02D; |
parameter P2SEL = 9'h02E; |
parameter P3IN = 9'h018; // Port 3 |
parameter P3OUT = 9'h019; |
parameter P3DIR = 9'h01A; |
parameter P3SEL = 9'h01B; |
parameter P4IN = 9'h01C; // Port 4 |
parameter P4OUT = 9'h01D; |
parameter P4DIR = 9'h01E; |
parameter P4SEL = 9'h01F; |
parameter P5IN = 9'h030; // Port 5 |
parameter P5OUT = 9'h031; |
parameter P5DIR = 9'h032; |
parameter P5SEL = 9'h033; |
parameter P6IN = 9'h034; // Port 6 |
parameter P6OUT = 9'h035; |
parameter P6DIR = 9'h036; |
parameter P6SEL = 9'h037; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0000; |
|
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 6; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] P1IN = 'h20, // Port 1 |
P1OUT = 'h21, |
P1DIR = 'h22, |
P1IFG = 'h23, |
P1IES = 'h24, |
P1IE = 'h25, |
P1SEL = 'h26, |
P2IN = 'h28, // Port 2 |
P2OUT = 'h29, |
P2DIR = 'h2A, |
P2IFG = 'h2B, |
P2IES = 'h2C, |
P2IE = 'h2D, |
P2SEL = 'h2E, |
P3IN = 'h18, // Port 3 |
P3OUT = 'h19, |
P3DIR = 'h1A, |
P3SEL = 'h1B, |
P4IN = 'h1C, // Port 4 |
P4OUT = 'h1D, |
P4DIR = 'h1E, |
P4SEL = 'h1F, |
P5IN = 'h30, // Port 5 |
P5OUT = 'h31, |
P5DIR = 'h32, |
P5SEL = 'h33, |
P6IN = 'h34, // Port 6 |
P6OUT = 'h35, |
P6DIR = 'h36, |
P6SEL = 'h37; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter P1IN_D = (256'h1 << (P1IN /2)); // Port 1 |
parameter P1OUT_D = (256'h1 << (P1OUT /2)); |
parameter P1DIR_D = (256'h1 << (P1DIR /2)); |
parameter P1IFG_D = (256'h1 << (P1IFG /2)); |
parameter P1IES_D = (256'h1 << (P1IES /2)); |
parameter P1IE_D = (256'h1 << (P1IE /2)); |
parameter P1SEL_D = (256'h1 << (P1SEL /2)); |
parameter P2IN_D = (256'h1 << (P2IN /2)); // Port 2 |
parameter P2OUT_D = (256'h1 << (P2OUT /2)); |
parameter P2DIR_D = (256'h1 << (P2DIR /2)); |
parameter P2IFG_D = (256'h1 << (P2IFG /2)); |
parameter P2IES_D = (256'h1 << (P2IES /2)); |
parameter P2IE_D = (256'h1 << (P2IE /2)); |
parameter P2SEL_D = (256'h1 << (P2SEL /2)); |
parameter P3IN_D = (256'h1 << (P3IN /2)); // Port 3 |
parameter P3OUT_D = (256'h1 << (P3OUT /2)); |
parameter P3DIR_D = (256'h1 << (P3DIR /2)); |
parameter P3SEL_D = (256'h1 << (P3SEL /2)); |
parameter P4IN_D = (256'h1 << (P4IN /2)); // Port 4 |
parameter P4OUT_D = (256'h1 << (P4OUT /2)); |
parameter P4DIR_D = (256'h1 << (P4DIR /2)); |
parameter P4SEL_D = (256'h1 << (P4SEL /2)); |
parameter P5IN_D = (256'h1 << (P5IN /2)); // Port 5 |
parameter P5OUT_D = (256'h1 << (P5OUT /2)); |
parameter P5DIR_D = (256'h1 << (P5DIR /2)); |
parameter P5SEL_D = (256'h1 << (P5SEL /2)); |
parameter P6IN_D = (256'h1 << (P6IN /2)); // Port 6 |
parameter P6OUT_D = (256'h1 << (P6OUT /2)); |
parameter P6DIR_D = (256'h1 << (P6DIR /2)); |
parameter P6SEL_D = (256'h1 << (P6SEL /2)); |
parameter [DEC_SZ-1:0] P1IN_D = (BASE_REG << P1IN), // Port 1 |
P1OUT_D = (BASE_REG << P1OUT), |
P1DIR_D = (BASE_REG << P1DIR), |
P1IFG_D = (BASE_REG << P1IFG), |
P1IES_D = (BASE_REG << P1IES), |
P1IE_D = (BASE_REG << P1IE), |
P1SEL_D = (BASE_REG << P1SEL), |
P2IN_D = (BASE_REG << P2IN), // Port 2 |
P2OUT_D = (BASE_REG << P2OUT), |
P2DIR_D = (BASE_REG << P2DIR), |
P2IFG_D = (BASE_REG << P2IFG), |
P2IES_D = (BASE_REG << P2IES), |
P2IE_D = (BASE_REG << P2IE), |
P2SEL_D = (BASE_REG << P2SEL), |
P3IN_D = (BASE_REG << P3IN), // Port 3 |
P3OUT_D = (BASE_REG << P3OUT), |
P3DIR_D = (BASE_REG << P3DIR), |
P3SEL_D = (BASE_REG << P3SEL), |
P4IN_D = (BASE_REG << P4IN), // Port 4 |
P4OUT_D = (BASE_REG << P4OUT), |
P4DIR_D = (BASE_REG << P4DIR), |
P4SEL_D = (BASE_REG << P4SEL), |
P5IN_D = (BASE_REG << P5IN), // Port 5 |
P5OUT_D = (BASE_REG << P5OUT), |
P5DIR_D = (BASE_REG << P5DIR), |
P5SEL_D = (BASE_REG << P5SEL), |
P6IN_D = (BASE_REG << P6IN), // Port 6 |
P6OUT_D = (BASE_REG << P6OUT), |
P6DIR_D = (BASE_REG << P6DIR), |
P6SEL_D = (BASE_REG << P6SEL); |
|
|
//============================================================================ |
208,54 → 217,54
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; |
|
// Register address decode |
reg [255:0] reg_dec; |
always @(per_addr) |
case (per_addr) |
(P1IN /2): reg_dec = P1IN_D & {256{P1_EN[0]}}; |
(P1OUT /2): reg_dec = P1OUT_D & {256{P1_EN[0]}}; |
(P1DIR /2): reg_dec = P1DIR_D & {256{P1_EN[0]}}; |
(P1IFG /2): reg_dec = P1IFG_D & {256{P1_EN[0]}}; |
(P1IES /2): reg_dec = P1IES_D & {256{P1_EN[0]}}; |
(P1IE /2): reg_dec = P1IE_D & {256{P1_EN[0]}}; |
(P1SEL /2): reg_dec = P1SEL_D & {256{P1_EN[0]}}; |
(P2IN /2): reg_dec = P2IN_D & {256{P2_EN[0]}}; |
(P2OUT /2): reg_dec = P2OUT_D & {256{P2_EN[0]}}; |
(P2DIR /2): reg_dec = P2DIR_D & {256{P2_EN[0]}}; |
(P2IFG /2): reg_dec = P2IFG_D & {256{P2_EN[0]}}; |
(P2IES /2): reg_dec = P2IES_D & {256{P2_EN[0]}}; |
(P2IE /2): reg_dec = P2IE_D & {256{P2_EN[0]}}; |
(P2SEL /2): reg_dec = P2SEL_D & {256{P2_EN[0]}}; |
(P3IN /2): reg_dec = P3IN_D & {256{P3_EN[0]}}; |
(P3OUT /2): reg_dec = P3OUT_D & {256{P3_EN[0]}}; |
(P3DIR /2): reg_dec = P3DIR_D & {256{P3_EN[0]}}; |
(P3SEL /2): reg_dec = P3SEL_D & {256{P3_EN[0]}}; |
(P4IN /2): reg_dec = P4IN_D & {256{P4_EN[0]}}; |
(P4OUT /2): reg_dec = P4OUT_D & {256{P4_EN[0]}}; |
(P4DIR /2): reg_dec = P4DIR_D & {256{P4_EN[0]}}; |
(P4SEL /2): reg_dec = P4SEL_D & {256{P4_EN[0]}}; |
(P5IN /2): reg_dec = P5IN_D & {256{P5_EN[0]}}; |
(P5OUT /2): reg_dec = P5OUT_D & {256{P5_EN[0]}}; |
(P5DIR /2): reg_dec = P5DIR_D & {256{P5_EN[0]}}; |
(P5SEL /2): reg_dec = P5SEL_D & {256{P5_EN[0]}}; |
(P6IN /2): reg_dec = P6IN_D & {256{P6_EN[0]}}; |
(P6OUT /2): reg_dec = P6OUT_D & {256{P6_EN[0]}}; |
(P6DIR /2): reg_dec = P6DIR_D & {256{P6_EN[0]}}; |
(P6SEL /2): reg_dec = P6SEL_D & {256{P6_EN[0]}}; |
default : reg_dec = {256{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (P1IN_D & {DEC_SZ{(reg_addr==(P1IN >>1)) & P1_EN[0]}}) | |
(P1OUT_D & {DEC_SZ{(reg_addr==(P1OUT >>1)) & P1_EN[0]}}) | |
(P1DIR_D & {DEC_SZ{(reg_addr==(P1DIR >>1)) & P1_EN[0]}}) | |
(P1IFG_D & {DEC_SZ{(reg_addr==(P1IFG >>1)) & P1_EN[0]}}) | |
(P1IES_D & {DEC_SZ{(reg_addr==(P1IES >>1)) & P1_EN[0]}}) | |
(P1IE_D & {DEC_SZ{(reg_addr==(P1IE >>1)) & P1_EN[0]}}) | |
(P1SEL_D & {DEC_SZ{(reg_addr==(P1SEL >>1)) & P1_EN[0]}}) | |
(P2IN_D & {DEC_SZ{(reg_addr==(P2IN >>1)) & P2_EN[0]}}) | |
(P2OUT_D & {DEC_SZ{(reg_addr==(P2OUT >>1)) & P2_EN[0]}}) | |
(P2DIR_D & {DEC_SZ{(reg_addr==(P2DIR >>1)) & P2_EN[0]}}) | |
(P2IFG_D & {DEC_SZ{(reg_addr==(P2IFG >>1)) & P2_EN[0]}}) | |
(P2IES_D & {DEC_SZ{(reg_addr==(P2IES >>1)) & P2_EN[0]}}) | |
(P2IE_D & {DEC_SZ{(reg_addr==(P2IE >>1)) & P2_EN[0]}}) | |
(P2SEL_D & {DEC_SZ{(reg_addr==(P2SEL >>1)) & P2_EN[0]}}) | |
(P3IN_D & {DEC_SZ{(reg_addr==(P3IN >>1)) & P3_EN[0]}}) | |
(P3OUT_D & {DEC_SZ{(reg_addr==(P3OUT >>1)) & P3_EN[0]}}) | |
(P3DIR_D & {DEC_SZ{(reg_addr==(P3DIR >>1)) & P3_EN[0]}}) | |
(P3SEL_D & {DEC_SZ{(reg_addr==(P3SEL >>1)) & P3_EN[0]}}) | |
(P4IN_D & {DEC_SZ{(reg_addr==(P4IN >>1)) & P4_EN[0]}}) | |
(P4OUT_D & {DEC_SZ{(reg_addr==(P4OUT >>1)) & P4_EN[0]}}) | |
(P4DIR_D & {DEC_SZ{(reg_addr==(P4DIR >>1)) & P4_EN[0]}}) | |
(P4SEL_D & {DEC_SZ{(reg_addr==(P4SEL >>1)) & P4_EN[0]}}) | |
(P5IN_D & {DEC_SZ{(reg_addr==(P5IN >>1)) & P5_EN[0]}}) | |
(P5OUT_D & {DEC_SZ{(reg_addr==(P5OUT >>1)) & P5_EN[0]}}) | |
(P5DIR_D & {DEC_SZ{(reg_addr==(P5DIR >>1)) & P5_EN[0]}}) | |
(P5SEL_D & {DEC_SZ{(reg_addr==(P5SEL >>1)) & P5_EN[0]}}) | |
(P6IN_D & {DEC_SZ{(reg_addr==(P6IN >>1)) & P6_EN[0]}}) | |
(P6OUT_D & {DEC_SZ{(reg_addr==(P6OUT >>1)) & P6_EN[0]}}) | |
(P6DIR_D & {DEC_SZ{(reg_addr==(P6DIR >>1)) & P6_EN[0]}}) | |
(P6SEL_D & {DEC_SZ{(reg_addr==(P6SEL >>1)) & P6_EN[0]}}); |
|
// Read/Write probes |
wire reg_lo_write = per_we[0] & per_en; |
wire reg_hi_write = per_we[1] & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_lo_write = per_we[0] & reg_sel; |
wire reg_hi_write = per_we[1] & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; |
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; |
wire [255:0] reg_rd = reg_dec & {256{reg_read}}; |
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; |
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
// 3) REGISTERS |
//============================================================================ |
262,20 → 271,16
|
// P1IN Register |
//--------------- |
reg [7:0] p1in_s; |
reg [7:0] p1in; |
wire [7:0] p1in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p1in_s <= 8'h00; |
p1in <= 8'h00; |
end |
else |
begin |
p1in_s <= p1_din & P1_EN_MSK; |
p1in <= p1in_s & P1_EN_MSK; |
end |
omsp_sync_cell sync_cell_p1in_0 (.data_out(p1in[0]), .clk(mclk), .data_in(p1_din[0] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_1 (.data_out(p1in[1]), .clk(mclk), .data_in(p1_din[1] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_2 (.data_out(p1in[2]), .clk(mclk), .data_in(p1_din[2] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_3 (.data_out(p1in[3]), .clk(mclk), .data_in(p1_din[3] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_4 (.data_out(p1in[4]), .clk(mclk), .data_in(p1_din[4] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_5 (.data_out(p1in[5]), .clk(mclk), .data_in(p1_din[5] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_6 (.data_out(p1in[6]), .clk(mclk), .data_in(p1_din[6] & P1_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p1in_7 (.data_out(p1in[7]), .clk(mclk), .data_in(p1_din[7] & P1_EN[0]), .rst(puc_rst)); |
|
|
// P1OUT Register |
282,11 → 287,11
//---------------- |
reg [7:0] p1out; |
|
wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT/2] : reg_lo_wr[P1OUT/2]; |
wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT] : reg_lo_wr[P1OUT]; |
wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1out <= 8'h00; |
else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK; |
|
assign p1_dout = p1out; |
296,11 → 301,11
//---------------- |
reg [7:0] p1dir; |
|
wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR/2] : reg_lo_wr[P1DIR/2]; |
wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR] : reg_lo_wr[P1DIR]; |
wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1dir <= 8'h00; |
else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK; |
|
assign p1_dout_en = p1dir; |
310,12 → 315,12
//---------------- |
reg [7:0] p1ifg; |
|
wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG/2] : reg_lo_wr[P1IFG/2]; |
wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0]; |
wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG] : reg_lo_wr[P1IFG]; |
wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0]; |
wire [7:0] p1ifg_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1ifg <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1ifg <= 8'h00; |
else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK; |
else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK; |
|
323,11 → 328,11
//---------------- |
reg [7:0] p1ies; |
|
wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES/2] : reg_lo_wr[P1IES/2]; |
wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0]; |
wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES] : reg_lo_wr[P1IES]; |
wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1ies <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1ies <= 8'h00; |
else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK; |
|
|
335,11 → 340,11
//---------------- |
reg [7:0] p1ie; |
|
wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE/2] : reg_lo_wr[P1IE/2]; |
wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0]; |
wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE] : reg_lo_wr[P1IE]; |
wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1ie <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1ie <= 8'h00; |
else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK; |
|
|
347,11 → 352,11
//---------------- |
reg [7:0] p1sel; |
|
wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL/2] : reg_lo_wr[P1SEL/2]; |
wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL] : reg_lo_wr[P1SEL]; |
wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p1sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1sel <= 8'h00; |
else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK; |
|
assign p1_sel = p1sel; |
359,20 → 364,16
|
// P2IN Register |
//--------------- |
reg [7:0] p2in_s; |
reg [7:0] p2in; |
wire [7:0] p2in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p2in_s <= 8'h00; |
p2in <= 8'h00; |
end |
else |
begin |
p2in_s <= p2_din & P2_EN_MSK; |
p2in <= p2in_s & P2_EN_MSK; |
end |
omsp_sync_cell sync_cell_p2in_0 (.data_out(p2in[0]), .clk(mclk), .data_in(p2_din[0] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_1 (.data_out(p2in[1]), .clk(mclk), .data_in(p2_din[1] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_2 (.data_out(p2in[2]), .clk(mclk), .data_in(p2_din[2] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_3 (.data_out(p2in[3]), .clk(mclk), .data_in(p2_din[3] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_4 (.data_out(p2in[4]), .clk(mclk), .data_in(p2_din[4] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_5 (.data_out(p2in[5]), .clk(mclk), .data_in(p2_din[5] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_6 (.data_out(p2in[6]), .clk(mclk), .data_in(p2_din[6] & P2_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p2in_7 (.data_out(p2in[7]), .clk(mclk), .data_in(p2_din[7] & P2_EN[0]), .rst(puc_rst)); |
|
|
// P2OUT Register |
379,11 → 380,11
//---------------- |
reg [7:0] p2out; |
|
wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT/2] : reg_lo_wr[P2OUT/2]; |
wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT] : reg_lo_wr[P2OUT]; |
wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2out <= 8'h00; |
else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK; |
|
assign p2_dout = p2out; |
393,11 → 394,11
//---------------- |
reg [7:0] p2dir; |
|
wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR/2] : reg_lo_wr[P2DIR/2]; |
wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR] : reg_lo_wr[P2DIR]; |
wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2dir <= 8'h00; |
else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK; |
|
assign p2_dout_en = p2dir; |
407,12 → 408,12
//---------------- |
reg [7:0] p2ifg; |
|
wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG/2] : reg_lo_wr[P2IFG/2]; |
wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0]; |
wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG] : reg_lo_wr[P2IFG]; |
wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0]; |
wire [7:0] p2ifg_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2ifg <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2ifg <= 8'h00; |
else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK; |
else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK; |
|
421,11 → 422,11
//---------------- |
reg [7:0] p2ies; |
|
wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES/2] : reg_lo_wr[P2IES/2]; |
wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0]; |
wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES] : reg_lo_wr[P2IES]; |
wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2ies <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2ies <= 8'h00; |
else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK; |
|
|
433,11 → 434,11
//---------------- |
reg [7:0] p2ie; |
|
wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE/2] : reg_lo_wr[P2IE/2]; |
wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0]; |
wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE] : reg_lo_wr[P2IE]; |
wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2ie <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2ie <= 8'h00; |
else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK; |
|
|
445,11 → 446,11
//---------------- |
reg [7:0] p2sel; |
|
wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL/2] : reg_lo_wr[P2SEL/2]; |
wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL] : reg_lo_wr[P2SEL]; |
wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p2sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2sel <= 8'h00; |
else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK; |
|
assign p2_sel = p2sel; |
457,20 → 458,16
|
// P3IN Register |
//--------------- |
reg [7:0] p3in_s; |
reg [7:0] p3in; |
wire [7:0] p3in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p3in_s <= 8'h00; |
p3in <= 8'h00; |
end |
else |
begin |
p3in_s <= p3_din & P3_EN_MSK; |
p3in <= p3in_s & P3_EN_MSK; |
end |
omsp_sync_cell sync_cell_p3in_0 (.data_out(p3in[0]), .clk(mclk), .data_in(p3_din[0] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_1 (.data_out(p3in[1]), .clk(mclk), .data_in(p3_din[1] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_2 (.data_out(p3in[2]), .clk(mclk), .data_in(p3_din[2] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_3 (.data_out(p3in[3]), .clk(mclk), .data_in(p3_din[3] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_4 (.data_out(p3in[4]), .clk(mclk), .data_in(p3_din[4] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_5 (.data_out(p3in[5]), .clk(mclk), .data_in(p3_din[5] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_6 (.data_out(p3in[6]), .clk(mclk), .data_in(p3_din[6] & P3_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p3in_7 (.data_out(p3in[7]), .clk(mclk), .data_in(p3_din[7] & P3_EN[0]), .rst(puc_rst)); |
|
|
// P3OUT Register |
477,11 → 474,11
//---------------- |
reg [7:0] p3out; |
|
wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT/2] : reg_lo_wr[P3OUT/2]; |
wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT] : reg_lo_wr[P3OUT]; |
wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p3out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p3out <= 8'h00; |
else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK; |
|
assign p3_dout = p3out; |
491,11 → 488,11
//---------------- |
reg [7:0] p3dir; |
|
wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR/2] : reg_lo_wr[P3DIR/2]; |
wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR] : reg_lo_wr[P3DIR]; |
wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p3dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p3dir <= 8'h00; |
else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK; |
|
assign p3_dout_en = p3dir; |
505,11 → 502,11
//---------------- |
reg [7:0] p3sel; |
|
wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL/2] : reg_lo_wr[P3SEL/2]; |
wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL] : reg_lo_wr[P3SEL]; |
wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p3sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p3sel <= 8'h00; |
else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK; |
|
assign p3_sel = p3sel; |
517,20 → 514,16
|
// P4IN Register |
//--------------- |
reg [7:0] p4in_s; |
reg [7:0] p4in; |
wire [7:0] p4in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p4in_s <= 8'h00; |
p4in <= 8'h00; |
end |
else |
begin |
p4in_s <= p4_din & P4_EN_MSK; |
p4in <= p4in_s & P4_EN_MSK; |
end |
omsp_sync_cell sync_cell_p4in_0 (.data_out(p4in[0]), .clk(mclk), .data_in(p4_din[0] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_1 (.data_out(p4in[1]), .clk(mclk), .data_in(p4_din[1] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_2 (.data_out(p4in[2]), .clk(mclk), .data_in(p4_din[2] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_3 (.data_out(p4in[3]), .clk(mclk), .data_in(p4_din[3] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_4 (.data_out(p4in[4]), .clk(mclk), .data_in(p4_din[4] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_5 (.data_out(p4in[5]), .clk(mclk), .data_in(p4_din[5] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_6 (.data_out(p4in[6]), .clk(mclk), .data_in(p4_din[6] & P4_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p4in_7 (.data_out(p4in[7]), .clk(mclk), .data_in(p4_din[7] & P4_EN[0]), .rst(puc_rst)); |
|
|
// P4OUT Register |
537,11 → 530,11
//---------------- |
reg [7:0] p4out; |
|
wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT/2] : reg_lo_wr[P4OUT/2]; |
wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT] : reg_lo_wr[P4OUT]; |
wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p4out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p4out <= 8'h00; |
else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK; |
|
assign p4_dout = p4out; |
551,11 → 544,11
//---------------- |
reg [7:0] p4dir; |
|
wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR/2] : reg_lo_wr[P4DIR/2]; |
wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR] : reg_lo_wr[P4DIR]; |
wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p4dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p4dir <= 8'h00; |
else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK; |
|
assign p4_dout_en = p4dir; |
565,11 → 558,11
//---------------- |
reg [7:0] p4sel; |
|
wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL/2] : reg_lo_wr[P4SEL/2]; |
wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL] : reg_lo_wr[P4SEL]; |
wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p4sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p4sel <= 8'h00; |
else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK; |
|
assign p4_sel = p4sel; |
577,20 → 570,16
|
// P5IN Register |
//--------------- |
reg [7:0] p5in_s; |
reg [7:0] p5in; |
wire [7:0] p5in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p5in_s <= 8'h00; |
p5in <= 8'h00; |
end |
else |
begin |
p5in_s <= p5_din & P5_EN_MSK; |
p5in <= p5in_s & P5_EN_MSK; |
end |
omsp_sync_cell sync_cell_p5in_0 (.data_out(p5in[0]), .clk(mclk), .data_in(p5_din[0] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_1 (.data_out(p5in[1]), .clk(mclk), .data_in(p5_din[1] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_2 (.data_out(p5in[2]), .clk(mclk), .data_in(p5_din[2] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_3 (.data_out(p5in[3]), .clk(mclk), .data_in(p5_din[3] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_4 (.data_out(p5in[4]), .clk(mclk), .data_in(p5_din[4] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_5 (.data_out(p5in[5]), .clk(mclk), .data_in(p5_din[5] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_6 (.data_out(p5in[6]), .clk(mclk), .data_in(p5_din[6] & P5_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p5in_7 (.data_out(p5in[7]), .clk(mclk), .data_in(p5_din[7] & P5_EN[0]), .rst(puc_rst)); |
|
|
// P5OUT Register |
597,11 → 586,11
//---------------- |
reg [7:0] p5out; |
|
wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT/2] : reg_lo_wr[P5OUT/2]; |
wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT] : reg_lo_wr[P5OUT]; |
wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p5out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p5out <= 8'h00; |
else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK; |
|
assign p5_dout = p5out; |
611,11 → 600,11
//---------------- |
reg [7:0] p5dir; |
|
wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR/2] : reg_lo_wr[P5DIR/2]; |
wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR] : reg_lo_wr[P5DIR]; |
wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p5dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p5dir <= 8'h00; |
else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK; |
|
assign p5_dout_en = p5dir; |
625,11 → 614,11
//---------------- |
reg [7:0] p5sel; |
|
wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL/2] : reg_lo_wr[P5SEL/2]; |
wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL] : reg_lo_wr[P5SEL]; |
wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p5sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p5sel <= 8'h00; |
else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK; |
|
assign p5_sel = p5sel; |
637,20 → 626,16
|
// P6IN Register |
//--------------- |
reg [7:0] p6in_s; |
reg [7:0] p6in; |
wire [7:0] p6in; |
|
always @ (posedge mclk or posedge puc) |
if (puc) |
begin |
p6in_s <= 8'h00; |
p6in <= 8'h00; |
end |
else |
begin |
p6in_s <= p6_din & P6_EN_MSK; |
p6in <= p6in_s & P6_EN_MSK; |
end |
omsp_sync_cell sync_cell_p6in_0 (.data_out(p6in[0]), .clk(mclk), .data_in(p6_din[0] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_1 (.data_out(p6in[1]), .clk(mclk), .data_in(p6_din[1] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_2 (.data_out(p6in[2]), .clk(mclk), .data_in(p6_din[2] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_3 (.data_out(p6in[3]), .clk(mclk), .data_in(p6_din[3] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_4 (.data_out(p6in[4]), .clk(mclk), .data_in(p6_din[4] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_5 (.data_out(p6in[5]), .clk(mclk), .data_in(p6_din[5] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_6 (.data_out(p6in[6]), .clk(mclk), .data_in(p6_din[6] & P6_EN[0]), .rst(puc_rst)); |
omsp_sync_cell sync_cell_p6in_7 (.data_out(p6in[7]), .clk(mclk), .data_in(p6_din[7] & P6_EN[0]), .rst(puc_rst)); |
|
|
// P6OUT Register |
657,11 → 642,11
//---------------- |
reg [7:0] p6out; |
|
wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT/2] : reg_lo_wr[P6OUT/2]; |
wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0]; |
wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT] : reg_lo_wr[P6OUT]; |
wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p6out <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p6out <= 8'h00; |
else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK; |
|
assign p6_dout = p6out; |
671,11 → 656,11
//---------------- |
reg [7:0] p6dir; |
|
wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR/2] : reg_lo_wr[P6DIR/2]; |
wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0]; |
wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR] : reg_lo_wr[P6DIR]; |
wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p6dir <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p6dir <= 8'h00; |
else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK; |
|
assign p6_dout_en = p6dir; |
685,11 → 670,11
//---------------- |
reg [7:0] p6sel; |
|
wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL/2] : reg_lo_wr[P6SEL/2]; |
wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0]; |
wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL] : reg_lo_wr[P6SEL]; |
wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) p6sel <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p6sel <= 8'h00; |
else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK; |
|
assign p6_sel = p6sel; |
705,8 → 690,8
|
// Delay input |
reg [7:0] p1in_dly; |
always @ (posedge mclk or posedge puc) |
if (puc) p1in_dly <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p1in_dly <= 8'h00; |
else p1in_dly <= p1in & P1_EN_MSK; |
|
// Edge detection |
732,8 → 717,8
|
// Delay input |
reg [7:0] p2in_dly; |
always @ (posedge mclk or posedge puc) |
if (puc) p2in_dly <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) p2in_dly <= 8'h00; |
else p2in_dly <= p2in & P2_EN_MSK; |
|
// Edge detection |
759,36 → 744,36
//============================================================================ |
|
// Data output mux |
wire [15:0] p1in_rd = {8'h00, (p1in & {8{reg_rd[P1IN/2]}})} << (8 & {4{P1IN[0]}}); |
wire [15:0] p1out_rd = {8'h00, (p1out & {8{reg_rd[P1OUT/2]}})} << (8 & {4{P1OUT[0]}}); |
wire [15:0] p1dir_rd = {8'h00, (p1dir & {8{reg_rd[P1DIR/2]}})} << (8 & {4{P1DIR[0]}}); |
wire [15:0] p1ifg_rd = {8'h00, (p1ifg & {8{reg_rd[P1IFG/2]}})} << (8 & {4{P1IFG[0]}}); |
wire [15:0] p1ies_rd = {8'h00, (p1ies & {8{reg_rd[P1IES/2]}})} << (8 & {4{P1IES[0]}}); |
wire [15:0] p1ie_rd = {8'h00, (p1ie & {8{reg_rd[P1IE/2]}})} << (8 & {4{P1IE[0]}}); |
wire [15:0] p1sel_rd = {8'h00, (p1sel & {8{reg_rd[P1SEL/2]}})} << (8 & {4{P1SEL[0]}}); |
wire [15:0] p2in_rd = {8'h00, (p2in & {8{reg_rd[P2IN/2]}})} << (8 & {4{P2IN[0]}}); |
wire [15:0] p2out_rd = {8'h00, (p2out & {8{reg_rd[P2OUT/2]}})} << (8 & {4{P2OUT[0]}}); |
wire [15:0] p2dir_rd = {8'h00, (p2dir & {8{reg_rd[P2DIR/2]}})} << (8 & {4{P2DIR[0]}}); |
wire [15:0] p2ifg_rd = {8'h00, (p2ifg & {8{reg_rd[P2IFG/2]}})} << (8 & {4{P2IFG[0]}}); |
wire [15:0] p2ies_rd = {8'h00, (p2ies & {8{reg_rd[P2IES/2]}})} << (8 & {4{P2IES[0]}}); |
wire [15:0] p2ie_rd = {8'h00, (p2ie & {8{reg_rd[P2IE/2]}})} << (8 & {4{P2IE[0]}}); |
wire [15:0] p2sel_rd = {8'h00, (p2sel & {8{reg_rd[P2SEL/2]}})} << (8 & {4{P2SEL[0]}}); |
wire [15:0] p3in_rd = {8'h00, (p3in & {8{reg_rd[P3IN/2]}})} << (8 & {4{P3IN[0]}}); |
wire [15:0] p3out_rd = {8'h00, (p3out & {8{reg_rd[P3OUT/2]}})} << (8 & {4{P3OUT[0]}}); |
wire [15:0] p3dir_rd = {8'h00, (p3dir & {8{reg_rd[P3DIR/2]}})} << (8 & {4{P3DIR[0]}}); |
wire [15:0] p3sel_rd = {8'h00, (p3sel & {8{reg_rd[P3SEL/2]}})} << (8 & {4{P3SEL[0]}}); |
wire [15:0] p4in_rd = {8'h00, (p4in & {8{reg_rd[P4IN/2]}})} << (8 & {4{P4IN[0]}}); |
wire [15:0] p4out_rd = {8'h00, (p4out & {8{reg_rd[P4OUT/2]}})} << (8 & {4{P4OUT[0]}}); |
wire [15:0] p4dir_rd = {8'h00, (p4dir & {8{reg_rd[P4DIR/2]}})} << (8 & {4{P4DIR[0]}}); |
wire [15:0] p4sel_rd = {8'h00, (p4sel & {8{reg_rd[P4SEL/2]}})} << (8 & {4{P4SEL[0]}}); |
wire [15:0] p5in_rd = {8'h00, (p5in & {8{reg_rd[P5IN/2]}})} << (8 & {4{P5IN[0]}}); |
wire [15:0] p5out_rd = {8'h00, (p5out & {8{reg_rd[P5OUT/2]}})} << (8 & {4{P5OUT[0]}}); |
wire [15:0] p5dir_rd = {8'h00, (p5dir & {8{reg_rd[P5DIR/2]}})} << (8 & {4{P5DIR[0]}}); |
wire [15:0] p5sel_rd = {8'h00, (p5sel & {8{reg_rd[P5SEL/2]}})} << (8 & {4{P5SEL[0]}}); |
wire [15:0] p6in_rd = {8'h00, (p6in & {8{reg_rd[P6IN/2]}})} << (8 & {4{P6IN[0]}}); |
wire [15:0] p6out_rd = {8'h00, (p6out & {8{reg_rd[P6OUT/2]}})} << (8 & {4{P6OUT[0]}}); |
wire [15:0] p6dir_rd = {8'h00, (p6dir & {8{reg_rd[P6DIR/2]}})} << (8 & {4{P6DIR[0]}}); |
wire [15:0] p6sel_rd = {8'h00, (p6sel & {8{reg_rd[P6SEL/2]}})} << (8 & {4{P6SEL[0]}}); |
wire [15:0] p1in_rd = {8'h00, (p1in & {8{reg_rd[P1IN]}})} << (8 & {4{P1IN[0]}}); |
wire [15:0] p1out_rd = {8'h00, (p1out & {8{reg_rd[P1OUT]}})} << (8 & {4{P1OUT[0]}}); |
wire [15:0] p1dir_rd = {8'h00, (p1dir & {8{reg_rd[P1DIR]}})} << (8 & {4{P1DIR[0]}}); |
wire [15:0] p1ifg_rd = {8'h00, (p1ifg & {8{reg_rd[P1IFG]}})} << (8 & {4{P1IFG[0]}}); |
wire [15:0] p1ies_rd = {8'h00, (p1ies & {8{reg_rd[P1IES]}})} << (8 & {4{P1IES[0]}}); |
wire [15:0] p1ie_rd = {8'h00, (p1ie & {8{reg_rd[P1IE]}})} << (8 & {4{P1IE[0]}}); |
wire [15:0] p1sel_rd = {8'h00, (p1sel & {8{reg_rd[P1SEL]}})} << (8 & {4{P1SEL[0]}}); |
wire [15:0] p2in_rd = {8'h00, (p2in & {8{reg_rd[P2IN]}})} << (8 & {4{P2IN[0]}}); |
wire [15:0] p2out_rd = {8'h00, (p2out & {8{reg_rd[P2OUT]}})} << (8 & {4{P2OUT[0]}}); |
wire [15:0] p2dir_rd = {8'h00, (p2dir & {8{reg_rd[P2DIR]}})} << (8 & {4{P2DIR[0]}}); |
wire [15:0] p2ifg_rd = {8'h00, (p2ifg & {8{reg_rd[P2IFG]}})} << (8 & {4{P2IFG[0]}}); |
wire [15:0] p2ies_rd = {8'h00, (p2ies & {8{reg_rd[P2IES]}})} << (8 & {4{P2IES[0]}}); |
wire [15:0] p2ie_rd = {8'h00, (p2ie & {8{reg_rd[P2IE]}})} << (8 & {4{P2IE[0]}}); |
wire [15:0] p2sel_rd = {8'h00, (p2sel & {8{reg_rd[P2SEL]}})} << (8 & {4{P2SEL[0]}}); |
wire [15:0] p3in_rd = {8'h00, (p3in & {8{reg_rd[P3IN]}})} << (8 & {4{P3IN[0]}}); |
wire [15:0] p3out_rd = {8'h00, (p3out & {8{reg_rd[P3OUT]}})} << (8 & {4{P3OUT[0]}}); |
wire [15:0] p3dir_rd = {8'h00, (p3dir & {8{reg_rd[P3DIR]}})} << (8 & {4{P3DIR[0]}}); |
wire [15:0] p3sel_rd = {8'h00, (p3sel & {8{reg_rd[P3SEL]}})} << (8 & {4{P3SEL[0]}}); |
wire [15:0] p4in_rd = {8'h00, (p4in & {8{reg_rd[P4IN]}})} << (8 & {4{P4IN[0]}}); |
wire [15:0] p4out_rd = {8'h00, (p4out & {8{reg_rd[P4OUT]}})} << (8 & {4{P4OUT[0]}}); |
wire [15:0] p4dir_rd = {8'h00, (p4dir & {8{reg_rd[P4DIR]}})} << (8 & {4{P4DIR[0]}}); |
wire [15:0] p4sel_rd = {8'h00, (p4sel & {8{reg_rd[P4SEL]}})} << (8 & {4{P4SEL[0]}}); |
wire [15:0] p5in_rd = {8'h00, (p5in & {8{reg_rd[P5IN]}})} << (8 & {4{P5IN[0]}}); |
wire [15:0] p5out_rd = {8'h00, (p5out & {8{reg_rd[P5OUT]}})} << (8 & {4{P5OUT[0]}}); |
wire [15:0] p5dir_rd = {8'h00, (p5dir & {8{reg_rd[P5DIR]}})} << (8 & {4{P5DIR[0]}}); |
wire [15:0] p5sel_rd = {8'h00, (p5sel & {8{reg_rd[P5SEL]}})} << (8 & {4{P5SEL[0]}}); |
wire [15:0] p6in_rd = {8'h00, (p6in & {8{reg_rd[P6IN]}})} << (8 & {4{P6IN[0]}}); |
wire [15:0] p6out_rd = {8'h00, (p6out & {8{reg_rd[P6OUT]}})} << (8 & {4{P6OUT[0]}}); |
wire [15:0] p6dir_rd = {8'h00, (p6dir & {8{reg_rd[P6DIR]}})} << (8 & {4{P6DIR[0]}}); |
wire [15:0] p6sel_rd = {8'h00, (p6sel & {8{reg_rd[P6SEL]}})} << (8 & {4{P6SEL[0]}}); |
|
wire [15:0] per_dout = p1in_rd | |
p1out_rd | |
/verilog/periph/omsp_timerA.v
63,7 → 63,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc, // Main system reset |
puc_rst, // Main system reset |
smclk_en, // SMCLK enable (from CPU) |
ta_cci0a, // Timer A capture 0 input A |
ta_cci0b, // Timer A capture 0 input B |
93,11 → 93,11
input inclk; // INCLK external timer clock (SLOW) |
input irq_ta0_acc; // Interrupt request TACCR0 accepted |
input mclk; // Main system clock |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
input smclk_en; // SMCLK enable (from CPU) |
input ta_cci0a; // Timer A capture 0 input A |
input ta_cci0b; // Timer A capture 0 input B |
112,28 → 112,37
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter TACTL = 9'h160; |
parameter TAR = 9'h170; |
parameter TACCTL0 = 9'h162; |
parameter TACCR0 = 9'h172; |
parameter TACCTL1 = 9'h164; |
parameter TACCR1 = 9'h174; |
parameter TACCTL2 = 9'h166; |
parameter TACCR2 = 9'h176; |
parameter TAIV = 9'h12E; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0100; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 7; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] TACTL = 'h60, |
TAR = 'h70, |
TACCTL0 = 'h62, |
TACCR0 = 'h72, |
TACCTL1 = 'h64, |
TACCR1 = 'h74, |
TACCTL2 = 'h66, |
TACCR2 = 'h76, |
TAIV = 'h2E; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter TACTL_D = (512'h1 << TACTL); |
parameter TAR_D = (512'h1 << TAR); |
parameter TACCTL0_D = (512'h1 << TACCTL0); |
parameter TACCR0_D = (512'h1 << TACCR0); |
parameter TACCTL1_D = (512'h1 << TACCTL1); |
parameter TACCR1_D = (512'h1 << TACCR1); |
parameter TACCTL2_D = (512'h1 << TACCTL2); |
parameter TACCR2_D = (512'h1 << TACCR2); |
parameter TAIV_D = (512'h1 << TAIV); |
parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL), |
TAR_D = (BASE_REG << TAR), |
TACCTL0_D = (BASE_REG << TACCTL0), |
TACCR0_D = (BASE_REG << TACCR0), |
TACCTL1_D = (BASE_REG << TACCTL1), |
TACCR1_D = (BASE_REG << TACCR1), |
TACCTL2_D = (BASE_REG << TACCTL2), |
TACCR2_D = (BASE_REG << TACCR2), |
TAIV_D = (BASE_REG << TAIV); |
|
|
//============================================================================ |
140,29 → 149,30
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; |
|
// Register address decode |
reg [511:0] reg_dec; |
always @(per_addr) |
case ({per_addr,1'b0}) |
TACTL : reg_dec = TACTL_D; |
TAR : reg_dec = TAR_D; |
TACCTL0: reg_dec = TACCTL0_D; |
TACCR0 : reg_dec = TACCR0_D; |
TACCTL1: reg_dec = TACCTL1_D; |
TACCR1 : reg_dec = TACCR1_D; |
TACCTL2: reg_dec = TACCTL2_D; |
TACCR2 : reg_dec = TACCR2_D; |
TAIV : reg_dec = TAIV_D; |
default: reg_dec = {512{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) | |
(TAR_D & {DEC_SZ{(reg_addr == TAR )}}) | |
(TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) | |
(TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) | |
(TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) | |
(TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) | |
(TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) | |
(TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) | |
(TAIV_D & {DEC_SZ{(reg_addr == TAIV )}}); |
|
// Read/Write probes |
wire reg_write = |per_we & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_write = |per_we & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [511:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [511:0] reg_rd = reg_dec & {512{reg_read}}; |
wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}}; |
|
|
//============================================================================ |
178,8 → 188,8
wire taifg_set; |
wire taifg_clr; |
|
always @ (posedge mclk or posedge puc) |
if (puc) tactl <= 10'h000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tactl <= 10'h000; |
else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; |
else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; |
|
198,8 → 208,8
tar_dec ? 16'hffff : 16'h0000; |
wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add); |
|
always @ (posedge mclk or posedge puc) |
if (puc) tar <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tar <= 16'h0000; |
else if (tar_wr) tar <= per_din; |
else if (taclr) tar <= 16'h0000; |
else if (tar_clk & ~dbg_freeze) tar <= tar_nxt; |
213,8 → 223,8
wire ccifg0_set; |
wire cov0_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) tacctl0 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tacctl0 <= 16'h0000; |
else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; |
else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; |
|
230,8 → 240,8
wire taccr0_wr = reg_wr[TACCR0]; |
wire cci0_cap; |
|
always @ (posedge mclk or posedge puc) |
if (puc) taccr0 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) taccr0 <= 16'h0000; |
else if (taccr0_wr) taccr0 <= per_din; |
else if (cci0_cap) taccr0 <= tar; |
|
245,8 → 255,8
wire ccifg1_clr; |
wire cov1_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) tacctl1 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tacctl1 <= 16'h0000; |
else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; |
else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; |
|
262,8 → 272,8
wire taccr1_wr = reg_wr[TACCR1]; |
wire cci1_cap; |
|
always @ (posedge mclk or posedge puc) |
if (puc) taccr1 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) taccr1 <= 16'h0000; |
else if (taccr1_wr) taccr1 <= per_din; |
else if (cci1_cap) taccr1 <= tar; |
|
277,8 → 287,8
wire ccifg2_clr; |
wire cov2_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) tacctl2 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tacctl2 <= 16'h0000; |
else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; |
else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; |
|
294,8 → 304,8
wire taccr2_wr = reg_wr[TACCR2]; |
wire cci2_cap; |
|
always @ (posedge mclk or posedge puc) |
if (puc) taccr2 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) taccr2 <= 16'h0000; |
else if (taccr2_wr) taccr2 <= per_din; |
else if (cci2_cap) taccr2 <= tar; |
|
345,22 → 355,43
|
// Clock input synchronization (TACLK & INCLK) |
//----------------------------------------------------------- |
reg [2:0] taclk_s; |
wire taclk_s; |
wire inclk_s; |
|
omsp_sync_cell sync_cell_taclk ( |
.data_out (taclk_s), |
.clk (mclk), |
.data_in (taclk), |
.rst (puc_rst) |
); |
|
omsp_sync_cell sync_cell_inclk ( |
.data_out (inclk_s), |
.clk (mclk), |
.data_in (inclk), |
.rst (puc_rst) |
); |
|
|
// Clock edge detection (TACLK & INCLK) |
//----------------------------------------------------------- |
|
reg taclk_dly; |
|
always @ (posedge mclk or posedge puc) |
if (puc) taclk_s <= 3'b000; |
else taclk_s <= {taclk_s[1:0], taclk}; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) taclk_dly <= 1'b0; |
else taclk_dly <= taclk_s; |
|
wire taclk_en = taclk_s[1] & ~taclk_s[2]; |
wire taclk_en = taclk_s & ~taclk_dly; |
|
|
reg [2:0] inclk_s; |
reg inclk_dly; |
|
always @ (posedge mclk or posedge puc) |
if (puc) inclk_s <= 3'b000; |
else inclk_s <= {inclk_s[1:0], inclk}; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) inclk_dly <= 1'b0; |
else inclk_dly <= inclk_s; |
|
wire inclk_en = inclk_s[1] & ~inclk_s[2]; |
wire inclk_en = inclk_s & ~inclk_dly; |
|
|
// Timer clock input mux |
380,8 → 411,8
(tactl[`TAIDx]==2'b10) ? &clk_div[1:0] : |
&clk_div[2:0]); |
|
always @ (posedge mclk or posedge puc) |
if (puc) clk_div <= 3'h0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) clk_div <= 3'h0; |
else if (tar_clk | taclr) clk_div <= 3'h0; |
else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1; |
|
396,8 → 427,8
((tactl[`TAMCx]==2'b11) & ~tar_dec); |
|
reg tar_dir; |
always @ (posedge mclk or posedge puc) |
if (puc) tar_dir <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) tar_dir <= 1'b0; |
else if (taclr) tar_dir <= 1'b0; |
else if (tactl[`TAMCx]==2'b11) |
begin |
436,89 → 467,118
(tacctl2[`TACCISx]==2'b01) ? ta_cci2b : |
(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1; |
|
// Register CCIx for synchronization and edge detection |
reg [2:0] cci_s; |
always @ (posedge mclk or posedge puc) |
if (puc) cci_s <= 3'h0; |
else cci_s <= {cci2, cci1, cci0}; |
reg [2:0] cci_ss; |
always @ (posedge mclk or posedge puc) |
if (puc) cci_ss <= 3'h0; |
else cci_ss <= cci_s; |
reg [2:0] cci_sss; |
always @ (posedge mclk or posedge puc) |
if (puc) cci_sss <= 3'h0; |
else cci_sss <= cci_ss; |
// CCIx synchronization |
wire cci0_s; |
wire cci1_s; |
wire cci2_s; |
|
omsp_sync_cell sync_cell_cci0 ( |
.data_out (cci0_s), |
.clk (mclk), |
.data_in (cci0), |
.rst (puc_rst) |
); |
omsp_sync_cell sync_cell_cci1 ( |
.data_out (cci1_s), |
.clk (mclk), |
.data_in (cci1), |
.rst (puc_rst) |
); |
omsp_sync_cell sync_cell_cci2 ( |
.data_out (cci2_s), |
.clk (mclk), |
.data_in (cci2), |
.rst (puc_rst) |
); |
|
// Register CCIx for edge detection |
reg cci0_dly; |
reg cci1_dly; |
reg cci2_dly; |
|
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) |
begin |
cci0_dly <= 1'b0; |
cci1_dly <= 1'b0; |
cci2_dly <= 1'b0; |
end |
else |
begin |
cci0_dly <= cci0_s; |
cci1_dly <= cci1_s; |
cci2_dly <= cci2_s; |
end |
|
|
// Generate SCCIx |
//------------------ |
|
always @ (posedge mclk or posedge puc) |
if (puc) scci0 <= 1'b0; |
else if (tar_clk & equ0) scci0 <= cci_ss[0]; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) scci0 <= 1'b0; |
else if (tar_clk & equ0) scci0 <= cci0_s; |
|
always @ (posedge mclk or posedge puc) |
if (puc) scci1 <= 1'b0; |
else if (tar_clk & equ1) scci1 <= cci_ss[1]; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) scci1 <= 1'b0; |
else if (tar_clk & equ1) scci1 <= cci1_s; |
|
always @ (posedge mclk or posedge puc) |
if (puc) scci2 <= 1'b0; |
else if (tar_clk & equ2) scci2 <= cci_ss[2]; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) scci2 <= 1'b0; |
else if (tar_clk & equ2) scci2 <= cci2_s; |
|
|
// Capture mode |
//------------------ |
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 : |
(tacctl0[`TACMx]==2'b01) ? ( cci_ss[0] & ~cci_sss[0]) : // Rising edge |
(tacctl0[`TACMx]==2'b10) ? (~cci_ss[0] & cci_sss[0]) : // Falling edge |
( cci_ss[0] ^ cci_sss[0]); // Both edges |
(tacctl0[`TACMx]==2'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge |
(tacctl0[`TACMx]==2'b10) ? (~cci0_s & cci0_dly) : // Falling edge |
( cci0_s ^ cci0_dly); // Both edges |
|
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 : |
(tacctl1[`TACMx]==2'b01) ? ( cci_ss[1] & ~cci_sss[1]) : // Rising edge |
(tacctl1[`TACMx]==2'b10) ? (~cci_ss[1] & cci_sss[1]) : // Falling edge |
( cci_ss[1] ^ cci_sss[1]); // Both edges |
(tacctl1[`TACMx]==2'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge |
(tacctl1[`TACMx]==2'b10) ? (~cci1_s & cci1_dly) : // Falling edge |
( cci1_s ^ cci1_dly); // Both edges |
|
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 : |
(tacctl2[`TACMx]==2'b01) ? ( cci_ss[2] & ~cci_sss[2]) : // Rising edge |
(tacctl2[`TACMx]==2'b10) ? (~cci_ss[2] & cci_sss[2]) : // Falling edge |
( cci_ss[2] ^ cci_sss[2]); // Both edges |
(tacctl2[`TACMx]==2'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge |
(tacctl2[`TACMx]==2'b10) ? (~cci2_s & cci2_dly) : // Falling edge |
( cci2_s ^ cci2_dly); // Both edges |
|
// Event Synchronization |
//----------------------- |
|
reg cci0_evt_s; |
always @ (posedge mclk or posedge puc) |
if (puc) cci0_evt_s <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci0_evt_s <= 1'b0; |
else if (tar_clk) cci0_evt_s <= 1'b0; |
else if (cci0_evt) cci0_evt_s <= 1'b1; |
|
reg cci1_evt_s; |
always @ (posedge mclk or posedge puc) |
if (puc) cci1_evt_s <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci1_evt_s <= 1'b0; |
else if (tar_clk) cci1_evt_s <= 1'b0; |
else if (cci1_evt) cci1_evt_s <= 1'b1; |
|
reg cci2_evt_s; |
always @ (posedge mclk or posedge puc) |
if (puc) cci2_evt_s <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci2_evt_s <= 1'b0; |
else if (tar_clk) cci2_evt_s <= 1'b0; |
else if (cci2_evt) cci2_evt_s <= 1'b1; |
|
reg cci0_sync; |
always @ (posedge mclk or posedge puc) |
if (puc) cci0_sync <= 1'b0; |
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s); |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci0_sync <= 1'b0; |
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s); |
|
reg cci1_sync; |
always @ (posedge mclk or posedge puc) |
if (puc) cci1_sync <= 1'b0; |
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s); |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci1_sync <= 1'b0; |
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s); |
|
reg cci2_sync; |
always @ (posedge mclk or posedge puc) |
if (puc) cci2_sync <= 1'b0; |
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s); |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cci2_sync <= 1'b0; |
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s); |
|
|
// Generate final capture command |
534,22 → 594,22
|
reg cap0_taken; |
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]); |
always @ (posedge mclk or posedge puc) |
if (puc) cap0_taken <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cap0_taken <= 1'b0; |
else if (cci0_cap) cap0_taken <= 1'b1; |
else if (cap0_taken_clr) cap0_taken <= 1'b0; |
|
reg cap1_taken; |
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]); |
always @ (posedge mclk or posedge puc) |
if (puc) cap1_taken <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cap1_taken <= 1'b0; |
else if (cci1_cap) cap1_taken <= 1'b1; |
else if (cap1_taken_clr) cap1_taken <= 1'b0; |
|
reg cap2_taken; |
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]); |
always @ (posedge mclk or posedge puc) |
if (puc) cap2_taken <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cap2_taken <= 1'b0; |
else if (cci2_cap) cap2_taken <= 1'b1; |
else if (cap2_taken_clr) cap2_taken <= 1'b0; |
|
589,8 → 649,8
(tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 : |
ta_out0_mode7; |
|
always @ (posedge mclk or posedge puc) |
if (puc) ta_out0 <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) ta_out0 <= 1'b0; |
else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0; |
else if (tar_clk) ta_out0 <= ta_out0_nxt; |
|
623,8 → 683,8
(tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 : |
ta_out1_mode7; |
|
always @ (posedge mclk or posedge puc) |
if (puc) ta_out1 <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) ta_out1 <= 1'b0; |
else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0; |
else if (tar_clk) ta_out1 <= ta_out1_nxt; |
|
657,8 → 717,8
(tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 : |
ta_out2_mode7; |
|
always @ (posedge mclk or posedge puc) |
if (puc) ta_out2 <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) ta_out2 <= 1'b0; |
else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0; |
else if (tar_clk) ta_out2 <= ta_out2_nxt; |
|
/verilog/periph/template_periph_16b.v
52,7 → 52,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
62,11 → 62,11
// INPUTs |
//========= |
input mclk; // Main system clock |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
73,18 → 73,27
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter CNTRL1 = 9'h190; |
parameter CNTRL2 = 9'h192; |
parameter CNTRL3 = 9'h194; |
parameter CNTRL4 = 9'h196; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0190; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 3; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] CNTRL1 = 'h0, |
CNTRL2 = 'h2, |
CNTRL3 = 'h4, |
CNTRL4 = 'h6; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter CNTRL1_D = (512'h1 << CNTRL1); |
parameter CNTRL2_D = (512'h1 << CNTRL2); |
parameter CNTRL3_D = (512'h1 << CNTRL3); |
parameter CNTRL4_D = (512'h1 << CNTRL4); |
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1), |
CNTRL2_D = (BASE_REG << CNTRL2), |
CNTRL3_D = (BASE_REG << CNTRL3), |
CNTRL4_D = (BASE_REG << CNTRL4); |
|
|
//============================================================================ |
91,24 → 100,25
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; |
|
// Register address decode |
reg [511:0] reg_dec; |
always @(per_addr) |
case ({per_addr,1'b0}) |
CNTRL1 : reg_dec = CNTRL1_D; |
CNTRL2 : reg_dec = CNTRL2_D; |
CNTRL3 : reg_dec = CNTRL3_D; |
CNTRL4 : reg_dec = CNTRL4_D; |
default: reg_dec = {512{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) | |
(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}) | |
(CNTRL3_D & {DEC_SZ{(reg_addr == CNTRL3 )}}) | |
(CNTRL4_D & {DEC_SZ{(reg_addr == CNTRL4 )}}); |
|
// Read/Write probes |
wire reg_write = |per_we & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_write = |per_we & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [511:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [511:0] reg_rd = reg_dec & {512{reg_read}}; |
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
121,8 → 131,8
|
wire cntrl1_wr = reg_wr[CNTRL1]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl1 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl1 <= 16'h0000; |
else if (cntrl1_wr) cntrl1 <= per_din; |
|
|
132,8 → 142,8
|
wire cntrl2_wr = reg_wr[CNTRL2]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl2 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl2 <= 16'h0000; |
else if (cntrl2_wr) cntrl2 <= per_din; |
|
|
143,8 → 153,8
|
wire cntrl3_wr = reg_wr[CNTRL3]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl3 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl3 <= 16'h0000; |
else if (cntrl3_wr) cntrl3 <= per_din; |
|
|
154,8 → 164,8
|
wire cntrl4_wr = reg_wr[CNTRL4]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) cntrl4 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cntrl4 <= 16'h0000; |
else if (cntrl4_wr) cntrl4 <= per_din; |
|
|
/verilog/omsp_multiplier.v
52,7 → 52,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
62,11 → 62,11
// INPUTs |
//========= |
input mclk; // Main system clock |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
73,26 → 73,35
// 1) PARAMETER/REGISTERS & WIRE DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter OP1_MPY = 9'h130; |
parameter OP1_MPYS = 9'h132; |
parameter OP1_MAC = 9'h134; |
parameter OP1_MACS = 9'h136; |
parameter OP2 = 9'h138; |
parameter RESLO = 9'h13A; |
parameter RESHI = 9'h13C; |
parameter SUMEXT = 9'h13E; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0130; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 4; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] OP1_MPY = 'h0, |
OP1_MPYS = 'h2, |
OP1_MAC = 'h4, |
OP1_MACS = 'h6, |
OP2 = 'h8, |
RESLO = 'hA, |
RESHI = 'hC, |
SUMEXT = 'hE; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter OP1_MPY_D = (512'h1 << OP1_MPY); |
parameter OP1_MPYS_D = (512'h1 << OP1_MPYS); |
parameter OP1_MAC_D = (512'h1 << OP1_MAC); |
parameter OP1_MACS_D = (512'h1 << OP1_MACS); |
parameter OP2_D = (512'h1 << OP2); |
parameter RESLO_D = (512'h1 << RESLO); |
parameter RESHI_D = (512'h1 << RESHI); |
parameter SUMEXT_D = (512'h1 << SUMEXT); |
parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY), |
OP1_MPYS_D = (BASE_REG << OP1_MPYS), |
OP1_MAC_D = (BASE_REG << OP1_MAC), |
OP1_MACS_D = (BASE_REG << OP1_MACS), |
OP2_D = (BASE_REG << OP2), |
RESLO_D = (BASE_REG << RESLO), |
RESHI_D = (BASE_REG << RESHI), |
SUMEXT_D = (BASE_REG << SUMEXT); |
|
|
// Wire pre-declarations |
105,28 → 114,29
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; |
|
// Register address decode |
reg [511:0] reg_dec; |
always @(per_addr) |
case ({per_addr,1'b0}) |
OP1_MPY : reg_dec = OP1_MPY_D; |
OP1_MPYS : reg_dec = OP1_MPYS_D; |
OP1_MAC : reg_dec = OP1_MAC_D; |
OP1_MACS : reg_dec = OP1_MACS_D; |
OP2 : reg_dec = OP2_D; |
RESLO : reg_dec = RESLO_D; |
RESHI : reg_dec = RESHI_D; |
SUMEXT : reg_dec = SUMEXT_D; |
default : reg_dec = {512{1'b0}}; |
endcase |
|
wire [DEC_SZ-1:0] reg_dec = (OP1_MPY_D & {DEC_SZ{(reg_addr == OP1_MPY )}}) | |
(OP1_MPYS_D & {DEC_SZ{(reg_addr == OP1_MPYS )}}) | |
(OP1_MAC_D & {DEC_SZ{(reg_addr == OP1_MAC )}}) | |
(OP1_MACS_D & {DEC_SZ{(reg_addr == OP1_MACS )}}) | |
(OP2_D & {DEC_SZ{(reg_addr == OP2 )}}) | |
(RESLO_D & {DEC_SZ{(reg_addr == RESLO )}}) | |
(RESHI_D & {DEC_SZ{(reg_addr == RESHI )}}) | |
(SUMEXT_D & {DEC_SZ{(reg_addr == SUMEXT )}}); |
|
// Read/Write probes |
wire reg_write = |per_we & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_write = |per_we & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [511:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [511:0] reg_rd = reg_dec & {512{reg_read}}; |
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
142,8 → 152,8
reg_wr[OP1_MAC] | |
reg_wr[OP1_MACS]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) op1 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) op1 <= 16'h0000; |
else if (op1_wr) op1 <= per_din; |
|
wire [15:0] op1_rd = op1; |
155,8 → 165,8
|
wire op2_wr = reg_wr[OP2]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) op2 <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) op2 <= 16'h0000; |
else if (op2_wr) op2 <= per_din; |
|
wire [15:0] op2_rd = op2; |
169,8 → 179,8
wire [15:0] reslo_nxt; |
wire reslo_wr = reg_wr[RESLO]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) reslo <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) reslo <= 16'h0000; |
else if (reslo_wr) reslo <= per_din; |
else if (result_clr) reslo <= 16'h0000; |
else if (result_wr) reslo <= reslo_nxt; |
185,8 → 195,8
wire [15:0] reshi_nxt; |
wire reshi_wr = reg_wr[RESHI]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) reshi <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) reshi <= 16'h0000; |
else if (reshi_wr) reshi <= per_din; |
else if (result_clr) reshi <= 16'h0000; |
else if (result_wr) reshi <= reshi_nxt; |
200,8 → 210,8
|
wire [1:0] sumext_s_nxt; |
|
always @ (posedge mclk or posedge puc) |
if (puc) sumext_s <= 2'b00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) sumext_s <= 2'b00; |
else if (op2_wr) sumext_s <= 2'b00; |
else if (result_wr) sumext_s <= sumext_s_nxt; |
|
240,15 → 250,15
|
// Detect signed mode |
reg sign_sel; |
always @ (posedge mclk or posedge puc) |
if (puc) sign_sel <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) sign_sel <= 1'b0; |
else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS]; |
|
|
// Detect accumulate mode |
reg acc_sel; |
always @ (posedge mclk or posedge puc) |
if (puc) acc_sel <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) acc_sel <= 1'b0; |
else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS]; |
|
|
265,9 → 275,9
|
// Detect start of a multiplication |
reg cycle; |
always @ (posedge mclk or posedge puc) |
if (puc) cycle <= 1'b0; |
else cycle <= op2_wr; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cycle <= 1'b0; |
else cycle <= op2_wr; |
|
assign result_wr = cycle; |
|
301,9 → 311,9
|
// Detect start of a multiplication |
reg [1:0] cycle; |
always @ (posedge mclk or posedge puc) |
if (puc) cycle <= 2'b00; |
else cycle <= {cycle[0], op2_wr}; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) cycle <= 2'b00; |
else cycle <= {cycle[0], op2_wr}; |
|
assign result_wr = |cycle; |
|
/verilog/omsp_dbg_uart.v
88,20 → 88,37
// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING |
//============================================================================= |
|
// Synchronize RXD input & buffer |
// Synchronize RXD input |
//-------------------------------- |
reg [3:0] rxd_sync; |
`ifdef SYNC_DBG_UART_RXD |
|
wire uart_rxd_n; |
|
omsp_sync_cell sync_cell_uart_rxd ( |
.data_out (uart_rxd_n), |
.clk (dbg_clk), |
.data_in (~dbg_uart_rxd), |
.rst (dbg_rst) |
); |
wire uart_rxd = ~uart_rxd_n; |
`else |
wire uart_rxd = dbg_uart_rxd; |
`endif |
|
// RXD input buffer |
//-------------------------------- |
reg [1:0] rxd_buf; |
always @ (posedge dbg_clk or posedge dbg_rst) |
if (dbg_rst) rxd_sync <= 4'hf; |
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd}; |
if (dbg_rst) rxd_buf <= 2'h3; |
else rxd_buf <= {rxd_buf[0], uart_rxd}; |
|
// Majority decision |
//------------------------ |
reg rxd_maj; |
|
wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} + |
{1'b0, rxd_sync[2]} + |
{1'b0, rxd_sync[3]}; |
wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd} + |
{1'b0, rxd_buf[0]} + |
{1'b0, rxd_buf[1]}; |
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10); |
|
always @ (posedge dbg_clk or posedge dbg_rst) |
/verilog/omsp_sfr.v
57,7 → 57,7
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
por, // Power-on reset |
puc, // Main system reset |
puc_rst, // Main system reset |
wdtifg_clr, // Clear Watchdog-timer interrupt flag |
wdtifg_set, // Set Watchdog-timer interrupt flag |
wdtpw_error, // Watchdog-timer password error |
76,12 → 76,12
//========= |
input mclk; // Main system clock |
input nmi_acc; // Non-Maskable interrupt request accepted |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input por; // Power-on reset |
input puc; // Main system reset |
input puc_rst; // Main system reset |
input wdtifg_clr; // Clear Watchdog-timer interrupt flag |
input wdtifg_set; // Set Watchdog-timer interrupt flag |
input wdtpw_error; // Watchdog-timer password error |
92,13 → 92,23
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter IE1 = 9'h000; |
parameter IFG1 = 9'h002; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0000; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 2; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] IE1 = 'h0, |
IFG1 = 'h2; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter IE1_D = (256'h1 << (IE1 /2)); |
parameter IFG1_D = (256'h1 << (IFG1 /2)); |
parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1), |
IFG1_D = (BASE_REG << IFG1); |
|
|
//============================================================================ |
105,24 → 115,25
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; |
|
// Register address decode |
reg [255:0] reg_dec; |
always @(per_addr) |
case (per_addr) |
(IE1 /2): reg_dec = IE1_D; |
(IFG1 /2): reg_dec = IFG1_D; |
default : reg_dec = {256{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) | |
(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}); |
|
// Read/Write probes |
wire reg_lo_write = per_we[0] & per_en; |
wire reg_hi_write = per_we[1] & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_lo_write = per_we[0] & reg_sel; |
wire reg_hi_write = per_we[1] & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; |
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; |
wire [255:0] reg_rd = reg_dec & {256{reg_read}}; |
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; |
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
132,19 → 143,19
// IE1 Register |
//-------------- |
wire [7:0] ie1; |
wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2]; |
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0]; |
wire ie1_wr = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1]; |
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0]; |
|
reg nmie; |
always @ (posedge mclk or posedge puc) |
if (puc) nmie <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) nmie <= 1'b0; |
else if (nmi_acc) nmie <= 1'b0; |
else if (ie1_wr) nmie <= ie1_nxt[4]; |
|
reg wdtie; |
always @ (posedge mclk or posedge puc) |
if (puc) wdtie <= 1'b0; |
else if (ie1_wr) wdtie <= ie1_nxt[0]; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) wdtie <= 1'b0; |
else if (ie1_wr) wdtie <= ie1_nxt[0]; |
|
assign ie1 = {3'b000, nmie, 3'b000, wdtie}; |
|
152,12 → 163,12
// IFG1 Register |
//--------------- |
wire [7:0] ifg1; |
wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2]; |
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0]; |
wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1]; |
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0]; |
|
reg nmiifg; |
always @ (posedge mclk or posedge puc) |
if (puc) nmiifg <= 1'b0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) nmiifg <= 1'b0; |
else if (nmi_acc) nmiifg <= 1'b1; |
else if (ifg1_wr) nmiifg <= ifg1_nxt[4]; |
|
176,8 → 187,8
//============================================================================ |
|
// Data output mux |
wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1/2]}})} << (8 & {4{IE1[0]}}); |
wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1/2]}})} << (8 & {4{IFG1[0]}}); |
wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}}); |
wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}}); |
|
wire [15:0] per_dout = ie1_rd | |
ifg1_rd; |
/verilog/omsp_dbg.v
72,7 → 72,7
fe_mb_en, // Frontend Memory bus enable |
fe_mdb_in, // Frontend Memory data bus input |
pc, // Program counter |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
107,7 → 107,7
input fe_mb_en; // Frontend Memory bus enable |
input [15:0] fe_mdb_in; // Frontend Memory data bus input |
input [15:0] pc; // Program counter |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
212,7 → 212,7
reg [1:0] puc_sync; |
always @ (posedge dbg_clk or posedge dbg_rst) |
if (dbg_rst) puc_sync <= 2'b11; |
else puc_sync <= {puc_sync[0] , puc}; |
else puc_sync <= {puc_sync[0] , puc_rst}; |
wire puc_s = puc_sync[1]; |
|
|
277,12 → 277,41
|
// CPU_ID Register |
//----------------- |
// ------------------------------------------------------------------- |
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 | |
// |----------------------------+-----------------+------+-------------| |
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION | |
// -------------------------------------------------------------------- |
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 | |
// |----------------------------+-------------------------------+------| |
// | PMEM_SIZE | DMEM_SIZE | MPY | |
// ------------------------------------------------------------------- |
|
wire [15:0] cpu_id_pmem = `PMEM_SIZE; |
wire [15:0] cpu_id_dmem = `DMEM_SIZE; |
wire [31:0] cpu_id = {cpu_id_pmem, cpu_id_dmem}; |
wire [2:0] cpu_version = `CPU_VERSION; |
`ifdef ASIC |
wire cpu_asic = 1'b1; |
`else |
wire cpu_asic = 1'b0; |
`endif |
wire [4:0] user_version = `USER_VERSION; |
wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size |
`ifdef MULTIPLIER |
wire mpy_info = 1'b1; |
`else |
wire mpy_info = 1'b0; |
`endif |
wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size |
wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size |
|
wire [31:0] cpu_id = {pmem_size, |
dmem_size, |
mpy_info, |
per_space, |
user_version, |
cpu_asic, |
cpu_version}; |
|
|
// CPU_CTL Register |
//----------------------------------------------------------------------------- |
// 7 6 5 4 3 2 1 0 |
/verilog/omsp_clock_module.v
55,7 → 55,7
mclk, // Main system clock |
per_dout, // Peripheral data output |
por, // Power-on reset |
puc, // Main system reset |
puc_rst, // Main system reset |
smclk_en, // SMCLK enable |
|
// INPUTs |
84,7 → 84,7
output mclk; // Main system clock |
output [15:0] per_dout; // Peripheral data output |
output por; // Power-on reset |
output puc; // Main system reset |
output puc_rst; // Main system reset |
output smclk_en; // SMCLK enable |
|
// INPUTs |
95,7 → 95,7
input dco_clk; // Fast oscillator (fast clock) |
input lfxt_clk; // Low frequency oscillator (typ 32kHz) |
input oscoff; // Turns off LFXT1 clock input |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
108,13 → 108,23
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter BCSCTL1 = 9'h057; |
parameter BCSCTL2 = 9'h058; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0050; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 4; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] BCSCTL1 = 'h7, |
BCSCTL2 = 'h8; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2)); |
parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2)); |
parameter [DEC_SZ-1:0] BCSCTL1_D = (BASE_REG << BCSCTL1), |
BCSCTL2_D = (BASE_REG << BCSCTL2); |
|
|
//============================================================================ |
121,24 → 131,25
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; |
|
// Register address decode |
reg [255:0] reg_dec; |
always @(per_addr) |
case (per_addr) |
(BCSCTL1 /2): reg_dec = BCSCTL1_D; |
(BCSCTL2 /2): reg_dec = BCSCTL2_D; |
default : reg_dec = {256{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (BCSCTL1_D & {DEC_SZ{(reg_addr==(BCSCTL1 >>1))}}) | |
(BCSCTL2_D & {DEC_SZ{(reg_addr==(BCSCTL2 >>1))}}); |
|
// Read/Write probes |
wire reg_lo_write = per_we[0] & per_en; |
wire reg_hi_write = per_we[1] & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_lo_write = per_we[0] & reg_sel; |
wire reg_hi_write = per_we[1] & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; |
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; |
wire [255:0] reg_rd = reg_dec & {256{reg_read}}; |
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; |
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
148,11 → 159,11
// BCSCTL1 Register |
//-------------- |
reg [7:0] bcsctl1; |
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2]; |
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; |
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1]; |
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) bcsctl1 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) bcsctl1 <= 8'h00; |
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits |
|
|
159,11 → 170,11
// BCSCTL2 Register |
//-------------- |
reg [7:0] bcsctl2; |
wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2]; |
wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0]; |
wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2] : reg_lo_wr[BCSCTL2]; |
wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) bcsctl2 <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) bcsctl2 <= 8'h00; |
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits |
|
|
172,8 → 183,8
//============================================================================ |
|
// Data output mux |
wire [15:0] bcsctl1_rd = {8'h00, (bcsctl1 & {8{reg_rd[BCSCTL1/2]}})} << (8 & {4{BCSCTL1[0]}}); |
wire [15:0] bcsctl2_rd = {8'h00, (bcsctl2 & {8{reg_rd[BCSCTL2/2]}})} << (8 & {4{BCSCTL2[0]}}); |
wire [15:0] bcsctl1_rd = {8'h00, (bcsctl1 & {8{reg_rd[BCSCTL1]}})} << (8 & {4{BCSCTL1[0]}}); |
wire [15:0] bcsctl2_rd = {8'h00, (bcsctl2 & {8{reg_rd[BCSCTL2]}})} << (8 & {4{BCSCTL2[0]}}); |
|
wire [15:0] per_dout = bcsctl1_rd | |
bcsctl2_rd; |
185,23 → 196,35
|
// Synchronize CPU_EN signal |
//--------------------------------------- |
reg [1:0] cpu_en_sync; |
always @ (posedge mclk or posedge por) |
if (por) cpu_en_sync <= 2'b00; |
else cpu_en_sync <= {cpu_en_sync[0], cpu_en}; |
`ifdef SYNC_CPU_EN |
omsp_sync_cell sync_cell_cpu_en ( |
.data_out (cpu_en_s), |
.clk (mclk), |
.data_in (cpu_en), |
.rst (por) |
); |
`else |
assign cpu_en_s = cpu_en; |
`endif |
|
assign cpu_en_s = cpu_en_sync[1]; |
|
|
// Synchronize LFXT_CLK & edge detection |
//--------------------------------------- |
reg [2:0] lfxt_clk_s; |
wire lfxt_clk_s; |
|
omsp_sync_cell sync_cell_lfxt_clk ( |
.data_out (lfxt_clk_s), |
.clk (mclk), |
.data_in (lfxt_clk), |
.rst (por) |
); |
|
reg lfxt_clk_dly; |
|
always @ (posedge mclk or posedge por) |
if (por) lfxt_clk_s <= 3'b000; |
else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk}; |
if (por) lfxt_clk_dly <= 1'b0; |
else lfxt_clk_dly <= lfxt_clk_s; |
|
wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]); |
wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & ~(oscoff & ~bcsctl2[`SELS]); |
|
|
// Generate main system clock |
222,12 → 245,12
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] : |
&aclk_div[2:0]); |
|
always @ (posedge mclk or posedge puc) |
if (puc) aclk_en <= 1'b0; |
else aclk_en <= aclk_en_nxt & cpu_en_s; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) aclk_en <= 1'b0; |
else aclk_en <= aclk_en_nxt & cpu_en_s; |
|
always @ (posedge mclk or posedge puc) |
if (puc) aclk_div <= 3'h0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) aclk_div <= 3'h0; |
else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1; |
|
|
244,12 → 267,12
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] : |
&smclk_div[2:0]); |
|
always @ (posedge mclk or posedge puc) |
if (puc) smclk_en <= 1'b0; |
else smclk_en <= smclk_en_nxt & cpu_en_s; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) smclk_en <= 1'b0; |
else smclk_en <= smclk_en_nxt & cpu_en_s; |
|
always @ (posedge mclk or posedge puc) |
if (puc) smclk_div <= 3'h0; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) smclk_div <= 3'h0; |
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1; |
|
|
264,38 → 287,48
//============================================================================= |
|
// Generate synchronized POR |
wire por_n; |
wire por_reset_a = !reset_n; |
|
reg [1:0] por_s; |
always @(posedge mclk or posedge por_reset_a) |
if (por_reset_a) por_s <= 2'b11; |
else por_s <= {por_s[0], 1'b0}; |
wire por = por_s[1]; |
omsp_sync_cell sync_cell_por ( |
.data_out (por_n), |
.clk (mclk), |
.data_in (1'b1), |
.rst (por_reset_a) |
); |
|
wire por = ~por_n; |
|
|
// Generate main system reset |
wire puc_reset = por | wdt_reset | dbg_cpu_reset; |
wire puc_rst_comb = por | wdt_reset | dbg_cpu_reset; |
reg puc_rst; |
always @(posedge mclk or posedge puc_rst_comb) |
if (puc_rst_comb) puc_rst <= 1'b1; |
else puc_rst <= 1'b0; |
|
reg [1:0] puc_s; |
always @(posedge mclk or posedge puc_reset) |
if (puc_reset) puc_s <= 2'b11; |
else puc_s <= {puc_s[0], 1'b0}; |
wire puc = puc_s[1]; |
|
|
// Generate debug unit reset |
`ifdef DBG_EN |
reg [1:0] dbg_rst_s; |
always @(posedge mclk or posedge por) |
if (por) dbg_rst_s <= 2'b11; |
else dbg_rst_s <= {dbg_rst_s[0], ~dbg_en}; |
`ifdef DBG_EN |
wire dbg_rst_n; |
|
`ifdef SYNC_DBG_EN |
omsp_sync_cell sync_cell_dbg_en ( |
.data_out (dbg_rst_n), |
.clk (mclk), |
.data_in (dbg_en), |
.rst (por) |
); |
`else |
assign dbg_rst_n = dbg_en; |
`endif |
|
`else |
wire [1:0] dbg_rst_s = 2'b11; |
wire dbg_rst_n = 1'b0; |
`endif |
|
wire dbg_en_s = ~dbg_rst_s[1]; |
wire dbg_rst = dbg_rst_s[1]; |
wire dbg_en_s = dbg_rst_n; |
wire dbg_rst = ~dbg_rst_n; |
|
|
endmodule // omsp_clock_module |
/verilog/omsp_watchdog.v
59,7 → 59,7
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_we, // Peripheral write enable (high active) |
puc, // Main system reset |
puc_rst, // Main system reset |
smclk_en, // SMCLK enable |
wdtie // Watchdog timer interrupt enable |
); |
79,11 → 79,11
input mclk; // Main system clock |
input nmi; // Non-maskable interrupt (asynchronous) |
input nmie; // Non-maskable interrupt enable |
input [7:0] per_addr; // Peripheral address |
input [13:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_we; // Peripheral write enable (high active) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
input smclk_en; // SMCLK enable |
input wdtie; // Watchdog timer interrupt enable |
|
92,12 → 92,21
// 1) PARAMETER DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter WDTCTL = 9'h120; |
// Register base address (must be aligned to decoder bit width) |
parameter [14:0] BASE_ADDR = 15'h0120; |
|
// Decoder bit width (defines how many bits are considered for address decoding) |
parameter DEC_WD = 2; |
|
// Register addresses offset |
parameter [DEC_WD-1:0] WDTCTL = 'h0; |
|
// Register one-hot decoder utilities |
parameter DEC_SZ = 2**DEC_WD; |
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; |
|
// Register one-hot decoder |
parameter WDTCTL_D = (512'h1 << WDTCTL); |
parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL); |
|
|
//============================================================================ |
104,21 → 113,22
// 2) REGISTER DECODER |
//============================================================================ |
|
// Local register selection |
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); |
|
// Register local address |
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; |
|
// Register address decode |
reg [511:0] reg_dec; |
always @(per_addr) |
case ({per_addr,1'b0}) |
WDTCTL : reg_dec = WDTCTL_D; |
default: reg_dec = {512{1'b0}}; |
endcase |
wire [DEC_SZ-1:0] reg_dec = (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}}); |
|
// Read/Write probes |
wire reg_write = |per_we & per_en; |
wire reg_read = ~|per_we & per_en; |
wire reg_write = |per_we & reg_sel; |
wire reg_read = ~|per_we & reg_sel; |
|
// Read/Write vectors |
wire [511:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [511:0] reg_rd = reg_dec & {512{reg_read}}; |
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; |
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; |
|
|
//============================================================================ |
133,8 → 143,8
|
wire wdtctl_wr = reg_wr[WDTCTL]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) wdtctl <= 8'h00; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) wdtctl <= 8'h00; |
else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7; |
|
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a); |
155,15 → 165,28
// 4) NMI GENERATION |
//============================================================================= |
|
// Synchronization state |
reg [2:0] nmi_sync; |
always @ (posedge mclk or posedge puc) |
if (puc) nmi_sync <= 3'h0; |
else nmi_sync <= {nmi_sync[1:0], nmi}; |
// Synchronization |
wire nmi_s; |
`ifdef SYNC_NMI |
omsp_sync_cell sync_cell_nmi ( |
.data_out (nmi_s), |
.clk (mclk), |
.data_in (nmi), |
.rst (puc_rst) |
); |
`else |
assign nmi_s = nmi; |
`endif |
|
// Delay |
reg nmi_dly; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) nmi_dly <= 1'b0; |
else nmi_dly <= nmi_s; |
|
// Edge detection |
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie; |
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie; |
wire nmi_re = ~nmi_dly & nmi_s & nmie; |
wire nmi_fe = nmi_dly & ~nmi_s & nmie; |
|
// NMI event |
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re; |
184,8 → 207,8
|
wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set; |
|
always @ (posedge mclk or posedge puc) |
if (puc) wdtcnt <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) wdtcnt <= 16'h0000; |
else if (wdtcnt_clr) wdtcnt <= 16'h0000; |
else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001; |
|
207,9 → 230,9
//----------------------------- |
reg wdtqn_dly; |
|
always @ (posedge mclk or posedge puc) |
if (puc) wdtqn_dly <= 1'b0; |
else wdtqn_dly <= wdtqn; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) wdtqn_dly <= 1'b0; |
else wdtqn_dly <= wdtqn; |
|
wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error; |
|
/verilog/omsp_execution_unit.v
78,7 → 78,7
mdb_in, // Memory data bus input |
pc, // Program counter |
pc_nxt, // Next PC value (for CALL & IRQ) |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
119,7 → 119,7
input [15:0] mdb_in; // Memory data bus input |
input [15:0] pc; // Program counter |
input [15:0] pc_nxt; // Next PC value (for CALL & IRQ) |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
190,7 → 190,7
.inst_src (inst_src), // Register source selection |
.mclk (mclk), // Main system clock |
.pc (pc), // Program counter |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.reg_dest_val (alu_out), // Selected register destination value |
.reg_dest_wr (reg_dest_wr), // Write selected register destination |
.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction |
337,8 → 337,8
|
// Memory data bus output |
reg [15:0] mdb_out_nxt; |
always @(posedge mclk or posedge puc) |
if (puc) mdb_out_nxt <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) mdb_out_nxt <= 16'h0000; |
else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt; |
else if ((e_state==`E_EXEC & ~inst_so[`CALL]) | |
(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out; |
347,8 → 347,8
|
// Format memory data bus input depending on BW |
reg mab_lsb; |
always @(posedge mclk or posedge puc) |
if (puc) mab_lsb <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) mab_lsb <= 1'b0; |
else if (mb_en) mab_lsb <= alu_out_add[0]; |
|
assign mdb_in_bw = ~inst_bw ? mdb_in : |
356,19 → 356,19
|
// Memory data bus input buffer (buffer after a source read) |
reg mdb_in_buf_en; |
always @(posedge mclk or posedge puc) |
if (puc) mdb_in_buf_en <= 1'b0; |
else mdb_in_buf_en <= (e_state==`E_SRC_RD); |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) mdb_in_buf_en <= 1'b0; |
else mdb_in_buf_en <= (e_state==`E_SRC_RD); |
|
reg mdb_in_buf_valid; |
always @(posedge mclk or posedge puc) |
if (puc) mdb_in_buf_valid <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) mdb_in_buf_valid <= 1'b0; |
else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0; |
else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1; |
|
reg [15:0] mdb_in_buf; |
always @(posedge mclk or posedge puc) |
if (puc) mdb_in_buf <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) mdb_in_buf <= 16'h0000; |
else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw; |
|
assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw; |
/verilog/omsp_mem_backbone.v
76,7 → 76,7
mclk, // Main system clock |
per_dout, // Peripheral data output |
pmem_dout, // Program Memory data output |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
89,7 → 89,7
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input |
output [15:0] fe_mdb_in; // Frontend Memory data bus input |
output fe_pmem_wait; // Frontend wait for Instruction fetch |
output [7:0] per_addr; // Peripheral address |
output [13:0] per_addr; // Peripheral address |
output [15:0] per_din; // Peripheral data input |
output [1:0] per_we; // Peripheral write enable (high active) |
output per_en; // Peripheral enable (high active) |
115,7 → 115,7
input mclk; // Main system clock |
input [15:0] per_dout; // Peripheral data output |
input [15:0] pmem_dout; // Program Memory data output |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
128,12 → 128,12
// Execution unit access |
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) & |
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1))); |
wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1); |
wire [15:0] eu_dmem_addr = {1'b0, eu_mab}-(`DMEM_BASE>>1); |
|
// Debug interface access |
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) & |
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1))); |
wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1); |
wire [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(`DMEM_BASE>>1); |
|
|
// RAM Interface |
157,7 → 157,7
|
// Debug interface access |
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1))); |
wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1); |
wire [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1); |
|
|
// ROM Interface (Execution unit has priority) |
172,17 → 172,19
|
// Peripherals |
//-------------------- |
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00); |
wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00); |
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:`PER_AWIDTH+1]=={15-`PER_AWIDTH{1'b0}}); |
wire eu_per_en = eu_mb_en & (eu_mab[14:`PER_AWIDTH] =={15-`PER_AWIDTH{1'b0}}); |
|
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0]; |
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out; |
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr; |
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en; |
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out; |
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr; |
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en; |
wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0]; |
wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1'b0}}, per_addr_mux}; |
wire [13:0] per_addr = per_addr_ful[13:0]; |
|
reg [15:0] per_dout_val; |
always @ (posedge mclk or posedge puc) |
if (puc) per_dout_val <= 16'h0000; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) per_dout_val <= 16'h0000; |
else per_dout_val <= per_dout; |
|
|
192,8 → 194,8
|
// Detect whenever the data should be backuped and restored |
reg fe_pmem_cen_dly; |
always @(posedge mclk or posedge puc) |
if (puc) fe_pmem_cen_dly <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) fe_pmem_cen_dly <= 1'b0; |
else fe_pmem_cen_dly <= fe_pmem_cen; |
|
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st; |
200,14 → 202,14
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st; |
|
reg [15:0] pmem_dout_bckup; |
always @(posedge mclk or posedge puc) |
if (puc) pmem_dout_bckup <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) pmem_dout_bckup <= 16'h0000; |
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout; |
|
// Mux between the ROM data and the backup |
reg pmem_dout_bckup_sel; |
always @(posedge mclk or posedge puc) |
if (puc) pmem_dout_bckup_sel <= 1'b0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) pmem_dout_bckup_sel <= 1'b0; |
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1; |
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0; |
|
219,9 → 221,9
|
// Select between peripherals, RAM and ROM |
reg [1:0] eu_mdb_in_sel; |
always @(posedge mclk or posedge puc) |
if (puc) eu_mdb_in_sel <= 2'b00; |
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en}; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) eu_mdb_in_sel <= 2'b00; |
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en}; |
|
// Mux |
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout : |
233,9 → 235,9
// Select between peripherals, RAM and ROM |
`ifdef DBG_EN |
reg [1:0] dbg_mem_din_sel; |
always @(posedge mclk or posedge puc) |
if (puc) dbg_mem_din_sel <= 2'b00; |
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en}; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) dbg_mem_din_sel <= 2'b00; |
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en}; |
|
`else |
wire [1:0] dbg_mem_din_sel = 2'b00; |
/verilog/openMSP430_defines.v
41,11 → 41,14
`include "openMSP430_undefines.v" |
`endif |
|
//---------------------------------------------------------------------------- |
// SYSTEM CONFIGURATION |
//---------------------------------------------------------------------------- |
//============================================================================ |
//============================================================================ |
// BASIC SYSTEM CONFIGURATION |
//============================================================================ |
//============================================================================ |
// |
// Note: the sum of both program and data memories should not exceed 63.5 kB |
// Note: the sum of program, data and peripheral memory spaces must not |
// exceed 64 kB |
// |
|
// Program Memory Size: |
66,6 → 69,7
`define PMEM_SIZE_2_KB |
//`define PMEM_SIZE_1_KB |
|
|
// Data Memory Size: |
// Uncomment the required memory size |
//------------------------------------------------------- |
83,45 → 87,129
//`define DMEM_SIZE_256_B |
`define DMEM_SIZE_128_B |
|
|
|
// Include/Exclude Hardware Multiplier |
`define MULTIPLIER |
|
|
//---------------------------------------------------------------------------- |
// REMOTE DEBUGGING INTERFACE CONFIGURATION |
//---------------------------------------------------------------------------- |
|
// Include Debug interface |
// Include/Exclude Serial Debug interface |
`define DBG_EN |
|
// Debug interface selection |
// `define DBG_UART -> Enable UART (8N1) debug interface |
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED |
// |
`define DBG_UART |
//`define DBG_JTAG |
|
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) |
// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 |
// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 |
// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 |
// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 |
//============================================================================ |
//============================================================================ |
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS) |
//============================================================================ |
//============================================================================ |
|
//------------------------------------------------------- |
// Peripheral Memory Space: |
//------------------------------------------------------- |
// The original MSP430 architecture map the peripherals |
// from 0x0000 to 0x01FF (i.e. 512B of the memory space). |
// The following defines allow you to expand this space |
// up to 32 kB (i.e. from 0x0000 to 0x7fff). |
// As a consequence, the data memory mapping will be |
// shifted up and a custom linker script will therefore |
// be required by the GCC compiler. |
//------------------------------------------------------- |
//`define PER_SIZE_32_KB |
//`define PER_SIZE_16_KB |
//`define PER_SIZE_8_KB |
//`define PER_SIZE_4_KB |
//`define PER_SIZE_2_KB |
//`define PER_SIZE_1_KB |
`define PER_SIZE_512_B |
|
|
//------------------------------------------------------- |
// Defines the debugger CPU_CTL.RST_BRK_EN reset value |
// (CPU break on PUC reset) |
//------------------------------------------------------- |
// When defined, the CPU will automatically break after |
// a PUC occurrence by default. This is typically usefull |
// when the program memory can only be initialized through |
// the serial debug interface. |
//------------------------------------------------------- |
//`define DBG_RST_BRK_EN |
|
|
//------------------------------------------------------- |
// Custom user version number |
//------------------------------------------------------- |
// This 5 bit field can be freely used in order to allow |
// custom identification of the system where the openMSP430 |
// is included through the debug interface. |
// (see CPU_ID.USER_VERSION field in the documentation) |
//------------------------------------------------------- |
`define USER_VERSION 5'b00000 |
|
|
//============================================================================ |
//============================================================================ |
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) |
//============================================================================ |
//============================================================================ |
// |
`define DBG_HWBRK_0 |
`define DBG_HWBRK_1 |
`define DBG_HWBRK_2 |
`define DBG_HWBRK_3 |
// IMPORTANT NOTE: Please update following configuration options ONLY if |
// you have a good reason to do so... and if you know what |
// you are doing :-P |
// |
//============================================================================ |
|
// Defines the debugger CPU_CTL.RST_BRK_EN reset value (CPU break on PUC reset) |
//------------------------------------------------------- |
// Number of hardware breakpoint units (each unit contains |
// two hardware address breakpoints): |
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0 |
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1 |
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2 |
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3 |
//------------------------------------------------------- |
// Please keep in mind that hardware breakpoints only |
// make sense whenever the program memory is not an SRAM |
// (i.e. Flash/OTP/ROM/...) or when you are interested |
// in data breakpoints (btw. not supported by GDB). |
//------------------------------------------------------- |
//`define DBG_HWBRK_0 |
//`define DBG_HWBRK_1 |
//`define DBG_HWBRK_2 |
//`define DBG_HWBRK_3 |
|
|
//------------------------------------------------------- |
// Enable/Disable the hardware breakpoint RANGE mode |
//------------------------------------------------------- |
// When enabled this feature allows the hardware breakpoint |
// units to stop the cpu whenever an instruction or data |
// access lays within an address range. |
// Note that this feature is not supported by GDB. |
//------------------------------------------------------- |
//`define DBG_HWBRK_RANGE |
|
|
//------------------------------------------------------- |
// Input synchronizers |
//------------------------------------------------------- |
// In some cases, the asynchronous input ports might |
// already be synchronized externally. |
// If an extensive CDC design review showed that this |
// is really the case, the individual synchronizers |
// can be disabled with the following defines. |
// |
// When defined, this concretely bring the CPU to break after a PUC |
// occurrence by default. This is typically usefull when the program |
// memory can only be initialized through the serial debug interface. |
// Notes: |
// - the dbg_en signal will reset the debug interface |
// when 0. Therefore make sure it is glitch free. |
// |
//`define DBG_RST_BRK_EN |
// - the dbg_uart_rxd synchronizer must be set to 1 |
// when its reset is active. |
//------------------------------------------------------- |
`define SYNC_CPU_EN |
`define SYNC_DBG_EN |
`define SYNC_DBG_UART_RXD |
`define SYNC_NMI |
|
|
|
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
133,8 → 221,8
//==========================================================================// |
|
// |
// PROGRAM & DATA MEMORY CONFIGURATION |
//====================================== |
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION |
//================================================== |
|
// Program Memory Size |
`ifdef PMEM_SIZE_59_KB |
248,12 → 336,43
`define DMEM_SIZE 128 |
`endif |
|
// Peripheral Memory Size |
`ifdef PER_SIZE_32_KB |
`define PER_AWIDTH 14 |
`define PER_SIZE 32768 |
`endif |
`ifdef PER_SIZE_16_KB |
`define PER_AWIDTH 13 |
`define PER_SIZE 16384 |
`endif |
`ifdef PER_SIZE_8_KB |
`define PER_AWIDTH 12 |
`define PER_SIZE 8192 |
`endif |
`ifdef PER_SIZE_4_KB |
`define PER_AWIDTH 11 |
`define PER_SIZE 4096 |
`endif |
`ifdef PER_SIZE_2_KB |
`define PER_AWIDTH 10 |
`define PER_SIZE 2048 |
`endif |
`ifdef PER_SIZE_1_KB |
`define PER_AWIDTH 9 |
`define PER_SIZE 1024 |
`endif |
`ifdef PER_SIZE_512_B |
`define PER_AWIDTH 8 |
`define PER_SIZE 512 |
`endif |
|
// Data Memory Base Adresses |
`define DMEM_BASE 16'h0200 |
`define DMEM_BASE `PER_SIZE |
|
// Program & Data Memory most significant address bit (for 16 bit words) |
`define PMEM_MSB `PMEM_AWIDTH-1 |
`define DMEM_MSB `DMEM_AWIDTH-1 |
`define PER_MSB `PER_AWIDTH-1 |
|
// |
// STATES, REGISTER FIELDS, ... |
308,21 → 427,29
`define ABS 6 |
`define CONST 7 |
|
// Instruction state machine |
`define I_IRQ_FETCH 3'h0 |
`define I_IRQ_DONE 3'h1 |
`define I_DEC 3'h2 |
`define I_EXT1 3'h3 |
`define I_EXT2 3'h4 |
`define I_IDLE 3'h5 |
|
// Execution state machine |
`define E_IRQ_0 4'h0 |
`define E_IRQ_1 4'h1 |
`define E_IRQ_2 4'h2 |
`define E_IRQ_3 4'h3 |
`define E_IRQ_4 4'h4 |
`define E_SRC_AD 4'h5 |
`define E_SRC_RD 4'h6 |
`define E_SRC_WR 4'h7 |
`define E_DST_AD 4'h8 |
`define E_DST_RD 4'h9 |
`define E_DST_WR 4'hA |
`define E_EXEC 4'hB |
`define E_JUMP 4'hC |
`define E_IDLE 4'hD |
`define E_IRQ_0 4'h0 |
`define E_IRQ_1 4'h1 |
`define E_IRQ_2 4'h2 |
`define E_IRQ_3 4'h3 |
`define E_IRQ_4 4'h4 |
`define E_SRC_AD 4'h5 |
`define E_SRC_RD 4'h6 |
`define E_SRC_WR 4'h7 |
`define E_DST_AD 4'h8 |
`define E_DST_RD 4'h9 |
`define E_DST_WR 4'hA |
`define E_EXEC 4'hB |
`define E_JUMP 4'hC |
`define E_IDLE 4'hD |
|
// ALU control signals |
`define ALU_SRC_INV 0 |
379,6 → 506,9
// DEBUG INTERFACE EXTRA CONFIGURATION |
//====================================== |
|
// Debug interface: CPU version |
`define CPU_VERSION 3'h1 |
|
// Debug interface: Software breakpoint opcode |
`define DBG_SWBRK_OP 16'h4343 |
|
406,8 → 536,19
`define DBG_DCO_FREQ 20000000 |
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) |
|
// Debug interface selection |
// `define DBG_UART -> Enable UART (8N1) debug interface |
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED |
// |
`define DBG_UART |
//`define DBG_JTAG |
|
// Enable/Disable the hardware breakpoint RANGE mode |
`define HWBRK_RANGE 1'b0 |
`ifdef DBG_HWBRK_RANGE |
`define HWBRK_RANGE 1'b1 |
`else |
`define HWBRK_RANGE 1'b0 |
`endif |
|
// Counter width for the debug interface UART |
`define DBG_UART_XFER_CNT_W 16 |
/verilog/openMSP430.v
60,7 → 60,7
pmem_cen, // Program Memory chip enable (low active) |
pmem_din, // Program Memory data input (optional) |
pmem_wen, // Program Memory write enable (low active) (optional) |
puc, // Main system reset |
puc_rst, // Main system reset |
smclk_en, // SMCLK enable |
|
// INPUTs |
88,7 → 88,7
output [1:0] dmem_wen; // Data Memory write enable (low active) |
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) |
output mclk; // Main system clock |
output [7:0] per_addr; // Peripheral address |
output [13:0] per_addr; // Peripheral address |
output [15:0] per_din; // Peripheral data input |
output [1:0] per_we; // Peripheral write enable (high active) |
output per_en; // Peripheral enable (high active) |
96,7 → 96,7
output pmem_cen; // Program Memory chip enable (low active) |
output [15:0] pmem_din; // Program Memory data input (optional) |
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional) |
output puc; // Main system reset |
output puc_rst; // Main system reset |
output smclk_en; // SMCLK enable |
|
|
124,6 → 124,8
wire [7:0] inst_as; |
wire [11:0] inst_alu; |
wire inst_bw; |
wire inst_irq_rst; |
wire inst_mov; |
wire [15:0] inst_dest; |
wire [15:0] inst_dext; |
wire [15:0] inst_sext; |
130,21 → 132,47
wire [7:0] inst_so; |
wire [15:0] inst_src; |
wire [2:0] inst_type; |
wire [7:0] inst_jmp; |
wire [3:0] e_state; |
wire exec_done; |
wire decode_noirq; |
wire cpu_en_s; |
wire cpuoff; |
wire oscoff; |
wire scg1; |
wire por; |
wire gie; |
|
wire [15:0] eu_mab; |
wire [15:0] eu_mdb_in; |
wire [15:0] eu_mdb_out; |
wire [1:0] eu_mb_wr; |
wire eu_mb_en; |
wire [15:0] fe_mab; |
wire [15:0] fe_mdb_in; |
wire fe_mb_en; |
wire fe_pmem_wait; |
|
wire pc_sw_wr; |
wire [15:0] pc_sw; |
wire [7:0] inst_jmp; |
wire [15:0] pc; |
wire [15:0] pc_nxt; |
|
wire nmie; |
wire nmi_acc; |
wire nmi_evt; |
|
wire wdtie; |
wire wdtifg_set; |
wire wdtpw_error; |
wire wdttmsel; |
wire wdt_irq; |
wire wdt_reset; |
|
wire dbg_clk; |
wire dbg_rst; |
wire dbg_en_s; |
wire dbg_halt_st; |
wire dbg_halt_cmd; |
wire dbg_mem_en; |
wire dbg_reg_wr; |
177,7 → 205,7
.mclk (mclk), // Main system clock |
.per_dout (per_dout_clk), // Peripheral data output |
.por (por), // Power-on reset |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.smclk_en (smclk_en), // SMCLK enable |
|
// INPUTs |
241,7 → 269,7
.nmi_evt (nmi_evt), // Non-maskable interrupt event |
.pc_sw (pc_sw), // Program counter software value |
.pc_sw_wr (pc_sw_wr), // Program counter software write |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.wdt_irq (wdt_irq) // Watchdog-timer interrupt |
); |
|
288,7 → 316,7
.mdb_in (eu_mdb_in), // Memory data bus input |
.pc (pc), // Program counter |
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
|
332,7 → 360,7
.mclk (mclk), // Main system clock |
.per_dout (per_dout_or), // Peripheral data output |
.pmem_dout (pmem_dout), // Program Memory data output |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
|
357,7 → 385,7
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.por (por), // Power-on reset |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag |
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag |
.wdtpw_error (wdtpw_error), // Watchdog-timer password error |
388,7 → 416,7
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.smclk_en (smclk_en), // SMCLK enable |
.wdtie (wdtie) // Watchdog-timer interrupt enable |
); |
409,7 → 437,7
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
`else |
assign per_dout_mpy = 16'h0000; |
463,7 → 491,7
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input |
.pc (pc), // Program counter |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
`else |
/verilog/openMSP430_undefines.v
37,72 → 37,10
//---------------------------------------------------------------------------- |
|
//---------------------------------------------------------------------------- |
// SYSTEM CONFIGURATION |
// BASIC SYSTEM CONFIGURATION |
//---------------------------------------------------------------------------- |
|
// Program Memory Size: |
`ifdef PMEM_AWIDTH |
`undef PMEM_AWIDTH |
`endif |
|
// Data Memory Size: |
`ifdef DMEM_AWIDTH |
`undef DMEM_AWIDTH |
`endif |
|
// Include/Exclude Hardware Multiplier |
`ifdef MULTIPLIER |
`undef MULTIPLIER |
`endif |
|
//---------------------------------------------------------------------------- |
// REMOTE DEBUGGING INTERFACE CONFIGURATION |
//---------------------------------------------------------------------------- |
|
// Include Debug interface |
`ifdef DBG_EN |
`undef DBG_EN |
`endif |
|
// Debug interface selection |
`ifdef DBG_UART |
`undef DBG_UART |
`endif |
`ifdef DBG_JTAG |
`undef DBG_JTAG |
`endif |
|
// Number of hardware breakpoints |
`ifdef DBG_HWBRK_0 |
`undef DBG_HWBRK_0 |
`endif |
`ifdef DBG_HWBRK_1 |
`undef DBG_HWBRK_1 |
`endif |
`ifdef DBG_HWBRK_2 |
`undef DBG_HWBRK_2 |
`endif |
`ifdef DBG_HWBRK_3 |
`undef DBG_HWBRK_3 |
`endif |
|
// Let the CPU break after a PUC occurrence by default |
`ifdef DBG_RST_BRK_EN |
`undef DBG_RST_BRK_EN |
`endif |
|
|
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
|
// Program and Data Memory sizes |
// Program Memory sizes |
`ifdef PMEM_SIZE_59_KB |
`undef PMEM_SIZE_59_KB |
`endif |
145,6 → 83,8
`ifdef PMEM_SIZE_1_KB |
`undef PMEM_SIZE_1_KB |
`endif |
|
// Data Memory sizes |
`ifdef DMEM_SIZE_32_KB |
`undef DMEM_SIZE_32_KB |
`endif |
184,19 → 124,128
`ifdef DMEM_SIZE_128_B |
`undef DMEM_SIZE_128_B |
`endif |
`ifdef PMEM_SIZE |
`undef PMEM_SIZE |
|
// Include/Exclude Hardware Multiplier |
`ifdef MULTIPLIER |
`undef MULTIPLIER |
`endif |
|
// Include Debug interface |
`ifdef DBG_EN |
`undef DBG_EN |
`endif |
|
|
//---------------------------------------------------------------------------- |
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS) |
//---------------------------------------------------------------------------- |
|
// Peripheral Memory Space: |
`ifdef PER_SIZE_32_KB |
`undef PER_SIZE_32_KB |
`endif |
`ifdef PER_SIZE_16_KB |
`undef PER_SIZE_16_KB |
`endif |
`ifdef PER_SIZE_8_KB |
`undef PER_SIZE_8_KB |
`endif |
`ifdef PER_SIZE_4_KB |
`undef PER_SIZE_4_KB |
`endif |
`ifdef PER_SIZE_2_KB |
`undef PER_SIZE_2_KB |
`endif |
`ifdef PER_SIZE_1_KB |
`undef PER_SIZE_1_KB |
`endif |
`ifdef PER_SIZE_512_B |
`undef PER_SIZE_512_B |
`endif |
|
// Let the CPU break after a PUC occurrence by default |
`ifdef DBG_RST_BRK_EN |
`undef DBG_RST_BRK_EN |
`endif |
|
// Custom user version number |
`ifdef USER_VERSION |
`undef USER_VERSION |
`endif |
|
|
//---------------------------------------------------------------------------- |
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) |
//---------------------------------------------------------------------------- |
|
// Number of hardware breakpoint units |
`ifdef DBG_HWBRK_0 |
`undef DBG_HWBRK_0 |
`endif |
`ifdef DBG_HWBRK_1 |
`undef DBG_HWBRK_1 |
`endif |
`ifdef DBG_HWBRK_2 |
`undef DBG_HWBRK_2 |
`endif |
`ifdef DBG_HWBRK_3 |
`undef DBG_HWBRK_3 |
`endif |
|
// Enable/Disable the hardware breakpoint RANGE mode |
`ifdef DBG_HWBRK_RANGE |
`undef DBG_HWBRK_RANGE |
`endif |
|
// Input synchronizers |
`ifdef SYNC_CPU_EN |
`undef SYNC_CPU_EN |
`endif |
`ifdef SYNC_DBG_EN |
`undef SYNC_DBG_EN |
`endif |
`ifdef SYNC_DBG_UART_RXD |
`undef SYNC_DBG_UART_RXD |
`endif |
`ifdef SYNC_NMI |
`undef SYNC_NMI |
`endif |
|
|
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
//==========================================================================// |
|
// Program Memory Size |
`ifdef PMEM_AWIDTH |
`undef PMEM_AWIDTH |
`endif |
`ifdef DMEM_SIZE |
`undef DMEM_SIZE |
`ifdef PMEM_SIZE |
`undef PMEM_SIZE |
`endif |
|
// Data Memory Size |
`ifdef DMEM_AWIDTH |
`undef DMEM_AWIDTH |
`endif |
`ifdef DMEM_SIZE |
`undef DMEM_SIZE |
`endif |
|
// Peripheral Memory Size |
`ifdef PER_AWIDTH |
`undef PER_AWIDTH |
`endif |
`ifdef PER_SIZE |
`undef PER_SIZE |
`endif |
|
// Data Memory Base Adresses |
`ifdef DMEM_BASE |
`undef DMEM_BASE |
209,8 → 258,10
`ifdef DMEM_MSB |
`undef DMEM_MSB |
`endif |
`ifdef PER_MSB |
`undef PER_MSB |
`endif |
|
|
// Instructions type |
`ifdef INST_SO |
`undef INST_SO |
338,6 → 389,26
`undef CONST |
`endif |
|
// Instruction state machine |
`ifdef I_IRQ_FETCH |
`undef I_IRQ_FETCH |
`endif |
`ifdef I_IRQ_DONE |
`undef I_IRQ_DONE |
`endif |
`ifdef I_DEC |
`undef I_DEC |
`endif |
`ifdef I_EXT1 |
`undef I_EXT1 |
`endif |
`ifdef I_EXT2 |
`undef I_EXT2 |
`endif |
`ifdef I_IDLE |
`undef I_IDLE |
`endif |
|
// Execution state machine |
`ifdef E_IRQ_0 |
`undef E_IRQ_0 |
509,6 → 580,11
// DEBUG INTERFACE EXTRA CONFIGURATION |
//====================================== |
|
// Debug interface: CPU version |
`ifdef CPU_VERSION |
`undef CPU_VERSION |
`endif |
|
// Debug interface: Software breakpoint opcode |
`ifdef DBG_SWBRK_OP |
`undef DBG_SWBRK_OP |
530,6 → 606,14
`undef DBG_UART_CNT |
`endif |
|
// Debug interface selection |
`ifdef DBG_UART |
`undef DBG_UART |
`endif |
`ifdef DBG_JTAG |
`undef DBG_JTAG |
`endif |
|
// Enable/Disable the hardware breakpoint RANGE mode |
`ifdef HWBRK_RANGE |
`undef HWBRK_RANGE |
/verilog/omsp_sync_cell.v
0,0 → 1,75
//---------------------------------------------------------------------------- |
// Copyright (C) 2001 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//---------------------------------------------------------------------------- |
// |
// *File Name: omsp_sync_cell.v |
// |
// *Module Description: |
// Generic synchronizer for the openMSP430 |
// |
// *Author(s): |
// - Olivier Girard, olgirard@gmail.com |
// |
//---------------------------------------------------------------------------- |
// $Rev: 103 $ |
// $LastChangedBy: olivier.girard $ |
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ |
//---------------------------------------------------------------------------- |
|
module omsp_sync_cell ( |
|
// OUTPUTs |
data_out, // Synchronized data output |
|
// INPUTs |
clk, // Receiving clock |
data_in, // Asynchronous data input |
rst // Receiving reset (active high) |
); |
|
// OUTPUTs |
//========= |
output data_out; // Synchronized data output |
|
// INPUTs |
//========= |
input clk; // Receiving clock |
input data_in; // Asynchronous data input |
input rst; // Receiving reset (active high) |
|
|
//============================================================================= |
// 1) SYNCHRONIZER |
//============================================================================= |
|
reg [1:0] data_sync; |
|
always @(posedge clk or posedge rst) |
if (rst) data_sync <= 2'b00; |
else data_sync <= {data_sync[0], data_in}; |
|
assign data_out = data_sync[1]; |
|
|
endmodule // omsp_sync_cell |
|
verilog/omsp_sync_cell.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property