URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/rtl
- from Rev 72 to Rev 74
- ↔ Reverse comparison
Rev 72 → Rev 74
/verilog/omsp_dbg_uart.v
182,14 → 182,14
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`ifdef DBG_UART_AUTO_SYNC |
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reg [14:0] sync_cnt; |
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt; |
always @ (posedge mclk or posedge por) |
if (por) sync_cnt <= 15'h7ff8; |
else if (sync_busy) sync_cnt <= sync_cnt+15'h0001; |
if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000}; |
else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1}; |
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wire [11:0] bit_cnt_max = sync_cnt[14:3]; |
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3]; |
`else |
wire [11:0] bit_cnt_max = `DBG_UART_CNT; |
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT; |
`endif |
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199,12 → 199,12
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// Transfer counter |
//------------------------ |
reg [3:0] xfer_bit; |
reg [11:0] xfer_cnt; |
reg [3:0] xfer_bit; |
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt; |
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1)); |
wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC)); |
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000); |
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}}); |
assign xfer_done = (xfer_bit==4'hb); |
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always @ (posedge mclk or posedge por) |
214,10 → 214,10
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1; |
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always @ (posedge mclk or posedge por) |
if (por) xfer_cnt <= 12'h000; |
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]}; |
if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}}; |
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]}; |
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max; |
else xfer_cnt <= xfer_cnt+12'hfff; |
else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}}; |
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// Receive/Transmit buffer |
/verilog/omsp_dbg.v
265,9 → 265,9
// CPU_ID Register |
//----------------- |
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wire [3:0] cpu_id_pmem = `PMEM_AWIDTH; |
wire [3:0] cpu_id_dmem = `DMEM_AWIDTH; |
wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem}; |
wire [15:0] cpu_id_pmem = `PMEM_SIZE; |
wire [15:0] cpu_id_dmem = `DMEM_SIZE; |
wire [31:0] cpu_id = {cpu_id_pmem, cpu_id_dmem}; |
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// CPU_CTL Register |
/verilog/openMSP430_defines.v
391,9 → 391,6
// Debug interface: Software breakpoint opcode |
`define DBG_SWBRK_OP 16'h4343 |
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// Debug interface ID |
`define DBG_ID 24'h4D5350 |
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// Debug UART interface auto data synchronization |
// If the following define is commented out, then |
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly |
421,6 → 418,9
// Enable/Disable the hardware breakpoint RANGE mode |
`define HWBRK_RANGE 1'b0 |
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// Counter width for the debug interface UART |
`define DBG_UART_XFER_CNT_W 16 |
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// Check configuration |
`ifdef DBG_EN |
`ifdef DBG_UART |
/verilog/openMSP430_undefines.v
563,11 → 563,6
`undef DBG_SWBRK_OP |
`endif |
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// Debug interface ID |
`ifdef DBG_ID |
`undef DBG_ID |
`endif |
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// Debug UART interface auto data synchronization |
`ifdef DBG_UART_AUTO_SYNC |
`undef DBG_UART_AUTO_SYNC |
589,6 → 584,11
`undef HWBRK_RANGE |
`endif |
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// Counter width for the debug interface UART |
`ifdef DBG_UART_XFER_CNT_W |
`undef DBG_UART_XFER_CNT_W |
`endif |
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// |
// MULTIPLIER CONFIGURATION |
//====================================== |