OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim/src
    from Rev 55 to Rev 58
    ↔ Reverse comparison
  •

Rev 55 → Rev 58

/dbg_hwbrk3.v
109,6 → 109,8
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
//----------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
133,7 → 135,7
dbg_uart_wr(BRK3_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
 
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
390,6 → 392,8
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
//----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
430,10 → 434,13
dbg_uart_wr(BRK3_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
//-----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
450,15 → 457,15
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
465,15 → 472,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
480,15 → 487,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
495,15 → 502,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
510,19 → 517,22
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
//----------------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
624,6 → 634,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
end
 
// RE-RUN UNTIL END OF PATTERN
dbg_uart_wr(BRK3_CTL, 16'h0000);
/dbg_hwbrk0.v
109,7 → 109,9
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
//----------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
dbg_uart_wr(CPU_CTL, 16'h0020);
133,8 → 135,8
dbg_uart_wr(BRK0_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
//----------------------------------------------------------------------------
194,7 → 196,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 =====");
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
//-----------------------------------------------------------------------------
 
283,7 → 285,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
 
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE
//----------------------------------------------------------------------------------
 
390,6 → 392,8
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
//----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
430,10 → 434,13
dbg_uart_wr(BRK0_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
//-----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
450,15 → 457,15
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
465,15 → 472,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
480,15 → 487,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
495,15 → 502,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
510,19 → 517,22
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
 
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
//----------------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
624,6 → 634,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
end
 
// RE-RUN UNTIL END OF PATTERN
dbg_uart_wr(BRK0_CTL, 16'h0000);
/dbg_hwbrk2.v
109,7 → 109,9
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
//----------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
dbg_uart_wr(CPU_CTL, 16'h0020);
133,7 → 135,7
dbg_uart_wr(BRK2_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
 
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
390,6 → 392,8
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
//----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
430,11 → 434,15
dbg_uart_wr(BRK2_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
//-----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
dbg_uart_wr(CPU_CTL, 16'h0020);
450,15 → 458,15
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
465,15 → 473,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
480,15 → 488,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
495,15 → 503,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
510,19 → 518,22
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
end
 
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
//----------------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
624,6 → 635,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
end
 
// RE-RUN UNTIL END OF PATTERN
dbg_uart_wr(BRK2_CTL, 16'h0000);
/dbg_uart.v
126,7 → 126,14
 
dbg_uart_wr(BRK0_CTL , 16'hffff);
dbg_uart_rd(BRK0_CTL);
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
if (`HWBRK_RANGE)
begin
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
end
else
begin
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect =====");
end
dbg_uart_wr(BRK0_CTL , 16'h0000);
dbg_uart_rd(BRK0_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");
158,7 → 165,14
 
dbg_uart_wr(BRK1_CTL , 16'hffff);
dbg_uart_rd(BRK1_CTL);
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
if (`HWBRK_RANGE)
begin
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
end
else
begin
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect =====");
end
dbg_uart_wr(BRK1_CTL , 16'h0000);
dbg_uart_rd(BRK1_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");
190,7 → 204,14
 
dbg_uart_wr(BRK2_CTL , 16'hffff);
dbg_uart_rd(BRK2_CTL);
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
if (`HWBRK_RANGE)
begin
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
end
else
begin
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect =====");
end
dbg_uart_wr(BRK2_CTL , 16'h0000);
dbg_uart_rd(BRK2_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");
222,7 → 243,14
 
dbg_uart_wr(BRK3_CTL , 16'hffff);
dbg_uart_rd(BRK3_CTL);
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
if (`HWBRK_RANGE)
begin
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
end
else
begin
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect =====");
end
dbg_uart_wr(BRK3_CTL , 16'h0000);
dbg_uart_rd(BRK3_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");
/dbg_hwbrk1.v
109,6 → 109,8
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
//----------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
133,7 → 135,7
dbg_uart_wr(BRK1_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
 
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
390,6 → 392,8
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
//----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
430,10 → 434,13
dbg_uart_wr(BRK1_STAT, 16'h0010);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
 
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
//-----------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
450,15 → 457,15
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
if (r0 !== 16'hf836) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
465,15 → 472,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
if (r0 !== 16'hf83a) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
480,15 → 487,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
495,15 → 502,15
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
if (r0 !== 16'hf80C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
 
// RE-RUN
dbg_uart_wr(CPU_CTL, 16'h0002);
510,19 → 517,21
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
if (r0 !== 16'hf808) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
 
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
end
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
//----------------------------------------------------------------------------------
if (`HWBRK_RANGE)
begin
 
// RESET, BREAK & CLEAR STATUS
dbg_uart_wr(CPU_CTL, 16'h0060);
624,6 → 633,7
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
end
 
// RE-RUN UNTIL END OF PATTERN
dbg_uart_wr(BRK1_CTL, 16'h0000);

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