OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openmsp430/trunk/core/sim/rtl_sim/src
    from Rev 74 to Rev 79
    Reverse comparison

Rev 74 → Rev 79

/gpio_rdwr.s43
290,6 → 290,7
/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0200, r15 ;# Test Input path
nop
p1_din_loop:
mov.b &P1IN, 0(r15)
inc r15
332,6 → 333,7
/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0210, r15 ;# Test Input path
nop
p2_din_loop:
mov.b &P2IN, 0(r15)
inc r15
374,6 → 376,7
/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0220, r15 ;# Test Input path
nop
p3_din_loop:
mov.b &P3IN, 0(r15)
inc r15
416,6 → 419,7
/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0230, r15 ;# Test Input path
nop
p4_din_loop:
mov.b &P4IN, 0(r15)
inc r15
458,6 → 462,7
/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0240, r15 ;# Test Input path
nop
p5_din_loop:
mov.b &P5IN, 0(r15)
inc r15
500,6 → 505,7
/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0250, r15 ;# Test Input path
nop
p6_din_loop:
mov.b &P6IN, 0(r15)
inc r15
/op_modes.v
161,8 → 161,8
@(negedge mclk);
inst_cnt = 0;
repeat (80) @(negedge mclk);
if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
 
if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
@(r1==16'h0250);
repeat (3) @(negedge mclk);
inst_cnt = 0;
176,7 → 176,7
@(negedge mclk);
inst_cnt = 0;
repeat (80) @(negedge mclk);
if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
 
@(r15==16'h3003);
@(negedge mclk);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.