URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/sim/rtl_sim
- from Rev 103 to Rev 105
- ↔ Reverse comparison
Rev 103 → Rev 105
/src/submit.f
34,6 → 34,16
//============================================================================= |
|
//============================================================================= |
// Testbench related |
//============================================================================= |
|
+incdir+../../../bench/verilog/ |
../../../bench/verilog/tb_openMSP430.v |
../../../bench/verilog/ram.v |
../../../bench/verilog/msp_debug.v |
|
|
//============================================================================= |
// Module specific modules |
//============================================================================= |
+incdir+../../../rtl/verilog/ |
55,13 → 65,3
../../../rtl/verilog/periph/omsp_timerA.v |
../../../rtl/verilog/periph/template_periph_8b.v |
../../../rtl/verilog/periph/template_periph_16b.v |
|
|
//============================================================================= |
// Testbench related |
//============================================================================= |
|
+incdir+../../../bench/verilog/ |
../../../bench/verilog/tb_openMSP430.v |
../../../bench/verilog/ram.v |
../../../bench/verilog/msp_debug.v |