URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/sim
- from Rev 128 to Rev 134
- ↔ Reverse comparison
Rev 128 → Rev 134
/rtl_sim/run/run_all_mpy
4,7 → 4,20
OMSP_NODUMP=1 |
export OMSP_NODUMP |
|
rm -rf *.log |
# Choose simulator: |
# - iverilog : Icarus Verilog (default) |
# - cver : CVer |
# - verilog : Verilog-XL |
# - ncverilog : NC-Verilog |
# - vcs : VCS |
# - vsim : Modelsim |
# - isim : Xilinx simulator |
OMSP_SIMULATOR=iverilog |
export OMSP_SIMULATOR |
|
rm -rf ./log/*.log |
mkdir ./log |
|
echo "" |
echo " ====================================================" |
echo "| WARNING: Complete Hardware Multiplier verification |" |
13,22 → 26,25
echo "" |
|
# Hardware multiplier test patterns |
../bin/msp430sim mpy_basic | tee mpy_basic.log |
../bin/msp430sim mpy_mpy | tee mpy_mpy.log |
../bin/msp430sim mpy_mpys | tee mpy_mpys.log |
../bin/msp430sim mpy_mac | tee mpy_mac.log |
../bin/msp430sim mpy_macs | tee mpy_macs.log |
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log |
../bin/msp430sim mpy_mpy | tee ./log/mpy_mpy.log |
../bin/msp430sim mpy_mpys | tee ./log/mpy_mpys.log |
../bin/msp430sim mpy_mac | tee ./log/mpy_mac.log |
../bin/msp430sim mpy_macs | tee ./log/mpy_macs.log |
|
grep FAILED *.log |
grep SKIPPED ./log/*.log |
grep FAILED ./log/*.log |
echo "" |
echo " ================================" |
echo -n "| Number of passed patterns: " |
cat *.log | grep -c PASSED |
echo -n "| Number of failed patterns: " |
cat *.log | grep -c FAILED |
echo -n "| Number of passed patterns : " |
cat ./log/*.log | grep -c PASSED |
echo -n "| Number of failed patterns : " |
cat ./log/*.log | grep -c FAILED |
echo -n "| Number of skipped patterns: " |
cat ./log/*.log | grep -c SKIPPED |
echo "|--------------------------------" |
echo -n "| Number of patterns: " |
ls -1 *.log | wc -l |
ls -1 ./log/*.log | wc -l |
echo " ================================" |
echo " Make sure passed == total" |
echo "" |
/rtl_sim/run/run_coverage_analysis
6,10 → 6,10
# WAS RUN USING "ncverilog" SIMULATOR |
|
# Remove old merged report |
rm -rf cov_work/design/merged_coverage |
rm -rf cov_work/scope/merged_coverage |
|
# Merge all available coverage reports |
iccr ../bin/cov_iccr_merge.cf |
imc -batch ../bin/cov_iccr_merge.cf |
|
# Launch GUI |
iccr -test cov_work/design/merged_coverage -GUI |
imc -gui -load cov_work/scope/merged_coverage |
/rtl_sim/run/run
15,4 → 15,6
OMSP_SIMULATOR=iverilog |
export OMSP_SIMULATOR |
|
../bin/msp430sim two-op_mov |
rm -rf cov_work |
|
../bin/msp430sim sing-op_reti |
/rtl_sim/run/run_c
1,4 → 1,19
#!/bin/csh -f |
|
# Enable/Disable waveform dumping |
OMSP_NODUMP=0 |
export OMSP_NODUMP |
|
# Choose simulator: |
# - iverilog : Icarus Verilog (default) |
# - cver : CVer |
# - verilog : Verilog-XL |
# - ncverilog : NC-Verilog |
# - vcs : VCS |
# - vsim : Modelsim |
OMSP_SIMULATOR=ncverilog |
export OMSP_SIMULATOR |
|
|
../bin/msp430sim_c sandbox |
|
/rtl_sim/run/run_all
15,89 → 15,114
OMSP_SIMULATOR=iverilog |
export OMSP_SIMULATOR |
|
rm -rf ./cov_work |
rm -rf ./log/*.log |
mkdir ./log |
|
# Two-Operand Arithmetic test patterns |
../bin/msp430sim two-op_mov | tee ./log/two-op_mov.log |
../bin/msp430sim two-op_mov-b | tee ./log/two-op_mov-b.log |
../bin/msp430sim two-op_add | tee ./log/two-op_add.log |
../bin/msp430sim two-op_add-b | tee ./log/two-op_add-b.log |
../bin/msp430sim two-op_addc | tee ./log/two-op_addc.log |
../bin/msp430sim two-op_sub | tee ./log/two-op_sub.log |
../bin/msp430sim two-op_subc | tee ./log/two-op_subc.log |
../bin/msp430sim two-op_cmp | tee ./log/two-op_cmp.log |
../bin/msp430sim two-op_bit | tee ./log/two-op_bit.log |
../bin/msp430sim two-op_bic | tee ./log/two-op_bic.log |
../bin/msp430sim two-op_bis | tee ./log/two-op_bis.log |
../bin/msp430sim two-op_xor | tee ./log/two-op_xor.log |
../bin/msp430sim two-op_and | tee ./log/two-op_and.log |
../bin/msp430sim two-op_dadd | tee ./log/two-op_dadd.log |
../bin/msp430sim two-op_mov | tee ./log/two-op_mov.log |
../bin/msp430sim two-op_mov-b | tee ./log/two-op_mov-b.log |
../bin/msp430sim two-op_add | tee ./log/two-op_add.log |
../bin/msp430sim two-op_add-b | tee ./log/two-op_add-b.log |
../bin/msp430sim two-op_addc | tee ./log/two-op_addc.log |
../bin/msp430sim two-op_sub | tee ./log/two-op_sub.log |
../bin/msp430sim two-op_subc | tee ./log/two-op_subc.log |
../bin/msp430sim two-op_cmp | tee ./log/two-op_cmp.log |
../bin/msp430sim two-op_bit | tee ./log/two-op_bit.log |
../bin/msp430sim two-op_bic | tee ./log/two-op_bic.log |
../bin/msp430sim two-op_bis | tee ./log/two-op_bis.log |
../bin/msp430sim two-op_xor | tee ./log/two-op_xor.log |
../bin/msp430sim two-op_and | tee ./log/two-op_and.log |
../bin/msp430sim two-op_dadd | tee ./log/two-op_dadd.log |
../bin/msp430sim two-op_autoincr | tee ./log/two-op_autoincr.log |
../bin/msp430sim two-op_autoincr-b | tee ./log/two-op_autoincr-b.log |
|
# Conditional Jump test patterns |
../bin/msp430sim c-jump_jeq | tee ./log/c-jump_jeq.log |
../bin/msp430sim c-jump_jne | tee ./log/c-jump_jne.log |
../bin/msp430sim c-jump_jc | tee ./log/c-jump_jc.log |
../bin/msp430sim c-jump_jnc | tee ./log/c-jump_jnc.log |
../bin/msp430sim c-jump_jn | tee ./log/c-jump_jn.log |
../bin/msp430sim c-jump_jge | tee ./log/c-jump_jge.log |
../bin/msp430sim c-jump_jl | tee ./log/c-jump_jl.log |
../bin/msp430sim c-jump_jmp | tee ./log/c-jump_jmp.log |
../bin/msp430sim c-jump_jeq | tee ./log/c-jump_jeq.log |
../bin/msp430sim c-jump_jne | tee ./log/c-jump_jne.log |
../bin/msp430sim c-jump_jc | tee ./log/c-jump_jc.log |
../bin/msp430sim c-jump_jnc | tee ./log/c-jump_jnc.log |
../bin/msp430sim c-jump_jn | tee ./log/c-jump_jn.log |
../bin/msp430sim c-jump_jge | tee ./log/c-jump_jge.log |
../bin/msp430sim c-jump_jl | tee ./log/c-jump_jl.log |
../bin/msp430sim c-jump_jmp | tee ./log/c-jump_jmp.log |
|
# Single-Operand Arithmetic test patterns |
../bin/msp430sim sing-op_rrc | tee ./log/sing-op_rrc.log |
../bin/msp430sim sing-op_rra | tee ./log/sing-op_rra.log |
../bin/msp430sim sing-op_swpb | tee ./log/sing-op_swpb.log |
../bin/msp430sim sing-op_sxt | tee ./log/sing-op_sxt.log |
../bin/msp430sim sing-op_push | tee ./log/sing-op_push.log |
../bin/msp430sim sing-op_call | tee ./log/sing-op_call.log |
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log |
../bin/msp430sim sing-op_rrc | tee ./log/sing-op_rrc.log |
../bin/msp430sim sing-op_rra | tee ./log/sing-op_rra.log |
../bin/msp430sim sing-op_swpb | tee ./log/sing-op_swpb.log |
../bin/msp430sim sing-op_sxt | tee ./log/sing-op_sxt.log |
../bin/msp430sim sing-op_push | tee ./log/sing-op_push.log |
../bin/msp430sim sing-op_call | tee ./log/sing-op_call.log |
|
# Interrupts & NMI |
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log |
../bin/msp430sim nmi | tee ./log/nmi.log |
|
# ROM Data Read access |
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log |
../bin/msp430sim sing-op_push_rom-rd | tee ./log/sing-op_push_rom-rd.log |
../bin/msp430sim sing-op_call_rom-rd | tee ./log/sing-op_call_rom-rd.log |
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log |
../bin/msp430sim sing-op_push_rom-rd | tee ./log/sing-op_push_rom-rd.log |
../bin/msp430sim sing-op_call_rom-rd | tee ./log/sing-op_call_rom-rd.log |
|
# Power saving modes (CPUOFF, OSCOFF, SCG1) |
../bin/msp430sim op_modes | tee ./log/op_modes.log |
# Power saving modes (CPUOFF, OSCOFF, SCG0, SCG1) |
../bin/msp430sim op_modes | tee ./log/op_modes.log |
../bin/msp430sim op_modes_asic | tee ./log/op_modes_asic.log |
../bin/msp430sim lp_modes_asic | tee ./log/lp_modes_asic.log |
../bin/msp430sim lp_modes_dbg_asic | tee ./log/lp_modes_dbg_asic.log |
|
# CPU startup conditions |
../bin/msp430sim cpu_startup_asic | tee ./log/cpu_startup_asic.log |
|
# Basic clock module |
../bin/msp430sim clock_module | tee ./log/clock_module.log |
../bin/msp430sim clock_module | tee ./log/clock_module.log |
../bin/msp430sim clock_module_asic | tee ./log/clock_module_asic.log |
../bin/msp430sim clock_module_asic_mclk | tee ./log/clock_module_asic_mclk.log |
../bin/msp430sim clock_module_asic_smclk | tee ./log/clock_module_asic_smclk.log |
../bin/msp430sim clock_module_asic_lfxt | tee ./log/clock_module_asic_lfxt.log |
|
# Serial Debug Interface |
../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log |
../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log |
../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log |
../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log |
../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log |
../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log |
../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log |
../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log |
../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log |
../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log |
../bin/msp430sim dbg_uart_sync | tee ./log/dbg_uart_sync.log |
../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log |
../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log |
../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log |
../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log |
../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log |
../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log |
../bin/msp430sim dbg_rdwr | tee ./log/dbg_rdwr.log |
../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log |
../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log |
../bin/msp430sim dbg_onoff_asic | tee ./log/dbg_onoff_asic.log |
|
# SFR test patterns |
../bin/msp430sim sfr | tee ./log/sfr.log |
|
# SCAN test patterns (only to increase coverage) |
../bin/msp430sim scan | tee ./log/scan.log |
|
# Watchdog test patterns |
../bin/msp430sim wdt_interval | tee ./log/wdt_interval.log |
../bin/msp430sim wdt_watchdog | tee ./log/wdt_watchdog.log |
../bin/msp430sim wdt_clkmux | tee ./log/wdt_clkmux.log |
../bin/msp430sim wdt_interval | tee ./log/wdt_interval.log |
../bin/msp430sim wdt_watchdog | tee ./log/wdt_watchdog.log |
../bin/msp430sim wdt_clkmux | tee ./log/wdt_clkmux.log |
../bin/msp430sim wdt_wkup | tee ./log/wdt_wkup.log |
|
# GPIO test patterns |
../bin/msp430sim gpio_rdwr | tee ./log/gpio_rdwr.log |
../bin/msp430sim gpio_irq | tee ./log/gpio_irq.log |
../bin/msp430sim gpio_rdwr | tee ./log/gpio_rdwr.log |
../bin/msp430sim gpio_irq | tee ./log/gpio_irq.log |
|
# Peripheral templates test patterns |
../bin/msp430sim template_periph_8b | tee ./log/template_periph_8b.log |
../bin/msp430sim template_periph_16b | tee ./log/template_periph_16b.log |
../bin/msp430sim template_periph_8b | tee ./log/template_periph_8b.log |
../bin/msp430sim template_periph_16b | tee ./log/template_periph_16b.log |
|
# Timer A patterns |
../bin/msp430sim tA_modes | tee ./log/tA_modes.log |
../bin/msp430sim tA_compare | tee ./log/tA_compare.log |
../bin/msp430sim tA_output | tee ./log/tA_output.log |
../bin/msp430sim tA_capture | tee ./log/tA_capture.log |
../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log |
../bin/msp430sim tA_modes | tee ./log/tA_modes.log |
../bin/msp430sim tA_compare | tee ./log/tA_compare.log |
../bin/msp430sim tA_output | tee ./log/tA_output.log |
../bin/msp430sim tA_capture | tee ./log/tA_capture.log |
../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log |
|
|
# Hardware multiplier test patterns |
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log |
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log |
|
|
grep SKIPPED ./log/*.log |
/rtl_sim/run/load_waveform.sav
1,11 → 1,13
[timestart] 0 |
[size] 1680 991 |
[pos] -1 -1 |
*-21.526770 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
[timestart] 2700000 |
[size] 1680 990 |
[pos] -678 -4 |
*-23.404364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
[treeopen] tb_openMSP430. |
[treeopen] tb_openMSP430.dut. |
@22 |
tb_openMSP430.r15[15:0] |
tb_openMSP430.error[31:0] |
tb_openMSP430.dut.pmem_dout[15:0] |
@820 |
tb_openMSP430.inst_full[255:0] |
@22 |
19,3 → 21,44
tb_openMSP430.r6[15:0] |
tb_openMSP430.mem250[15:0] |
tb_openMSP430.mem24E[15:0] |
@200 |
- |
@28 |
(10)tb_openMSP430.wkup[13:0] |
(10)tb_openMSP430.irq[13:0] |
(11)tb_openMSP430.wkup[13:0] |
(11)tb_openMSP430.irq[13:0] |
@200 |
- |
@28 |
tb_openMSP430.dco_wkup |
tb_openMSP430.dco_enable |
tb_openMSP430.dco_clk |
@200 |
- |
@28 |
tb_openMSP430.lfxt_wkup |
tb_openMSP430.lfxt_enable |
tb_openMSP430.lfxt_clk |
@200 |
- |
@28 |
tb_openMSP430.dut.clock_module_0.cpu_en |
@29 |
tb_openMSP430.dut.clock_module_0.dbg_en |
@28 |
tb_openMSP430.dut.frontend_0.cpuoff |
tb_openMSP430.dut.clock_module_0.oscoff |
tb_openMSP430.dut.clock_module_0.scg0 |
tb_openMSP430.dut.clock_module_0.scg1 |
@200 |
- |
@28 |
tb_openMSP430.mclk |
tb_openMSP430.smclk |
tb_openMSP430.aclk |
tb_openMSP430.dbg_clk |
tb_openMSP430.dut.clock_module_0.mclk_enable |
tb_openMSP430.dut.clock_module_0.mclk_wkup |
[pattern_trace] 1 |
[pattern_trace] 0 |
/rtl_sim/src/wdt_watchdog.v
45,23 → 45,89
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef WATCHDOG |
|
// WATCHDOG TEST: RD/WR ACCESS |
//-------------------------------------------------------- |
|
@(mem250===16'h1000); |
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 ====="); |
if (mem202 !== 16'h69d7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69d3 ====="); |
if (mem204 !== 16'h6955) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6951 ====="); |
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 ====="); |
if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 ====="); |
`ifdef NMI |
`ifdef WATCHDOG_MUX |
if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) ====="); |
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) ====="); |
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) ====="); |
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) ====="); |
if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) ====="); |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
if (mem200 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) ====="); |
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) ====="); |
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) ====="); |
if (mem206 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) ====="); |
if (mem208 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) ====="); |
`else |
if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) ====="); |
`ifdef ASIC |
if (mem202 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) ====="); |
if (mem204 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) ====="); |
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) ====="); |
`else |
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) ====="); |
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) ====="); |
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) ====="); |
`endif |
if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) ====="); |
`endif |
`endif |
`else |
`ifdef WATCHDOG_MUX |
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) ====="); |
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) ====="); |
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) ====="); |
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) ====="); |
if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) ====="); |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
if (mem200 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) ====="); |
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) ====="); |
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) ====="); |
if (mem206 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) ====="); |
if (mem208 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) ====="); |
`else |
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) ====="); |
`ifdef ASIC |
if (mem202 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) ====="); |
if (mem204 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) ====="); |
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) ====="); |
`else |
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) ====="); |
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) ====="); |
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) ====="); |
`endif |
if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) ====="); |
`endif |
`endif |
`endif |
|
`ifdef ASIC |
`ifdef WATCHDOG_MUX |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
// From there, force the watchdog clock to DCO_CLK to speedup simulation |
force lfxt_clk = dco_clk; |
`endif |
`endif |
`endif |
|
|
// WATCHDOG TEST: WATCHDOG MODE /64 |
//-------------------------------------------------------- |
|
@(mem250===16'h2000); |
`ifdef ASIC |
if (mem200 !== 16'h000B) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000B ====="); |
`else |
if (mem200 !== 16'h000A) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000A ====="); |
`endif |
|
$display("Watchdog mode /64 mode test completed..."); |
|
70,7 → 136,11
//-------------------------------------------------------- |
|
@(mem250===16'h3000); |
`ifdef ASIC |
if (mem202 !== 16'h0056) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0056 ====="); |
`else |
if (mem202 !== 16'h0055) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0055 ====="); |
`endif |
|
$display("Watchdog mode /512 mode test completed..."); |
|
79,7 → 149,11
//-------------------------------------------------------- |
|
@(mem250===16'h4000); |
`ifdef ASIC |
if (mem204 !== 16'h0556) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0556 ====="); |
`else |
if (mem204 !== 16'h0555) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0555 ====="); |
`endif |
|
$display("Watchdog mode /8192 mode test completed..."); |
|
88,10 → 162,21
//-------------------------------------------------------- |
|
@(mem250===16'h5000); |
`ifdef ASIC |
if (mem206 !== 16'h1556) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1556 ====="); |
`else |
if (mem206 !== 16'h1555) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1555 ====="); |
`endif |
|
$display("Watchdog mode /32768 mode test completed..."); |
|
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (the Watchdog is not included) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
|
stimulus_done = 1; |
end |
/rtl_sim/src/tA_clkmux.v
73,6 → 73,14
stimulus_done = 0; |
|
|
`ifdef ASIC |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
$display(" ==============================================="); |
$finish; |
`else |
|
// TIMER A TEST: INPUT MUX - TACLK |
//-------------------------------------------------------- |
// @(r15 === 16'h0000); |
116,7 → 124,8
repeat(300) @(posedge mclk); |
if (tar !== 16'h001E) tb_error("====== TIMER A TEST: INPUT MUX - INCLK ====="); |
|
|
`endif |
|
stimulus_done = 1; |
end |
|
/rtl_sim/src/two-op_mov-b.s43
121,7 → 121,7
|
main: |
/* ---------------------- INITIALIZE REGISTERS --------------------- */ |
mov #0x2222, r2 |
mov #0x2202, r2 |
mov #0x3333, r3 |
mov #0x4444, r4 |
mov #0x5555, r5 |
/rtl_sim/src/submit.prj
0,0 → 1,31
|
verilog work ../../../bench/verilog/tb_openMSP430.v |
verilog work ../../../bench/verilog/ram.v |
verilog work ../../../bench/verilog/msp_debug.v |
|
verilog work ../../../rtl/verilog/openMSP430_defines.v |
verilog work ../../../rtl/verilog/openMSP430.v |
verilog work ../../../rtl/verilog/omsp_frontend.v |
verilog work ../../../rtl/verilog/omsp_execution_unit.v |
verilog work ../../../rtl/verilog/omsp_register_file.v |
verilog work ../../../rtl/verilog/omsp_alu.v |
verilog work ../../../rtl/verilog/omsp_sfr.v |
verilog work ../../../rtl/verilog/omsp_clock_module.v |
verilog work ../../../rtl/verilog/omsp_mem_backbone.v |
verilog work ../../../rtl/verilog/omsp_watchdog.v |
verilog work ../../../rtl/verilog/omsp_dbg.v |
verilog work ../../../rtl/verilog/omsp_dbg_uart.v |
verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v |
verilog work ../../../rtl/verilog/omsp_multiplier.v |
verilog work ../../../rtl/verilog/omsp_sync_reset.v |
verilog work ../../../rtl/verilog/omsp_sync_cell.v |
verilog work ../../../rtl/verilog/omsp_scan_mux.v |
verilog work ../../../rtl/verilog/omsp_and_gate.v |
verilog work ../../../rtl/verilog/omsp_wakeup_cell.v |
verilog work ../../../rtl/verilog/omsp_clock_gate.v |
verilog work ../../../rtl/verilog/omsp_clock_mux.v |
|
verilog work ../../../rtl/verilog/periph/omsp_gpio.v |
verilog work ../../../rtl/verilog/periph/omsp_timerA.v |
verilog work ../../../rtl/verilog/periph/template_periph_8b.v |
verilog work ../../../rtl/verilog/periph/template_periph_16b.v |
rtl_sim/src/submit.prj
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_autoincr.s43
===================================================================
--- rtl_sim/src/two-op_autoincr.s43 (nonexistent)
+++ rtl_sim/src/two-op_autoincr.s43 (revision 134)
@@ -0,0 +1,483 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */
+/*---------------------------------------------------------------------------*/
+/* Test the MOV instruction with all addressing modes */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_202, (__data_start+0x02)
+.set DMEM_204, (__data_start+0x04)
+.set DMEM_206, (__data_start+0x06)
+.set DMEM_208, (__data_start+0x08)
+.set DMEM_20A, (__data_start+0x0A)
+.set DMEM_20C, (__data_start+0x0C)
+.set DMEM_20E, (__data_start+0x0E)
+.set DMEM_210, (__data_start+0x10)
+.set DMEM_212, (__data_start+0x12)
+.set DMEM_214, (__data_start+0x14)
+.set DMEM_216, (__data_start+0x16)
+.set DMEM_218, (__data_start+0x18)
+.set DMEM_21A, (__data_start+0x1A)
+.set DMEM_21C, (__data_start+0x1C)
+.set DMEM_21E, (__data_start+0x1E)
+.set DMEM_220, (__data_start+0x20)
+.set DMEM_222, (__data_start+0x22)
+
+.global main
+
+main:
+ /* ---------------------- INITIALIZE MEMORY --------------------- */
+
+ mov #0x0000, &DMEM_200
+ mov #0x0000, &DMEM_202
+ mov #0x1111, &DMEM_204
+ mov #0x2222, &DMEM_206
+ mov #0x3333, &DMEM_208
+ mov #0x4444, &DMEM_20A
+ mov #0x5555, &DMEM_20C
+ mov #0x6666, &DMEM_20E
+ mov #0x7777, &DMEM_210
+ mov #0x8888, &DMEM_212
+ mov #0x9999, &DMEM_214
+ mov #0xAAAA, &DMEM_216
+ mov #0xBBBB, &DMEM_218
+ mov #0xCCCC, &DMEM_21A
+ mov #0xDDDD, &DMEM_21C
+ mov #0xEEEE, &DMEM_21E
+ mov #0xFFFF, &DMEM_220
+ mov #0x1122, &DMEM_222
+
+ mov #0x0001, &DMEM_200
+
+ /* ---------------------- AUTO-INCREMENT: R1 --------------------- */
+
+ mov #DMEM_204, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x1000, &DMEM_200
+ mov @r1+, &DMEM_202
+ mov #0x1001, &DMEM_200
+ mov @r1+, &DMEM_202
+ mov #0x1002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R2 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0004, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x2000, &DMEM_200
+ mov @r2+, &DMEM_202
+ mov #0x2001, &DMEM_200
+ mov @r2+, &DMEM_202
+ mov #0x2002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R3 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #DMEM_208, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x3000, &DMEM_200
+ mov @r3+, &DMEM_202
+ mov #0x3001, &DMEM_200
+ mov @r3+, &DMEM_202
+ mov #0x3002, &DMEM_200
+ swpb @r3+
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R4 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #DMEM_20A, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x4000, &DMEM_200
+ mov @r4+, &DMEM_202
+ mov #0x4001, &DMEM_200
+ mov @r4+, &DMEM_202
+ mov #0x4002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R5 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #DMEM_20C, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x5000, &DMEM_200
+ mov @r5+, &DMEM_202
+ mov #0x5001, &DMEM_200
+ mov @r5+, &DMEM_202
+ mov #0x5002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R6 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #DMEM_20E, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x6000, &DMEM_200
+ mov @r6+, &DMEM_202
+ mov #0x6001, &DMEM_200
+ mov @r6+, &DMEM_202
+ mov #0x6002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R7 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #DMEM_210, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x7000, &DMEM_200
+ mov @r7+, &DMEM_202
+ mov #0x7001, &DMEM_200
+ mov @r7+, &DMEM_202
+ mov #0x7002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R8 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #DMEM_212, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x8000, &DMEM_200
+ mov @r8+, &DMEM_202
+ mov #0x8001, &DMEM_200
+ mov @r8+, &DMEM_202
+ mov #0x8002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R9 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #DMEM_214, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x9000, &DMEM_200
+ mov @r9+, &DMEM_202
+ mov #0x9001, &DMEM_200
+ mov @r9+, &DMEM_202
+ mov #0x9002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R10 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #DMEM_216, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xA000, &DMEM_200
+ mov @r10+, &DMEM_202
+ mov #0xA001, &DMEM_200
+ mov @r10+, &DMEM_202
+ mov #0xA002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R11 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #DMEM_218, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xB000, &DMEM_200
+ mov @r11+, &DMEM_202
+ mov #0xB001, &DMEM_200
+ mov @r11+, &DMEM_202
+ mov #0xB002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R12 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #DMEM_21A, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xC000, &DMEM_200
+ mov @r12+, &DMEM_202
+ mov #0xC001, &DMEM_200
+ mov @r12+, &DMEM_202
+ mov #0xC002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R13 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #DMEM_21C, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xD000, &DMEM_200
+ mov @r13+, &DMEM_202
+ mov #0xD001, &DMEM_200
+ mov @r13+, &DMEM_202
+ mov #0xD002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R14 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #DMEM_21E, r14
+ mov #0x0000, r15
+
+ mov #0xE000, &DMEM_200
+ mov @r14+, &DMEM_202
+ mov #0xE001, &DMEM_200
+ mov @r14+, &DMEM_202
+ mov #0xE002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R15 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #DMEM_220, r15
+
+ mov #0xF000, &DMEM_200
+ mov @r15+, &DMEM_202
+ mov #0xF001, &DMEM_200
+ mov @r15+, &DMEM_202
+ mov #0xF002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/two-op_autoincr.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/wdt_interval.v
===================================================================
--- rtl_sim/src/wdt_interval.v (revision 128)
+++ rtl_sim/src/wdt_interval.v (revision 134)
@@ -45,18 +45,76 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef WATCHDOG
// WATCHDOG TEST: RD/WR ACCESS
//--------------------------------------------------------
@(r15==16'h1000);
- if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
- if (r5 !== 16'h69d7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69d3 =====");
- if (r6 !== 16'h6955) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6951 =====");
- if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 =====");
- if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
+`ifdef NMI
+ `ifdef WATCHDOG_MUX
+ if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
+ if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) =====");
+ if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) =====");
+ if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) =====");
+ if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ if (r4 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
+ if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) =====");
+ if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) =====");
+ if (r7 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) =====");
+ if (r8 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
+ `else
+ if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
+ `ifdef ASIC
+ if (r5 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) =====");
+ if (r6 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) =====");
+ if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) =====");
+ `else
+ if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) =====");
+ if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) =====");
+ if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) =====");
+ `endif
+ if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
+ `endif
+ `endif
+`else
+ `ifdef WATCHDOG_MUX
+ if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
+ if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) =====");
+ if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) =====");
+ if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) =====");
+ if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ if (r4 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
+ if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) =====");
+ if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) =====");
+ if (r7 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) =====");
+ if (r8 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
+ `else
+ if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
+ `ifdef ASIC
+ if (r5 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) =====");
+ if (r6 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) =====");
+ if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) =====");
+ `else
+ if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) =====");
+ if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) =====");
+ if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) =====");
+ `endif
+ if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
+ `endif
+ `endif
+`endif
+`ifdef NMI
+ if (r9 !== 16'h0010) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1 != 0x10 =====");
+`else
+ if (r9 !== 16'h0000) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1 != 0x00 =====");
+`endif
-
+
// WATCHDOG TEST: INTERVAL MODE /64
//--------------------------------------------------------
@@ -63,7 +121,23 @@
@(r15==16'h2000);
if (r5 !== 16'h3401) tb_error("====== WATCHDOG INTERVAL MODE /64: R5 != 0x3401 =====");
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64: R6 != 0x0000 =====");
- if (r7 !== 16'h000D) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000D =====");
+`ifdef ASIC
+ `ifdef WATCHDOG_MUX
+ if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ `ifdef ACLK_DIVIDER
+ if (r7 !== 16'h019F) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x019F (CONFIG 1) =====");
+ `else
+ if (r7 !== 16'h0199) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x0199 (CONFIG 1) =====");
+ `endif
+ `else
+ if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
+ `endif
+ `endif
+`else
+ if (r7 !== 16'h000D) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000D (CONFIG 1) =====");
+`endif
@(r15==16'h2001);
if (r5 !== 16'h0002) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R5 != 0x0002 =====");
@@ -70,6 +144,16 @@
if (r6 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R6 != 0x0001 =====");
if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R7 != 0x0000 =====");
if (r8 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R8 != 0x0000 =====");
+
+`ifdef ASIC
+ `ifdef WATCHDOG_MUX
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ // From there, force the watchdog clock to DCO_CLK to speedup simulation
+ force lfxt_clk = dco_clk;
+ `endif
+ `endif
+`endif
@(r15==16'h2002);
if (r5 !== 16'h0022) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R5 != 0x0022 =====");
@@ -83,8 +167,8 @@
if (r8 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ CNT CLEAR: R8 != 0x0001 =====");
$display("Interval mode /64 mode test completed...");
-
+
// WATCHDOG TEST: INTERVAL MODE /512
//--------------------------------------------------------
@@ -91,7 +175,11 @@
@(r15==16'h3000);
if (r5 !== 16'h3403) tb_error("====== WATCHDOG INTERVAL MODE /512: R5 != 0x3403 =====");
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /512: R6 != 0x0000 =====");
- if (r7 !== 16'h0067) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0067 =====");
+`ifdef ASIC
+ if (r7 !== 16'h0068) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0068 =====");
+`else
+ if (r7 !== 16'h0066) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0066 =====");
+`endif
$display("Interval mode /512 mode test completed...");
@@ -102,7 +190,11 @@
@(r15==16'h4000);
if (r5 !== 16'h3404) tb_error("====== WATCHDOG INTERVAL MODE /8192: R5 != 0x3404 =====");
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /8192: R6 != 0x0000 =====");
+`ifdef ASIC
+ if (r7 !== 16'h0668) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0668 =====");
+`else
if (r7 !== 16'h0667) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0667 =====");
+`endif
$display("Interval mode /8192 mode test completed...");
@@ -113,10 +205,21 @@
@(r15==16'h5000);
if (r5 !== 16'h3405) tb_error("====== WATCHDOG INTERVAL MODE /32768: R5 != 0x3405 =====");
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /32768: R6 != 0x0000 =====");
- if (r7 !== 16'h199a) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A =====");
+`ifdef ASIC
+ if (r7 !== 16'h199B) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199B =====");
+`else
+ if (r7 !== 16'h199A) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A =====");
+`endif
$display("Interval mode /32768 mode test completed...");
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (the Watchdog is not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
stimulus_done = 1;
end
/rtl_sim/src/sing-op_reti.s43
66,7 → 66,7
# Pre-initialize stack |
mov #DMEM_252, r1 |
push #RETI_ROUTINE |
push #0x0145 |
push #0x010f |
mov #0x0000, &0x0200 |
|
# Run RETI test |
304,14 → 304,19
|
# Test IRQ NMI: rising edge |
#---------------------------- |
|
.set WDTCTL, 0x0120 |
.set IE1, 0x0000 |
.set IFG1, 0x0002 |
|
|
mov #0x5a00, &WDTCTL ; NMI Edge selection: rising |
bic.b #0x0010, &IFG1 ; Clear NMI flag |
bis.b #0x0010, &IE1 ; Enable NMI |
|
bit #0x0010, &IE1 ; skip this test if the NMI is not included |
jz skip_nmi |
|
mov #0x0000, r6 |
mov #0xaaaa, r7 |
mov #0x5555, r8 |
323,8 → 328,11
jne wait_nmi |
|
mov.b &IE1, r9 |
mov.b &IFG1, r10 |
mov.b &IFG1, r10 |
bic.b #0x10, &IFG1 ; Clear NMI flag |
bis.b #0x10, &IE1 ; Enable NMI |
|
skip_nmi: |
mov #0xf201, r15 |
|
|
/rtl_sim/src/lp_modes_asic.s43
0,0 → 1,230
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* CPU OPERATING MODES */ |
/*---------------------------------------------------------------------------*/ |
/* Test the CPU Low Power modes: */ |
/* - LPM0 <=> CPUOFF */ |
/* - LPM1 <=> CPUOFF + SCG0 */ |
/* - LPM2 <=> CPUOFF + SCG1 */ |
/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */ |
/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */ |
/* */ |
/* Reminder: */ |
/* - CPUOFF <=> turns off CPU. */ |
/* - SCG0 <=> turns off DCO. */ |
/* - SCG1 <=> turns off SMCLK. */ |
/* - OSCOFF <=> turns off LFXT_CLK. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
.set DMEM_BASE, (__data_start ) |
.set DMEM_200, (__data_start+0x00) |
.set DMEM_250, (__data_start+0x50) |
|
.set BCSCTL1, 0x0057 |
.set BCSCTL2, 0x0058 |
|
.macro LPM0 |
bis #0x0010, r2 |
.endm |
.macro LPM1 |
bis #0x0050, r2 |
.endm |
.macro LPM2 |
bis #0x0090, r2 |
.endm |
.macro LPM3 |
bis #0x00D0, r2 |
.endm |
.macro LPM4 |
bis #0x00F0, r2 |
.endm |
|
.macro LPM0_exit |
bic #0x0010, @r1 |
.endm |
.macro LPM1_exit |
bic #0x0050, @r1 |
.endm |
.macro LPM2_exit |
bic #0x0090, @r1 |
.endm |
.macro LPM3_exit |
bic #0x00D0, @r1 |
.endm |
.macro LPM4_exit |
bic #0x00F0, @r1 |
.endm |
|
|
WAIT_FUNC: |
dec r14 |
jnz WAIT_FUNC |
ret |
|
main: |
|
; Initialize stack and enable global interrupts |
mov #DMEM_250, r1 |
eint |
|
; Wait for a while to give enough time to ACLK |
mov #0x0050, r14 |
call #WAIT_FUNC |
mov #0x1000, r15 |
|
/* --------------- ACTIVE ------------------------------------------ */ |
|
mov #0x1001, r15 |
mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = DCO_CLK |
mov #0x0080, r14 |
call #WAIT_FUNC |
|
mov #0x2000, r15 |
|
|
/* --------------- LPM0 ( CPUOFF ) -------------------------------- */ |
|
mov #0x2001, r15 |
mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = DCO_CLK |
|
LPM0 ; # MCLK off |
mov #0x0090, r14 |
call #WAIT_FUNC |
|
mov #0x3000, r15 |
|
|
/* --------------- LPM1 ( CPUOFF + SCG0 ) ------------------------- */ |
|
mov #0x3001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM1 ; # MCLK off + DCO off |
mov #0x0090, r14 |
call #WAIT_FUNC |
|
mov #0x4000, r15 |
|
|
/*---------------- LPM2 ( CPUOFF + SCG1 ) ------------------------- */ |
|
mov #0x4001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM2 ; # MCLK off + SMCLK off |
mov #0x0190, r14 |
call #WAIT_FUNC |
|
mov #0x5000, r15 |
|
|
/*---------------- LPM3 ( CPUOFF + SCG0 + SCG1 ) ------------------ */ |
|
mov #0x5001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM3 ; # MCLK off + DCO off + SMCLK off |
mov #0x0190, r14 |
call #WAIT_FUNC |
|
mov #0x6000, r15 |
|
|
/*---------------- LPM4 ( CPUOFF + SCG0 + SCG1 + OSCOFF ) --------- */ |
|
mov #0x6001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM4 ; # MCLK off + DCO off + SMCLK off + LFXT off |
mov #0x0100, r14 |
call #WAIT_FUNC |
|
mov #0x6000, r15 |
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
/* ---------------------- INTERRUPT ROUTINES --------------- */ |
|
PORT1_VECTOR: |
push r13 |
push r14 |
mov #0x0060, r14 |
call #WAIT_FUNC |
mov #0xaaaa, r13 |
pop r14 |
pop r13 |
reti |
|
PORT2_VECTOR: |
push r13 |
push r14 |
mov #0x0060, r14 |
call #WAIT_FUNC |
mov #0xbbbb, r13 |
pop r14 |
pop r13 |
bic #0xf0, 0(r1) ;exit all lowpower mode |
reti |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word PORT1_VECTOR ; Interrupt 2 <unused> |
.word PORT2_VECTOR ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/lp_modes_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/op_modes_asic.s43
===================================================================
--- rtl_sim/src/op_modes_asic.s43 (nonexistent)
+++ rtl_sim/src/op_modes_asic.s43 (revision 134)
@@ -0,0 +1,246 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU OPERATING MODES */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU Operating modes: */
+/* - CPUOFF (<=> R2[4]): turn off CPU. */
+/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
+/* - SCG0 (<=> R2[6]): turn off DCO. */
+/* - SCG1 (<=> R2[7]): turn off SMCLK. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set BCSCTL1, 0x0057
+.set BCSCTL2, 0x0058
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+
+ ; Initialize stack and enable global interrupts
+ mov #DMEM_250, r1
+ eint
+
+ mov #0x1000, r15
+
+
+ /* -------------- SCG1 (<=> R2[7]): turn off SMCLK --------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1
+
+ mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
+ mov #0x1001, r15
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x0088, r2 ; # SCG1=1 (SMCLK off)
+ mov #0x1002, r15
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x1003, r15 ; # SCG1=1 (SMCLK off) with IRQ PORT2 (extiting power mode)
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x1004, r15 ; # SCG1=1 (SMCLK off) return from IRQ PORT2
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x0088, r2 ; # SCG1=1 (SMCLK off)
+ mov #0x1005, r15
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x1006, r15 ; # SCG1=1 (SMCLK off) with IRQ PORT1 (staying in power mode)
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x1007, r15 ; # SCG1=1 (SMCLK off) return from IRQ PORT1
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
+ mov #0x1008, r15
+ mov #0x0030, r14
+ call #WAIT_FUNC
+
+ mov #0x2000, r15
+
+
+ /* -------------- OSCOFF (<=> R2[5]): turn off LFXT1CLK --------------- */
+
+ mov.b #0x00, &BCSCTL1 ; # ACLK Div /1
+
+ mov #0x0008, r2 ; # OSCOFF=0 (ACLK on)
+ mov #0x2001, r15
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x0028, r2 ; # OSCOFF=1 (ACLK off)
+ mov #0x2002, r15
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x2003, r15 ; # OSCOFF=1 (ACLK off) with IRQ PORT2 (extiting power mode)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x2004, r15 ; # OSCOFF=1 (ACLK off) return from IRQ PORT2
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x0028, r2 ; # OSCOFF=1 (ACLK off)
+ mov #0x2005, r15
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x2006, r15 ; # OSCOFF=1 (ACLK off) with IRQ PORT1 (staying in power mode)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x2007, r15 ; # OSCOFF=1 (ACLK off) return from IRQ PORT1
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x0008, r2 ; # OSCOFF=0 (ACLK on)
+ mov #0x2008, r15
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+
+ mov #0x3000, r15
+
+
+ /* -------------- CPUOFF (<=> R2[4]): turn off CPU --------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
+
+ mov #0x3001, r15
+ mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x3002, r15
+ mov #0x0018, r2 ; # CPUOFF=1 (CPU off)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x3003, r15
+ mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+
+ mov #0x4000, r15
+
+
+ /* -------------- SCG0 (<=> R2[6]): turn off DCO oscillator --------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
+
+ mov #0x4001, r15
+ mov #0x0008, r2 ; # SCG0=0 (DCO on)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x4002, r15
+ mov #0x0048, r2 ; # SCG0=1 (DCO off)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+ mov #0x4003, r15
+ mov #0x0008, r2 ; # SCG0=0 (DCO on)
+ mov #0x0060, r14
+ call #WAIT_FUNC
+
+
+ mov #0x5000, r15
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT ROUTINES --------------- */
+
+PORT1_VECTOR:
+ push r13
+ push r14
+ mov #0x0060, r14
+ call #WAIT_FUNC
+ mov #0xaaaa, r13
+ pop r14
+ pop r13
+ reti
+
+PORT2_VECTOR:
+ push r13
+ push r14
+ mov #0x0060, r14
+ call #WAIT_FUNC
+ mov #0xbbbb, r13
+ pop r14
+ pop r13
+ bic #0xf0, 0(r1) ;exit all lowpower mode
+ reti
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word PORT1_VECTOR ; Interrupt 2
+.word PORT2_VECTOR ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/op_modes_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic_smclk.v
===================================================================
--- rtl_sim/src/clock_module_asic_smclk.v (nonexistent)
+++ rtl_sim/src/clock_module_asic_smclk.v (revision 134)
@@ -0,0 +1,374 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the SMCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+integer smclk_counter;
+always @ (negedge smclk)
+ smclk_counter <= smclk_counter+1;
+
+integer dco_clk_counter;
+always @ (negedge dco_clk)
+ dco_clk_counter <= dco_clk_counter+1;
+
+integer lfxt_clk_counter;
+always @ (negedge lfxt_clk)
+ lfxt_clk_counter <= lfxt_clk_counter+1;
+
+reg [15:0] reg_val;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge smclk);
+ stimulus_done = 0;
+
+`ifdef ASIC
+
+ //--------------------------------------------------------
+ // SMCLK GENERATION - LFXT_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h0001);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h0002);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h0003);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h0004);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
+
+
+ //--------------------------------------------------------
+ // SSMCLK GENERATION - DCO_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h1001);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+ $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h1002);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h1003);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h1004);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
+
+
+ //--------------------------------------------------------
+ // SMCLK GENERATION - LFXT_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h2001);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h2002);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h2003);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h2004);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef SMCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
+ `endif
+ `endif
+ $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
+
+
+ //--------------------------------------------------------
+ // SSMCLK GENERATION - DCO_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h3001);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+ $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h3002);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h3003);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h3004);
+ repeat(2) @(posedge smclk);
+ smclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge smclk);
+ if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef SMCLK_DIVIDER
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/clock_module_asic_smclk.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/wdt_wkup.v
===================================================================
--- rtl_sim/src/wdt_wkup.v (nonexistent)
+++ rtl_sim/src/wdt_wkup.v (revision 134)
@@ -0,0 +1,210 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* WATCHDOG TIMER */
+/*---------------------------------------------------------------------------*/
+/* Test the Watdog timer: */
+/* - Interval timer mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+integer dco_clk_cnt;
+always @(negedge dco_clk)
+ dco_clk_cnt <= dco_clk_cnt+1;
+
+integer mclk_cnt;
+always @(negedge mclk)
+ mclk_cnt <= mclk_cnt+1;
+
+integer smclk_cnt;
+always @(negedge smclk)
+ smclk_cnt <= smclk_cnt+1;
+
+integer aclk_cnt;
+`ifdef ASIC
+always @(negedge aclk)
+ aclk_cnt <= aclk_cnt+1;
+`else
+always @(negedge lfxt_clk)
+ aclk_cnt <= aclk_cnt+1;
+`endif
+
+integer inst_cnt;
+always @(inst_number)
+ inst_cnt <= inst_cnt+1;
+
+reg watchdog_clock;
+`ifdef ASIC
+ `ifdef WATCHDOG_MUX
+ always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
+ `else
+ always @(posedge dco_clk or negedge dco_clk) watchdog_clock <= dco_clk;
+ `endif
+ `endif
+`else
+ always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
+`endif
+
+integer watchdog_clock_cnt;
+always @(posedge watchdog_clock)
+ watchdog_clock_cnt <= watchdog_clock_cnt+1;
+
+always @(posedge dut.wdt_irq)
+ watchdog_clock_cnt = 1'b0;
+
+
+integer ii;
+integer jj;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+ ii = 0;
+ jj = 0;
+
+`ifdef WATCHDOG
+
+
+ // WATCHDOG TEST: INTERVAL MODE /64
+ //--------------------------------------------------------
+
+ @(r15==16'h1000);
+
+`ifdef ASIC
+ `ifdef WATCHDOG_MUX
+ `ifdef ACLK_DIVIDER
+ repeat(5) @(posedge watchdog_clock);
+ `else
+ repeat(4) @(posedge watchdog_clock);
+ `endif
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ `ifdef ACLK_DIVIDER
+ repeat(6) @(posedge watchdog_clock);
+ `else
+ repeat(5) @(posedge watchdog_clock);
+ `endif
+ `else
+ repeat(21) @(posedge watchdog_clock);
+ `endif
+ `endif
+`endif
+
+ for ( ii=0; ii < 9; ii=ii+1)
+ begin
+ repeat(1) @(posedge watchdog_clock);
+ jj = 1;
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ `ifdef ASIC
+ `ifdef WATCHDOG_MUX
+ repeat(62) @(posedge watchdog_clock);
+ jj = 2;
+ if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 1) =====");
+ if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 1) =====");
+ if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 1) =====");
+ if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 1) =====");
+ if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 1) =====");
+ if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");
+ repeat(1) @(posedge watchdog_clock);
+ jj = 3;
+ if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 1) =====");
+ `else
+ `ifdef WATCHDOG_NOMUX_ACLK
+ repeat(62) @(posedge watchdog_clock);
+ jj = 2;
+ if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 2) =====");
+ if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 2) =====");
+ if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 2) =====");
+ if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 2) =====");
+ if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 2) =====");
+ if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");
+ repeat(1) @(posedge watchdog_clock);
+ jj = 3;
+ if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 2) =====");
+ `else
+ repeat(39) @(posedge watchdog_clock);
+ jj = 2;
+ if (dco_clk_cnt !== 39) tb_error("====== DCO_CLK is not running (CONFIG 3) =====");
+ if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 3) =====");
+ if (smclk_cnt !== 39) tb_error("====== SMCLK is not running (CONFIG 3) =====");
+ if (aclk_cnt === 0) tb_error("====== ACLK is not running (CONFIG 3) =====");
+ if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 3) =====");
+ if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");
+ repeat(24) @(posedge watchdog_clock);
+ jj = 3;
+ if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 3) =====");
+ `endif
+ `endif
+ `else
+ repeat(62) @(posedge watchdog_clock);
+ jj = 2;
+ if (dco_clk_cnt < 1800) tb_error("====== DCO_CLK is not running (CONFIG 4) =====");
+ if (mclk_cnt < 1800) tb_error("====== MCLK is not running (CONFIG 4) =====");
+ if (smclk_cnt < 1800) tb_error("====== SMCLK is not running (CONFIG 4) =====");
+ if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 4) =====");
+ if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 4) =====");
+ if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");
+ repeat(1) @(posedge watchdog_clock);
+ jj = 3;
+ if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 4) =====");
+ `endif
+ end
+
+ // WATCHDOG TEST: RESET MODE /64
+ //--------------------------------------------------------
+
+ @(r15==16'h5000);
+ if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (the Watchdog is not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/wdt_wkup.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic_mclk.s43
===================================================================
--- rtl_sim/src/clock_module_asic_mclk.s43 (nonexistent)
+++ rtl_sim/src/clock_module_asic_mclk.s43 (revision 134)
@@ -0,0 +1,182 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the MCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set BCSCTL1, 0x0057
+.set BCSCTL2, 0x0058
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+
+
+ /* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */
+
+ mov.b #0x80, &BCSCTL2 ; # Div /1
+ mov #0x0001, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x90, &BCSCTL2 ; # Div /2
+ mov #0x0002, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0xA0, &BCSCTL2 ; # Div /4
+ mov #0x0003, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0xB0, &BCSCTL2 ; # Div /8
+ mov #0x0004, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x1000, r15
+
+ /* -------------- MCLK GENERATION - DCO_CLK INPUT ----------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1
+ mov #0x1001, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x10, &BCSCTL2 ; # Div /2
+ mov #0x1002, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x20, &BCSCTL2 ; # Div /4
+ mov #0x1003, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x30, &BCSCTL2 ; # Div /8
+ mov #0x1004, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x2000, r15
+
+
+ /* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */
+
+ mov.b #0x80, &BCSCTL2 ; # Div /1
+ mov #0x2001, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x90, &BCSCTL2 ; # Div /2
+ mov #0x2002, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0xA0, &BCSCTL2 ; # Div /4
+ mov #0x2003, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0xB0, &BCSCTL2 ; # Div /8
+ mov #0x2004, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x3000, r15
+
+ /* -------------- MCLK GENERATION - DCO_CLK INPUT ----------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1
+ mov #0x3001, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x10, &BCSCTL2 ; # Div /2
+ mov #0x3002, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x20, &BCSCTL2 ; # Div /4
+ mov #0x3003, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov.b #0x30, &BCSCTL2 ; # Div /8
+ mov #0x3004, r15
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x4000, r15
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/clock_module_asic_mclk.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/cpu_startup_asic.s43
===================================================================
--- rtl_sim/src/cpu_startup_asic.s43 (nonexistent)
+++ rtl_sim/src/cpu_startup_asic.s43 (revision 134)
@@ -0,0 +1,93 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU STARTUP */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU startup in ASIC mode: */
+/* - Check the CPU startup depending on the */
+/* CPU_EN / DBG_EN / RESET_N signal. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set BCSCTL1, 0x0057
+.set BCSCTL2, 0x0058
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+
+ /* -------------- SIMPLE LOOP ----------------- */
+
+ mov #0x1000, r15
+
+ mov #0x0500, r14
+ call #WAIT_FUNC
+
+ mov #0x2000, r15
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/cpu_startup_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_autoincr-b.s43
===================================================================
--- rtl_sim/src/two-op_autoincr-b.s43 (nonexistent)
+++ rtl_sim/src/two-op_autoincr-b.s43 (revision 134)
@@ -0,0 +1,485 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */
+/*---------------------------------------------------------------------------*/
+/* Test the MOV instruction with all addressing modes */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_202, (__data_start+0x02)
+.set DMEM_204, (__data_start+0x04)
+.set DMEM_206, (__data_start+0x06)
+.set DMEM_208, (__data_start+0x08)
+.set DMEM_20A, (__data_start+0x0A)
+.set DMEM_20C, (__data_start+0x0C)
+.set DMEM_20E, (__data_start+0x0E)
+.set DMEM_210, (__data_start+0x10)
+.set DMEM_212, (__data_start+0x12)
+.set DMEM_214, (__data_start+0x14)
+.set DMEM_216, (__data_start+0x16)
+.set DMEM_218, (__data_start+0x18)
+.set DMEM_21A, (__data_start+0x1A)
+.set DMEM_21C, (__data_start+0x1C)
+.set DMEM_21E, (__data_start+0x1E)
+.set DMEM_220, (__data_start+0x20)
+.set DMEM_222, (__data_start+0x22)
+
+.global main
+
+main:
+ /* ---------------------- INITIALIZE MEMORY --------------------- */
+
+ mov #0x0000, &DMEM_200
+ mov #0x1020, &DMEM_202
+ mov #0x1122, &DMEM_204
+ mov #0x3344, &DMEM_206
+ mov #0x5566, &DMEM_208
+ mov #0x7788, &DMEM_20A
+ mov #0x99AA, &DMEM_20C
+ mov #0xBBCC, &DMEM_20E
+ mov #0xDDEE, &DMEM_210
+ mov #0xFF21, &DMEM_212
+ mov #0x1223, &DMEM_214
+ mov #0x3445, &DMEM_216
+ mov #0x5667, &DMEM_218
+ mov #0x7889, &DMEM_21A
+ mov #0x9AAB, &DMEM_21C
+ mov #0xBCCD, &DMEM_21E
+ mov #0xDEEF, &DMEM_220
+ mov #0xF001, &DMEM_222
+
+ mov #0x0001, &DMEM_200
+
+ /* ---------------------- AUTO-INCREMENT: R1 --------------------- */
+ /* */
+ /* NOTE: it increment by 2 even in byte mode */
+
+ mov #DMEM_204, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x1000, &DMEM_200
+ mov.b @r1+, &DMEM_202
+ mov #0x1001, &DMEM_200
+ mov.b @r1+, &DMEM_202
+ mov #0x1002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R2 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0004, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x2000, &DMEM_200
+ mov.b @r2+, &DMEM_202
+ mov #0x2001, &DMEM_200
+ mov.b @r2+, &DMEM_202
+ mov #0x2002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R3 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #DMEM_208, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x3000, &DMEM_200
+ mov.b @r3+, &DMEM_202
+ mov #0x3001, &DMEM_200
+ mov.b @r3+, &DMEM_202
+ mov #0x3002, &DMEM_200
+ swpb @r3+
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R4 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #DMEM_20A, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x4000, &DMEM_200
+ mov.b @r4+, &DMEM_202
+ mov #0x4001, &DMEM_200
+ mov.b @r4+, &DMEM_202
+ mov #0x4002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R5 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #DMEM_20C, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x5000, &DMEM_200
+ mov.b @r5+, &DMEM_202
+ mov #0x5001, &DMEM_200
+ mov.b @r5+, &DMEM_202
+ mov #0x5002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R6 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #DMEM_20E, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x6000, &DMEM_200
+ mov.b @r6+, &DMEM_202
+ mov #0x6001, &DMEM_200
+ mov.b @r6+, &DMEM_202
+ mov #0x6002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R7 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #DMEM_210, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x7000, &DMEM_200
+ mov.b @r7+, &DMEM_202
+ mov #0x7001, &DMEM_200
+ mov.b @r7+, &DMEM_202
+ mov #0x7002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R8 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #DMEM_212, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x8000, &DMEM_200
+ mov.b @r8+, &DMEM_202
+ mov #0x8001, &DMEM_200
+ mov.b @r8+, &DMEM_202
+ mov #0x8002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R9 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #DMEM_214, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0x9000, &DMEM_200
+ mov.b @r9+, &DMEM_202
+ mov #0x9001, &DMEM_200
+ mov.b @r9+, &DMEM_202
+ mov #0x9002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R10 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #DMEM_216, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xA000, &DMEM_200
+ mov.b @r10+, &DMEM_202
+ mov #0xA001, &DMEM_200
+ mov.b @r10+, &DMEM_202
+ mov #0xA002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R11 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #DMEM_218, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xB000, &DMEM_200
+ mov.b @r11+, &DMEM_202
+ mov #0xB001, &DMEM_200
+ mov.b @r11+, &DMEM_202
+ mov #0xB002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R12 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #DMEM_21A, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xC000, &DMEM_200
+ mov.b @r12+, &DMEM_202
+ mov #0xC001, &DMEM_200
+ mov.b @r12+, &DMEM_202
+ mov #0xC002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R13 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #DMEM_21C, r13
+ mov #0x0000, r14
+ mov #0x0000, r15
+
+ mov #0xD000, &DMEM_200
+ mov.b @r13+, &DMEM_202
+ mov #0xD001, &DMEM_200
+ mov.b @r13+, &DMEM_202
+ mov #0xD002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R14 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #DMEM_21E, r14
+ mov #0x0000, r15
+
+ mov #0xE000, &DMEM_200
+ mov.b @r14+, &DMEM_202
+ mov #0xE001, &DMEM_200
+ mov.b @r14+, &DMEM_202
+ mov #0xE002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- AUTO-INCREMENT: R15 --------------------- */
+
+ mov #0x0000, r1
+ mov #0x0000, r2
+ mov #0x0000, r3
+ mov #0x0000, r4
+ mov #0x0000, r5
+ mov #0x0000, r6
+ mov #0x0000, r7
+ mov #0x0000, r8
+ mov #0x0000, r9
+ mov #0x0000, r10
+ mov #0x0000, r11
+ mov #0x0000, r12
+ mov #0x0000, r13
+ mov #0x0000, r14
+ mov #DMEM_220, r15
+
+ mov #0xF000, &DMEM_200
+ mov.b @r15+, &DMEM_202
+ mov #0xF001, &DMEM_200
+ mov.b @r15+, &DMEM_202
+ mov #0xF002, &DMEM_200
+ mov #0x0000, &DMEM_202
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/two-op_autoincr-b.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/scan.v
===================================================================
--- rtl_sim/src/scan.v (nonexistent)
+++ rtl_sim/src/scan.v (revision 134)
@@ -0,0 +1,132 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* SCAN test */
+/*---------------------------------------------------------------------------*/
+/* The purpose of this test is to let the scan_mode and scan_enable signals */
+/* toggle a bit in order to clean-up code coverage and give more visibility */
+/* on potential "real" coverage loss. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 85 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $ */
+/*===========================================================================*/
+
+integer ii;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ // Disable detection of the end of test
+ force inst_pc = 16'h0000;
+
+
+ // SCAN MODE
+ //------------------------------
+
+ for ( ii=0; ii < 8; ii=ii+1)
+ begin
+ scan_mode = ~scan_mode;
+ repeat(5) @(posedge mclk);
+ end
+ scan_mode = 1'b0;
+
+ reset_n = 1'b1;
+ #93;
+ reset_n = 1'b0;
+ #593;
+ reset_n = 1'b1;
+ repeat(20) @(posedge mclk);
+
+ // SCAN ENABLE
+ //------------------------------
+
+ for ( ii=0; ii < 8; ii=ii+1)
+ begin
+ scan_enable = ~scan_enable;
+ repeat(5) @(posedge mclk);
+ end
+ scan_enable = 1'b0;
+
+ reset_n = 1'b1;
+ #93;
+ reset_n = 1'b0;
+ #593;
+ reset_n = 1'b1;
+ repeat(20) @(posedge mclk);
+
+ // SCAN MODE & SCAN ENABLE
+ //------------------------------
+
+ for ( ii=0; ii < 8; ii=ii+1)
+ begin
+ scan_mode = ~scan_mode;
+ repeat(5) @(posedge mclk);
+ scan_enable = ~scan_enable;
+ repeat(5) @(posedge mclk);
+ scan_enable = ~scan_enable;
+ repeat(5) @(posedge mclk);
+ scan_mode = ~scan_mode;
+ repeat(5) @(posedge mclk);
+ end
+ scan_mode = 1'b0;
+ scan_enable = 1'b0;
+ repeat(5) @(posedge mclk);
+
+ for ( ii=0; ii < 8; ii=ii+1)
+ begin
+ scan_enable = ~scan_enable;
+ repeat(5) @(posedge mclk);
+ scan_mode = ~scan_mode;
+ repeat(5) @(posedge mclk);
+ scan_mode = ~scan_mode;
+ repeat(5) @(posedge mclk);
+ scan_enable = ~scan_enable;
+ repeat(5) @(posedge mclk);
+ end
+ scan_mode = 1'b0;
+ scan_enable = 1'b0;
+
+ reset_n = 1'b1;
+ #93;
+ reset_n = 1'b0;
+ #593;
+ reset_n = 1'b1;
+ repeat(20) @(posedge mclk);
+
+ release inst_pc;
+
+
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/scan.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/wdt_clkmux.s43
===================================================================
--- rtl_sim/src/wdt_clkmux.s43 (revision 128)
+++ rtl_sim/src/wdt_clkmux.s43 (revision 134)
@@ -65,10 +65,11 @@
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
mov #0x0001, r15
- mov #0x0170, r14
+ mov #0x0470, r14
call #WAIT_FUNC
mov #0x1000, r15
+ mov.b #0x00, &BCSCTL2 ;# SMCLK = MCLK
/* ------- WATCHDOG TEST INTERVAL MODE /64 - ACLK ------ */
/rtl_sim/src/clock_module_asic_lfxt.v
0,0 → 1,138
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* CLOCK MODULE */ |
/*---------------------------------------------------------------------------*/ |
/* Test the clock module: */ |
/* - Check the LFXT wakeup when selected sa MCLK. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
`define LONG_TIMEOUT |
|
integer mclk_counter; |
always @ (negedge mclk) |
mclk_counter <= mclk_counter+1; |
|
integer lfxt_clk_counter; |
always @ (negedge lfxt_clk) |
lfxt_clk_counter <= lfxt_clk_counter+1; |
|
reg [15:0] reg_val; |
|
initial |
begin |
$display(" ==============================================="); |
$display("| START SIMULATION |"); |
$display(" ==============================================="); |
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef OSCOFF_EN |
`ifdef MCLK_MUX |
|
//-------------------------------------------------------- |
// First make sure CPU runs with LFXT_CLK |
//-------------------------------------------------------- |
|
@(r15 === 16'h0001); |
#10; |
mclk_counter = 0; |
lfxt_clk_counter = 0; |
@(r15 === 16'h0002); |
#10; |
if (mclk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 1 ====="); |
if (lfxt_clk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 2 ====="); |
if (r10 !== 0) tb_error("====== CLOCK GENERATOR: TEST 3 ====="); |
|
|
//-------------------------------------------------------- |
// Make sure the CPU stops and LFXT oscillator too |
//-------------------------------------------------------- |
|
#10000; |
mclk_counter = 0; |
lfxt_clk_counter = 0; |
#10000; |
if (mclk_counter !== 0) tb_error("====== CLOCK GENERATOR: TEST 4 ====="); |
if (lfxt_clk_counter !== 0) tb_error("====== CLOCK GENERATOR: TEST 5 ====="); |
if (r10 !== 0) tb_error("====== CLOCK GENERATOR: TEST 6 ====="); |
#10000; |
|
|
//-------------------------------------------------------- |
// Generate IRQ and make sure CPU re-runs with LFXT_CLK |
//-------------------------------------------------------- |
|
wkup[0] = 1'b1; |
@(negedge mclk); |
irq[0] = 1'b1; |
@(negedge irq_acc[0]) |
@(negedge mclk); |
wkup[0] = 1'b0; |
irq[0] = 1'b0; |
|
@(r15 === 16'h0003); |
#10; |
mclk_counter = 0; |
lfxt_clk_counter = 0; |
@(r15 === 16'h0004); |
#10; |
if (mclk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 7 ====="); |
if (lfxt_clk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 8 ====="); |
if (r10 !== 16'h5678) tb_error("====== CLOCK GENERATOR: TEST 9 ====="); |
|
|
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test requires the MCLK clock mux) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test requires the OSCOFF option) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in FPGA mode) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
|
stimulus_done = 1; |
end |
|
rtl_sim/src/clock_module_asic_lfxt.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module.v
===================================================================
--- rtl_sim/src/clock_module.v (revision 128)
+++ rtl_sim/src/clock_module.v (revision 134)
@@ -59,6 +59,13 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
// ACLK GENERATION
//--------------------------------------------------------
@@ -198,6 +205,7 @@
reg_val = r14; // Read R14 register & initialize aclk/smclk counters
aclk_counter = 0;
smclk_counter = 0;
+ repeat(3) @(posedge mclk);
if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
repeat(500) @(posedge mclk); // Make sure that the CPU is stopped
@@ -233,6 +241,7 @@
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
+`endif
stimulus_done = 1;
end
/rtl_sim/src/core.f
0,0 → 1,59
//============================================================================= |
// Copyright (C) 2001 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//----------------------------------------------------------------------------- |
// |
// File Name: submit.f |
// |
// Author(s): |
// - Olivier Girard, olgirard@gmail.com |
// |
//----------------------------------------------------------------------------- |
// $Rev: 103 $ |
// $LastChangedBy: olivier.girard $ |
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ |
//============================================================================= |
|
//============================================================================= |
// Module specific modules |
//============================================================================= |
../../../rtl/verilog/openMSP430_defines.v |
../../../rtl/verilog/openMSP430.v |
../../../rtl/verilog/omsp_frontend.v |
../../../rtl/verilog/omsp_execution_unit.v |
../../../rtl/verilog/omsp_register_file.v |
../../../rtl/verilog/omsp_alu.v |
../../../rtl/verilog/omsp_sfr.v |
../../../rtl/verilog/omsp_clock_module.v |
../../../rtl/verilog/omsp_mem_backbone.v |
../../../rtl/verilog/omsp_watchdog.v |
../../../rtl/verilog/omsp_dbg.v |
../../../rtl/verilog/omsp_dbg_uart.v |
../../../rtl/verilog/omsp_dbg_hwbrk.v |
../../../rtl/verilog/omsp_multiplier.v |
../../../rtl/verilog/omsp_sync_reset.v |
../../../rtl/verilog/omsp_sync_cell.v |
../../../rtl/verilog/omsp_scan_mux.v |
../../../rtl/verilog/omsp_and_gate.v |
../../../rtl/verilog/omsp_wakeup_cell.v |
../../../rtl/verilog/omsp_clock_gate.v |
../../../rtl/verilog/omsp_clock_mux.v |
rtl_sim/src/core.f
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/tA_compare.v
===================================================================
--- rtl_sim/src/tA_compare.v (revision 128)
+++ rtl_sim/src/tA_compare.v (revision 134)
@@ -48,6 +48,14 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
+
// TIMER A TEST: UP MODE
//--------------------------------------------------------
@@ -245,6 +253,8 @@
if (mem226 !== 16'h2480) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
if (mem228 !== 16'h2081) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
+`endif
+
stimulus_done = 1;
end
/rtl_sim/src/two-op_add-b.v
64,7 → 64,7
//-------------------------------------------------------- |
@(r15==16'h1000); |
|
if (r2 !==16'h0022) tb_error("R2 initialization"); |
if (r2 !==16'h0002) tb_error("R2 initialization"); |
if (r3 !==16'h3333) tb_error("R3 initialization"); |
if (r4 !==16'h4444) tb_error("R4 initialization"); |
if (r5 !==16'h5555) tb_error("R5 initialization"); |
/rtl_sim/src/submit.f
44,26 → 44,20
|
|
//============================================================================= |
// Module specific modules |
// CPU |
//============================================================================= |
|
+incdir+../../../rtl/verilog/ |
-f ../src/core.f |
|
|
//============================================================================= |
// Peripherals |
//============================================================================= |
|
+incdir+../../../rtl/verilog/periph/ |
../../../rtl/verilog/openMSP430_defines.v |
../../../rtl/verilog/openMSP430.v |
../../../rtl/verilog/omsp_frontend.v |
../../../rtl/verilog/omsp_execution_unit.v |
../../../rtl/verilog/omsp_register_file.v |
../../../rtl/verilog/omsp_alu.v |
../../../rtl/verilog/omsp_mem_backbone.v |
../../../rtl/verilog/omsp_clock_module.v |
../../../rtl/verilog/omsp_sfr.v |
../../../rtl/verilog/omsp_dbg.v |
../../../rtl/verilog/omsp_dbg_hwbrk.v |
../../../rtl/verilog/omsp_dbg_uart.v |
../../../rtl/verilog/omsp_watchdog.v |
../../../rtl/verilog/omsp_multiplier.v |
../../../rtl/verilog/omsp_sync_cell.v |
../../../rtl/verilog/periph/omsp_gpio.v |
../../../rtl/verilog/periph/omsp_timerA.v |
//../../../rtl/verilog/periph/omsp_uart.v |
../../../rtl/verilog/periph/template_periph_8b.v |
../../../rtl/verilog/periph/template_periph_16b.v |
/rtl_sim/src/two-op_mov-b.v
64,7 → 64,7
//-------------------------------------------------------- |
@(r15==16'h1000); |
|
if (r2 !==16'h0022) tb_error("R2 initialization"); |
if (r2 !==16'h0002) tb_error("R2 initialization"); |
if (r3 !==16'h3333) tb_error("R3 initialization"); |
if (r4 !==16'h4444) tb_error("R4 initialization"); |
if (r5 !==16'h5555) tb_error("R5 initialization"); |
/rtl_sim/src/two-op_autoincr.v
0,0 → 1,929
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */ |
/*---------------------------------------------------------------------------*/ |
/* Test the MOV instruction with all addressing modes */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
initial |
begin |
$display(" ==============================================="); |
$display("| START SIMULATION |"); |
$display(" ==============================================="); |
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
// Initialize memory |
//-------------------------------------------------------- |
@(mem200==16'h0000); |
|
@(mem200==16'h0001); |
if (mem200 !== 16'h0001) tb_error("====== Initialize memory error: @0x200 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Initialize memory error: @0x202 ====="); |
if (mem204 !== 16'h1111) tb_error("====== Initialize memory error: @0x204 ====="); |
if (mem206 !== 16'h2222) tb_error("====== Initialize memory error: @0x206 ====="); |
if (mem208 !== 16'h3333) tb_error("====== Initialize memory error: @0x208 ====="); |
if (mem20A !== 16'h4444) tb_error("====== Initialize memory error: @0x20A ====="); |
if (mem20C !== 16'h5555) tb_error("====== Initialize memory error: @0x20C ====="); |
if (mem20E !== 16'h6666) tb_error("====== Initialize memory error: @0x20E ====="); |
if (mem210 !== 16'h7777) tb_error("====== Initialize memory error: @0x210 ====="); |
if (mem212 !== 16'h8888) tb_error("====== Initialize memory error: @0x212 ====="); |
if (mem214 !== 16'h9999) tb_error("====== Initialize memory error: @0x214 ====="); |
if (mem216 !== 16'hAAAA) tb_error("====== Initialize memory error: @0x216 ====="); |
if (mem218 !== 16'hBBBB) tb_error("====== Initialize memory error: @0x218 ====="); |
if (mem21A !== 16'hCCCC) tb_error("====== Initialize memory error: @0x21A ====="); |
if (mem21C !== 16'hDDDD) tb_error("====== Initialize memory error: @0x21C ====="); |
if (mem21E !== 16'hEEEE) tb_error("====== Initialize memory error: @0x21E ====="); |
if (mem220 !== 16'hFFFF) tb_error("====== Initialize memory error: @0x220 ====="); |
if (mem222 !== 16'h1122) tb_error("====== Initialize memory error: @0x222 ====="); |
|
// Auto-increment: R1 |
//-------------------------------------------------------- |
@(mem200==16'h1000); |
if (r1 !== (`DMEM_BASE+16'h0004)) tb_error("====== Auto-increment (R1): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R1): @0x202 - test 1 ====="); |
|
@(mem200==16'h1001); |
if (r1 !== (`DMEM_BASE+16'h0006)) tb_error("====== Auto-increment (R1): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 2 ====="); |
if (mem202 !== 16'h1111) tb_error("====== Auto-increment (R1): @0x202 - test 2 ====="); |
|
@(mem200==16'h1002); |
if (r1 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R1): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 3 ====="); |
if (mem202 !== 16'h2222) tb_error("====== Auto-increment (R1): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R2 (@R2+ addressing mode generated constant 8) |
//---------------------------------------------------------------- |
@(mem200==16'h2000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 1 ====="); |
if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R2): @0x202 - test 1 ====="); |
|
@(mem200==16'h2001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 2 ====="); |
if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 2 ====="); |
if (mem202 !== 16'h0008) tb_error("====== Auto-increment (R2): @0x202 - test 2 ====="); |
|
@(mem200==16'h2002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 3 ====="); |
if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 3 ====="); |
if (mem202 !== 16'h0008) tb_error("====== Auto-increment (R2): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R3 |
//-------------------------------------------------------- |
@(mem200==16'h3000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 1 ====="); |
if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R3): @0x202 - test 1 ====="); |
|
@(mem200==16'h3001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 2 ====="); |
if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 2 ====="); |
if (mem202 !== 16'hFFFF) tb_error("====== Auto-increment (R3): @0x202 - test 2 ====="); |
|
@(mem200==16'h3002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 3 ====="); |
if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 3 ====="); |
if (mem202 !== 16'hFFFF) tb_error("====== Auto-increment (R3): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R4 |
//-------------------------------------------------------- |
@(mem200==16'h4000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 1 ====="); |
if (r4 !== (`DMEM_BASE+16'h000A)) tb_error("====== Auto-increment (R4): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R4): @0x202 - test 1 ====="); |
|
@(mem200==16'h4001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 2 ====="); |
if (r4 !== (`DMEM_BASE+16'h000C)) tb_error("====== Auto-increment (R4): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 2 ====="); |
if (mem202 !== 16'h4444) tb_error("====== Auto-increment (R4): @0x202 - test 2 ====="); |
|
@(mem200==16'h4002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 3 ====="); |
if (r4 !== (`DMEM_BASE+16'h000E)) tb_error("====== Auto-increment (R4): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 3 ====="); |
if (mem202 !== 16'h5555) tb_error("====== Auto-increment (R4): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R5 |
//-------------------------------------------------------- |
@(mem200==16'h5000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 1 ====="); |
if (r5 !== (`DMEM_BASE+16'h000C)) tb_error("====== Auto-increment (R5): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R5): @0x202 - test 1 ====="); |
|
@(mem200==16'h5001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 2 ====="); |
if (r5 !== (`DMEM_BASE+16'h000E)) tb_error("====== Auto-increment (R5): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 2 ====="); |
if (mem202 !== 16'h5555) tb_error("====== Auto-increment (R5): @0x202 - test 2 ====="); |
|
@(mem200==16'h5002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 3 ====="); |
if (r5 !== (`DMEM_BASE+16'h0010)) tb_error("====== Auto-increment (R5): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 3 ====="); |
if (mem202 !== 16'h6666) tb_error("====== Auto-increment (R5): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R6 |
//-------------------------------------------------------- |
@(mem200==16'h6000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 1 ====="); |
if (r6 !== (`DMEM_BASE+16'h000E)) tb_error("====== Auto-increment (R6): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R6): @0x202 - test 1 ====="); |
|
@(mem200==16'h6001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 2 ====="); |
if (r6 !== (`DMEM_BASE+16'h0010)) tb_error("====== Auto-increment (R6): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 2 ====="); |
if (mem202 !== 16'h6666) tb_error("====== Auto-increment (R6): @0x202 - test 2 ====="); |
|
@(mem200==16'h6002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 3 ====="); |
if (r6 !== (`DMEM_BASE+16'h0012)) tb_error("====== Auto-increment (R6): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 3 ====="); |
if (mem202 !== 16'h7777) tb_error("====== Auto-increment (R6): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R7 |
//-------------------------------------------------------- |
@(mem200==16'h7000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 1 ====="); |
if (r7 !== (`DMEM_BASE+16'h0010)) tb_error("====== Auto-increment (R7): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R7): @0x202 - test 1 ====="); |
|
@(mem200==16'h7001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 2 ====="); |
if (r7 !== (`DMEM_BASE+16'h0012)) tb_error("====== Auto-increment (R7): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 2 ====="); |
if (mem202 !== 16'h7777) tb_error("====== Auto-increment (R7): @0x202 - test 2 ====="); |
|
@(mem200==16'h7002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 3 ====="); |
if (r7 !== (`DMEM_BASE+16'h0014)) tb_error("====== Auto-increment (R7): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 3 ====="); |
if (mem202 !== 16'h8888) tb_error("====== Auto-increment (R7): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R8 |
//-------------------------------------------------------- |
@(mem200==16'h8000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 1 ====="); |
if (r8 !== (`DMEM_BASE+16'h0012)) tb_error("====== Auto-increment (R8): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R8): @0x202 - test 1 ====="); |
|
@(mem200==16'h8001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 2 ====="); |
if (r8 !== (`DMEM_BASE+16'h0014)) tb_error("====== Auto-increment (R8): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 2 ====="); |
if (mem202 !== 16'h8888) tb_error("====== Auto-increment (R8): @0x202 - test 2 ====="); |
|
@(mem200==16'h8002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 3 ====="); |
if (r8 !== (`DMEM_BASE+16'h0016)) tb_error("====== Auto-increment (R8): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 3 ====="); |
if (mem202 !== 16'h9999) tb_error("====== Auto-increment (R8): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R9 |
//-------------------------------------------------------- |
@(mem200==16'h9000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 1 ====="); |
if (r9 !== (`DMEM_BASE+16'h0014)) tb_error("====== Auto-increment (R9): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R9): @0x202 - test 1 ====="); |
|
@(mem200==16'h9001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 2 ====="); |
if (r9 !== (`DMEM_BASE+16'h0016)) tb_error("====== Auto-increment (R9): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 2 ====="); |
if (mem202 !== 16'h9999) tb_error("====== Auto-increment (R9): @0x202 - test 2 ====="); |
|
@(mem200==16'h9002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 3 ====="); |
if (r9 !== (`DMEM_BASE+16'h0018)) tb_error("====== Auto-increment (R9): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 3 ====="); |
if (mem202 !== 16'hAAAA) tb_error("====== Auto-increment (R9): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R10 |
//-------------------------------------------------------- |
@(mem200==16'hA000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 1 ====="); |
if (r10 !== (`DMEM_BASE+16'h0016)) tb_error("====== Auto-increment (R10): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R10): @0x202 - test 1 ====="); |
|
@(mem200==16'hA001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 2 ====="); |
if (r10 !== (`DMEM_BASE+16'h0018)) tb_error("====== Auto-increment (R10): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 2 ====="); |
if (mem202 !== 16'hAAAA) tb_error("====== Auto-increment (R10): @0x202 - test 2 ====="); |
|
@(mem200==16'hA002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 3 ====="); |
if (r10 !== (`DMEM_BASE+16'h001A)) tb_error("====== Auto-increment (R10): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 3 ====="); |
if (mem202 !== 16'hBBBB) tb_error("====== Auto-increment (R10): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R11 |
//-------------------------------------------------------- |
@(mem200==16'hB000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 1 ====="); |
if (r11 !== (`DMEM_BASE+16'h0018)) tb_error("====== Auto-increment (R11): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R11): @0x202 - test 1 ====="); |
|
@(mem200==16'hB001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 2 ====="); |
if (r11 !== (`DMEM_BASE+16'h001A)) tb_error("====== Auto-increment (R11): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 2 ====="); |
if (mem202 !== 16'hBBBB) tb_error("====== Auto-increment (R11): @0x202 - test 2 ====="); |
|
@(mem200==16'hB002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 3 ====="); |
if (r11 !== (`DMEM_BASE+16'h001C)) tb_error("====== Auto-increment (R11): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 3 ====="); |
if (mem202 !== 16'hCCCC) tb_error("====== Auto-increment (R11): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R12 |
//-------------------------------------------------------- |
@(mem200==16'hC000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 1 ====="); |
if (r12 !== (`DMEM_BASE+16'h001A)) tb_error("====== Auto-increment (R12): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R12): @0x202 - test 1 ====="); |
|
@(mem200==16'hC001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 2 ====="); |
if (r12 !== (`DMEM_BASE+16'h001C)) tb_error("====== Auto-increment (R12): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 2 ====="); |
if (mem202 !== 16'hCCCC) tb_error("====== Auto-increment (R12): @0x202 - test 2 ====="); |
|
@(mem200==16'hC002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 3 ====="); |
if (r12 !== (`DMEM_BASE+16'h001E)) tb_error("====== Auto-increment (R12): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 3 ====="); |
if (mem202 !== 16'hDDDD) tb_error("====== Auto-increment (R12): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R13 |
//-------------------------------------------------------- |
@(mem200==16'hD000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 1 ====="); |
if (r13 !== (`DMEM_BASE+16'h001C)) tb_error("====== Auto-increment (R13): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R13): @0x202 - test 1 ====="); |
|
@(mem200==16'hD001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 2 ====="); |
if (r13 !== (`DMEM_BASE+16'h001E)) tb_error("====== Auto-increment (R13): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 2 ====="); |
if (mem202 !== 16'hDDDD) tb_error("====== Auto-increment (R13): @0x202 - test 2 ====="); |
|
@(mem200==16'hD002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 3 ====="); |
if (r13 !== (`DMEM_BASE+16'h0020)) tb_error("====== Auto-increment (R13): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 3 ====="); |
if (mem202 !== 16'hEEEE) tb_error("====== Auto-increment (R13): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R14 |
//-------------------------------------------------------- |
@(mem200==16'hE000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 1 ====="); |
if (r14 !== (`DMEM_BASE+16'h001E)) tb_error("====== Auto-increment (R14): R14 - test 1 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R14): @0x202 - test 1 ====="); |
|
@(mem200==16'hE001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 2 ====="); |
if (r14 !== (`DMEM_BASE+16'h0020)) tb_error("====== Auto-increment (R14): R14 - test 2 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 2 ====="); |
if (mem202 !== 16'hEEEE) tb_error("====== Auto-increment (R14): @0x202 - test 2 ====="); |
|
@(mem200==16'hE002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 3 ====="); |
if (r14 !== (`DMEM_BASE+16'h0022)) tb_error("====== Auto-increment (R14): R14 - test 3 ====="); |
if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 3 ====="); |
if (mem202 !== 16'hFFFF) tb_error("====== Auto-increment (R14): @0x202 - test 3 ====="); |
|
|
// Auto-increment: R15 |
//-------------------------------------------------------- |
@(mem200==16'hF000); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 1 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 1 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 1 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 1 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 1 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 1 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 1 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 1 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 1 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 1 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 1 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 1 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 1 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 1 ====="); |
if (r15 !== (`DMEM_BASE+16'h0020)) tb_error("====== Auto-increment (R15): R15 - test 1 ====="); |
if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R15): @0x202 - test 1 ====="); |
|
@(mem200==16'hF001); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 2 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 2 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 2 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 2 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 2 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 2 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 2 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 2 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 2 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 2 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 2 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 2 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 2 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 2 ====="); |
if (r15 !== (`DMEM_BASE+16'h0022)) tb_error("====== Auto-increment (R15): R15 - test 2 ====="); |
if (mem202 !== 16'hFFFF) tb_error("====== Auto-increment (R15): @0x202 - test 2 ====="); |
|
@(mem200==16'hF002); |
if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 3 ====="); |
if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 3 ====="); |
if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 3 ====="); |
if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 3 ====="); |
if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 3 ====="); |
if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 3 ====="); |
if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 3 ====="); |
if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 3 ====="); |
if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 3 ====="); |
if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 3 ====="); |
if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 3 ====="); |
if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 3 ====="); |
if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 3 ====="); |
if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 3 ====="); |
if (r15 !== (`DMEM_BASE+16'h0024)) tb_error("====== Auto-increment (R15): R15 - test 3 ====="); |
if (mem202 !== 16'h1122) tb_error("====== Auto-increment (R15): @0x202 - test 3 ====="); |
|
|
|
|
|
stimulus_done = 1; |
end |
|
rtl_sim/src/two-op_autoincr.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic.v
===================================================================
--- rtl_sim/src/clock_module_asic.v (nonexistent)
+++ rtl_sim/src/clock_module_asic.v (revision 134)
@@ -0,0 +1,589 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the ACLK and SMCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+
+integer dco_clk_counter;
+always @ (negedge dco_clk)
+ dco_clk_counter <= dco_clk_counter+1;
+
+integer lfxt_clk_counter;
+always @ (negedge lfxt_clk)
+ lfxt_clk_counter <= lfxt_clk_counter+1;
+
+integer mclk_counter;
+always @ (posedge mclk)
+ mclk_counter <= mclk_counter+1;
+
+integer aclk_counter;
+always @ (negedge aclk)
+ aclk_counter <= aclk_counter+1;
+
+integer smclk_counter;
+always @ (negedge smclk)
+ smclk_counter <= smclk_counter+1;
+
+integer dbg_clk_counter;
+always @ (negedge dbg_clk)
+ dbg_clk_counter <= dbg_clk_counter+1;
+
+reg [15:0] reg_val;
+reg [15:0] bcsctl1_mask;
+reg [15:0] bcsctl2_mask;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ force tb_openMSP430.dut.wdt_reset = 1'b0;
+
+`ifdef ASIC
+
+ // MCLK GENERATION: SELECTING DCO_CLK
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h0001);
+ @(posedge mclk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+
+
+ `ifdef MCLK_DIVIDER
+ // ------- Divider /2 ----------
+ @(r15 === 16'h0002);
+ @(posedge mclk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ if (mclk_counter !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h0003);
+ @(posedge mclk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ if (mclk_counter !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h0004);
+ @(posedge mclk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ if (mclk_counter !== 91) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+
+ `else
+ // ------- Divider /2 ----------
+ @(r15 === 16'h0002);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h0003);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h0004);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ mclk_counter = 0;
+ repeat(735) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+
+
+ `endif
+
+ @(r15 === 16'h1000);
+
+
+ // MCLK GENERATION: SELECTING LFXT_CLK
+ //--------------------------------------------------------
+ // VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN
+ @(r15 === 16'h2000);
+
+
+ // ACLK GENERATION
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h2001);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
+`endif
+
+
+ `ifdef ACLK_DIVIDER
+ // ------- Divider /2 ----------
+ @(r15 === 16'h2002);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ #1;
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
+ if (aclk_counter !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
+ if (aclk_counter !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
+`endif
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h2003);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
+ if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
+ if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
+`endif
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h2004);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
+ if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
+ if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
+`endif
+
+ `else
+ // ------- Divider /2 ----------
+ @(r15 === 16'h2002);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ #1;
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
+`endif
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h2003);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ #1;
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
+`endif
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h2004);
+`ifdef LFXT_DOMAIN
+ @(posedge lfxt_clk);
+`else
+ @(posedge dco_clk);
+`endif
+ #1;
+ dco_clk_counter = 0;
+ lfxt_clk_counter = 0;
+ aclk_counter = 0;
+`ifdef LFXT_DOMAIN
+ repeat(54) @(posedge lfxt_clk);
+ #1;
+ if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
+`else
+ repeat(54) @(posedge dco_clk);
+ #1;
+ if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
+ if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
+`endif
+
+ `endif
+
+ @(r15 === 16'h3000);
+
+
+ // SMCLK GENERATION - DCO_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h3001);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+
+ `ifdef SMCLK_DIVIDER
+ // ------- Divider /2 ----------
+ @(r15 === 16'h3002);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h3003);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h3004);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+
+ `else
+ // ------- Divider /2 ----------
+ @(r15 === 16'h3002);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h3003);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h3004);
+ @(posedge dco_clk);
+ #1;
+ dco_clk_counter = 0;
+ smclk_counter = 0;
+ repeat(600) @(posedge dco_clk);
+ if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+
+ `endif
+
+ @(r15 === 16'h4000);
+
+
+ // SMCLK GENERATION - LFXT_CLK INPUT
+ //--------------------------------------------------------
+ // VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN
+ @(r15 === 16'h5000);
+
+
+ // CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT
+ //--------------------------------------------------------
+
+ @(r15 === 16'h5001);
+ repeat(50) @(negedge dco_clk);
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
+ cpu_en = 1'b0;
+ #(3*763*2);
+ reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk counters
+ mclk_counter = 0;
+ aclk_counter = 0;
+ smclk_counter = 0;
+
+ #(50*500); // Make sure that the CPU is stopped
+ if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
+ if (mclk_counter !== 0) tb_error("====== MCLK is not stopped (test 4) =====");
+`ifdef OSCOFF_EN
+ if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 5) =====");
+`else
+ `ifdef LFXT_DOMAIN
+ `ifdef ACLK_DIVIDER
+ if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
+ `else
+ if (aclk_counter !== 17) tb_error("====== ACLK is not running (test 5) =====");
+ `endif
+ `else
+ if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
+ `endif
+`endif
+ if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 6) =====");
+ cpu_en = 1'b1;
+
+ #(50*500); // Make sure that the CPU runs again
+ if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
+ if (mclk_counter == 0) tb_error("====== MCLK is not running (test 8) =====");
+ if (aclk_counter == 0) tb_error("====== ACLK is not running (test 9) =====");
+ if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 10) =====");
+
+
+ @(r15 === 16'h5002);
+`ifdef DBG_EN
+ repeat(50) @(posedge dco_clk);
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
+ if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");
+
+ dbg_en = 1'b1;
+ repeat(6) @(posedge mclk);
+ reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
+ mclk_counter = 0;
+ aclk_counter = 0;
+ smclk_counter = 0;
+ dbg_clk_counter = 0;
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");
+ if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");
+
+ repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs
+ if (reg_val == r14) tb_error("====== CPU is stopped (test 5) =====");
+ if (mclk_counter == 0) tb_error("====== MCLK is stopped (test 6) =====");
+ if (aclk_counter == 0) tb_error("====== ACLK is stopped (test 7) =====");
+ if (smclk_counter == 0) tb_error("====== SMCLK is stopped (test 8) =====");
+ if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is stopped (test 9) =====");
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
+ if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 11) =====");
+
+ dbg_en = 1'b0;
+ repeat(6) @(posedge mclk);
+ reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
+ mclk_counter = 0;
+ aclk_counter = 0;
+ smclk_counter = 0;
+ dbg_clk_counter = 0;
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 12) =====");
+ if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 13) =====");
+
+ repeat(500) @(posedge dco_clk); // Make sure that the DBG interface is stopped
+ if (reg_val == r14) tb_error("====== CPU is not running (test 14) =====");
+ if (mclk_counter == 0) tb_error("====== MCLK is not running (test 15) =====");
+ if (aclk_counter == 0) tb_error("====== ACLK is not running (test 16) =====");
+ if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 17) =====");
+ if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 18) =====");
+ if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 19) =====");
+ if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 20) =====");
+
+ if (r15 !== 16'h5002) tb_error("====== DBG_EN did generate a PUC reset (test 21) =====");
+`endif
+
+ @(r15 === 16'h6000);
+
+
+ // RD/WR ACCESS TO REGISTERS
+ //--------------------------------------------------------
+
+ bcsctl1_mask = 16'h0000;
+ bcsctl2_mask = 16'h0000;
+
+`ifdef ASIC
+ `ifdef ACLK_DIVIDER
+ bcsctl1_mask = bcsctl1_mask | 16'h0030;
+ `endif
+`else
+ bcsctl1_mask = bcsctl1_mask | 16'h0030;
+`endif
+
+`ifdef MCLK_MUX
+ bcsctl2_mask = bcsctl2_mask | 16'h0080;
+`endif
+`ifdef MCLK_DIVIDER
+ bcsctl2_mask = bcsctl2_mask | 16'h0030;
+`endif
+`ifdef ASIC
+ `ifdef SMCLK_MUX
+ bcsctl2_mask = bcsctl2_mask | 16'h0008;
+ `endif
+ `ifdef SMCLK_DIVIDER
+ bcsctl2_mask = bcsctl2_mask | 16'h0006;
+ `endif
+`else
+ bcsctl2_mask = bcsctl2_mask | 16'h0008;
+ bcsctl2_mask = bcsctl2_mask | 16'h0006;
+`endif
+
+ @(r15 === 16'h7000);
+ if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
+ if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
+
+ if (r6 !== bcsctl1_mask) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
+ if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
+
+ if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
+ if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
+
+ if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
+ if (r11 !== bcsctl2_mask) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
+
+ if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
+ if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/clock_module_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/lp_modes_asic.v
===================================================================
--- rtl_sim/src/lp_modes_asic.v (nonexistent)
+++ rtl_sim/src/lp_modes_asic.v (revision 134)
@@ -0,0 +1,765 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU LOW POWER MODES */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU Low Power modes: */
+/* - LPM0 <=> CPUOFF */
+/* - LPM1 <=> CPUOFF + SCG0 */
+/* - LPM2 <=> CPUOFF + SCG1 */
+/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
+/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
+/* */
+/* Reminder: */
+/* - CPUOFF <=> turns off CPU. */
+/* - SCG0 <=> turns off DCO. */
+/* - SCG1 <=> turns off SMCLK. */
+/* - OSCOFF <=> turns off LFXT_CLK. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 95 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
+/*===========================================================================*/
+
+integer dco_clk_cnt;
+always @(negedge dco_clk)
+ dco_clk_cnt <= dco_clk_cnt+1;
+
+integer mclk_cnt;
+always @(negedge mclk)
+ mclk_cnt <= mclk_cnt+1;
+
+integer smclk_cnt;
+always @(negedge smclk)
+ smclk_cnt <= smclk_cnt+1;
+
+integer aclk_cnt;
+always @(negedge aclk)
+ aclk_cnt <= aclk_cnt+1;
+
+integer inst_cnt;
+always @(inst_number)
+ inst_cnt <= inst_cnt+1;
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup2_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup2_sync <= 2'b00;
+ else wkup2_sync <= {wkup2_sync[0], wkup[2]};
+
+always @(wkup2_sync)
+ irq[2] = wkup2_sync[1];
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup3_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup3_sync <= 2'b00;
+ else wkup3_sync <= {wkup3_sync[0], wkup[3]};
+
+always @(wkup3_sync)
+ irq[3] = wkup3_sync[1];
+
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ irq[2] = 0;
+ wkup[2] = 0;
+
+ irq[3] = 0;
+ wkup[3] = 0;
+
+
+`ifdef ASIC
+
+ // ACTIVE
+ //--------------------------------------------------------
+
+ @(r15==16'h1001);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== ACTIVE TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== ACTIVE TEST 2: MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== ACTIVE TEST 3: SMCLK IS NOT RUNNING =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== ACTIVE TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== ACTIVE TEST 4: ACLK IS NOT RUNNING =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== ACTIVE TEST 5: CPU IS NOT EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+
+ // LPM0 ( CPUOFF )
+ //--------------------------------------------------------
+
+ @(r15==16'h2001);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM0 TEST 2: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 3: SMCLK IS NOT RUNNING =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM0 TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM0 TEST 4: ACLK IS NOT RUNNING =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM0 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ @(posedge dco_clk); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM0 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM0 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM0 TEST 12: MCLK IS RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM0 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM0 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM0 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM0 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM0 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM0 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM0 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM1 ( CPUOFF + SCG0 )
+ //--------------------------------------------------------
+
+ @(r15==16'h3001);
+ // Until the SMCLK clock mux is implemented, force SMCLK to LFXT_CLK;
+ force dut.clock_module_0.nodiv_smclk = lfxt_clk;
+ //force dut.clock_module_0.smclk = lfxt_clk;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM1 TEST 1: DCO_CLK IS RUNNING =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM1 TEST 2: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM1 TEST 3: SMCLK IS NOT RUNNING =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM1 TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM1 TEST 4: ACLK IS RUNNING =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM1 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM1 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM1 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM1 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(15*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM1 TEST 11: DCO_CLK IS RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM1 TEST 12: MCLK IS RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM1 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM1 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM1 TEST 14: ACLK IS RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM1 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM1 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM1 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM1 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM1 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM1 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM1 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM2 ( CPUOFF + SCG1 )
+ //--------------------------------------------------------
+
+ @(r15==16'h4001);
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM2 TEST 2: MCLK IS RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM2 TEST 3: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt !== 3) tb_error("====== LPM2 TEST 3: SMCLK IS NOT RUNNING =====");
+`endif
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM2 TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM2 TEST 4: ACLK IS NOT RUNNING =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM2 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM2 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM2 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM2 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM2 TEST 12: MCLK IS RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM2 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+`else
+ if (smclk_cnt !== 3) tb_error("====== LPM2 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+`endif
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM2 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM2 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM2 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM2 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM2 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM2 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM2 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM2 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM2 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM3 ( CPUOFF + SCG0 + SCG1 )
+ //--------------------------------------------------------
+
+ @(r15==16'h5001);
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM3 TEST 1: DCO_CLK IS RUNNING =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM3 TEST 2: MCLK IS RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM3 TEST 3: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt !== 3) tb_error("====== LPM3 TEST 3: SMCLK IS NOT RUNNING =====");
+`endif
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM3 TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM3 TEST 4: ACLK IS RUNNING =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM3 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM3 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM3 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM3 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM3 TEST 11: DCO_CLK IS RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM3 TEST 12: MCLK IS RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM3 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+`else
+ if (smclk_cnt !== 3) tb_error("====== LPM3 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+`endif
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM3 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM3 TEST 14: ACLK IS RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt !== 0) tb_error("====== LPM3 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM3 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM3 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM3 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM3 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM3 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM3 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM4 ( CPUOFF + SCG0 + SCG1 + OSCOFF)
+ //--------------------------------------------------------
+
+ @(r15==16'h6001);
+
+ #(100*70);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM4 TEST 1: DCO_CLK IS RUNNING =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM4 TEST 2: MCLK IS RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 3: SMCLK IS RUNNING =====");
+`else
+ `ifdef OSCOFF_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 3: SMCLK IS RUNNING =====");
+ `else
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 3: SMCLK IS NOT RUNNING =====");
+ `endif
+`endif
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 4: ACLK IS RUNNING =====");
+`else
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 4: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 4: ACLK IS RUNNING =====");
+ `endif
+`endif
+ if (inst_cnt !== 0) tb_error("====== LPM4 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 3) tb_error("====== LPM4 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== LPM4 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM4 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== LPM4 TEST 11: DCO_CLK IS RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 0) tb_error("====== LPM4 TEST 12: MCLK IS RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+`else
+ `ifdef OSCOFF_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+ `else
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+`endif
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 14: ACLK IS RUNNING AFTER IRQ =====");
+`else
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 14: ACLK IS RUNNING AFTER IRQ =====");
+ `endif
+`endif
+ if (inst_cnt !== 0) tb_error("====== LPM4 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM4 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== LPM4 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/lp_modes_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/op_modes.v
===================================================================
--- rtl_sim/src/op_modes.v (revision 128)
+++ rtl_sim/src/op_modes.v (revision 134)
@@ -57,6 +57,13 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
// SCG1 (<=> R2[7]): turn off SMCLK
//--------------------------------------------------------
@@ -184,7 +191,8 @@
repeat (80) @(negedge mclk);
if (inst_cnt <= 16'h0030) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
-
+`endif
+
stimulus_done = 1;
end
/rtl_sim/src/lp_modes_dbg_asic.s43
0,0 → 1,230
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* CPU OPERATING MODES */ |
/*---------------------------------------------------------------------------*/ |
/* Test the CPU Low Power modes: */ |
/* - LPM0 <=> CPUOFF */ |
/* - LPM1 <=> CPUOFF + SCG0 */ |
/* - LPM2 <=> CPUOFF + SCG1 */ |
/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */ |
/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */ |
/* */ |
/* Reminder: */ |
/* - CPUOFF <=> turns off CPU. */ |
/* - SCG0 <=> turns off DCO. */ |
/* - SCG1 <=> turns off SMCLK. */ |
/* - OSCOFF <=> turns off LFXT_CLK. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
.set DMEM_BASE, (__data_start ) |
.set DMEM_200, (__data_start+0x00) |
.set DMEM_250, (__data_start+0x50) |
|
.set BCSCTL1, 0x0057 |
.set BCSCTL2, 0x0058 |
|
.macro LPM0 |
bis #0x0010, r2 |
.endm |
.macro LPM1 |
bis #0x0050, r2 |
.endm |
.macro LPM2 |
bis #0x0090, r2 |
.endm |
.macro LPM3 |
bis #0x00D0, r2 |
.endm |
.macro LPM4 |
bis #0x00F0, r2 |
.endm |
|
.macro LPM0_exit |
bic #0x0010, @r1 |
.endm |
.macro LPM1_exit |
bic #0x0050, @r1 |
.endm |
.macro LPM2_exit |
bic #0x0090, @r1 |
.endm |
.macro LPM3_exit |
bic #0x00D0, @r1 |
.endm |
.macro LPM4_exit |
bic #0x00F0, @r1 |
.endm |
|
|
WAIT_FUNC: |
dec r14 |
jnz WAIT_FUNC |
ret |
|
main: |
|
; Initialize stack and enable global interrupts |
mov #DMEM_250, r1 |
eint |
|
; Wait for a while to give enough time to ACLK |
mov #0x0050, r14 |
call #WAIT_FUNC |
mov #0x1000, r15 |
|
/* --------------- ACTIVE ------------------------------------------ */ |
|
mov #0x1001, r15 |
mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = DCO_CLK |
mov #0x0080, r14 |
call #WAIT_FUNC |
|
mov #0x2000, r15 |
|
|
/* --------------- LPM0 ( CPUOFF ) -------------------------------- */ |
|
mov #0x2001, r15 |
mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = DCO_CLK |
|
LPM0 ; # MCLK off |
mov #0x0090, r14 |
call #WAIT_FUNC |
|
mov #0x3000, r15 |
|
|
/* --------------- LPM1 ( CPUOFF + SCG0 ) ------------------------- */ |
|
mov #0x3001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM1 ; # MCLK off + DCO off |
mov #0x0090, r14 |
call #WAIT_FUNC |
|
mov #0x4000, r15 |
|
|
/*---------------- LPM2 ( CPUOFF + SCG1 ) ------------------------- */ |
|
mov #0x4001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM2 ; # MCLK off + SMCLK off |
mov #0x0190, r14 |
call #WAIT_FUNC |
|
mov #0x5000, r15 |
|
|
/*---------------- LPM3 ( CPUOFF + SCG0 + SCG1 ) ------------------ */ |
|
mov #0x5001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM3 ; # MCLK off + DCO off + SMCLK off |
mov #0x0190, r14 |
call #WAIT_FUNC |
|
mov #0x6000, r15 |
|
|
/*---------------- LPM4 ( CPUOFF + SCG0 + SCG1 + OSCOFF ) --------- */ |
|
mov #0x6001, r15 |
mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK |
; # SMCLK = LFXT_CLK |
|
LPM4 ; # MCLK off + DCO off + SMCLK off + LFXT off |
mov #0x0100, r14 |
call #WAIT_FUNC |
|
mov #0x6000, r15 |
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
/* ---------------------- INTERRUPT ROUTINES --------------- */ |
|
PORT1_VECTOR: |
push r13 |
push r14 |
mov #0x0060, r14 |
call #WAIT_FUNC |
mov #0xaaaa, r13 |
pop r14 |
pop r13 |
reti |
|
PORT2_VECTOR: |
push r13 |
push r14 |
mov #0x0060, r14 |
call #WAIT_FUNC |
mov #0xbbbb, r13 |
pop r14 |
pop r13 |
bic #0xf0, 0(r1) ;exit all lowpower mode |
reti |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word PORT1_VECTOR ; Interrupt 2 <unused> |
.word PORT2_VECTOR ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/lp_modes_dbg_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/tA_output.v
===================================================================
--- rtl_sim/src/tA_output.v (revision 128)
+++ rtl_sim/src/tA_output.v (revision 134)
@@ -49,6 +49,14 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
+
// TIMER A TEST: COMPARATOR 0
//--------------------------------------------------------
@@ -370,6 +378,7 @@
@(tar === 16'h0020);
if (ta_out2 !== 1'b1) tb_error("====== TIMER_A COMPARE 2: Reset/Set (mode 7) =====");
+`endif
stimulus_done = 1;
end
/rtl_sim/src/dbg_onoff_asic.s43
0,0 → 1,88
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* DEBUG INTERFACE */ |
/*---------------------------------------------------------------------------*/ |
/* Test the debug interface: */ |
/* - CPU Control features. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
.set DMEM_BASE, (__data_start ) |
.set DMEM_250, (__data_start+0x50) |
|
main: |
mov #DMEM_250, r1 ; Initialize stack |
mov #0x0000, r15 |
mov #0x0000, r14 |
mov #0x0000, r13 |
nop |
eint |
|
test_loop: |
add #0x0001, r14 |
cmp #0xffff, r13 |
jne test_loop |
|
mov #0x1000, r15 |
|
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
isr_1: |
mov #0xffff, r13 |
reti |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word isr_1 ; Interrupt 1 <unused> |
.word end_of_test ; Interrupt 2 <unused> |
.word end_of_test ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/dbg_onoff_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic_smclk.s43
===================================================================
--- rtl_sim/src/clock_module_asic_smclk.s43 (nonexistent)
+++ rtl_sim/src/clock_module_asic_smclk.s43 (revision 134)
@@ -0,0 +1,182 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the SMCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set BCSCTL1, 0x0057
+.set BCSCTL2, 0x0058
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+
+
+ /* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */
+
+ mov.b #0x08, &BCSCTL2 ; # Div /1
+ mov #0x0001, r15
+ mov #0x00F0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0A, &BCSCTL2 ; # Div /2
+ mov #0x0002, r15
+ mov #0x01E0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0C, &BCSCTL2 ; # Div /4
+ mov #0x0003, r15
+ mov #0x03C0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0E, &BCSCTL2 ; # Div /8
+ mov #0x0004, r15
+ mov #0x0780, r14
+ call #WAIT_FUNC
+
+ mov #0x1000, r15
+
+ /* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1
+ mov #0x1001, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x02, &BCSCTL2 ; # Div /2
+ mov #0x1002, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x04, &BCSCTL2 ; # Div /4
+ mov #0x1003, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x06, &BCSCTL2 ; # Div /8
+ mov #0x1004, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov #0x2000, r15
+
+
+ /* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */
+
+ mov.b #0x08, &BCSCTL2 ; # Div /1
+ mov #0x2001, r15
+ mov #0x00F0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0A, &BCSCTL2 ; # Div /2
+ mov #0x2002, r15
+ mov #0x01E0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0C, &BCSCTL2 ; # Div /4
+ mov #0x2003, r15
+ mov #0x03C0, r14
+ call #WAIT_FUNC
+
+ mov.b #0x0E, &BCSCTL2 ; # Div /8
+ mov #0x2004, r15
+ mov #0x0780, r14
+ call #WAIT_FUNC
+
+ mov #0x3000, r15
+
+ /* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */
+
+ mov.b #0x00, &BCSCTL2 ; # Div /1
+ mov #0x3001, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x02, &BCSCTL2 ; # Div /2
+ mov #0x3002, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x04, &BCSCTL2 ; # Div /4
+ mov #0x3003, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov.b #0x06, &BCSCTL2 ; # Div /8
+ mov #0x3004, r15
+ mov #0x0050, r14
+ call #WAIT_FUNC
+
+ mov #0x4000, r15
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/clock_module_asic_smclk.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_add.s43
===================================================================
--- rtl_sim/src/two-op_add.s43 (revision 128)
+++ rtl_sim/src/two-op_add.s43 (revision 134)
@@ -91,7 +91,7 @@
main:
/* ---------------------- INITIALIZE REGISTERS --------------------- */
- mov #0x2222, r2
+ mov #0x2202, r2
mov #0x3333, r3
mov #0x4444, r4
mov #0x5555, r5
/rtl_sim/src/clock_module_asic.s43
0,0 → 1,257
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* CLOCK MODULE */ |
/*---------------------------------------------------------------------------*/ |
/* Test the clock module: */ |
/* - Check the ACLK and SMCLK clock generation. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
.set DMEM_BASE, (__data_start ) |
.set DMEM_200, (__data_start+0x00) |
.set DMEM_250, (__data_start+0x50) |
|
.set BCSCTL1, 0x0057 |
.set BCSCTL2, 0x0058 |
|
.set WDTCTL, 0x0120 |
|
|
WAIT_FUNC: |
dec r14 |
jnz WAIT_FUNC |
ret |
|
main: |
mov #DMEM_250, r1 ; # Initialize stack pointer |
mov #0x0000, &DMEM_200 |
mov #0x0000, r15 |
|
|
/* -------------- MCLK GENERATION - DCO_CLK INPUT ----------------- */ |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x0001, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x10, &BCSCTL2 ; # Div /2 |
mov #0x0002, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x20, &BCSCTL2 ; # Div /4 |
mov #0x0003, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x30, &BCSCTL2 ; # Div /8 |
mov #0x0004, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x1000, r15 |
|
|
/* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */ |
|
# mov.b #0x80, &BCSCTL2 ; # Div /1 |
# mov #0x1001, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0x90, &BCSCTL2 ; # Div /2 |
# mov #0x1002, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0xA0, &BCSCTL2 ; # Div /4 |
# mov #0x1003, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0xB0, &BCSCTL2 ; # Div /8 |
# mov #0x1004, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x2000, r15 |
|
|
/* -------------- ACLK GENERATION ----------------- */ |
|
mov.b #0x00, &BCSCTL1 ; # Div /1 |
mov #0x2001, r15 |
mov #0x0230, r14 |
call #WAIT_FUNC |
|
mov.b #0x10, &BCSCTL1 ; # Div /2 |
mov #0x2002, r15 |
mov #0x0230, r14 |
call #WAIT_FUNC |
|
mov.b #0x20, &BCSCTL1 ; # Div /4 |
mov #0x2003, r15 |
mov #0x0230, r14 |
call #WAIT_FUNC |
|
mov.b #0x30, &BCSCTL1 ; # Div /8 |
mov #0x2004, r15 |
mov #0x0230, r14 |
call #WAIT_FUNC |
|
mov.b #0x00, &BCSCTL1 ; # Div /1 |
mov #0x3000, r15 |
|
|
/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */ |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x3001, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x02, &BCSCTL2 ; # Div /2 |
mov #0x3002, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x04, &BCSCTL2 ; # Div /4 |
mov #0x3003, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x06, &BCSCTL2 ; # Div /8 |
mov #0x3004, r15 |
mov #0x0130, r14 |
call #WAIT_FUNC |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x4000, r15 |
|
|
/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */ |
|
# mov.b #0x08, &BCSCTL2 ; # Div /1 |
# mov #0x4001, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0x0A, &BCSCTL2 ; # Div /2 |
# mov #0x4002, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0x0C, &BCSCTL2 ; # Div /4 |
# mov #0x4003, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
# mov.b #0x0E, &BCSCTL2 ; # Div /8 |
# mov #0x4004, r15 |
# mov #0x0130, r14 |
# call #WAIT_FUNC |
|
mov.b #0x00, &BCSCTL2 ; # Div /1 |
mov #0x5000, r15 |
|
|
/* -------------- CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT ----------------- */ |
|
mov #0x0800, r14 ; CPU ENABLE |
mov #0x5001, r15 |
call #WAIT_FUNC |
|
mov #0x0800, r14 ; DBG ENABLE |
mov #0x5002, r15 |
call #WAIT_FUNC |
|
mov #0x6000, r15 |
|
|
/* -------------- RD/WR ACCESS TO REGISTERS ----------------- */ |
|
mov.b #0x00, &BCSCTL1 |
mov.b #0x00, &BCSCTL2 |
mov.b &BCSCTL1, r4 |
mov.b &BCSCTL2, r5 |
|
mov.b #0xff, &BCSCTL1 |
mov.b &BCSCTL1, r6 |
mov.b &BCSCTL2, r7 |
|
mov.b #0x00, &BCSCTL1 |
mov.b &BCSCTL1, r8 |
mov.b &BCSCTL2, r9 |
|
mov.b #0xff, &BCSCTL2 |
mov.b &BCSCTL1, r10 |
mov.b &BCSCTL2, r11 |
|
mov.b #0x00, &BCSCTL2 |
mov.b &BCSCTL1, r12 |
mov.b &BCSCTL2, r13 |
|
|
mov #0x7000, r15 |
mov #0x0010, r14 |
call #WAIT_FUNC |
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word end_of_test ; Interrupt 2 <unused> |
.word end_of_test ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/clock_module_asic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic_mclk.v
===================================================================
--- rtl_sim/src/clock_module_asic_mclk.v (nonexistent)
+++ rtl_sim/src/clock_module_asic_mclk.v (revision 134)
@@ -0,0 +1,360 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the MCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+integer mclk_counter;
+always @ (negedge mclk)
+ mclk_counter <= mclk_counter+1;
+
+integer dco_clk_counter;
+always @ (negedge dco_clk)
+ dco_clk_counter <= dco_clk_counter+1;
+
+integer lfxt_clk_counter;
+always @ (negedge lfxt_clk)
+ lfxt_clk_counter <= lfxt_clk_counter+1;
+
+reg [15:0] reg_val;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ force tb_openMSP430.dut.wdt_reset = 1'b0;
+
+`ifdef ASIC
+
+ //--------------------------------------------------------
+ // MCLK GENERATION - LFXT_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h0001);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h0002);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
+ `endif
+ `endif
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h0003);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
+ `endif
+ `endif
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h0004);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
+ `endif
+ `endif
+
+
+ //--------------------------------------------------------
+ // SMCLK GENERATION - DCO_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h1001);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h1002);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h1003);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h1004);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+
+
+ //--------------------------------------------------------
+ // MCLK GENERATION - LFXT_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h2001);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h2002);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
+ `endif
+ `endif
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h2003);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
+ `endif
+ `endif
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h2004);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+ `else
+ `ifdef MCLK_MUX
+ if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
+ `endif
+ `endif
+
+
+ //--------------------------------------------------------
+ // SMCLK GENERATION - DCO_CLK INPUT
+ //--------------------------------------------------------
+
+ // ------- Divider /1 ----------
+ @(r15 === 16'h3001);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
+
+ // ------- Divider /2 ----------
+ @(r15 === 16'h3002);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /4 ----------
+ @(r15 === 16'h3003);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
+ `endif
+
+ // ------- Divider /8 ----------
+ @(r15 === 16'h3004);
+ repeat(2) @(posedge mclk);
+ mclk_counter = 0;
+ lfxt_clk_counter = 0;
+ dco_clk_counter = 0;
+ repeat(15) @(posedge mclk);
+ if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
+ `ifdef MCLK_DIVIDER
+ if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
+ `else
+ if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
+ `endif
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/clock_module_asic_mclk.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/wdt_wkup.s43
===================================================================
--- rtl_sim/src/wdt_wkup.s43 (nonexistent)
+++ rtl_sim/src/wdt_wkup.s43 (revision 134)
@@ -0,0 +1,191 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* WATCHDOG TIMER */
+/*---------------------------------------------------------------------------*/
+/* Test the Watdog timer: */
+/* - Interval timer mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+/* */
+/* Low Power modes: */
+/* - LPM0 <=> CPUOFF */
+/* - LPM1 <=> CPUOFF + SCG0 */
+/* - LPM2 <=> CPUOFF + SCG1 */
+/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
+/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
+/* */
+/* Reminder: */
+/* - CPUOFF <=> turns off CPU. */
+/* - SCG0 <=> turns off DCO. */
+/* - SCG1 <=> turns off SMCLK. */
+/* - OSCOFF <=> turns off LFXT_CLK. */
+/* */
+/*---------------------------------------------------------------------------*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set IE1, 0x0000
+.set IFG1, 0x0002
+.set WDTCTL, 0x0120
+
+.macro LPM0
+ bis #0x0010, r2
+.endm
+.macro LPM1
+ bis #0x0050, r2
+.endm
+.macro LPM2
+ bis #0x0090, r2
+.endm
+.macro LPM3
+ bis #0x00D0, r2
+.endm
+.macro LPM4
+ bis #0x00F0, r2
+.endm
+
+.macro LPM0_exit
+ bic #0x0010, @r1
+.endm
+.macro LPM1_exit
+ bic #0x0050, @r1
+.endm
+.macro LPM2_exit
+ bic #0x0090, @r1
+.endm
+.macro LPM3_exit
+ bic #0x00D0, @r1
+.endm
+.macro LPM4_exit
+ bic #0x00F0, @r1
+.endm
+
+
+main:
+
+ /* -------------- WATCHDOG TEST: WAKE-UP INTERVAL MODE ------------ */
+
+ mov &IFG1, r4
+ cmp #0x0001, &IFG1 ;# Check if we come out of a watchdog reset
+ jeq end_of_test
+
+ mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
+ eint
+ bis.b #0x01, &IE1
+
+ mov #0x0000, r6
+
+ mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 and select ACLK
+
+ mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
+ bit #0x0004, r5
+ jnz lpm3_test
+ lpm0_test:
+ mov #0x1000, r15
+ LPM0
+ jmp lpm_test_done
+ lpm3_test:
+ mov #0x1000, r15
+ LPM3
+ lpm_test_done:
+
+ /* -------------- WATCHDOG TEST: WAKE-UP RESET MODE ------------ */
+
+ mov #0x5a0f, &WDTCTL ;# Enable reset mode /64 and select ACLK
+ mov #0x5555, r7
+
+ mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
+ bit #0x0004, r5
+ jnz lpm3_rst_test
+ lpm0_rst_test:
+ mov #0x1000, r15
+ LPM0
+ jmp lpm_rst_test_done
+ lpm3_rst_test:
+ mov #0x1000, r15
+ LPM3
+ lpm_rst_test_done:
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ mov #0x5000, r15
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT ROUTINES --------------- */
+
+WDOG_VECTOR:
+ inc r6 ;# Increment counter variable
+ cmp #10, r6
+ jl end_of_irq
+
+ mov &WDTCTL, r5 ;# If ACLK is selected, exit LPM3... otherwhise exit LPM0
+ bit #0x0004, r5
+ jnz lpm3_test_exit
+ lpm0_test_exit:
+ mov #0x2000, r15
+ LPM0_exit
+ reti
+ lpm3_test_exit:
+ mov #0x2000, r15
+ LPM3_exit
+
+ end_of_irq:
+ mov #0x6666, r7
+ reti
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/wdt_wkup.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_mov.s43
===================================================================
--- rtl_sim/src/two-op_mov.s43 (revision 128)
+++ rtl_sim/src/two-op_mov.s43 (revision 134)
@@ -91,7 +91,7 @@
main:
/* ---------------------- INITIALIZE REGISTERS --------------------- */
- mov #0x2222, r2
+ mov #0x2202, r2
mov #0x3333, r3
mov #0x4444, r4
mov #0x5555, r5
/rtl_sim/src/wdt_clkmux.v
53,6 → 53,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef WATCHDOG |
|
// WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2 |
//-------------------------------------------------------- |
63,10 → 64,34
mclk_counter = 0; |
r5_counter = 0; |
repeat(1024) @(negedge mclk); |
if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK ====="); |
if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK ====="); |
if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 ====="); |
`ifdef ASIC |
`ifdef WATCHDOG_MUX |
`ifdef SMCLK_DIVIDER |
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 ====="); |
`else |
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 ====="); |
`endif |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
`ifdef LFXT_DOMAIN |
if (r5_counter !== 0) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 ====="); |
`else |
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 ====="); |
`endif |
`else |
`ifdef SMCLK_DIVIDER |
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 ====="); |
`else |
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 ====="); |
`endif |
`endif |
`endif |
`else |
if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 ====="); |
`endif |
|
|
|
// WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1 |
//-------------------------------------------------------- |
|
76,10 → 101,32
mclk_counter = 0; |
r5_counter = 0; |
repeat(7815) @(negedge mclk); |
if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK ====="); |
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK ====="); |
if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 ====="); |
`ifdef ASIC |
`ifdef WATCHDOG_MUX |
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 ====="); |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
`ifdef LFXT_DOMAIN |
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 ====="); |
`else |
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 ====="); |
`endif |
`else |
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 ====="); |
`endif |
`endif |
`else |
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 ====="); |
`endif |
|
|
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (the Watchdog is not included) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
|
stimulus_done = 1; |
end |
/rtl_sim/src/dbg_onoff_asic.v
0,0 → 1,260
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* DEBUG INTERFACE */ |
/*---------------------------------------------------------------------------*/ |
/* Test the debug interface: */ |
/* - CPU Control features. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 95 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ |
/*===========================================================================*/ |
|
|
integer test_nr; |
integer test_var; |
|
integer dco_clk_counter; |
always @ (negedge dco_clk) |
dco_clk_counter <= dco_clk_counter+1; |
|
integer dbg_clk_counter; |
always @ (negedge dbg_clk) |
dbg_clk_counter <= dbg_clk_counter+1; |
|
|
initial |
begin |
$display(" ==============================================="); |
$display("| START SIMULATION |"); |
$display(" ==============================================="); |
`ifdef DBG_EN |
`ifdef ASIC |
test_nr = 0; |
#1 dbg_en = 0; |
repeat(30) @(posedge dco_clk); |
stimulus_done = 0; |
|
// Make sure the CPU always starts executing when the |
// debug interface is disabled during POR. |
// Also make sure that the debug interface clock is stopped |
// and that it is under reset |
//-------------------------------------------------------- |
dbg_en = 0; |
test_nr = 1; |
|
@(negedge dco_clk) dbg_clk_counter = 0; |
|
repeat(300) @(posedge dco_clk); |
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); |
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) ====="); |
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) ====="); |
test_var = r14; |
|
|
// Make sure that enabling the debug interface after the POR |
// don't stop the cpu |
// Also make sure that the debug interface clock is running |
// and that its reset is released |
//-------------------------------------------------------- |
dbg_en = 1; |
test_nr = 2; |
|
@(negedge dco_clk) dbg_clk_counter = 0; |
|
repeat(300) @(posedge dco_clk); |
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 ====="); |
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) ====="); |
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) ====="); |
|
|
// Make sure that disabling the CPU with debug enabled |
// will stop the CPU |
// Also make sure that the debug interface clock is stopped |
// and that it is NOT under reset |
//-------------------------------------------------------- |
cpu_en = 0; |
dbg_en = 1; |
test_nr = 3; |
|
#(6*50); |
test_var = r14; |
dbg_clk_counter = 0; |
|
#(300*50); |
if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) ====="); |
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) ====="); |
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) ====="); |
|
cpu_en = 1; |
repeat(6) @(negedge dco_clk); |
|
|
// Create POR with debug enable and observe the |
// behavior depending on the DBG_RST_BRK_EN define |
//-------------------------------------------------------- |
dbg_en = 1; |
test_nr = 4; |
|
@(posedge dco_clk); // Generate POR |
reset_n = 1'b0; |
@(posedge dco_clk); |
reset_n = 1'b1; |
|
repeat(300) @(posedge dco_clk); |
`ifdef DBG_RST_BRK_EN |
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); |
`else |
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); |
`endif |
|
// Send uart synchronization frame |
dbg_uart_tx(DBG_SYNC); |
|
// Check CPU_CTL reset value |
dbg_uart_rd(CPU_CTL); |
`ifdef DBG_RST_BRK_EN |
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); |
`else |
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); |
`endif |
|
|
// Make sure that DBG_EN resets the debug interface |
//-------------------------------------------------------- |
test_nr = 5; |
|
// Let the CPU run |
dbg_uart_wr(CPU_CTL, 16'h0002); |
|
repeat(300) @(posedge dco_clk); |
dbg_uart_wr(CPU_CTL, 16'h0000); |
dbg_uart_wr(MEM_DATA, 16'haa55); |
dbg_uart_rd(CPU_CTL); |
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); |
dbg_uart_rd(MEM_DATA); |
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); |
|
|
test_var = r14; // Backup the current register value |
|
|
@(posedge dco_clk); // Resets the debug interface |
dbg_en = 1'b0; |
repeat(2) @(posedge dco_clk); |
dbg_en = 1'b1; |
|
// Make sure that the register was not reseted |
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); |
repeat(2) @(posedge dco_clk); |
|
// Send uart synchronization frame |
dbg_uart_tx(DBG_SYNC); |
|
// Check CPU_CTL reset value |
dbg_uart_rd(CPU_CTL); |
`ifdef DBG_RST_BRK_EN |
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); |
`else |
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); |
`endif |
dbg_uart_rd(MEM_DATA); |
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); |
|
|
// Make sure that RESET_N resets the debug interface |
//-------------------------------------------------------- |
test_nr = 6; |
|
// Let the CPU run |
dbg_uart_wr(CPU_CTL, 16'h0002); |
|
repeat(300) @(posedge dco_clk); |
dbg_uart_wr(CPU_CTL, 16'h0000); |
dbg_uart_wr(MEM_DATA, 16'haa55); |
dbg_uart_rd(CPU_CTL); |
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); |
dbg_uart_rd(MEM_DATA); |
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); |
|
test_nr = 7; |
|
@(posedge dco_clk); // Generates POR |
reset_n = 1'b0; |
repeat(2) @(posedge dco_clk); |
reset_n = 1'b1; |
|
// Make sure that the register was reseted |
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); |
repeat(2) @(posedge dco_clk); |
|
// Send uart synchronization frame |
dbg_uart_tx(DBG_SYNC); |
|
test_nr = 8; |
|
// Check CPU_CTL reset value |
dbg_uart_rd(CPU_CTL); |
`ifdef DBG_RST_BRK_EN |
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); |
`else |
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); |
`endif |
dbg_uart_rd(MEM_DATA); |
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); |
|
|
// Let the CPU run |
dbg_uart_wr(CPU_CTL, 16'h0002); |
|
test_nr = 9; |
|
// Generate IRQ to terminate the test pattern |
irq[1] = 1'b1; |
@(r13); |
irq[1] = 1'b0; |
|
stimulus_done = 1; |
|
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in FPGA mode) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
`else |
|
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (serial debug interface not included) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
end |
|
rtl_sim/src/dbg_onoff_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/dbg_uart_sync.v
===================================================================
--- rtl_sim/src/dbg_uart_sync.v (nonexistent)
+++ rtl_sim/src/dbg_uart_sync.v (revision 134)
@@ -0,0 +1,266 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* DEBUG INTERFACE: UART */
+/*---------------------------------------------------------------------------*/
+/* Test the UART debug interface: */
+/* - Check synchronization of the serial */
+/* debug interface input. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 95 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
+/*===========================================================================*/
+
+`define VERY_LONG_TIMEOUT
+
+integer ii;
+reg [15:0] jj;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+`ifdef DBG_EN
+`ifdef DBG_UART
+ #1 dbg_en = 1;
+ repeat(30) @(posedge mclk);
+ stimulus_done = 0;
+
+ // Enable metastablity emulation for the RXD path
+ dbg_uart_rxd_meta = 1'b1;
+
+ //--------------------------------------------------------
+ // TRY VARIOUS SERIAL DEBUG INTERFACE TRANSFER
+ // WITH DIFFERENT BAUD-RATES
+ //--------------------------------------------------------
+
+ for ( ii=0; ii < 500; ii=ii+1)
+ begin
+ #1 reset_n = 0;
+ repeat(1) @(posedge mclk);
+ #1 reset_n = 1;
+ repeat(10) @(posedge mclk);
+
+ UART_PERIOD = 650 + 1*ii;
+ $display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
+
+ // SEND UART SYNCHRONIZATION FRAME
+ dbg_uart_sync;
+
+ // READ CPU_ID
+ dbg_uart_rd(CPU_ID_LO);
+ if (dbg_uart_buf !== dbg_cpu_id[15:0])
+ begin
+ $display("CPU_ID_LO: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[15:0]);
+ tb_error("====== CPU_ID_LO incorrect (test 1) =====");
+ force_end_of_sim;
+ end
+ dbg_uart_rd(CPU_ID_HI);
+ if (dbg_uart_buf !== dbg_cpu_id[31:16])
+ begin
+ $display("CPU_ID_HI: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[31:16]);
+ tb_error("====== CPU_ID_HI incorrect (test 1) =====");
+ force_end_of_sim;
+ end
+
+ //-----------------------------------
+ // MAKE SOME READ/WRITE ACCESS
+ //-----------------------------------
+ jj = 'h4328;
+ dbg_uart_wr(MEM_DATA, 16'h4328);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h4328)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x4328", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 1) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h3280;
+ dbg_uart_wr(MEM_DATA, 16'h3280);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h3280)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x3280", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h2800;
+ dbg_uart_wr(MEM_DATA, 16'h2800);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h2800)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x2800", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 1) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h8000;
+ dbg_uart_wr(MEM_DATA, 16'h8000);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h8000)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x8000", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h0000;
+ dbg_uart_wr(MEM_DATA, 16'h0000);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h0000)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x0000", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'hffff;
+ dbg_uart_wr(MEM_DATA, 16'hffff);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'hffff)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0xffff", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h7f7f;
+ dbg_uart_wr(MEM_DATA, 16'h7f7f);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h7f7f)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x7f7f", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h55aa;
+ dbg_uart_wr(MEM_DATA, 16'h55aa);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h55aa)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x55aa", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+
+ jj = 'h5aa5;
+ dbg_uart_wr(MEM_DATA, 16'h5aa5);
+ dbg_uart_rd(MEM_DATA);
+ if (dbg_uart_buf !== 16'h5aa5)
+ begin
+ $display("DMEM_DATA: read = 0x%-4h / expected = 0x5aa5", dbg_uart_buf);
+ tb_error("====== MEM_DATA incorrect (test 2) =====");
+ force_end_of_sim;
+ end
+ end
+
+
+ //--------------------------------------------------------
+ // TRY LONGEST POSSIBLE SYNCHRONIZATION FRAME
+ //--------------------------------------------------------
+
+ #1 reset_n = 0;
+ repeat(1) @(posedge mclk);
+ #1 reset_n = 1;
+ repeat(10) @(posedge mclk);
+
+ dbg_uart_rxd_pre = 1'b0;
+ @(posedge dut.dbg_0.dbg_uart_0.sync_cnt[`DBG_UART_XFER_CNT_W+2]);
+ dbg_uart_rxd_pre = 1'b1;
+
+ repeat(100) @(posedge mclk);
+
+ dbg_uart_rxd_pre = 1'b0;
+ @(posedge dut.dbg_0.dbg_uart_0.xfer_cnt[`DBG_UART_XFER_CNT_W-1]);
+ dbg_uart_rxd_pre = 1'b1;
+
+ repeat(100) @(posedge mclk);
+
+
+ //--------------------------------------------------------
+ // END OF TEST
+ //--------------------------------------------------------
+
+ #1 reset_n = 0;
+ repeat(1) @(posedge mclk);
+ #1 reset_n = 1;
+ repeat(10) @(posedge mclk);
+
+ UART_PERIOD = 550;
+ $display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
+
+ // SEND UART SYNCHRONIZATION FRAME
+ dbg_uart_sync;
+
+ // Let the CPU run
+ dbg_uart_wr(CPU_CTL, 16'h0002);
+
+ // Generate an IRQ
+ wkup[0] = 1'b1;
+ @(negedge mclk);
+ irq[0] = 1'b1;
+ @(negedge irq_acc[0])
+ @(negedge mclk);
+ wkup[0] = 1'b0;
+ irq[0] = 1'b0;
+
+ repeat(10) @(posedge mclk);
+
+ stimulus_done = 1;
+`else
+
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (serial debug interface UART not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+`else
+
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (serial debug interface not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+ end
+
+ task force_end_of_sim;
+ begin
+ repeat(10) @(posedge mclk);
+ $display(" ===============================================");
+ $display("| SIMULATION FAILED |");
+ $display("| (some verilog stimulus checks failed) |");
+ $display(" ===============================================");
+ $finish;
+ end
+ endtask
rtl_sim/src/dbg_uart_sync.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/dbg_onoff.v
===================================================================
--- rtl_sim/src/dbg_onoff.v (revision 128)
+++ rtl_sim/src/dbg_onoff.v (revision 134)
@@ -46,6 +46,13 @@
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DBG_EN
+ `ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+ `else
test_nr = 0;
#1 dbg_en = 0;
repeat(30) @(posedge mclk);
@@ -96,9 +103,9 @@
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
- if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
+ if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
- if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
+ if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
@@ -136,9 +143,9 @@
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
- if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
+ if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
- if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
+ if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
@@ -178,9 +185,9 @@
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
- if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
+ if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
- if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
+ if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
@@ -197,6 +204,8 @@
irq[1] = 1'b0;
stimulus_done = 1;
+
+ `endif
`else
$display(" ===============================================");
/rtl_sim/src/scan.s43
0,0 → 1,73
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* SCAN test */ |
/*---------------------------------------------------------------------------*/ |
/* The purpose of this test is to let the scan_mode and scan_enable signals */ |
/* toggle a bit in order to clean-up code coverage and give more visibility */ |
/* on potential "real" coverage loss. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
main: |
|
mov #0x0080, r14 |
wait_loop: |
dec r14 |
jnz wait_loop |
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word end_of_test ; Interrupt 2 <unused> |
.word end_of_test ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/scan.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/clock_module_asic_lfxt.s43
===================================================================
--- rtl_sim/src/clock_module_asic_lfxt.s43 (nonexistent)
+++ rtl_sim/src/clock_module_asic_lfxt.s43 (revision 134)
@@ -0,0 +1,121 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CLOCK MODULE */
+/*---------------------------------------------------------------------------*/
+/* Test the clock module: */
+/* - Check the MCLK clock generation. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.set BCSCTL1, 0x0057
+.set BCSCTL2, 0x0058
+
+.macro LPM_CUSTOM ; # Stop CPU and LFXT oscillator
+ bis #0x0030, r2
+.endm
+.macro LPM_CUSTOM_exit
+ bic #0x0030, @r1
+.endm
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ eint ; # Enable interrupts
+
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+ mov #0x0000, r10
+
+
+ /* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */
+
+ mov.b #0x80, &BCSCTL2 ; # Div /1
+ mov #0x0003, r14
+ call #WAIT_FUNC
+
+ mov #0x0001, r15 ; # First make sure CPU runs with LFXT_CLK
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x0002, r15 ; # Make sure the CPU stops and LFXT oscillator too
+ LPM_CUSTOM
+
+ mov #0x0003, r15 ; # Make sure CPU re-runs with LFXT_CLK
+ mov #0x000A, r14
+ call #WAIT_FUNC
+
+ mov #0x0004, r15
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- FUNCTIONS --------------- */
+
+IRQ00_ROUTINE:
+ add #0x5678, r10
+ LPM_CUSTOM_exit
+ reti
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/clock_module_asic_lfxt.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/op_modes_asic.v
===================================================================
--- rtl_sim/src/op_modes_asic.v (nonexistent)
+++ rtl_sim/src/op_modes_asic.v (revision 134)
@@ -0,0 +1,416 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU OPERATING MODES */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU Operating modes: */
+/* - CPUOFF (<=> R2[4]): turn off CPU. */
+/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
+/* - SCG0 (<=> R2[6]): turn off DCO. */
+/* - SCG1 (<=> R2[7]): turn off SMCLK. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 95 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
+/*===========================================================================*/
+
+integer dco_clk_cnt;
+always @(negedge dco_clk)
+ dco_clk_cnt <= dco_clk_cnt+1;
+
+integer mclk_cnt;
+always @(negedge mclk)
+ mclk_cnt <= mclk_cnt+1;
+
+integer smclk_cnt;
+always @(negedge smclk)
+ smclk_cnt <= smclk_cnt+1;
+
+integer aclk_cnt;
+always @(negedge aclk)
+ aclk_cnt <= aclk_cnt+1;
+
+integer inst_cnt;
+always @(inst_number)
+ inst_cnt = inst_cnt+1;
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup2_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup2_sync <= 2'b00;
+ else wkup2_sync <= {wkup2_sync[0], wkup[2]};
+
+always @(wkup2_sync)
+ irq[2] = wkup2_sync[1];
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup3_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup3_sync <= 2'b00;
+ else wkup3_sync <= {wkup3_sync[0], wkup[3]};
+
+always @(wkup3_sync)
+ irq[3] = wkup3_sync[1];
+
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ irq[2] = 0;
+ wkup[2] = 0;
+
+ irq[3] = 0;
+ wkup[3] = 0;
+
+
+`ifdef ASIC
+
+ // SCG1 (<=> R2[7]): turn off SMCLK
+ //--------------------------------------------------------
+
+ @(r15==16'h1001);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+ if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 1: SMCLK IS NOT RUNNING =====");
+ smclk_cnt = 0;
+
+ @(r15==16'h1002);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 2: SMCLK IS NOT STOPPED =====");
+`else
+ if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 2: SMCLK IS STOPPED =====");
+`endif
+ smclk_cnt = 0;
+
+
+ @(r15==16'h1003); //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ aclk_cnt = 0;
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (50) @(posedge mclk);
+ if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 3: SMCLK IS NOT RUNNING DURING IRQ =====");
+ smclk_cnt = 0;
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ @(r15==16'h1004);
+ smclk_cnt = 0;
+ repeat (50) @(posedge mclk);
+ if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 4: SMCLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
+ smclk_cnt = 0;
+
+
+ @(r15==16'h1005);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 5: SMCLK IS NOT STOPPED =====");
+`else
+ if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 5: SMCLK IS STOPPED =====");
+`endif
+ smclk_cnt = 0;
+
+
+ @(r15==16'h1006); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (50) @(posedge mclk);
+ if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 6: SMCLK IS NOT RUNNING DURING IRQ =====");
+ smclk_cnt = 0;
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ @(r15==16'h1007);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (50) @(posedge mclk);
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 7: SMCLK IS NOT STOPPED WHEN RETURNING FROM IRQ =====");
+`else
+ if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 7: SMCLK IS STOPPED WHEN RETURNING FROM IRQ =====");
+`endif
+ smclk_cnt = 0;
+
+
+ @(r15==16'h1008);
+ repeat (10) @(posedge mclk);
+ smclk_cnt = 0;
+ repeat (50) @(posedge mclk);
+ if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 8: SMCLK IS NOT RUNNING =====");
+ smclk_cnt = 0;
+
+
+ // OSCOFF (<=> R2[5]): turn off LFXT1CLK
+ //--------------------------------------------------------
+
+ @(r15==16'h2001);
+ repeat (10) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (200) @(posedge mclk);
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 7) tb_error("====== OSCOFF TEST 1: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 200) tb_error("====== OSCOFF TEST 1: ACLK IS NOT RUNNING =====");
+ `endif
+ aclk_cnt = 0;
+
+ @(r15==16'h2002);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 2: ACLK IS NOT STOPPED =====");
+`else
+ if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 2: ACLK IS STOPPED =====");
+`endif
+ aclk_cnt = 0;
+
+
+ @(r15==16'h2003); //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 3: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 3: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ aclk_cnt = 0;
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ @(r15==16'h2004);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 4: ACLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 4: ACLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
+ `endif
+ aclk_cnt = 0;
+
+
+ @(r15==16'h2005);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 5: ACLK IS NOT STOPPED =====");
+`else
+ if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 5: ACLK IS STOPPED =====");
+`endif
+ aclk_cnt = 0;
+
+
+ @(r15==16'h2006); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 6: ACLK IS NOT RUNNING DURING IRQ =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 6: ACLK IS NOT RUNNING DURING IRQ =====");
+ `endif
+ aclk_cnt = 0;
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ @(r15==16'h2007);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 7: ACLK IS NOT STOPPED WHEN RETURNING FROM IRQ =====");
+`else
+ if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 7: ACLK IS STOPPED WHEN RETURNING FROM IRQ =====");
+`endif
+ aclk_cnt = 0;
+
+
+ @(r15==16'h2008);
+ repeat (100) @(posedge mclk);
+ aclk_cnt = 0;
+ repeat (100) @(posedge mclk);
+ `ifdef LFXT_DOMAIN
+ if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 8: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 8: ACLK IS NOT RUNNING =====");
+ `endif
+ aclk_cnt = 0;
+
+
+ // CPUOFF (<=> R2[4]): turn off CPU
+ //--------------------------------------------------------
+
+ @(r15==16'h3001);
+ repeat (10) @(negedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(negedge dco_clk);
+ if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 1: CPU IS NOT RUNNING =====");
+
+ @(r15==16'h3002);
+ repeat (10) @(negedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(negedge dco_clk);
+ if (mclk_cnt !== 0) tb_error("====== CPUOFF TEST 2: CPU IS NOT STOPPED =====");
+
+ @(posedge dco_clk); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ repeat(10) @(negedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(negedge dco_clk);
+ if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
+ mclk_cnt = 0;
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ @(r1==(`PER_SIZE+16'h0050));
+ repeat (10) @(negedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(negedge dco_clk);
+ if (mclk_cnt !== 0) tb_error("====== CPUOFF TEST 4: CPU IS NOT STOPPED AFTER IRQ =====");
+
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ repeat (10) @(posedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(posedge dco_clk);
+ if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ =====");
+ mclk_cnt = 0;
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ @(r1==(`PER_SIZE+16'h0050));
+ repeat (10) @(negedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(negedge dco_clk);
+ if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING AFTER IRQ =====");
+
+
+
+ @(r15==16'h3003);
+ repeat (10) @(posedge dco_clk);
+ mclk_cnt = 0;
+ repeat (80) @(posedge dco_clk);
+ if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 7: CPU IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
+ mclk_cnt = 0;
+
+
+
+ // SCG0 (<=> R2[6]): turn off DCO oscillator
+ //--------------------------------------------------------
+
+ @(r15==16'h4001);
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 1: DCO IS NOT RUNNING =====");
+
+ @(r15==16'h4002);
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 0) tb_error("====== SCG0 TEST 2: DCO IS NOT STOPPED =====");
+
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 3: DCO IS NOT RUNNING DURING IRQ (PORT 1) =====");
+ dco_clk_cnt = 0;
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 0) tb_error("====== SCG0 TEST 4: DCO IS NOT STOPPED AFTER IRQ =====");
+
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 5: DCO IS NOT RUNNING DURING IRQ =====");
+ dco_clk_cnt = 0;
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 6: DCO IS NOT RUNNING AFTER IRQ =====");
+
+
+
+ @(r15==16'h4003);
+ #(10*50);
+ dco_clk_cnt = 0;
+ #(80*50);
+ if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 7: DCO IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
+ dco_clk_cnt = 0;
+
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/op_modes_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_mov.v
===================================================================
--- rtl_sim/src/two-op_mov.v (revision 128)
+++ rtl_sim/src/two-op_mov.v (revision 134)
@@ -64,7 +64,7 @@
//--------------------------------------------------------
@(r15==16'h1000);
- if (r2 !==16'h0022) tb_error("R2 initialization");
+ if (r2 !==16'h0002) tb_error("R2 initialization");
if (r3 !==16'h3333) tb_error("R3 initialization");
if (r4 !==16'h4444) tb_error("R4 initialization");
if (r5 !==16'h5555) tb_error("R5 initialization");
/rtl_sim/src/two-op_add-b.s43
120,7 → 120,7
|
main: |
/* ---------------------- INITIALIZE REGISTERS --------------------- */ |
mov #0x2222, r2 |
mov #0x2202, r2 |
mov #0x3333, r3 |
mov #0x4444, r4 |
mov #0x5555, r5 |
/rtl_sim/src/nmi.v
0,0 → 1,208
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* SINGLE-OPERAND ARITHMETIC: RETI INSTRUCTION */ |
/*---------------------------------------------------------------------------*/ |
/* Test the RETI instruction. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 95 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ |
/*===========================================================================*/ |
|
integer i; |
reg [15:0] temp_val; |
|
integer inst_cnt; |
always @(inst_number) |
inst_cnt <= inst_cnt+1; |
|
initial |
begin |
$display(" ==============================================="); |
$display("| START SIMULATION |"); |
$display(" ==============================================="); |
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef NMI |
|
// Test NMI disabled |
//-------------------------- |
@(r15==16'h1000); |
$display(" Test NMI disabled"); |
|
@(r15==16'h1001); |
#(2000); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping ====="); |
nmi = 1'b1; |
#(6000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping ====="); |
|
wkup[0] = 1'b1; |
@(negedge mclk) |
irq[0] = 1'b1; |
@(negedge irq_acc[0]) |
wkup[0] = 1'b0; |
irq[0] = 1'b0; |
|
@(r15==16'h1002); |
nmi = 1'b0; |
|
if (r6 !==16'h0000) tb_error("====== NMI disabled: NMI irq was taken ====="); |
if (r14 !==16'h0000) tb_error("====== NMI disabled: flag is set after reset ====="); |
if (r13 !==16'h0010) tb_error("====== NMI disabled: flag is not set ====="); |
if (r12 !==16'h0000) tb_error("====== NMI disabled: flag was not cleared ====="); |
if (r11 !==16'h0000) tb_error("====== NMI disabled: flag is set ====="); |
|
|
// Test NMI rising edge |
//-------------------------- |
@(r15==16'h2000); |
$display(" Test NMI rising edge"); |
|
@(r15==16'h2001); |
|
#(2000); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b1; |
|
#(2000); |
if (r6 !==16'h0001) tb_error("====== NMI rising edge: NMI irq was not taken first time ====="); |
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU did not woke up because of NMI ====="); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b0; |
|
#(4000); |
if (r6 !==16'h0001) tb_error("====== NMI rising edge: NMI irq was taken with falling edge ====="); |
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b1; |
|
#(2000); |
if (r6 !==16'h0002) tb_error("====== NMI rising edge: NMI irq was not taken second time ====="); |
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU did not woke up because of NMI ====="); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU is not running ====="); |
#(2000); |
nmi = 1'b0; |
#(4000); |
if (r6 !==16'h0002) tb_error("====== NMI rising edge: NMI irq was taken with falling edge ====="); |
|
|
// Test NMI falling edge |
//-------------------------- |
@(r15==16'h3000); |
$display(" Test NMI falling edge"); |
|
@(r15==16'h3001); |
|
#(2000); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b1; |
|
#(2000); |
if (r6 !==16'h0000) tb_error("====== NMI falling edge: NMI irq was taken with rising edge ====="); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b0; |
|
#(2000); |
if (r6 !==16'h0001) tb_error("====== NMI falling edge: NMI irq was not taken first time ====="); |
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU did not woke up because of NMI ====="); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b1; |
|
#(2000); |
if (r6 !==16'h0001) tb_error("====== NMI falling edge: NMI irq was taken with rising edge ====="); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping ====="); |
#(2000); |
nmi = 1'b0; |
|
#(2000); |
if (r6 !==16'h0002) tb_error("====== NMI falling edge: NMI irq was not taken second time ====="); |
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU did not woke up because of NMI ====="); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU is not out of LPM4 ====="); |
#(2000); |
|
|
// Test NMI nested from Maskable-IRQ |
//----------------------------------- |
@(r15==16'h4000); |
$display(" Test NMI nested from Maskable-IRQ"); |
|
@(r15==16'h4001); |
#(2000); |
inst_cnt = 0; |
#(2000); |
if (inst_cnt !==16'h0000) tb_error("====== NMI nested: CPU is not sleeping ====="); |
#(2000); |
wkup[0] = 1'b1; |
irq[0] = 1'b1; |
@(negedge irq_acc[0]) |
wkup[0] = 1'b0; |
irq[0] = 1'b0; |
nmi = 1'b1; |
|
@(r15==16'h4002); |
if (r6 !==16'h0001) tb_error("====== NMI nested: NMI irq was not taken ====="); |
if (inst_cnt ===16'h0000) tb_error("====== NMI nested: CPU did not woke up ====="); |
if (r10 !==16'h5679) tb_error("====== NMI nested: NMI was not nested from IRQ ====="); |
|
|
`else |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (the NMI support is not included) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
|
stimulus_done = 1; |
end |
|
rtl_sim/src/nmi.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/dbg_uart_sync.s43
===================================================================
--- rtl_sim/src/dbg_uart_sync.s43 (nonexistent)
+++ rtl_sim/src/dbg_uart_sync.s43 (revision 134)
@@ -0,0 +1,90 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* DEBUG INTERFACE: UART */
+/*---------------------------------------------------------------------------*/
+/* Test the UART debug interface: */
+/* - Check synchronization of the serial */
+/* debug interface input. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.global main
+
+.macro LPM0
+ bis #0x0010, r2
+.endm
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+
+ eint
+ LPM0
+
+ mov #0x1000, r15
+
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ mov #0x0010, r14
+ wait_loop:
+ dec r14
+ jnz wait_loop
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/dbg_uart_sync.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/dbg_rdwr.s43
===================================================================
--- rtl_sim/src/dbg_rdwr.s43 (nonexistent)
+++ rtl_sim/src/dbg_rdwr.s43 (revision 134)
@@ -0,0 +1,89 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* DEBUG INTERFACE: RD / WR */
+/*---------------------------------------------------------------------------*/
+/* Test the UART debug interface: */
+/* - Check RD/WR access to all adressable */
+/* debug registers. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_250, (__data_start+0x50)
+
+.global main
+
+
+WAIT_FUNC:
+ dec r14
+ jnz WAIT_FUNC
+ ret
+
+main:
+ mov #DMEM_250, r1 ; # Initialize stack pointer
+ mov #0x0000, &DMEM_200
+ mov #0x0000, r15
+
+
+ mov #0x0300, r14
+ call #WAIT_FUNC
+
+ mov #0x1000, r15
+
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/dbg_rdwr.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/sfr.s43
===================================================================
--- rtl_sim/src/sfr.s43 (nonexistent)
+++ rtl_sim/src/sfr.s43 (revision 134)
@@ -0,0 +1,175 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* Special Function Registers (SFRs) */
+/*---------------------------------------------------------------------------*/
+/* Test the SFR registers. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set DMEM_BASE, (__data_start )
+.set DMEM_200, (__data_start+0x00)
+.set DMEM_202, (__data_start+0x02)
+
+.set IE1, 0x0000
+.set IE1_HI, 0x0001
+.set IFG1, 0x0002
+.set IFG1_HI, 0x0003
+.set CPU_ID_LO, 0x0004
+.set CPU_ID_HI, 0x0006
+.set WDTCTL, 0x0120
+
+main:
+
+ /* ------- NMI ------ */
+
+ mov #0x1000, r15
+
+ ;; NMI feature is verified in the NMI.S43 test
+
+ mov #0x1001, r15
+
+
+ /* ------- WATCHDOG ------ */
+
+ mov #0x2000, r15
+
+ ;; WATCHDOG feature is verified in the WDT_*.S43 tests
+ mov #0x5a90, &WDTCTL ;# Enable interval mode & disable timer
+
+ mov #0x2001, r15
+
+
+ /* ------- READ/WRITE IFG1 ------ */
+
+ mov #0x3000, r15
+
+ mov &IFG1, r10
+ mov #0x3001, r15
+
+ mov #0x5555, &IFG1
+ mov &IFG1, r10
+ mov #0x3002, r15
+
+ mov #0xAAAA, &IFG1
+ mov &IFG1, r10
+ mov #0x3003, r15
+
+ mov.b #0x55, &IFG1
+ mov.b &IFG1, r10
+ mov #0x3004, r15
+
+ mov.b #0xAA, &IFG1_HI
+ mov.b &IFG1_HI, r10
+ mov #0x3005, r15
+
+ mov #0x0000, &IFG1
+ mov &IFG1, r10
+ mov #0x3006, r15
+
+
+ /* ------- READ/WRITE IE1 ------ */
+
+ mov #0x4000, r15
+
+ mov &IE1, r10
+ mov #0x4001, r15
+
+ mov #0x5555, &IE1
+ mov &IE1, r10
+ mov #0x4002, r15
+
+ mov #0xAAAA, &IE1
+ mov &IE1, r10
+ mov #0x4003, r15
+
+ mov.b #0x55, &IE1
+ mov.b &IE1, r10
+ mov #0x4004, r15
+
+ mov.b #0xAA, &IE1_HI
+ mov.b &IE1_HI, r10
+ mov #0x4005, r15
+
+ mov #0x0000, &IE1
+ mov &IE1, r10
+ mov #0x4006, r15
+
+
+ /* ------- READ/WRITE CPU_ID ------ */
+
+ mov #0x5000, r15
+
+ mov &CPU_ID_LO, r10
+ mov &CPU_ID_HI, r11
+ mov #0x5001, r15
+
+ mov 0x5555, &CPU_ID_LO
+ mov 0xAAAA, &CPU_ID_HI
+ mov &CPU_ID_LO, r10
+ mov &CPU_ID_HI, r11
+ mov #0x5002, r15
+
+ mov 0xAAAA, &CPU_ID_LO
+ mov 0x5555, &CPU_ID_HI
+ mov &CPU_ID_LO, r10
+ mov &CPU_ID_HI, r11
+ mov #0x5003, r15
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
rtl_sim/src/sfr.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/cpu_startup_asic.v
===================================================================
--- rtl_sim/src/cpu_startup_asic.v (nonexistent)
+++ rtl_sim/src/cpu_startup_asic.v (revision 134)
@@ -0,0 +1,666 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU STARTUP */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU startup in ASIC mode: */
+/* - Check the CPU startup depending on the */
+/* CPU_EN / DBG_EN / RESET_N signal. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+
+integer dco_clk_cnt;
+always @(negedge dco_clk)
+ dco_clk_cnt <= dco_clk_cnt+1;
+
+integer mclk_cnt;
+always @(negedge mclk)
+ mclk_cnt <= mclk_cnt+1;
+
+integer smclk_cnt;
+always @(negedge smclk)
+ smclk_cnt <= smclk_cnt+1;
+
+integer aclk_cnt;
+always @(negedge aclk)
+ aclk_cnt <= aclk_cnt+1;
+
+integer inst_cnt;
+always @(inst_number)
+ inst_cnt = inst_cnt+1;
+
+integer test_nr;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+`ifdef ASIC
+ // #### CPU_EN=0 #### DBG_EN=0 #### RESET_N=0 #### //
+ test_nr = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== 0/0/0 TEST 1: DCO_CLK IS RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 0/0/0 TEST 2: DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 0) tb_error("====== 0/0/0 TEST 3: DCO_WKUP IS SET =====");
+ if (mclk_cnt !== 0) tb_error("====== 0/0/0 TEST 4: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 0/0/0 TEST 5: SMCLK IS RUNNING =====");
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== 0/0/0 TEST 6: ACLK IS RUNNING =====");
+ if (lfxt_enable !== 0) tb_error("====== 0/0/0 TEST 7: LFXT_ENABLE IS SET =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/0/0 TEST 8: LFXT_WKUP IS SET =====");
+`else
+ `ifdef LFXT_DOMAIN
+ `ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 0/0/0 TEST 6: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== 0/0/0 TEST 6: ACLK IS RUNNING =====");
+ `endif
+ `else
+ if (aclk_cnt !== 0) tb_error("====== 0/0/0 TEST 6: ACLK IS RUNNING =====");
+ `endif
+ if (lfxt_enable !== 1) tb_error("====== 0/0/0 TEST 7: LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/0/0 TEST 8: LFXT_WKUP IS SET =====");
+`endif
+
+ if (inst_cnt !== 0) tb_error("====== 0/0/0 TEST 9: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=0 #### DBG_EN=0 #### RESET_N=1 #### //
+ test_nr = 1;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 1;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== 0/0/1 TEST 1: DCO_CLK IS RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 0/0/1 TEST 2: DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 0) tb_error("====== 0/0/1 TEST 3: DCO_WKUP IS SET =====");
+ if (mclk_cnt !== 0) tb_error("====== 0/0/1 TEST 4: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 0/0/1 TEST 5: SMCLK IS RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== 0/0/1 TEST 6: CPU IS EXECUTING =====");
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== 0/0/1 TEST 7: ACLK IS RUNNING =====");
+ if (lfxt_enable !== 0) tb_error("====== 0/0/1 TEST 8: LFXT_ENABLE IS SET =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/0/1 TEST 9: LFXT_WKUP IS SET =====");
+`else
+ `ifdef LFXT_DOMAIN
+ `ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 0/0/1 TEST 7: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== 0/0/1 TEST 7: ACLK IS RUNNING =====");
+ `endif
+ `else
+ if (aclk_cnt !== 0) tb_error("====== 0/0/1 TEST 7: ACLK IS RUNNING =====");
+ `endif
+ if (lfxt_enable !== 1) tb_error("====== 0/0/1 TEST 8: LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/0/1 TEST 9: LFXT_WKUP IS SET =====");
+`endif
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=0 #### DBG_EN=1 #### RESET_N=0 #### //
+ test_nr = 2;
+
+ cpu_en = 0;
+ dbg_en = 1;
+ reset_n = 0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== 0/1/0 TEST 1: DCO_CLK IS RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 0/1/0 TEST 2: DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 0) tb_error("====== 0/1/0 TEST 3: DCO_WKUP IS SET =====");
+ if (mclk_cnt !== 0) tb_error("====== 0/1/0 TEST 4: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 0/1/0 TEST 5: SMCLK IS RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== 0/1/0 TEST 6: CPU IS EXECUTING =====");
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== 0/1/0 TEST 7: ACLK IS RUNNING =====");
+ if (lfxt_enable !== 0) tb_error("====== 0/1/0 TEST 8: LFXT_ENABLE IS SET =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/1/0 TEST 9: LFXT_WKUP IS SET =====");
+`else
+ `ifdef LFXT_DOMAIN
+ `ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 0/1/0 TEST 7: ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== 0/1/0 TEST 7: ACLK IS NOT RUNNING =====");
+ `endif
+ `else
+ if (aclk_cnt !== 0) tb_error("====== 0/1/0 TEST 7: ACLK IS RUNNING =====");
+ `endif
+ if (lfxt_enable !== 1) tb_error("====== 0/1/0 TEST 8: LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 0/1/0 TEST 9: LFXT_WKUP IS SET =====");
+`endif
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=0 #### RESET_N=0 #### //
+ test_nr = 3;
+
+ cpu_en = 1;
+ dbg_en = 0;
+ reset_n = 0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/0/0 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 1/0/0 TEST 2: DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 1) tb_error("====== 1/0/0 TEST 3: DCO_WKUP IS CLEARED =====");
+`ifdef SYNC_CPU_EN
+ if (mclk_cnt !== 0) tb_error("====== 1/0/0 TEST 4: MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 1/0/0 TEST 5: SMCLK IS RUNNING =====");
+`else
+ if (mclk_cnt !== 100) tb_error("====== 1/0/0 TEST 4: MCLK IS NOT RUNNING =====");
+ `ifdef SMCLK_MUX
+ if (smclk_cnt !== 0) tb_error("====== 1/0/0 TEST 5: SMCLK IS NOT RUNNING =====");
+ `else
+ if (smclk_cnt !== 100) tb_error("====== 1/0/0 TEST 5: SMCLK IS NOT RUNNING =====");
+ `endif
+`endif
+ if (inst_cnt !== 0) tb_error("====== 1/0/0 TEST 6: CPU IS EXECUTING =====");
+`ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 1/0/0 TEST 7: ACLK IS RUNNING =====");
+`else
+ if (aclk_cnt < 3) tb_error("====== 1/0/0 TEST 7: ACLK IS NOT RUNNING =====");
+`endif
+`ifdef OSCOFF_EN
+ if (lfxt_enable !== 0) tb_error("====== 1/0/0 TEST 8: LFXT_ENABLE IS SET =====");
+ if (lfxt_wkup !== 1) tb_error("====== 1/0/0 TEST 9: LFXT_WKUP IS CLEARED =====");
+`else
+ if (lfxt_enable !== 1) tb_error("====== 1/0/0 TEST 8: LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/0/0 TEST 9: LFXT_WKUP IS SET =====");
+`endif
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=0 #### //
+ test_nr = 4;
+
+ cpu_en = 1;
+ dbg_en = 1;
+ reset_n = 0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/0 TEST 1 (simultaneous): DCO_CLK IS NOT RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 1/1/0 TEST 2 (simultaneous): DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 1) tb_error("====== 1/1/0 TEST 3 (simultaneous): DCO_WKUP IS CLEARED =====");
+`ifdef SYNC_CPU_EN
+ if (mclk_cnt !== 0) tb_error("====== 1/1/0 TEST 4 (simultaneous): MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 1/1/0 TEST 5 (simultaneous): SMCLK IS RUNNING =====");
+`else
+ if (mclk_cnt !== 100) tb_error("====== 1/1/0 TEST 4 (simultaneous): MCLK IS NOT RUNNING =====");
+ `ifdef SMCLK_MUX
+ if (smclk_cnt !== 0) tb_error("====== 1/1/0 TEST 5 (simultaneous): SMCLK IS NOT RUNNING =====");
+ `else
+ if (smclk_cnt !== 100) tb_error("====== 1/1/0 TEST 5 (simultaneous): SMCLK IS NOT RUNNING =====");
+ `endif
+`endif
+ if (inst_cnt !== 0) tb_error("====== 1/1/0 TEST 6 (simultaneous): CPU IS EXECUTING =====");
+`ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 1/1/0 TEST 7 (simultaneous): ACLK IS RUNNING =====");
+`else
+ if (aclk_cnt < 3) tb_error("====== 1/1/0 TEST 7 (simultaneous): ACLK IS NOT RUNNING =====");
+`endif
+`ifdef OSCOFF_EN
+ if (lfxt_enable !== 0) tb_error("====== 1/1/0 TEST 8 (simultaneous): LFXT_ENABLE IS SET =====");
+ if (lfxt_wkup !== 1) tb_error("====== 1/1/0 TEST 9 (simultaneous): LFXT_WKUP IS CLEARED =====");
+`else
+ if (lfxt_enable !== 1) tb_error("====== 1/1/0 TEST 8 (simultaneous): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/0 TEST 9 (simultaneous): LFXT_WKUP IS SET =====");
+`endif
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=0 #### RESET_N=1 #### //
+ test_nr = 5;
+
+ cpu_en = 1;
+ dbg_en = 0;
+ reset_n = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/0/1 TEST 1 (simultaneous): DCO_CLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/0/1 TEST 2 (simultaneous): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/0/1 TEST 3 (simultaneous): DCO_WKUP IS SET =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/0/1 TEST 4 (simultaneous): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/0/1 TEST 5 (simultaneous): SMCLK IS NOT RUNNING =====");
+ if (inst_cnt === 0) tb_error("====== 1/0/1 TEST 6 (simultaneous): CPU IS NOT EXECUTING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/0/1 TEST 7 (simultaneous): ACLK IS NOT RUNNING =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/0/1 TEST 8 (simultaneous): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/0/1 TEST 9 (simultaneous): LFXT_WKUP IS SET =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=0 #### DBG_EN=1 #### RESET_N=1 #### //
+ test_nr = 6;
+
+ cpu_en = 0;
+ dbg_en = 1;
+ reset_n = 1;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 0) tb_error("====== 0/1/1 TEST 1 (simultaneous): DCO_CLK IS RUNNING =====");
+ if (dco_enable !== 0) tb_error("====== 0/1/1 TEST 2 (simultaneous): DCO_ENABLE IS SET =====");
+ if (dco_wkup !== 0) tb_error("====== 0/1/1 TEST 3 (simultaneous): DCO_WKUP IS SET =====");
+ if (mclk_cnt !== 0) tb_error("====== 0/1/1 TEST 4 (simultaneous): MCLK IS RUNNING =====");
+ if (smclk_cnt !== 0) tb_error("====== 0/1/1 TEST 5 (simultaneous): SMCLK IS RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== 0/1/1 TEST 6 (simultaneous): CPU IS EXECUTING =====");
+`ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== 0/1/1 TEST 7 (simultaneous): ACLK IS RUNNING =====");
+ if (lfxt_enable !== 0) tb_error("====== 0/1/1 TEST 8 (simultaneous): LFXT_ENABLE IS SET =====");
+`else
+ `ifdef LFXT_DOMAIN
+ `ifdef ACLK_DIVIDER
+ if (aclk_cnt !== 0) tb_error("====== 0/1/1 TEST 7 (simultaneous): ACLK IS NOT RUNNING =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== 0/1/1 TEST 7 (simultaneous): ACLK IS NOT RUNNING =====");
+ `endif
+ `else
+ if (aclk_cnt !== 0) tb_error("====== 0/1/1 TEST 7 (simultaneous): ACLK IS RUNNING =====");
+ `endif
+ if (lfxt_enable !== 1) tb_error("====== 0/1/1 TEST 8 (simultaneous): LFXT_ENABLE IS CLEARED =====");
+`endif
+ if (lfxt_wkup !== 0) tb_error("====== 0/1/1 TEST 9 (simultaneous): LFXT_WKUP IS SET =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### //
+ test_nr = 7;
+
+ cpu_en = 1;
+ dbg_en = 1;
+ reset_n = 1;
+
+ #(150*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (simultaneous): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (simultaneous): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (simultaneous): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (simultaneous): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (simultaneous): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (simultaneous): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (simultaneous): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (simultaneous): LFXT_WKUP IS SET =====");
+ if (inst_cnt !== 0) tb_error("====== 1/1/1 TEST 9 (simultaneous): CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 1: RESET_N -> CPU_EN -> DBG_EN
+ test_nr = 8;
+
+ reset_n = 1;
+ #(150*50);
+ cpu_en = 1;
+ #(150*50);
+ dbg_en = 1;
+
+ #(150*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 1): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 1): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 1): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 1): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 1): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 1): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 1): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 1): LFXT_WKUP IS SET =====");
+ if (inst_cnt === 0) tb_error("====== 1/1/1 TEST 9 (sequence 1): CPU IS NOT EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 2: RESET_N -> DBG_EN -> CPU_EN
+ test_nr = 9;
+
+ reset_n = 1;
+ #(150*50);
+ dbg_en = 1;
+ #(150*50);
+ cpu_en = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 2): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 2): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 2): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 2): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 2): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 2): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 2): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 2): LFXT_WKUP IS SET =====");
+ if (inst_cnt !== 0) tb_error("====== 1/1/1 TEST 9 (sequence 2): CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 3: DBG_EN -> RESET_N -> CPU_EN
+ test_nr = 10;
+
+ dbg_en = 1;
+ #(150*50);
+ reset_n = 1;
+ #(150*50);
+ cpu_en = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 3): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 3): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 3): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 3): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 3): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 3): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 3): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 3): LFXT_WKUP IS SET =====");
+ if (inst_cnt !== 0) tb_error("====== 1/1/1 TEST 9 (sequence 3): CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 4: DBG_EN -> CPU_EN -> RESET_N
+ test_nr = 10;
+
+ dbg_en = 1;
+ #(150*50);
+ cpu_en = 1;
+ #(150*50);
+ reset_n = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 4): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 4): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 4): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 4): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 4): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 4): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 4): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 4): LFXT_WKUP IS SET =====");
+ if (inst_cnt !== 0) tb_error("====== 1/1/1 TEST 9 (sequence 4): CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 5: CPU_EN -> DBG_EN -> RESET_N
+ test_nr = 10;
+
+ cpu_en = 1;
+ #(150*50);
+ dbg_en = 1;
+ #(150*50);
+ reset_n = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 5): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 5): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 5): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 5): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 5): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 5): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 5): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 5): LFXT_WKUP IS SET =====");
+ if (inst_cnt !== 0) tb_error("====== 1/1/1 TEST 9 (sequence 5): CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ cpu_en = 0;
+ dbg_en = 0;
+ reset_n = 0;
+ #(100*50);
+
+ // #### CPU_EN=1 #### DBG_EN=1 #### RESET_N=1 #### SEQUENCE 6: CPU_EN -> RESET_N -> DBG_EN
+ test_nr = 10;
+
+ cpu_en = 1;
+ #(150*50);
+ reset_n = 1;
+ #(150*50);
+ dbg_en = 1;
+
+ #(200*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== 1/1/1 TEST 1 (sequence 6): DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== 1/1/1 TEST 2 (sequence 6): MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== 1/1/1 TEST 3 (sequence 6): SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== 1/1/1 TEST 4 (sequence 6): ACLK IS NOT RUNNING =====");
+ if (dco_enable !== 1) tb_error("====== 1/1/1 TEST 5 (sequence 6): DCO_ENABLE IS CLEARED =====");
+ if (dco_wkup !== 0) tb_error("====== 1/1/1 TEST 6 (sequence 6): DCO_WKUP IS SET =====");
+ if (lfxt_enable !== 1) tb_error("====== 1/1/1 TEST 7 (sequence 6): LFXT_ENABLE IS CLEARED =====");
+ if (lfxt_wkup !== 0) tb_error("====== 1/1/1 TEST 8 (sequence 6): LFXT_WKUP IS SET =====");
+ if (inst_cnt === 0) tb_error("====== 1/1/1 TEST 9 (sequence 6): CPU IS NOT EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(100*50);
+
+
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/cpu_startup_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/two-op_autoincr-b.v
===================================================================
--- rtl_sim/src/two-op_autoincr-b.v (nonexistent)
+++ rtl_sim/src/two-op_autoincr-b.v (revision 134)
@@ -0,0 +1,929 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */
+/*---------------------------------------------------------------------------*/
+/* Test the MOV instruction with all addressing modes */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ // Initialize memory
+ //--------------------------------------------------------
+ @(mem200==16'h0000);
+
+ @(mem200==16'h0001);
+ if (mem200 !== 16'h0001) tb_error("====== Initialize memory error: @0x200 =====");
+ if (mem202 !== 16'h1020) tb_error("====== Initialize memory error: @0x202 =====");
+ if (mem204 !== 16'h1122) tb_error("====== Initialize memory error: @0x204 =====");
+ if (mem206 !== 16'h3344) tb_error("====== Initialize memory error: @0x206 =====");
+ if (mem208 !== 16'h5566) tb_error("====== Initialize memory error: @0x208 =====");
+ if (mem20A !== 16'h7788) tb_error("====== Initialize memory error: @0x20A =====");
+ if (mem20C !== 16'h99AA) tb_error("====== Initialize memory error: @0x20C =====");
+ if (mem20E !== 16'hBBCC) tb_error("====== Initialize memory error: @0x20E =====");
+ if (mem210 !== 16'hDDEE) tb_error("====== Initialize memory error: @0x210 =====");
+ if (mem212 !== 16'hFF21) tb_error("====== Initialize memory error: @0x212 =====");
+ if (mem214 !== 16'h1223) tb_error("====== Initialize memory error: @0x214 =====");
+ if (mem216 !== 16'h3445) tb_error("====== Initialize memory error: @0x216 =====");
+ if (mem218 !== 16'h5667) tb_error("====== Initialize memory error: @0x218 =====");
+ if (mem21A !== 16'h7889) tb_error("====== Initialize memory error: @0x21A =====");
+ if (mem21C !== 16'h9AAB) tb_error("====== Initialize memory error: @0x21C =====");
+ if (mem21E !== 16'hBCCD) tb_error("====== Initialize memory error: @0x21E =====");
+ if (mem220 !== 16'hDEEF) tb_error("====== Initialize memory error: @0x220 =====");
+ if (mem222 !== 16'hF001) tb_error("====== Initialize memory error: @0x222 =====");
+
+ // Auto-increment: R1 (increment by 2 even in byte mode)
+ //--------------------------------------------------------
+ @(mem200==16'h1000);
+ if (r1 !== (`DMEM_BASE+16'h0004)) tb_error("====== Auto-increment (R1): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 1 =====");
+ if (mem202 !== 16'h1020) tb_error("====== Auto-increment (R1): @0x202 - test 1 =====");
+
+ @(mem200==16'h1001);
+ if (r1 !== (`DMEM_BASE+16'h0006)) tb_error("====== Auto-increment (R1): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 2 =====");
+ if (mem202 !== 16'h1022) tb_error("====== Auto-increment (R1): @0x202 - test 2 =====");
+
+ @(mem200==16'h1002);
+ if (r1 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R1): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R1): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R1): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R1): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R1): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R1): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R1): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R1): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R1): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R1): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R1): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R1): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R1): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R1): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R1): R15 - test 3 =====");
+ if (mem202 !== 16'h1044) tb_error("====== Auto-increment (R1): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R2 (@R2+ addressing mode generated constant 8)
+ //----------------------------------------------------------------
+ @(mem200==16'h2000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 1 =====");
+ if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R2): @0x202 - test 1 =====");
+
+ @(mem200==16'h2001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 2 =====");
+ if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 2 =====");
+ if (mem202 !== 16'h0008) tb_error("====== Auto-increment (R2): @0x202 - test 2 =====");
+
+ @(mem200==16'h2002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R2): R1 - test 3 =====");
+ if (r2 !== 16'h0004) tb_error("====== Auto-increment (R2): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R2): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R2): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R2): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R2): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R2): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R2): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R2): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R2): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R2): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R2): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R2): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R2): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R2): R15 - test 3 =====");
+ if (mem202 !== 16'h0008) tb_error("====== Auto-increment (R2): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R3
+ //--------------------------------------------------------
+ @(mem200==16'h3000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 1 =====");
+ if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R3): @0x202 - test 1 =====");
+
+ @(mem200==16'h3001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 2 =====");
+ if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 2 =====");
+ if (mem202 !== 16'h00FF) tb_error("====== Auto-increment (R3): @0x202 - test 2 =====");
+
+ @(mem200==16'h3002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R3): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R3): R2 - test 3 =====");
+ if (r3 !== (`DMEM_BASE+16'h0008)) tb_error("====== Auto-increment (R3): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R3): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R3): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R3): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R3): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R3): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R3): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R3): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R3): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R3): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R3): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R3): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R3): R15 - test 3 =====");
+ if (mem202 !== 16'h00FF) tb_error("====== Auto-increment (R3): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R4
+ //--------------------------------------------------------
+ @(mem200==16'h4000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 1 =====");
+ if (r4 !== (`DMEM_BASE+16'h000A)) tb_error("====== Auto-increment (R4): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R4): @0x202 - test 1 =====");
+
+ @(mem200==16'h4001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 2 =====");
+ if (r4 !== (`DMEM_BASE+16'h000B)) tb_error("====== Auto-increment (R4): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 2 =====");
+ if (mem202 !== 16'h0088) tb_error("====== Auto-increment (R4): @0x202 - test 2 =====");
+
+ @(mem200==16'h4002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R4): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R4): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R4): R3 - test 3 =====");
+ if (r4 !== (`DMEM_BASE+16'h000C)) tb_error("====== Auto-increment (R4): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R4): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R4): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R4): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R4): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R4): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R4): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R4): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R4): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R4): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R4): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R4): R15 - test 3 =====");
+ if (mem202 !== 16'h0077) tb_error("====== Auto-increment (R4): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R5
+ //--------------------------------------------------------
+ @(mem200==16'h5000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 1 =====");
+ if (r5 !== (`DMEM_BASE+16'h000C)) tb_error("====== Auto-increment (R5): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R5): @0x202 - test 1 =====");
+
+ @(mem200==16'h5001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 2 =====");
+ if (r5 !== (`DMEM_BASE+16'h000D)) tb_error("====== Auto-increment (R5): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 2 =====");
+ if (mem202 !== 16'h00AA) tb_error("====== Auto-increment (R5): @0x202 - test 2 =====");
+
+ @(mem200==16'h5002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R5): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R5): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R5): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R5): R4 - test 3 =====");
+ if (r5 !== (`DMEM_BASE+16'h000E)) tb_error("====== Auto-increment (R5): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R5): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R5): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R5): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R5): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R5): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R5): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R5): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R5): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R5): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R5): R15 - test 3 =====");
+ if (mem202 !== 16'h0099) tb_error("====== Auto-increment (R5): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R6
+ //--------------------------------------------------------
+ @(mem200==16'h6000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 1 =====");
+ if (r6 !== (`DMEM_BASE+16'h000E)) tb_error("====== Auto-increment (R6): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R6): @0x202 - test 1 =====");
+
+ @(mem200==16'h6001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 2 =====");
+ if (r6 !== (`DMEM_BASE+16'h000F)) tb_error("====== Auto-increment (R6): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 2 =====");
+ if (mem202 !== 16'h00CC) tb_error("====== Auto-increment (R6): @0x202 - test 2 =====");
+
+ @(mem200==16'h6002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R6): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R6): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R6): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R6): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R6): R5 - test 3 =====");
+ if (r6 !== (`DMEM_BASE+16'h0010)) tb_error("====== Auto-increment (R6): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R6): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R6): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R6): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R6): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R6): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R6): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R6): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R6): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R6): R15 - test 3 =====");
+ if (mem202 !== 16'h00BB) tb_error("====== Auto-increment (R6): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R7
+ //--------------------------------------------------------
+ @(mem200==16'h7000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 1 =====");
+ if (r7 !== (`DMEM_BASE+16'h0010)) tb_error("====== Auto-increment (R7): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R7): @0x202 - test 1 =====");
+
+ @(mem200==16'h7001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 2 =====");
+ if (r7 !== (`DMEM_BASE+16'h0011)) tb_error("====== Auto-increment (R7): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 2 =====");
+ if (mem202 !== 16'h00EE) tb_error("====== Auto-increment (R7): @0x202 - test 2 =====");
+
+ @(mem200==16'h7002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R7): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R7): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R7): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R7): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R7): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R7): R6 - test 3 =====");
+ if (r7 !== (`DMEM_BASE+16'h0012)) tb_error("====== Auto-increment (R7): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R7): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R7): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R7): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R7): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R7): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R7): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R7): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R7): R15 - test 3 =====");
+ if (mem202 !== 16'h00DD) tb_error("====== Auto-increment (R7): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R8
+ //--------------------------------------------------------
+ @(mem200==16'h8000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 1 =====");
+ if (r8 !== (`DMEM_BASE+16'h0012)) tb_error("====== Auto-increment (R8): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R8): @0x202 - test 1 =====");
+
+ @(mem200==16'h8001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 2 =====");
+ if (r8 !== (`DMEM_BASE+16'h0013)) tb_error("====== Auto-increment (R8): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 2 =====");
+ if (mem202 !== 16'h0021) tb_error("====== Auto-increment (R8): @0x202 - test 2 =====");
+
+ @(mem200==16'h8002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R8): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R8): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R8): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R8): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R8): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R8): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R8): R7 - test 3 =====");
+ if (r8 !== (`DMEM_BASE+16'h0014)) tb_error("====== Auto-increment (R8): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R8): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R8): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R8): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R8): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R8): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R8): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R8): R15 - test 3 =====");
+ if (mem202 !== 16'h00FF) tb_error("====== Auto-increment (R8): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R9
+ //--------------------------------------------------------
+ @(mem200==16'h9000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 1 =====");
+ if (r9 !== (`DMEM_BASE+16'h0014)) tb_error("====== Auto-increment (R9): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R9): @0x202 - test 1 =====");
+
+ @(mem200==16'h9001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 2 =====");
+ if (r9 !== (`DMEM_BASE+16'h0015)) tb_error("====== Auto-increment (R9): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 2 =====");
+ if (mem202 !== 16'h0023) tb_error("====== Auto-increment (R9): @0x202 - test 2 =====");
+
+ @(mem200==16'h9002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R9): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R9): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R9): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R9): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R9): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R9): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R9): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R9): R8 - test 3 =====");
+ if (r9 !== (`DMEM_BASE+16'h0016)) tb_error("====== Auto-increment (R9): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R9): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R9): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R9): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R9): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R9): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R9): R15 - test 3 =====");
+ if (mem202 !== 16'h0012) tb_error("====== Auto-increment (R9): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R10
+ //--------------------------------------------------------
+ @(mem200==16'hA000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 1 =====");
+ if (r10 !== (`DMEM_BASE+16'h0016)) tb_error("====== Auto-increment (R10): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R10): @0x202 - test 1 =====");
+
+ @(mem200==16'hA001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 2 =====");
+ if (r10 !== (`DMEM_BASE+16'h0017)) tb_error("====== Auto-increment (R10): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 2 =====");
+ if (mem202 !== 16'h0045) tb_error("====== Auto-increment (R10): @0x202 - test 2 =====");
+
+ @(mem200==16'hA002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R10): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R10): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R10): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R10): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R10): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R10): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R10): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R10): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R10): R9 - test 3 =====");
+ if (r10 !== (`DMEM_BASE+16'h0018)) tb_error("====== Auto-increment (R10): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R10): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R10): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R10): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R10): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R10): R15 - test 3 =====");
+ if (mem202 !== 16'h0034) tb_error("====== Auto-increment (R10): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R11
+ //--------------------------------------------------------
+ @(mem200==16'hB000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 1 =====");
+ if (r11 !== (`DMEM_BASE+16'h0018)) tb_error("====== Auto-increment (R11): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R11): @0x202 - test 1 =====");
+
+ @(mem200==16'hB001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 2 =====");
+ if (r11 !== (`DMEM_BASE+16'h0019)) tb_error("====== Auto-increment (R11): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 2 =====");
+ if (mem202 !== 16'h0067) tb_error("====== Auto-increment (R11): @0x202 - test 2 =====");
+
+ @(mem200==16'hB002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R11): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R11): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R11): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R11): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R11): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R11): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R11): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R11): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R11): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R11): R10 - test 3 =====");
+ if (r11 !== (`DMEM_BASE+16'h001A)) tb_error("====== Auto-increment (R11): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R11): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R11): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R11): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R11): R15 - test 3 =====");
+ if (mem202 !== 16'h0056) tb_error("====== Auto-increment (R11): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R12
+ //--------------------------------------------------------
+ @(mem200==16'hC000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 1 =====");
+ if (r12 !== (`DMEM_BASE+16'h001A)) tb_error("====== Auto-increment (R12): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R12): @0x202 - test 1 =====");
+
+ @(mem200==16'hC001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 2 =====");
+ if (r12 !== (`DMEM_BASE+16'h001B)) tb_error("====== Auto-increment (R12): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 2 =====");
+ if (mem202 !== 16'h0089) tb_error("====== Auto-increment (R12): @0x202 - test 2 =====");
+
+ @(mem200==16'hC002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R12): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R12): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R12): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R12): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R12): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R12): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R12): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R12): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R12): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R12): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R12): R11 - test 3 =====");
+ if (r12 !== (`DMEM_BASE+16'h001C)) tb_error("====== Auto-increment (R12): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R12): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R12): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R12): R15 - test 3 =====");
+ if (mem202 !== 16'h0078) tb_error("====== Auto-increment (R12): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R13
+ //--------------------------------------------------------
+ @(mem200==16'hD000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 1 =====");
+ if (r13 !== (`DMEM_BASE+16'h001C)) tb_error("====== Auto-increment (R13): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R13): @0x202 - test 1 =====");
+
+ @(mem200==16'hD001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 2 =====");
+ if (r13 !== (`DMEM_BASE+16'h001D)) tb_error("====== Auto-increment (R13): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 2 =====");
+ if (mem202 !== 16'h00AB) tb_error("====== Auto-increment (R13): @0x202 - test 2 =====");
+
+ @(mem200==16'hD002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R13): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R13): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R13): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R13): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R13): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R13): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R13): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R13): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R13): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R13): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R13): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R13): R12 - test 3 =====");
+ if (r13 !== (`DMEM_BASE+16'h001E)) tb_error("====== Auto-increment (R13): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R13): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R13): R15 - test 3 =====");
+ if (mem202 !== 16'h009A) tb_error("====== Auto-increment (R13): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R14
+ //--------------------------------------------------------
+ @(mem200==16'hE000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 1 =====");
+ if (r14 !== (`DMEM_BASE+16'h001E)) tb_error("====== Auto-increment (R14): R14 - test 1 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R14): @0x202 - test 1 =====");
+
+ @(mem200==16'hE001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 2 =====");
+ if (r14 !== (`DMEM_BASE+16'h001F)) tb_error("====== Auto-increment (R14): R14 - test 2 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 2 =====");
+ if (mem202 !== 16'h00CD) tb_error("====== Auto-increment (R14): @0x202 - test 2 =====");
+
+ @(mem200==16'hE002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R14): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R14): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R14): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R14): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R14): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R14): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R14): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R14): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R14): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R14): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R14): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R14): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R14): R13 - test 3 =====");
+ if (r14 !== (`DMEM_BASE+16'h0020)) tb_error("====== Auto-increment (R14): R14 - test 3 =====");
+ if (r15 !== 16'h0000) tb_error("====== Auto-increment (R14): R15 - test 3 =====");
+ if (mem202 !== 16'h00BC) tb_error("====== Auto-increment (R14): @0x202 - test 3 =====");
+
+
+ // Auto-increment: R15
+ //--------------------------------------------------------
+ @(mem200==16'hF000);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 1 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 1 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 1 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 1 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 1 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 1 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 1 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 1 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 1 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 1 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 1 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 1 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 1 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 1 =====");
+ if (r15 !== (`DMEM_BASE+16'h0020)) tb_error("====== Auto-increment (R15): R15 - test 1 =====");
+ if (mem202 !== 16'h0000) tb_error("====== Auto-increment (R15): @0x202 - test 1 =====");
+
+ @(mem200==16'hF001);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 2 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 2 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 2 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 2 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 2 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 2 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 2 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 2 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 2 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 2 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 2 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 2 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 2 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 2 =====");
+ if (r15 !== (`DMEM_BASE+16'h0021)) tb_error("====== Auto-increment (R15): R15 - test 2 =====");
+ if (mem202 !== 16'h00EF) tb_error("====== Auto-increment (R15): @0x202 - test 2 =====");
+
+ @(mem200==16'hF002);
+ if (r1 !== 16'h0000) tb_error("====== Auto-increment (R15): R1 - test 3 =====");
+ if (r2 !== 16'h0000) tb_error("====== Auto-increment (R15): R2 - test 3 =====");
+ if (r3 !== 16'h0000) tb_error("====== Auto-increment (R15): R3 - test 3 =====");
+ if (r4 !== 16'h0000) tb_error("====== Auto-increment (R15): R4 - test 3 =====");
+ if (r5 !== 16'h0000) tb_error("====== Auto-increment (R15): R5 - test 3 =====");
+ if (r6 !== 16'h0000) tb_error("====== Auto-increment (R15): R6 - test 3 =====");
+ if (r7 !== 16'h0000) tb_error("====== Auto-increment (R15): R7 - test 3 =====");
+ if (r8 !== 16'h0000) tb_error("====== Auto-increment (R15): R8 - test 3 =====");
+ if (r9 !== 16'h0000) tb_error("====== Auto-increment (R15): R9 - test 3 =====");
+ if (r10 !== 16'h0000) tb_error("====== Auto-increment (R15): R10 - test 3 =====");
+ if (r11 !== 16'h0000) tb_error("====== Auto-increment (R15): R11 - test 3 =====");
+ if (r12 !== 16'h0000) tb_error("====== Auto-increment (R15): R12 - test 3 =====");
+ if (r13 !== 16'h0000) tb_error("====== Auto-increment (R15): R13 - test 3 =====");
+ if (r14 !== 16'h0000) tb_error("====== Auto-increment (R15): R14 - test 3 =====");
+ if (r15 !== (`DMEM_BASE+16'h0022)) tb_error("====== Auto-increment (R15): R15 - test 3 =====");
+ if (mem202 !== 16'h00DE) tb_error("====== Auto-increment (R15): @0x202 - test 3 =====");
+
+
+
+
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/two-op_autoincr-b.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/lp_modes_dbg_asic.v
===================================================================
--- rtl_sim/src/lp_modes_dbg_asic.v (nonexistent)
+++ rtl_sim/src/lp_modes_dbg_asic.v (revision 134)
@@ -0,0 +1,666 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* CPU LOW POWER MODES */
+/*---------------------------------------------------------------------------*/
+/* Test the CPU Low Power modes: */
+/* - LPM0 <=> CPUOFF */
+/* - LPM1 <=> CPUOFF + SCG0 */
+/* - LPM2 <=> CPUOFF + SCG1 */
+/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
+/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
+/* */
+/* Reminder: */
+/* - CPUOFF <=> turns off CPU. */
+/* - SCG0 <=> turns off DCO. */
+/* - SCG1 <=> turns off SMCLK. */
+/* - OSCOFF <=> turns off LFXT_CLK. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 95 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
+/*===========================================================================*/
+
+integer dco_clk_cnt;
+always @(negedge dco_clk)
+ dco_clk_cnt <= dco_clk_cnt+1;
+
+integer mclk_cnt;
+always @(negedge mclk)
+ mclk_cnt <= mclk_cnt+1;
+
+integer smclk_cnt;
+always @(negedge smclk)
+ smclk_cnt <= smclk_cnt+1;
+
+integer aclk_cnt;
+always @(negedge aclk)
+ aclk_cnt <= aclk_cnt+1;
+
+integer inst_cnt;
+always @(inst_number)
+ inst_cnt = inst_cnt+1;
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup2_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup2_sync <= 2'b00;
+ else wkup2_sync <= {wkup2_sync[0], wkup[2]};
+
+always @(wkup2_sync)
+ irq[2] = wkup2_sync[1];
+
+// Wakeup synchronizer to generate IRQ
+reg [1:0] wkup3_sync;
+always @(posedge mclk or posedge puc_rst)
+ if (puc_rst) wkup3_sync <= 2'b00;
+ else wkup3_sync <= {wkup3_sync[0], wkup[3]};
+
+always @(wkup3_sync)
+ irq[3] = wkup3_sync[1];
+
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ @(negedge puc_rst);
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ // Enable debug interface
+ dbg_en = 1;
+
+ irq[2] = 0;
+ wkup[2] = 0;
+
+ irq[3] = 0;
+ wkup[3] = 0;
+
+ //$display("dco_clk_cnt: %d / mclk_cnt: %d / smclk_cnt: %d / aclk_cnt: %d / inst_cnt: %d ", dco_clk_cnt, mclk_cnt, smclk_cnt, aclk_cnt, inst_cnt);
+
+`ifdef ASIC
+
+ // ACTIVE
+ //--------------------------------------------------------
+
+ @(r15==16'h1001);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== ACTIVE TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== ACTIVE TEST 2: MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== ACTIVE TEST 3: SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== ACTIVE TEST 4: ACLK IS NOT RUNNING =====");
+ if (inst_cnt < 60) tb_error("====== ACTIVE TEST 5: CPU IS NOT EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+
+ // LPM0 ( CPUOFF )
+ //--------------------------------------------------------
+
+ @(r15==16'h2001);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 2: MCLK IS NOT RUNNING =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 3: SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== LPM0 TEST 4: ACLK IS NOT RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== LPM0 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ @(posedge dco_clk); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM0 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 12: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM0 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt !== 0) tb_error("====== LPM0 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM0 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM0 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM0 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt !== 100) tb_error("====== LPM0 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM0 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM0 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM1 ( CPUOFF + SCG0 )
+ //--------------------------------------------------------
+
+ @(r15==16'h3001);
+ // Until the SMCLK clock mux is implemented, force SMCLK to LFXT_CLK;
+ force dut.clock_module_0.nodiv_smclk = lfxt_clk;
+ //force dut.clock_module_0.smclk = lfxt_clk;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 2: MCLK IS NOT RUNNING =====");
+ if (smclk_cnt < 3) tb_error("====== LPM1 TEST 3: SMCLK IS NOT RUNNING =====");
+ if (aclk_cnt < 3) tb_error("====== LPM1 TEST 4: ACLK IS NOT RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== LPM1 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM1 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM1 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 12: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM1 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM1 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt !== 0) tb_error("====== LPM1 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt !== 4) tb_error("====== LPM1 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM1 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(10*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM1 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM1 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM1 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM1 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM1 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM2 ( CPUOFF + SCG1 )
+ //--------------------------------------------------------
+
+ @(r15==16'h4001);
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 2: MCLK IS NOT RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM2 TEST 3: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM2 TEST 3: SMCLK IS NOT RUNNING =====");
+`endif
+ if (aclk_cnt < 3) tb_error("====== LPM2 TEST 4: ACLK IS NOT RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== LPM2 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM2 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM2 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 12: MCLK IS NOT RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM2 TEST 13: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM2 TEST 13: SMCLK IS NOT RUNNING =====");
+`endif
+ if (aclk_cnt < 3) tb_error("====== LPM2 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt !== 0) tb_error("====== LPM2 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM2 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM2 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM2 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM2 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM2 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM2 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM2 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM3 ( CPUOFF + SCG0 + SCG1 )
+ //--------------------------------------------------------
+
+ @(r15==16'h5001);
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 2: MCLK IS NOT RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM3 TEST 3: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM3 TEST 3: SMCLK IS NOT RUNNING =====");
+`endif
+ if (aclk_cnt < 3) tb_error("====== LPM3 TEST 4: ACLK IS NOT RUNNING =====");
+ if (inst_cnt !== 0) tb_error("====== LPM3 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM3 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM3 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 12: MCLK IS NOT RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM3 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM3 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+`endif
+ if (aclk_cnt < 3) tb_error("====== LPM3 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt !== 0) tb_error("====== LPM3 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM3 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM3 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM3 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM3 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM3 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM3 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM3 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+ // LPM4 ( CPUOFF + SCG0 + SCG1 + OSCOFF)
+ //--------------------------------------------------------
+
+ @(r15==16'h6001);
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 1: DCO_CLK IS NOT RUNNING =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 2: MCLK IS NOT RUNNING =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 3: SMCLK IS RUNNING =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 3: SMCLK IS NOT RUNNING =====");
+`endif
+`ifdef ACLK_DIVIDER
+ `ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 4: ACLK IS RUNNING =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 4: ACLK IS NOT RUNNING =====");
+ `endif
+`else
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 4: ACLK IS NOT RUNNING =====");
+`endif
+ if (inst_cnt !== 0) tb_error("====== LPM4 TEST 5: CPU IS EXECUTING =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ #(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
+ wkup[2] = 1'b1;
+ @(posedge irq_acc[2]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 6: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 7: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 8: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 9: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 10: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'haaaa);
+ wkup[2] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 11: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 12: MCLK IS NOT RUNNING AFTER IRQ =====");
+`ifdef SCG1_EN
+ if (smclk_cnt !== 0) tb_error("====== LPM4 TEST 13: SMCLK IS RUNNING AFTER IRQ =====");
+`else
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 13: SMCLK IS NOT RUNNING AFTER IRQ =====");
+`endif
+`ifdef ACLK_DIVIDER
+ `ifdef OSCOFF_EN
+ if (aclk_cnt !== 0) tb_error("====== LPM4 TEST 14: ACLK IS RUNNING AFTER IRQ =====");
+ `else
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+ `endif
+`else
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 14: ACLK IS NOT RUNNING AFTER IRQ =====");
+`endif
+ if (inst_cnt !== 0) tb_error("====== LPM4 TEST 15: CPU IS EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+ //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
+ wkup[3] = 1'b1;
+ @(posedge irq_acc[3]);
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 16: DCO_CLK IS NOT RUNNING DURING IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 17: MCLK IS NOT RUNNING DURING IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 18: SMCLK IS NOT RUNNING DURING IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 19: ACLK IS NOT RUNNING DURING IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 20: CPU IS NOT EXECUTING DURING IRQ =====");
+ @(r13==16'hbbbb);
+ wkup[3] = 1'b0;
+
+ #(100*50);
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+ #(100*50);
+ if (dco_clk_cnt !== 100) tb_error("====== LPM4 TEST 21: DCO_CLK IS NOT RUNNING AFTER IRQ =====");
+ if (mclk_cnt !== 100) tb_error("====== LPM4 TEST 22: MCLK IS NOT RUNNING AFTER IRQ =====");
+ if (smclk_cnt < 3) tb_error("====== LPM4 TEST 23: SMCLK IS NOT RUNNING AFTER IRQ =====");
+ if (aclk_cnt < 3) tb_error("====== LPM4 TEST 24: ACLK IS NOT RUNNING AFTER IRQ =====");
+ if (inst_cnt < 60) tb_error("====== LPM4 TEST 25: CPU IS NOT EXECUTING AFTER IRQ =====");
+ dco_clk_cnt = 0;
+ mclk_cnt = 0;
+ smclk_cnt = 0;
+ aclk_cnt = 0;
+ inst_cnt = 0;
+
+
+
+`else
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in FPGA mode) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/lp_modes_dbg_asic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/tA_capture.v
===================================================================
--- rtl_sim/src/tA_capture.v (revision 128)
+++ rtl_sim/src/tA_capture.v (revision 134)
@@ -49,6 +49,14 @@
repeat(5) @(posedge mclk);
stimulus_done = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
+
// TIMER A TEST: INPUT MUX (CCI)
//--------------------------------------------------------
@@ -492,7 +500,8 @@
if (mem204 !== 16'hC000) tb_error("====== TIMER_A CAPTURE OVERFLOW: COMPARATOR 2 =====");
-
+`endif
+
stimulus_done = 1;
end
/rtl_sim/src/dbg_uart.v
337,15 → 337,15
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access |
|
dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read |
dbg_uart_rx16(); // read 1st data |
dbg_uart_rx16; // read 1st data |
if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA ====="); |
dbg_uart_rx16(); // read 2nd data |
dbg_uart_rx16; // read 2nd data |
if (dbg_uart_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA ====="); |
dbg_uart_rx16(); // read 3rd data |
dbg_uart_rx16; // read 3rd data |
if (dbg_uart_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA ====="); |
dbg_uart_rx16(); // read 4th data |
dbg_uart_rx16; // read 4th data |
if (dbg_uart_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA ====="); |
dbg_uart_rx16(); // read 5th data |
dbg_uart_rx16; // read 5th data |
if (dbg_uart_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA ====="); |
|
|
376,15 → 376,15
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access |
|
dbg_uart_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read |
dbg_uart_rx16(); // read 1st data |
dbg_uart_rx16; // read 1st data |
if (dbg_uart_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA ====="); |
dbg_uart_rx16(); // read 2nd data |
dbg_uart_rx16; // read 2nd data |
if (dbg_uart_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA ====="); |
dbg_uart_rx16(); // read 3rd data |
dbg_uart_rx16; // read 3rd data |
if (dbg_uart_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA ====="); |
dbg_uart_rx16(); // read 4th data |
dbg_uart_rx16; // read 4th data |
if (dbg_uart_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA ====="); |
dbg_uart_rx16(); // read 5th data |
dbg_uart_rx16; // read 5th data |
if (dbg_uart_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA ====="); |
|
|
415,15 → 415,15
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access |
|
dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read |
dbg_uart_rx8(); // read 1st data |
dbg_uart_rx8; // read 1st data |
if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA ====="); |
dbg_uart_rx8(); // read 2nd data |
dbg_uart_rx8; // read 2nd data |
if (dbg_uart_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA ====="); |
dbg_uart_rx8(); // read 3rd data |
dbg_uart_rx8; // read 3rd data |
if (dbg_uart_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA ====="); |
dbg_uart_rx8(); // read 4th data |
dbg_uart_rx8; // read 4th data |
if (dbg_uart_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA ====="); |
dbg_uart_rx8(); // read 5th data |
dbg_uart_rx8; // read 5th data |
if (dbg_uart_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA ====="); |
|
|
/rtl_sim/src/nmi.s43
0,0 → 1,197
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */ |
/*---------------------------------------------------------------------------*/ |
/* Test the CALL instruction. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.set DMEM_BASE, (__data_start ) |
.set DMEM_200, (__data_start+0x00) |
.set DMEM_250, (__data_start+0x50) |
.set DMEM_252, (__data_start+0x52) |
.set DMEM_300, (__data_start+0x100) |
|
.set WDTCTL, 0x0120 |
.set IE1, 0x0000 |
.set IFG1, 0x0002 |
|
.global main |
|
.macro LPM4 |
bis #0x00F0, r2 |
.endm |
.macro LPM4_exit |
bic #0x00F0, @r1 |
.endm |
|
|
main: |
mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts |
eint |
|
mov #0x0000, r6 ;# R6 will be incremented with every NMI serviced interrupts |
mov #0x0000, r7 ;# Save Status register in NMI service routine |
mov #0x0000, r8 ;# Save Stack register in NMI service routine |
|
;# Test NMI disabled |
;#----------------------- |
mov #0x1000, r15 |
|
mov.b &IFG1, r14 ;# Check reset value |
mov #0x1001, r15 |
|
LPM4 |
|
mov #0x0100, r9 ;# Wait a while while .v stimulus plays with NMI pin |
wait_loop_nmi_dis: |
dec r9 |
jnz wait_loop_nmi_dis |
|
mov.b &IFG1, r13 ;# Check the flag |
bic.b #0x10, &IFG1 |
mov.b &IFG1, r12 |
nop |
nop |
nop |
nop |
mov.b &IFG1, r11 ;# Wait a while and re-check the flag |
|
mov #0x1002, r15 |
|
|
;# Test NMI rising edge |
;#----------------------- |
mov #0x2000, r15 |
|
mov #0x5a00, &WDTCTL ; NMI Edge selection: rising |
bic.b #0x10, &IFG1 ; Clear NMI flag |
bis.b #0x10, &IE1 ; Enable NMI |
|
mov #0x2001, r15 |
|
LPM4 |
|
mov #0x0100, r9 ;# Wait a while |
wait_loop_nmi_re: |
dec r9 |
jnz wait_loop_nmi_re |
|
|
;# Test NMI falling edge |
;#----------------------- |
mov #0x3000, r15 |
|
bic.b #0x10, &IE1 ; Disable NMI |
mov #0x5a40, &WDTCTL ; NMI Edge selection: falling |
bic.b #0x10, &IFG1 ; Clear NMI flag |
bis.b #0x10, &IE1 ; Enable NMI |
mov #0x0000, r6 |
|
mov #0x3001, r15 |
|
LPM4 |
|
mov #0x0100, r9 ;# Wait a while |
wait_loop_nmi_fe: |
dec r9 |
jnz wait_loop_nmi_fe |
|
|
;# Test NMI nested in maskable IRQ |
;#--------------------------------- |
mov #0x4000, r15 |
|
bic.b #0x10, &IE1 ; Disable NMI |
mov #0x5a00, &WDTCTL ; NMI Edge selection: rising |
bic.b #0x10, &IFG1 ; Clear NMI flag |
bis.b #0x10, &IE1 ; Enable NMI |
mov #0x0000, r6 |
|
mov #0x4001, r15 |
|
LPM4 |
|
mov #0x0100, r9 ;# Wait a while |
wait_loop_nmi_nested: |
dec r9 |
jnz wait_loop_nmi_nested |
|
mov #0x4002, r15 |
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
|
/* ---------------------- FUNCTIONS --------------- */ |
|
IRQ00_ROUTINE: |
mov #0x5678, r10 |
add r6, r10 ; If NMI was taken before, 1 will be added to R10 |
LPM4_exit |
reti |
|
NMI_ROUTINE: |
mov #0x1234, r10 |
inc r6 ; Increment R6 |
cmp #2, r6 |
jl end_of_nmi |
LPM4_exit |
end_of_nmi: |
mov r2, r7 ; Save Status register |
mov r1, r8 ; Save Stack register |
bic.b #0x10, &IFG1 ; Clear NMI flag |
bis.b #0x10, &IE1 ; Enable NMI |
reti |
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word end_of_test ; Interrupt 2 <unused> |
.word end_of_test ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word NMI_ROUTINE ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
rtl_sim/src/nmi.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/dbg_rdwr.v
===================================================================
--- rtl_sim/src/dbg_rdwr.v (nonexistent)
+++ rtl_sim/src/dbg_rdwr.v (revision 134)
@@ -0,0 +1,203 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* DEBUG INTERFACE: RD / WR */
+/*---------------------------------------------------------------------------*/
+/* Test the UART debug interface: */
+/* - Check RD/WR access to all adressable */
+/* debug registers. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 95 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
+/*===========================================================================*/
+
+`define LONG_TIMEOUT
+
+reg [2:0] cpu_version;
+reg cpu_asic;
+reg [4:0] user_version;
+reg [6:0] per_space;
+reg mpy_info;
+reg [8:0] dmem_size;
+reg [5:0] pmem_size;
+reg [31:0] dbg_id;
+
+integer ii;
+
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+`ifdef DBG_EN
+`ifdef DBG_UART
+ #1 dbg_en = 1;
+ repeat(30) @(posedge mclk);
+ stimulus_done = 0;
+
+ // SEND UART SYNCHRONIZATION FRAME
+ dbg_uart_tx(DBG_SYNC);
+
+ // STOP CPU
+ dbg_uart_wr(CPU_CTL , 16'h0001);
+
+ // TEST READ/WR TO ALL DEBUG REGISTERS
+ //--------------------------------------------------------
+
+ cpu_version = `CPU_VERSION;
+`ifdef ASIC
+ cpu_asic = 1'b1;
+`else
+ cpu_asic = 1'b0;
+`endif
+ user_version = `USER_VERSION;
+ per_space = (`PER_SIZE >> 9);
+`ifdef MULTIPLIER
+ mpy_info = 1'b1;
+`else
+ mpy_info = 1'b0;
+`endif
+ dmem_size = (`DMEM_SIZE >> 7);
+ pmem_size = (`PMEM_SIZE >> 10);
+
+ dbg_id = {pmem_size,
+ dmem_size,
+ mpy_info,
+ per_space,
+ user_version,
+ cpu_asic,
+ cpu_version};
+
+ // Check reset value
+ for ( ii=0; ii < 64; ii=ii+1)
+ begin
+ dbg_uart_rd(ii[7:0]);
+
+ case(ii)
+ 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 1 ERROR (CPU_ID_LO)");
+ 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)");
+ 2 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)");
+ 3 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)");
+ default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR");
+ endcase
+ end
+
+ // Write access
+ for ( ii=0; ii < 64; ii=ii+1)
+ begin
+ // Skip write for MEM_CNT
+ if (ii!=7)
+ dbg_uart_wr(ii[7:0] , 16'hffff);
+ end
+
+ // Read value back
+ for ( ii=0; ii < 64; ii=ii+1)
+ begin
+ dbg_uart_rd(ii[7:0]);
+
+ case(ii)
+ 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 2 ERROR (CPU_ID_LO)");
+ 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)");
+ 2 : if (dbg_uart_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)");
+ 3 : if ((dbg_uart_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)");
+ 4 : if (dbg_uart_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)");
+ 5 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)");
+ 6 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)");
+ 7 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)");
+`ifdef DBG_HWBRK_0
+ `ifdef DBG_HWBRK_RANGE
+ 8 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)");
+ 9 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)");
+ `else
+ 8 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)");
+ 9 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)");
+ `endif
+ 10 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)");
+ 11 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)");
+`endif
+`ifdef DBG_HWBRK_1
+ `ifdef DBG_HWBRK_RANGE
+ 12 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)");
+ 13 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)");
+ `else
+ 12 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)");
+ 13 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)");
+ `endif
+ 14 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)");
+ 15 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)");
+`endif
+`ifdef DBG_HWBRK_2
+ `ifdef DBG_HWBRK_RANGE
+ 16 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)");
+ 17 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)");
+ `else
+ 16 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)");
+ 17 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)");
+ `endif
+ 18 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)");
+ 19 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)");
+`endif
+`ifdef DBG_HWBRK_3
+ `ifdef DBG_HWBRK_RANGE
+ 20 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)");
+ 21 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)");
+ `else
+ 20 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)");
+ 21 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)");
+ `endif
+ 22 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)");
+ 23 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)");
+`endif
+ default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR");
+ endcase
+ end
+
+
+ dbg_uart_wr(CPU_CTL , 16'h0002);
+ repeat(10) @(posedge mclk);
+
+ stimulus_done = 1;
+`else
+
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (serial debug interface UART not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+`else
+
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (serial debug interface not included) |");
+ $display(" ===============================================");
+ $finish;
+`endif
+ end
+
rtl_sim/src/dbg_rdwr.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/sfr.v
===================================================================
--- rtl_sim/src/sfr.v (nonexistent)
+++ rtl_sim/src/sfr.v (revision 134)
@@ -0,0 +1,207 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* Special Function Registers (SFRs) */
+/*---------------------------------------------------------------------------*/
+/* Test the SFR registers. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 85 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $ */
+/*===========================================================================*/
+
+reg [2:0] cpu_version;
+reg cpu_asic;
+reg [4:0] user_version;
+reg [6:0] per_space;
+reg mpy_info;
+reg [8:0] dmem_size;
+reg [5:0] pmem_size;
+reg [31:0] dbg_id;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+ // NMI
+ //------------------------------
+ @(r15 === 16'h1000);
+
+ // NMI feature is verified in the NMI.S43 test
+
+ @(r15 === 16'h1001);
+
+ // WATCHDOG
+ //------------------------------
+ @(r15 === 16'h2000);
+
+ // WATCHDOG feature is verified in the WDT_*.S43 tests
+
+ @(r15 === 16'h2001);
+
+
+ // READ/WRITE IFG1
+ //------------------------------
+ @(r15 === 16'h3000);
+
+ @(r15 === 16'h3001);
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 1) =====");
+
+ @(r15 === 16'h3002);
+ `ifdef NMI
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0011) tb_error("====== IFG1 incorrect (test 2) =====");
+ `else
+ if (r10 !== 16'h0010) tb_error("====== IFG1 incorrect (test 3) =====");
+ `endif
+ `else
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0001) tb_error("====== IFG1 incorrect (test 4) =====");
+ `else
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 5) =====");
+ `endif
+ `endif
+
+ @(r15 === 16'h3003);
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 6) =====");
+
+ @(r15 === 16'h3004);
+ `ifdef NMI
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0011) tb_error("====== IFG1 incorrect (test 7) =====");
+ `else
+ if (r10 !== 16'h0010) tb_error("====== IFG1 incorrect (test 8) =====");
+ `endif
+ `else
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0001) tb_error("====== IFG1 incorrect (test 9) =====");
+ `else
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 10) =====");
+ `endif
+ `endif
+
+ @(r15 === 16'h3005);
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 11) =====");
+
+ @(r15 === 16'h3006);
+ if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 12) =====");
+
+
+ // READ/WRITE IE1
+ //------------------------------
+ @(r15 === 16'h4000);
+
+ @(r15 === 16'h4001);
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 1) =====");
+
+ @(r15 === 16'h4002);
+ `ifdef NMI
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0011) tb_error("====== IE1 incorrect (test 2) =====");
+ `else
+ if (r10 !== 16'h0010) tb_error("====== IE1 incorrect (test 3) =====");
+ `endif
+ `else
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0001) tb_error("====== IE1 incorrect (test 4) =====");
+ `else
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 5) =====");
+ `endif
+ `endif
+
+ @(r15 === 16'h4003);
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 6) =====");
+
+ @(r15 === 16'h4004);
+ `ifdef NMI
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0011) tb_error("====== IE1 incorrect (test 7) =====");
+ `else
+ if (r10 !== 16'h0010) tb_error("====== IE1 incorrect (test 8) =====");
+ `endif
+ `else
+ `ifdef WATCHDOG
+ if (r10 !== 16'h0001) tb_error("====== IE1 incorrect (test 9) =====");
+ `else
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 10) =====");
+ `endif
+ `endif
+
+ @(r15 === 16'h4005);
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 11) =====");
+
+ @(r15 === 16'h4006);
+ if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 12) =====");
+
+
+ // READ/WRITE CPU_ID
+ //------------------------------
+ @(r15 === 16'h5000);
+
+ cpu_version = `CPU_VERSION;
+`ifdef ASIC
+ cpu_asic = 1'b1;
+`else
+ cpu_asic = 1'b0;
+`endif
+ user_version = `USER_VERSION;
+ per_space = (`PER_SIZE >> 9);
+`ifdef MULTIPLIER
+ mpy_info = 1'b1;
+`else
+ mpy_info = 1'b0;
+`endif
+ dmem_size = (`DMEM_SIZE >> 7);
+ pmem_size = (`PMEM_SIZE >> 10);
+
+ dbg_id = {pmem_size,
+ dmem_size,
+ mpy_info,
+ per_space,
+ user_version,
+ cpu_asic,
+ cpu_version};
+
+ @(r15 === 16'h5001);
+ if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 1) =====");
+ if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 2) =====");
+
+ @(r15 === 16'h5002);
+ if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 3) =====");
+ if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 4) =====");
+
+ @(r15 === 16'h5003);
+ if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");
+ if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");
+
+ stimulus_done = 1;
+ end
+
rtl_sim/src/sfr.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/tA_modes.v
===================================================================
--- rtl_sim/src/tA_modes.v (revision 128)
+++ rtl_sim/src/tA_modes.v (revision 134)
@@ -52,6 +52,14 @@
stimulus_done = 0;
test_step = 0;
+`ifdef ASIC
+ $display(" ===============================================");
+ $display("| SIMULATION SKIPPED |");
+ $display("| (this test is not supported in ASIC mode) |");
+ $display(" ===============================================");
+ $finish;
+`else
+
// TIMER A TEST: RD/WR ACCESS
//--------------------------------------------------------
@@ -215,6 +223,7 @@
if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
test_step = 15;
+`endif
stimulus_done = 1;
end
/rtl_sim/src/two-op_add.v
64,7 → 64,7
//-------------------------------------------------------- |
@(r15==16'h1000); |
|
if (r2 !==16'h0022) tb_error("R2 initialization"); |
if (r2 !==16'h0002) tb_error("R2 initialization"); |
if (r3 !==16'h3333) tb_error("R3 initialization"); |
if (r4 !==16'h4444) tb_error("R4 initialization"); |
if (r5 !==16'h5555) tb_error("R5 initialization"); |
/rtl_sim/src/sing-op_reti.v
66,7 → 66,7
//-------------------------- |
@(r15==16'h2000); |
if (r1 !==(`PER_SIZE+16'h0052)) tb_error("====== RETI: SP value ====="); |
if (r2 !==16'h0145) tb_error("====== RETI: SR value ====="); |
if (r2 !==16'h010f) tb_error("====== RETI: SR value ====="); |
if (r5 !==16'h1234) tb_error("====== RETI: R5 value ====="); |
|
|
296,6 → 296,7
|
// Test interruption NMI: rising edge |
//-------------------------------------- |
`ifdef NMI |
@(r15==16'hf200); |
repeat(2) @(negedge mclk); |
nmi = 1'b1; |
315,8 → 316,8
|
if (r9 !==16'h0000) tb_error("====== NMI: NMIE value ====="); |
if (r10 !==16'h0010) tb_error("====== NMI: NMIIFG value ====="); |
`endif |
|
|
stimulus_done = 1; |
end |
|
/rtl_sim/src/wdt_interval.s43
50,15 → 50,17
|
/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */ |
|
mov &WDTCTL, r4 |
mov #0x5aff, &WDTCTL |
mov &WDTCTL, r5 |
mov #0x5a55, &WDTCTL |
mov &WDTCTL, r6 |
mov #0x5aaa, &WDTCTL |
mov &WDTCTL, r7 |
mov #0x5a00, &WDTCTL |
mov &WDTCTL, r8 |
mov &WDTCTL, r4 |
mov #0x5aff, &WDTCTL |
mov &WDTCTL, r5 |
mov #0x5a55, &WDTCTL |
mov &WDTCTL, r6 |
mov #0x5aaa, &WDTCTL |
mov &WDTCTL, r7 |
mov #0x5a00, &WDTCTL |
mov &WDTCTL, r8 |
mov &IFG1, r9 |
mov.b #0x00, &IFG1 |
|
mov #0x1000, r15 |
|
84,10 → 86,16
|
bic.b #0x01, &IE1 ;# Disable watchdog interrupt |
|
mov #0x0205, r4 |
mov &WDTCTL, r5 ;# Check if ACLK is selected |
bit #0x0004, r5 |
jnz aclk_sel_64 |
mov #0x0012, r4 |
aclk_sel_64: |
|
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter |
mov #0x0002, r5 |
|
mov #0x0010, r4 |
mov #0x0002, r5 |
wait_loop_64_no_irq: |
dec r4 |
cmp #0x0000, r4 |
101,7 → 109,6
mov #0x2001, r15 |
|
|
|
mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold |
|
mov #0x0020, r4 |
/rtl_sim/src-c/sandbox/linker.def
File deleted
rtl_sim/src-c/sandbox/linker.def
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Index: rtl_sim/src-c/sandbox/main.c
===================================================================
--- rtl_sim/src-c/sandbox/main.c (revision 128)
+++ rtl_sim/src-c/sandbox/main.c (revision 134)
@@ -35,6 +35,7 @@
#include
#include // Needed for using interrupts with msp430-gcc
+//#include
volatile char shift_direction = 0x01; // Global variable
/rtl_sim/src-c/sandbox/linker.x
0,0 → 1,177
/* Default linker script, for normal executables */ |
OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430") |
OUTPUT_ARCH("msp430") |
MEMORY |
{ |
text (rx) : ORIGIN = 0xF800, LENGTH = 0x800 |
data (rwx) : ORIGIN = 0x0200, LENGTH = 0x080 |
vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20 |
} |
/* INCLUDE periph.x */ |
SECTIONS |
{ |
/* Read-only sections, merged into text segment. */ |
.hash : { *(.hash) } |
.dynsym : { *(.dynsym) } |
.dynstr : { *(.dynstr) } |
.gnu.version : { *(.gnu.version) } |
.gnu.version_d : { *(.gnu.version_d) } |
.gnu.version_r : { *(.gnu.version_r) } |
.rel.init : { *(.rel.init) } |
.rela.init : { *(.rela.init) } |
.rel.text : |
{ |
*(.rel.text) |
*(.rel.text.*) |
*(.rel.gnu.linkonce.t*) |
} |
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{ |
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} |
.rel.fini : { *(.rel.fini) } |
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/* Internal text space. */ |
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*(.init4) /* Clear bss */ |
*(.init5) |
*(.init6) /* C++ constructors. */ |
*(.init7) |
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*(.init9) /* Call main(). */ |
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*(.fini4) |
*(.fini3) |
*(.fini2) |
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*(.fini0) /* Infinite loop after program termination. */ |
*(.fini) |
_etext = . ; |
} > text |
.data : AT (ADDR (.text) + SIZEOF (.text)) |
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*(.data) |
. = ALIGN(2); |
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. = ALIGN(2); |
_edata = . ; |
} > data |
PROVIDE (__data_load_start = LOADADDR(.data) ); |
PROVIDE (__data_size = SIZEOF(.data) ); |
.bss SIZEOF(.data) + ADDR(.data) : |
{ |
PROVIDE (__bss_start = .) ; |
*(.bss) |
*(COMMON) |
PROVIDE (__bss_end = .) ; |
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} > data |
PROVIDE (__bss_size = SIZEOF(.bss) ); |
.noinit SIZEOF(.bss) + ADDR(.bss) : |
{ |
PROVIDE (__noinit_start = .) ; |
*(.noinit) |
*(COMMON) |
PROVIDE (__noinit_end = .) ; |
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} > data |
.vectors : |
{ |
PROVIDE (__vectors_start = .) ; |
*(.vectors*) |
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/* Stabs debugging sections. */ |
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.debug_loc 0 : { *(.debug_loc) } |
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PROVIDE (__stack = 0x280) ; |
PROVIDE (__data_start_rom = _etext) ; |
PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; |
PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ; |
PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ; |
} |
rtl_sim/src-c/sandbox/linker.x
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src-c/sandbox/makefile
===================================================================
--- rtl_sim/src-c/sandbox/makefile (revision 128)
+++ rtl_sim/src-c/sandbox/makefile (revision 134)
@@ -22,7 +22,7 @@
#additional rules for files
${NAME}.elf: ${OBJECTS}
- ${CC} -T linker.def -o $@ ${OBJECTS}
+ ${CC} -T linker.x -o $@ ${OBJECTS}
${NAME}.a43: ${NAME}.elf
msp430-objcopy -O ihex $^ $@
/rtl_sim/src-c/sandbox/periph.x
0,0 → 1,29
__IE1 = 0x0000; |
__IFG1 = 0x0002; |
__WDTCTL = 0x0120; |
__P1IN = 0x0020; |
__P1OUT = 0x0021; |
__P1DIR = 0x0022; |
__P1IFG = 0x0023; |
__P1IES = 0x0024; |
__P1IE = 0x0025; |
__P1SEL = 0x0026; |
__P2IN = 0x0028; |
__P2OUT = 0x0029; |
__P2DIR = 0x002A; |
__P2IFG = 0x002B; |
__P2IES = 0x002C; |
__P2IE = 0x002D; |
__P2SEL = 0x002E; |
__TAIV = 0x012E; |
__TACTL = 0x0160; |
__TACCTL0 = 0x0162; |
__TACCTL1 = 0x0164; |
__TACCTL2 = 0x0166; |
__TAR = 0x0170; |
__TACCR0 = 0x0172; |
__TACCR1 = 0x0174; |
__TACCR2 = 0x0176; |
__DCOCTL = 0x0056; |
__BCSCTL1 = 0x0057; |
__BCSCTL2 = 0x0058; |
rtl_sim/src-c/sandbox/periph.x
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/bin/template.def
===================================================================
--- rtl_sim/bin/template.def (revision 128)
+++ rtl_sim/bin/template.def (nonexistent)
@@ -1,173 +0,0 @@
-/* Default linker script, for normal executables */
-OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430")
-OUTPUT_ARCH(msp430)
-MEMORY
-{
- text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE
- data (rwx) : ORIGIN = PER_SIZE, LENGTH = DMEM_SIZE
- vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20
-}
-SECTIONS
-{
- /* Read-only sections, merged into text segment. */
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- .gnu.version_d : { *(.gnu.version_d) }
- .gnu.version_r : { *(.gnu.version_r) }
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- .rela.init : { *(.rela.init) }
- .rel.text :
- {
- *(.rel.text)
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- *(.rela.text)
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- .rela.plt : { *(.rela.plt) }
- /* Internal text space. */
- .text :
- {
- . = ALIGN(2);
- *(.init)
- *(.init0) /* Start here after reset. */
- *(.init1)
- *(.init2) /* Copy data loop */
- *(.init3)
- *(.init4) /* Clear bss */
- *(.init5)
- *(.init6) /* C++ constructors. */
- *(.init7)
- *(.init8)
- *(.init9) /* Call main(). */
- __ctors_start = . ;
- *(.ctors)
- __ctors_end = . ;
- __dtors_start = . ;
- *(.dtors)
- __dtors_end = . ;
- . = ALIGN(2);
- *(.text)
- . = ALIGN(2);
- *(.text.*)
- . = ALIGN(2);
- *(.fini9) /* */
- *(.fini8)
- *(.fini7)
- *(.fini6) /* C++ destructors. */
- *(.fini5)
- *(.fini4)
- *(.fini3)
- *(.fini2)
- *(.fini1)
- *(.fini0) /* Infinite loop after program termination. */
- *(.fini)
- _etext = . ;
- } > text
- .data : AT (ADDR (.text) + SIZEOF (.text))
- {
- PROVIDE (__data_start = .) ;
- . = ALIGN(2);
- *(.data)
- . = ALIGN(2);
- *(.gnu.linkonce.d*)
- . = ALIGN(2);
- _edata = . ;
- } > data
- .bss SIZEOF(.data) + ADDR(.data) :
- {
- PROVIDE (__bss_start = .) ;
- *(.bss)
- *(COMMON)
- PROVIDE (__bss_end = .) ;
- _end = . ;
- } > data
- .noinit SIZEOF(.bss) + ADDR(.bss) :
- {
- PROVIDE (__noinit_start = .) ;
- *(.noinit)
- *(COMMON)
- PROVIDE (__noinit_end = .) ;
- _end = . ;
- } > data
- .vectors :
- {
- PROVIDE (__vectors_start = .) ;
- *(.vectors*)
- _vectors_end = . ;
- } > vectors
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- PROVIDE (__stack = STACK_INIT) ;
- PROVIDE (__data_start_rom = _etext) ;
- PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ;
- PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ;
- PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ;
-}
rtl_sim/bin/template.def
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Index: rtl_sim/bin/msp430sim
===================================================================
--- rtl_sim/bin/msp430sim (revision 128)
+++ rtl_sim/bin/msp430sim (revision 134)
@@ -64,7 +64,7 @@
asmfile=../src/$1.s43;
verfile=../src/$1.v;
incfile=../../../rtl/verilog/openMSP430_defines.v;
-deffile=../bin/template.def;
+linkfile=../bin/template.x;
submitfile=../src/submit.f;
if [ $OMSP_SIMULATOR == "isim" ]; then
submitfile=../src/submit.prj;
@@ -82,8 +82,8 @@
echo "Verilog submit file $submitfile doesn't exist: $submitfile"
exit 1
fi
-if [ ! -e $deffile ]; then
- echo "Linker definition file template doesn't exist: $deffile"
+if [ ! -e $linkfile ]; then
+ echo "Linker definition file template doesn't exist: $linkfile"
exit 1
fi
@@ -144,7 +144,7 @@
# Compile assembler code
echo "Compile, link & generate IHEX file (Program Memory: $pmemsize B, Data Memory: $dmemsize B, Peripheral Space: $persize B)..."
-../bin/asm2ihex.sh pmem pmem.s43 $deffile $pmemsize $dmemsize $persize
+../bin/asm2ihex.sh pmem pmem.s43 $linkfile $pmemsize $dmemsize $persize
# Generate Program memory file
echo "Convert IHEX file to Verilog MEMH format..."
/rtl_sim/bin/template.x
0,0 → 1,173
/* Default linker script, for normal executables */ |
OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430") |
OUTPUT_ARCH("msp430") |
MEMORY |
{ |
text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE |
data (rwx) : ORIGIN = PER_SIZE, LENGTH = DMEM_SIZE |
vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20 |
} |
SECTIONS |
{ |
/* Read-only sections, merged into text segment. */ |
.hash : { *(.hash) } |
.dynsym : { *(.dynsym) } |
.dynstr : { *(.dynstr) } |
.gnu.version : { *(.gnu.version) } |
.gnu.version_d : { *(.gnu.version_d) } |
.gnu.version_r : { *(.gnu.version_r) } |
.rel.init : { *(.rel.init) } |
.rela.init : { *(.rela.init) } |
.rel.text : |
{ |
*(.rel.text) |
*(.rel.text.*) |
*(.rel.gnu.linkonce.t*) |
} |
.rela.text : |
{ |
*(.rela.text) |
*(.rela.text.*) |
*(.rela.gnu.linkonce.t*) |
} |
.rel.fini : { *(.rel.fini) } |
.rela.fini : { *(.rela.fini) } |
.rel.rodata : |
{ |
*(.rel.rodata) |
*(.rel.rodata.*) |
*(.rel.gnu.linkonce.r*) |
} |
.rela.rodata : |
{ |
*(.rela.rodata) |
*(.rela.rodata.*) |
*(.rela.gnu.linkonce.r*) |
} |
.rel.data : |
{ |
*(.rel.data) |
*(.rel.data.*) |
*(.rel.gnu.linkonce.d*) |
} |
.rela.data : |
{ |
*(.rela.data) |
*(.rela.data.*) |
*(.rela.gnu.linkonce.d*) |
} |
.rel.ctors : { *(.rel.ctors) } |
.rela.ctors : { *(.rela.ctors) } |
.rel.dtors : { *(.rel.dtors) } |
.rela.dtors : { *(.rela.dtors) } |
.rel.got : { *(.rel.got) } |
.rela.got : { *(.rela.got) } |
.rel.bss : { *(.rel.bss) } |
.rela.bss : { *(.rela.bss) } |
.rel.plt : { *(.rel.plt) } |
.rela.plt : { *(.rela.plt) } |
/* Internal text space. */ |
.text : |
{ |
. = ALIGN(2); |
*(.init) |
*(.init0) /* Start here after reset. */ |
*(.init1) |
*(.init2) /* Copy data loop */ |
*(.init3) |
*(.init4) /* Clear bss */ |
*(.init5) |
*(.init6) /* C++ constructors. */ |
*(.init7) |
*(.init8) |
*(.init9) /* Call main(). */ |
__ctors_start = . ; |
*(.ctors) |
__ctors_end = . ; |
__dtors_start = . ; |
*(.dtors) |
__dtors_end = . ; |
. = ALIGN(2); |
*(.text) |
. = ALIGN(2); |
*(.text.*) |
. = ALIGN(2); |
*(.fini9) /* */ |
*(.fini8) |
*(.fini7) |
*(.fini6) /* C++ destructors. */ |
*(.fini5) |
*(.fini4) |
*(.fini3) |
*(.fini2) |
*(.fini1) |
*(.fini0) /* Infinite loop after program termination. */ |
*(.fini) |
_etext = . ; |
} > text |
.data : AT (ADDR (.text) + SIZEOF (.text)) |
{ |
PROVIDE (__data_start = .) ; |
. = ALIGN(2); |
*(.data) |
. = ALIGN(2); |
*(.gnu.linkonce.d*) |
. = ALIGN(2); |
_edata = . ; |
} > data |
.bss SIZEOF(.data) + ADDR(.data) : |
{ |
PROVIDE (__bss_start = .) ; |
*(.bss) |
*(COMMON) |
PROVIDE (__bss_end = .) ; |
_end = . ; |
} > data |
.noinit SIZEOF(.bss) + ADDR(.bss) : |
{ |
PROVIDE (__noinit_start = .) ; |
*(.noinit) |
*(COMMON) |
PROVIDE (__noinit_end = .) ; |
_end = . ; |
} > data |
.vectors : |
{ |
PROVIDE (__vectors_start = .) ; |
*(.vectors*) |
_vectors_end = . ; |
} > vectors |
/* Stabs debugging sections. */ |
.stab 0 : { *(.stab) } |
.stabstr 0 : { *(.stabstr) } |
.stab.excl 0 : { *(.stab.excl) } |
.stab.exclstr 0 : { *(.stab.exclstr) } |
.stab.index 0 : { *(.stab.index) } |
.stab.indexstr 0 : { *(.stab.indexstr) } |
.comment 0 : { *(.comment) } |
/* DWARF debug sections. |
Symbols in the DWARF debugging sections are relative to the beginning |
of the section so we begin them at 0. */ |
/* DWARF 1 */ |
.debug 0 : { *(.debug) } |
.line 0 : { *(.line) } |
/* GNU DWARF 1 extensions */ |
.debug_srcinfo 0 : { *(.debug_srcinfo) } |
.debug_sfnames 0 : { *(.debug_sfnames) } |
/* DWARF 1.1 and DWARF 2 */ |
.debug_aranges 0 : { *(.debug_aranges) } |
.debug_pubnames 0 : { *(.debug_pubnames) } |
/* DWARF 2 */ |
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } |
.debug_abbrev 0 : { *(.debug_abbrev) } |
.debug_line 0 : { *(.debug_line) } |
.debug_frame 0 : { *(.debug_frame) } |
.debug_str 0 : { *(.debug_str) } |
.debug_loc 0 : { *(.debug_loc) } |
.debug_macinfo 0 : { *(.debug_macinfo) } |
PROVIDE (__stack = STACK_INIT) ; |
PROVIDE (__data_start_rom = _etext) ; |
PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; |
PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ; |
PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ; |
} |
rtl_sim/bin/template.x
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/bin/rtlsim.sh
===================================================================
--- rtl_sim/bin/rtlsim.sh (revision 128)
+++ rtl_sim/bin/rtlsim.sh (revision 134)
@@ -99,7 +99,7 @@
vargs="$vargs +define+VXL" ;;
ncverilog* )
rm -rf INCA_libs
- vargs="$vargs +access+r +ncinput+../bin/cov_ncverilog.tcl -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
+ vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
vcs* )
rm -rf csrc simv*
vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
Index: rtl_sim/bin/cov_exclude.dat
===================================================================
--- rtl_sim/bin/cov_exclude.dat (revision 128)
+++ rtl_sim/bin/cov_exclude.dat (revision 134)
@@ -1,3 +1,3 @@
-module openMSP430.scan_enable
-module openMSP430.scan_mode
+#module openMSP430.scan_enable
+#module openMSP430.scan_mode
/rtl_sim/bin/cov_exclude_bits.dat
1,47 → 1,207
#============================================ |
# FRONTENT |
# CPU_ID related |
#============================================ |
|
# Exclude pc[0] as these are constant signals |
-ere instance tb_openMSP430\.dut\.frontend_0\.pc\[0\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.pc_incr\[0\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.cpu_version\[0\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.cpu_version\[1\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.cpu_version\[2\] |
|
# Exclude irq_addr[15:5] and irq_addr[0] as these are constant signals |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[15\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[14\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[13\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[12\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[11\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[10\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[9\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[8\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[7\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[6\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[5\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_asic |
|
# Exclude inst_ad[7/5/3/2] as these are constant signals |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[7\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[5\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[3\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[2\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[7\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[5\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[3\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[2\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.user_version\[0\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.user_version\[1\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.user_version\[2\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.user_version\[3\] |
# -ere instance tb_openMSP430\.dut\.sfr_0\.user_version\[4\] |
|
# Diverse remaining constants |
-ere instance tb_openMSP430\.dut\.frontend_0\.ext_incr\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_space\[6\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.mpy_info |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.dmem_size\[8\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.pmem_size\[5\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[15\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[16\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[17\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[18\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[19\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[20\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[21\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[22\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[23\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[24\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[25\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[26\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[27\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[28\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[29\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[30\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id\[31\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_lo_rd\[15\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[4\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.cpu_id_hi_rd\[15\] |
|
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[0\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[1\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[2\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[3\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[4\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[5\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[6\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[7\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[8\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[9\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[10\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[11\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[12\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[13\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[14\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_lo_rd\[15\] |
|
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[0\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[1\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[2\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[3\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[4\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[5\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[6\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[7\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[8\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[9\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[10\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[11\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[12\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[13\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[14\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.cpu_id_hi_rd\[15\] |
|
|
#============================================ |
# EXECUTION UNIT |
# SFR related |
#============================================ |
|
# Exclude pc[0] as these are constant signals |
-ere instance tb_openMSP430\.dut\.execution_unit_0\.pc\[0\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ie1_rd\[15\] |
|
# Exclude inst_ad[7/5/3/2] as these are constant signals |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.ifg1_rd\[15\] |
|
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[1\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[2\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[3\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[5\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[6\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[7\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[8\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[9\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[10\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[11\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[12\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[13\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[14\] |
-ere instance tb_openMSP430\.dut\.sfr_0\.per_dout\[15\] |
|
|
#============================================ |
# INST_AD related |
#============================================ |
|
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[7\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[5\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[3\] |
-ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[2\] |
|
-ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[7\] |
-ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[5\] |
-ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[3\] |
49,21 → 209,19
|
|
#============================================ |
# MEMORY BACKBONE |
# DBG related |
#============================================ |
|
# Higher peripheral address bits might be constants depending on the configuration |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[13\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[12\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[11\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[10\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[9\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[8\] |
|
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[14\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[13\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[12\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[11\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[10\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[9\] |
-ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[8\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[2\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[3\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[5\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[6\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[7\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[8\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[9\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[10\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[11\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[12\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[13\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[14\] |
-ere instance tb_openMSP430\.dut\.dbg_0\.mem_addr_inc\[15\] |
/rtl_sim/bin/asm2ihex.sh
10,7 → 10,7
# This source file is free software; you can redistribute it and/or modify |
# it under the terms of the GNU Lesser General Public License as published |
# by the Free Software Foundation; either version 2.1 of the License, or |
# (at your option) any later version. |
# (at your option) any later version.1 |
# |
# This source is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
40,8 → 40,8
EXPECTED_ARGS=6 |
if [ $# -ne $EXPECTED_ARGS ]; then |
echo "ERROR : wrong number of arguments" |
echo "USAGE : asm2ihex.sh <test name> <test assembler file> <definition file> <prog mem size> <data mem size> <peripheral addr space size>" |
echo "Example : asm2ihex.sh c-jump_jge ../src/c-jump_jge.s43 ../bin/template.def 2048 128 512" |
echo "USAGE : asm2ihex.sh <test name> <test assembler file> <linker script> <prog mem size> <data mem size> <peripheral addr space size>" |
echo "Example : asm2ihex.sh c-jump_jge ../src/c-jump_jge.s43 ../bin/template.x 2048 128 512" |
exit 1 |
fi |
|
70,12 → 70,12
PMEM_BASE=$((0x10000-$PMEM_SIZE)) |
STACK_INIT=$((PER_SIZE+0x0080)) |
|
cp $3 ./pmem.def |
sed -i "s/PMEM_BASE/$PMEM_BASE/g" pmem.def |
sed -i "s/PMEM_SIZE/$PMEM_SIZE/g" pmem.def |
sed -i "s/DMEM_SIZE/$DMEM_SIZE/g" pmem.def |
sed -i "s/PER_SIZE/$PER_SIZE/g" pmem.def |
sed -i "s/STACK_INIT/$STACK_INIT/g" pmem.def |
cp $3 ./pmem.x |
sed -i "s/PMEM_BASE/$PMEM_BASE/g" pmem.x |
sed -i "s/PMEM_SIZE/$PMEM_SIZE/g" pmem.x |
sed -i "s/DMEM_SIZE/$DMEM_SIZE/g" pmem.x |
sed -i "s/PER_SIZE/$PER_SIZE/g" pmem.x |
sed -i "s/STACK_INIT/$STACK_INIT/g" pmem.x |
|
|
############################################################################### |
83,5 → 83,5
############################################################################### |
msp430-as -alsm $2 -o $1.o > $1.l43 |
msp430-objdump -xdsStr $1.o >> $1.l43 |
msp430-ld -T ./pmem.def $1.o -o $1.elf |
msp430-ld -T ./pmem.x $1.o -o $1.elf |
msp430-objcopy -O ihex $1.elf $1.ihex |
/rtl_sim/bin/cov_ncverilog.ccf
1,4 → 1,7
|
#set_expr_scoring -all |
set_com -on |
|
set_expr_scoring -all |
|
set_toggle_excludefile ../bin/cov_exclude.dat |
set_toggle_excludefile -bitexclude ../bin/cov_exclude_bits.dat |
/rtl_sim/bin/cov_iccr_merge.cf
5,6 → 5,5
lappend mytests [file dirname $ucd_file] |
} |
|
eval load_test $mytests |
eval merge $mytests -output merged_coverage |
eval merge -out merged_coverage -metrics all $mytests |
quit |