URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/sim
- from Rev 180 to Rev 186
- ↔ Reverse comparison
Rev 180 → Rev 186
/rtl_sim/src/mpy_basic.s43
629,7 → 629,7
nop |
nop |
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/* -------------- RD/WR ACCESS OPERANDS --------------- */ |
/* -------------- 16-BIT RD/WR ACCESS OPERANDS --------------- */ |
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mov #0x1234, &MPY |
mov #0x5678, &OP2 |
691,6 → 691,65
nop |
nop |
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/* -------------- 8-BIT RD/WR ACCESS OPERANDS --------------- */ |
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mov #0x1234, &MPY |
mov &MPY, r10 |
mov.b #0xab, &MPY |
mov &MPY, r11 |
nop |
mov #0x0001, r15 |
nop |
|
mov #0x5678, &MPYS |
mov &MPYS, r10 |
mov.b #0xbc, &MPYS |
mov &MPYS, r11 |
nop |
mov #0x0002, r15 |
nop |
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mov #0x9abc, &MAC |
mov &MAC, r10 |
mov.b #0xde, &MAC |
mov &MAC, r11 |
nop |
mov #0x0003, r15 |
nop |
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mov #0xdef0, &MACS |
mov &MACS, r10 |
mov.b #0xed, &MACS |
mov &MACS, r11 |
nop |
mov #0x0004, r15 |
nop |
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mov #0x4321, &OP2 |
mov &OP2, r10 |
mov.b #0xdc, &OP2 |
mov &OP2, r11 |
nop |
mov #0x0005, r15 |
nop |
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mov #0x8765, &RESLO |
mov &RESLO, r10 |
mov.b #0xcb, &RESLO |
mov &RESLO, r11 |
nop |
mov #0x0006, r15 |
nop |
|
mov #0xcba9, &RESHI |
mov &RESHI, r10 |
mov.b #0xba, &RESHI |
mov &RESHI, r11 |
nop |
mov #0x0007, r15 |
nop |
|
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/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
/rtl_sim/src/mpy_basic.v
252,41 → 252,75
$display("Signed Multiply Accumulate test completed (MACS mode)"); |
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// RD/WR ACCESS OPERANDS |
// 16-BIT RD/WR ACCESS OPERANDS |
//-------------------------------------------------------- |
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@(r15===16'h0001); |
if (r10 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (1) ====="); |
if (r11 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (1) ====="); |
if (r12 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (1) ====="); |
if (r13 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (1) ====="); |
if (r14 !== 16'h5678) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (1) ====="); |
if (r10 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) ====="); |
if (r11 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) ====="); |
if (r12 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) ====="); |
if (r13 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) ====="); |
if (r14 !== 16'h5678) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (1) ====="); |
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@(r15===16'h0002); |
if (r10 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (2) ====="); |
if (r11 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (2) ====="); |
if (r12 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (2) ====="); |
if (r13 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (2) ====="); |
if (r14 !== 16'h8765) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (2) ====="); |
if (r10 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) ====="); |
if (r11 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) ====="); |
if (r12 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) ====="); |
if (r13 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) ====="); |
if (r14 !== 16'h8765) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (2) ====="); |
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@(r15===16'h0003); |
if (r10 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (3) ====="); |
if (r11 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (3) ====="); |
if (r12 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (3) ====="); |
if (r13 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (3) ====="); |
if (r14 !== 16'hDEF0) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (3) ====="); |
if (r10 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (3) ====="); |
if (r11 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (3) ====="); |
if (r12 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (3) ====="); |
if (r13 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (3) ====="); |
if (r14 !== 16'hDEF0) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (3) ====="); |
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@(r15===16'h0004); |
if (r10 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (4) ====="); |
if (r11 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (4) ====="); |
if (r12 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (4) ====="); |
if (r13 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (4) ====="); |
if (r14 !== 16'h0FED) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (4) ====="); |
if (r10 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (4) ====="); |
if (r11 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (4) ====="); |
if (r12 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (4) ====="); |
if (r13 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (4) ====="); |
if (r14 !== 16'h0FED) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (4) ====="); |
|
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$display("RD/WR Access operands test completed"); |
$display("16-BIT RD/WR Access operands test completed"); |
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// 8-BIT RD/WR ACCESS OPERANDS |
//-------------------------------------------------------- |
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@(r15===16'h0001); |
if (r10 !== 16'h1234) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) ====="); |
if (r11 !== 16'h00ab) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) ====="); |
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@(r15===16'h0002); |
if (r10 !== 16'h5678) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) ====="); |
if (r11 !== 16'h00bc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) ====="); |
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@(r15===16'h0003); |
if (r10 !== 16'h9abc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) ====="); |
if (r11 !== 16'h00de) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) ====="); |
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@(r15===16'h0004); |
if (r10 !== 16'hdef0) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) ====="); |
if (r11 !== 16'h00ed) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) ====="); |
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@(r15===16'h0005); |
if (r10 !== 16'h4321) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (1) ====="); |
if (r11 !== 16'h00dc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (2) ====="); |
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@(r15===16'h0006); |
if (r10 !== 16'h8765) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (1) ====="); |
if (r11 !== 16'h00cb) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (2) ====="); |
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@(r15===16'h0007); |
if (r10 !== 16'hcba9) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (1) ====="); |
if (r11 !== 16'h00ba) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (2) ====="); |
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$display("8-BIT RD/WR Access operands test completed"); |
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stimulus_done = 1; |
`else |
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