URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/synthesis
- from Rev 63 to Rev 64
- ↔ Reverse comparison
Rev 63 → Rev 64
/actel/design_files.v
0,0 → 1,67
//---------------------------------------------------------------------------- |
// Copyright (C) 2001 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//---------------------------------------------------------------------------- |
// |
// *File Name: openMSP430_fpga_top.v |
// |
// *Author(s): |
// - Olivier Girard, olgirard@gmail.com |
// |
//---------------------------------------------------------------------------- |
// $Rev: 37 $ |
// $LastChangedBy: olivier.girard $ |
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $ |
//---------------------------------------------------------------------------- |
|
//============================================================================= |
// FPGA Specific modules |
//============================================================================= |
|
`include "../src/openMSP430_fpga.v" |
`include "../src/smartgen/pmem.v" |
`include "../src/smartgen/dmem.v" |
|
|
//============================================================================= |
// openMSP430 |
//============================================================================= |
|
`include "../src/openMSP430.v" |
`include "../src/omsp_frontend.v" |
`include "../src/omsp_execution_unit.v" |
`include "../src/omsp_register_file.v" |
`include "../src/omsp_alu.v" |
`include "../src/omsp_mem_backbone.v" |
`include "../src/omsp_clock_module.v" |
`include "../src/omsp_sfr.v" |
`include "../src/omsp_watchdog.v" |
|
`include "../src/openMSP430_defines.v" |
`ifdef DBG_EN |
`include "../src/omsp_dbg.v" |
`include "../src/omsp_dbg_uart.v" |
`include "../src/openMSP430_defines.v" |
`ifdef DBG_HWBRK_0 |
`include "../src/omsp_dbg_hwbrk.v" |
`endif |
`endif |
actel/design_files.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/design_files.sdc
===================================================================
--- actel/design_files.sdc (nonexistent)
+++ actel/design_files.sdc (revision 64)
@@ -0,0 +1,4 @@
+# Design Constraints
+
+create_clock -period 40.0 -waveform {0.0 20.0} dco_clk
+
actel/design_files.sdc
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/smartgen/pmem.v
===================================================================
--- actel/src/smartgen/pmem.v (nonexistent)
+++ actel/src/smartgen/pmem.v (revision 64)
@@ -0,0 +1,185 @@
+`timescale 1 ns/100 ps
+// Version: 8.5 8.5.0.34
+
+
+module pmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
+input [7:0] WD;
+output [7:0] RD;
+input WEN, REN;
+input [11:0] WADDR, RADDR;
+input RWCLK, RESET;
+
+ wire VCC, GND;
+
+ VCC VCC_1_net(.Y(VCC));
+ GND GND_1_net(.Y(GND));
+ RAM4K9 pmem_R0C3(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[3]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[3]));
+ RAM4K9 pmem_R0C4(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[4]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[4]));
+ RAM4K9 pmem_R0C6(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[6]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[6]));
+ RAM4K9 pmem_R0C5(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[5]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[5]));
+ RAM4K9 pmem_R0C0(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[0]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[0]));
+ RAM4K9 pmem_R0C2(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[2]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[2]));
+ RAM4K9 pmem_R0C7(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[7]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[7]));
+ RAM4K9 pmem_R0C1(.ADDRA11(WADDR[11]), .ADDRA10(WADDR[10]),
+ .ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
+ .ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
+ .ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
+ .ADDRA0(WADDR[0]), .ADDRB11(RADDR[11]), .ADDRB10(
+ RADDR[10]), .ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(
+ RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(
+ RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(
+ RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND),
+ .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND),
+ .DINA2(GND), .DINA1(GND), .DINA0(WD[1]), .DINB8(GND),
+ .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND),
+ .DINB3(GND), .DINB2(GND), .DINB1(GND), .DINB0(GND),
+ .WIDTHA0(GND), .WIDTHA1(GND), .WIDTHB0(GND), .WIDTHB1(GND)
+ , .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
+ .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(
+ RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(),
+ .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(),
+ .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(),
+ .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(),
+ .DOUTB0(RD[1]));
+
+endmodule
actel/src/smartgen/pmem.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/smartgen/dmem.v
===================================================================
--- actel/src/smartgen/dmem.v (nonexistent)
+++ actel/src/smartgen/dmem.v (revision 64)
@@ -0,0 +1,59 @@
+`timescale 1 ns/100 ps
+// Version: 8.5 8.5.0.34
+
+
+module dmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
+input [7:0] WD;
+output [7:0] RD;
+input WEN, REN;
+input [9:0] WADDR, RADDR;
+input RWCLK, RESET;
+
+ wire VCC, GND;
+
+ VCC VCC_1_net(.Y(VCC));
+ GND GND_1_net(.Y(GND));
+ RAM4K9 dmem_R0C1(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
+ WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
+ WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
+ WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
+ WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
+ , .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
+ .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
+ .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
+ .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
+ .DINA4(GND), .DINA3(WD[7]), .DINA2(WD[6]), .DINA1(WD[5]),
+ .DINA0(WD[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
+ .DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
+ .DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
+ .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
+ .WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
+ GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
+ RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
+ .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
+ .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
+ .DOUTB3(RD[7]), .DOUTB2(RD[6]), .DOUTB1(RD[5]), .DOUTB0(
+ RD[4]));
+ RAM4K9 dmem_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
+ WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
+ WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
+ WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
+ WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
+ , .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
+ .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
+ .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
+ .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
+ .DINA4(GND), .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]),
+ .DINA0(WD[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
+ .DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
+ .DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
+ .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
+ .WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
+ GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
+ RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
+ .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
+ .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
+ .DOUTB3(RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(
+ RD[0]));
+
+endmodule
actel/src/smartgen/dmem.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_frontend.v
===================================================================
--- actel/src/omsp_frontend.v (nonexistent)
+++ actel/src/omsp_frontend.v (revision 64)
@@ -0,0 +1,754 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_frontend.v
+//
+// *Module Description:
+// openMSP430 Instruction fetch and decode unit
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 60 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-02-03 22:12:25 +0100 (Mi, 03 Feb 2010) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_frontend (
+
+// OUTPUTs
+ dbg_halt_st, // Halt/Run status from CPU
+ decode_noirq, // Frontend decode instruction
+ e_state, // Execution state
+ exec_done, // Execution completed
+ inst_ad, // Decoded Inst: destination addressing mode
+ inst_as, // Decoded Inst: source addressing mode
+ inst_alu, // ALU control signals
+ inst_bw, // Decoded Inst: byte width
+ inst_dest, // Decoded Inst: destination (one hot)
+ inst_dext, // Decoded Inst: destination extended instruction word
+ inst_irq_rst, // Decoded Inst: Reset interrupt
+ inst_jmp, // Decoded Inst: Conditional jump
+ inst_sext, // Decoded Inst: source extended instruction word
+ inst_so, // Decoded Inst: Single-operand arithmetic
+ inst_src, // Decoded Inst: source (one hot)
+ inst_type, // Decoded Instruction type
+ irq_acc, // Interrupt request accepted (one-hot signal)
+ mab, // Frontend Memory address bus
+ mb_en, // Frontend Memory bus enable
+ nmi_acc, // Non-Maskable interrupt request accepted
+ pc, // Program counter
+ pc_nxt, // Next PC value (for CALL & IRQ)
+
+// INPUTs
+ cpuoff, // Turns off the CPU
+ dbg_halt_cmd, // Halt CPU command
+ dbg_reg_sel, // Debug selected register for rd/wr access
+ fe_pmem_wait, // Frontend wait for Instruction fetch
+ gie, // General interrupt enable
+ irq, // Maskable interrupts
+ mclk, // Main system clock
+ mdb_in, // Frontend Memory data bus input
+ nmi_evt, // Non-maskable interrupt event
+ pc_sw, // Program counter software value
+ pc_sw_wr, // Program counter software write
+ puc, // Main system reset
+ wdt_irq // Watchdog-timer interrupt
+);
+
+// OUTPUTs
+//=========
+output dbg_halt_st; // Halt/Run status from CPU
+output decode_noirq; // Frontend decode instruction
+output [3:0] e_state; // Execution state
+output exec_done; // Execution completed
+output [7:0] inst_ad; // Decoded Inst: destination addressing mode
+output [7:0] inst_as; // Decoded Inst: source addressing mode
+output [11:0] inst_alu; // ALU control signals
+output inst_bw; // Decoded Inst: byte width
+output [15:0] inst_dest; // Decoded Inst: destination (one hot)
+output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
+output inst_irq_rst; // Decoded Inst: Reset interrupt
+output [7:0] inst_jmp; // Decoded Inst: Conditional jump
+output [15:0] inst_sext; // Decoded Inst: source extended instruction word
+output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
+output [15:0] inst_src; // Decoded Inst: source (one hot)
+output [2:0] inst_type; // Decoded Instruction type
+output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
+output [15:0] mab; // Frontend Memory address bus
+output mb_en; // Frontend Memory bus enable
+output nmi_acc; // Non-Maskable interrupt request accepted
+output [15:0] pc; // Program counter
+output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
+
+// INPUTs
+//=========
+input cpuoff; // Turns off the CPU
+input dbg_halt_cmd; // Halt CPU command
+input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
+input fe_pmem_wait; // Frontend wait for Instruction fetch
+input gie; // General interrupt enable
+input [13:0] irq; // Maskable interrupts
+input mclk; // Main system clock
+input [15:0] mdb_in; // Frontend Memory data bus input
+input nmi_evt; // Non-maskable interrupt event
+input [15:0] pc_sw; // Program counter software value
+input pc_sw_wr; // Program counter software write
+input puc; // Main system reset
+input wdt_irq; // Watchdog-timer interrupt
+
+
+//=============================================================================
+// 1) FRONTEND STATE MACHINE
+//=============================================================================
+
+// The wire "conv" is used as state bits to calculate the next response
+reg [2:0] i_state;
+reg [2:0] i_state_nxt;
+
+reg [1:0] inst_sz;
+wire [1:0] inst_sz_nxt;
+wire irq_detect;
+wire [2:0] inst_type_nxt;
+wire is_const;
+reg [15:0] sconst_nxt;
+reg [3:0] e_state_nxt;
+
+// State machine definitons
+parameter I_IRQ_FETCH = 3'h0;
+parameter I_IRQ_DONE = 3'h1;
+parameter I_DEC = 3'h2; // New instruction ready for decode
+parameter I_EXT1 = 3'h3; // 1st Extension word
+parameter I_EXT2 = 3'h4; // 2nd Extension word
+parameter I_IDLE = 3'h5; // CPU is in IDLE mode
+
+// States Transitions
+always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
+ exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
+ case(i_state)
+ I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
+ (~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
+ I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
+ I_IRQ_DONE : i_state_nxt = I_DEC;
+ I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
+ (cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
+ dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
+ pc_sw_wr ? I_DEC :
+ ~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
+ (inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
+ I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
+ pc_sw_wr ? I_DEC :
+ (inst_sz!=2'b01) ? I_EXT2 : I_DEC;
+ I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC;
+ default : i_state_nxt = I_IRQ_FETCH;
+ endcase
+
+// State machine
+always @(posedge mclk or posedge puc)
+ if (puc) i_state <= I_IRQ_FETCH;
+ else i_state <= i_state_nxt;
+
+// Utility signals
+wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE)));
+wire decode = decode_noirq | irq_detect;
+wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
+
+// Debug interface cpu status
+reg dbg_halt_st;
+always @(posedge mclk or posedge puc)
+ if (puc) dbg_halt_st <= 1'b0;
+ else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
+
+
+//=============================================================================
+// 2) INTERRUPT HANDLING
+//=============================================================================
+
+// Detect nmi interrupt
+reg inst_nmi;
+always @(posedge mclk or posedge puc)
+ if (puc) inst_nmi <= 1'b0;
+ else if (nmi_evt) inst_nmi <= 1'b1;
+ else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0;
+
+
+// Detect reset interrupt
+reg inst_irq_rst;
+always @(posedge mclk or posedge puc)
+ if (puc) inst_irq_rst <= 1'b1;
+ else if (exec_done) inst_irq_rst <= 1'b0;
+
+// Detect other interrupts
+assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE));
+
+// Select interrupt vector
+reg [3:0] irq_num;
+always @(posedge mclk or posedge puc)
+ if (puc) irq_num <= 4'hf;
+ else if (irq_detect) irq_num <= inst_nmi ? 4'he :
+ irq[13] ? 4'hd :
+ irq[12] ? 4'hc :
+ irq[11] ? 4'hb :
+ (irq[10] | wdt_irq) ? 4'ha :
+ irq[9] ? 4'h9 :
+ irq[8] ? 4'h8 :
+ irq[7] ? 4'h7 :
+ irq[6] ? 4'h6 :
+ irq[5] ? 4'h5 :
+ irq[4] ? 4'h4 :
+ irq[3] ? 4'h3 :
+ irq[2] ? 4'h2 :
+ irq[1] ? 4'h1 :
+ irq[0] ? 4'h0 : 4'hf;
+
+wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
+
+// Interrupt request accepted
+wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}};
+wire [13:0] irq_acc = irq_acc_all[13:0];
+wire nmi_acc = irq_acc_all[14];
+
+
+//=============================================================================
+// 3) FETCH INSTRUCTION
+//=============================================================================
+
+//
+// 3.1) PROGRAM COUNTER & MEMORY INTERFACE
+//-----------------------------------------
+
+// Program counter
+reg [15:0] pc;
+
+// Compute next PC value
+wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
+wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
+ (i_state==I_IRQ_FETCH) ? irq_addr :
+ (i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
+
+always @(posedge mclk or posedge puc)
+ if (puc) pc <= 16'h0000;
+ else pc <= pc_nxt;
+
+// Check if ROM has been busy in order to retry ROM access
+reg pmem_busy;
+always @(posedge mclk or posedge puc)
+ if (puc) pmem_busy <= 16'h0000;
+ else pmem_busy <= fe_pmem_wait;
+
+// Memory interface
+wire [15:0] mab = pc_nxt;
+wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
+
+
+//
+// 3.2) INSTRUCTION REGISTER
+//--------------------------------
+
+// Instruction register
+wire [15:0] ir = mdb_in;
+
+// Detect if source extension word is required
+wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
+
+// Detect if destination extension word is required
+wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]);
+
+// For the Symbolic addressing mode, add -2 to the extension word in order
+// to make up for the PC address
+wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
+ ((i_state==I_EXT2) & inst_ad[`SYMB]) |
+ ((i_state==I_EXT1) & ~inst_as[`SYMB] &
+ ~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000;
+
+wire [15:0] ext_nxt = ir + ext_incr;
+
+// Store source extension word
+reg [15:0] inst_sext;
+always @(posedge mclk or posedge puc)
+ if (puc) inst_sext <= 16'h0000;
+ else if (decode & is_const) inst_sext <= sconst_nxt;
+ else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
+ else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
+
+// Source extension word is ready
+wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
+
+
+// Store destination extension word
+reg [15:0] inst_dext;
+always @(posedge mclk or posedge puc)
+ if (puc) inst_dext <= 16'h0000;
+ else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
+ else if (i_state==I_EXT2) inst_dext <= ext_nxt;
+
+// Destination extension word is ready
+wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
+
+
+//=============================================================================
+// 4) DECODE INSTRUCTION
+//=============================================================================
+
+//
+// 4.1) OPCODE: INSTRUCTION TYPE
+//----------------------------------------
+// Instructions type is encoded in a one hot fashion as following:
+//
+// 3'b001: Single-operand arithmetic
+// 3'b010: Conditional jump
+// 3'b100: Two-operand arithmetic
+
+reg [2:0] inst_type;
+assign inst_type_nxt = {(ir[15:14]!=2'b00),
+ (ir[15:13]==3'b001),
+ (ir[15:13]==3'b000)} & {3{~irq_detect}};
+
+always @(posedge mclk or posedge puc)
+ if (puc) inst_type <= 3'b000;
+ else if (decode) inst_type <= inst_type_nxt;
+
+//
+// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC
+//----------------------------------------
+// Instructions are encoded in a one hot fashion as following:
+//
+// 8'b00000001: RRC
+// 8'b00000010: SWPB
+// 8'b00000100: RRA
+// 8'b00001000: SXT
+// 8'b00010000: PUSH
+// 8'b00100000: CALL
+// 8'b01000000: RETI
+// 8'b10000000: IRQ
+
+reg [7:0] inst_so;
+wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<
actel/src/omsp_frontend.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_alu.v
===================================================================
--- actel/src/omsp_alu.v (nonexistent)
+++ actel/src/omsp_alu.v (revision 64)
@@ -0,0 +1,248 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_alu.v
+//
+// *Module Description:
+// openMSP430 ALU
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_alu (
+
+// OUTPUTs
+ alu_out, // ALU output value
+ alu_out_add, // ALU adder output value
+ alu_stat, // ALU Status {V,N,Z,C}
+ alu_stat_wr, // ALU Status write {V,N,Z,C}
+
+// INPUTs
+ dbg_halt_st, // Halt/Run status from CPU
+ exec_cycle, // Instruction execution cycle
+ inst_alu, // ALU control signals
+ inst_bw, // Decoded Inst: byte width
+ inst_jmp, // Decoded Inst: Conditional jump
+ inst_so, // Single-operand arithmetic
+ op_dst, // Destination operand
+ op_src, // Source operand
+ status // R2 Status {V,N,Z,C}
+);
+
+// OUTPUTs
+//=========
+output [15:0] alu_out; // ALU output value
+output [15:0] alu_out_add; // ALU adder output value
+output [3:0] alu_stat; // ALU Status {V,N,Z,C}
+output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
+
+// INPUTs
+//=========
+input dbg_halt_st; // Halt/Run status from CPU
+input exec_cycle; // Instruction execution cycle
+input [11:0] inst_alu; // ALU control signals
+input inst_bw; // Decoded Inst: byte width
+input [7:0] inst_jmp; // Decoded Inst: Conditional jump
+input [7:0] inst_so; // Single-operand arithmetic
+input [15:0] op_dst; // Destination operand
+input [15:0] op_src; // Source operand
+input [3:0] status; // R2 Status {V,N,Z,C}
+
+
+//=============================================================================
+// 1) FUNCTIONS
+//=============================================================================
+
+function [4:0] bcd_add;
+
+ input [3:0] X;
+ input [3:0] Y;
+ input C;
+
+ reg [4:0] Z;
+ begin
+ Z = {1'b0,X}+{1'b0,Y}+C;
+ if (Z<10) bcd_add = Z;
+ else bcd_add = Z+6;
+ end
+
+endfunction
+
+
+//=============================================================================
+// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
+//=============================================================================
+// SINGLE-OPERAND ARITHMETIC:
+//-----------------------------------------------------------------------------
+// Mnemonic S-Reg, Operation Status bits
+// D-Reg, V N Z C
+//
+// RRC dst C->MSB->...LSB->C * * * *
+// RRA dst MSB->MSB->...LSB->C 0 * * *
+// SWPB dst Swap bytes - - - -
+// SXT dst Bit7->Bit8...Bit15 0 * * *
+// PUSH src SP-2->SP, src->@SP - - - -
+// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
+// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
+//
+//-----------------------------------------------------------------------------
+// TWO-OPERAND ARITHMETIC:
+//-----------------------------------------------------------------------------
+// Mnemonic S-Reg, Operation Status bits
+// D-Reg, V N Z C
+//
+// MOV src,dst src -> dst - - - -
+// ADD src,dst src + dst -> dst * * * *
+// ADDC src,dst src + dst + C -> dst * * * *
+// SUB src,dst dst + ~src + 1 -> dst * * * *
+// SUBC src,dst dst + ~src + C -> dst * * * *
+// CMP src,dst dst + ~src + 1 * * * *
+// DADD src,dst src + dst + C -> dst (decimaly) * * * *
+// BIT src,dst src & dst 0 * * *
+// BIC src,dst ~src & dst -> dst - - - -
+// BIS src,dst src | dst -> dst - - - -
+// XOR src,dst src ^ dst -> dst * * * *
+// AND src,dst src & dst -> dst 0 * * *
+//
+//-----------------------------------------------------------------------------
+// * the status bit is affected
+// - the status bit is not affected
+// 0 the status bit is cleared
+// 1 the status bit is set
+//-----------------------------------------------------------------------------
+
+// Invert source for substract and compare instructions.
+wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
+wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
+
+
+// Mask the bit 8 for the Byte instructions for correct flags generation
+wire op_bit8_msk = ~exec_cycle | ~inst_bw;
+wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]};
+wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]};
+
+// Clear the source operand (= jump offset) for conditional jumps
+wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
+ (inst_jmp[`JGE] & (status[3]^status[2])) |
+ (inst_jmp[`JN] & ~status[2]) |
+ (inst_jmp[`JC] & ~status[0]) |
+ (inst_jmp[`JNC] & status[0]) |
+ (inst_jmp[`JEQ] & ~status[1]) |
+ (inst_jmp[`JNE] & status[1]);
+wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
+
+// Adder / AND / OR / XOR
+wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
+wire [16:0] alu_and = op_src_in & op_dst_in;
+wire [16:0] alu_or = op_src_in | op_dst_in;
+wire [16:0] alu_xor = op_src_in ^ op_dst_in;
+
+
+// Incrementer
+wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
+ inst_alu[`ALU_INC]);
+wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc};
+
+
+
+// Decimal adder (DADD)
+wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
+wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
+wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
+wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
+wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
+
+
+// Shifter for rotate instructions (RRC & RRA)
+wire alu_shift_msb = inst_so[`RRC] ? status[0] :
+ inst_bw ? op_src[7] : op_src[15];
+wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
+wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
+
+
+// Swap bytes / Extend Sign
+wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]};
+wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]};
+
+
+// Combine short paths toghether to simplify final ALU mux
+wire alu_short_thro = ~(inst_alu[`ALU_AND] |
+ inst_alu[`ALU_OR] |
+ inst_alu[`ALU_XOR] |
+ inst_alu[`ALU_SHIFT] |
+ inst_so[`SWPB] |
+ inst_so[`SXT]);
+
+wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) |
+ ({16{inst_alu[`ALU_OR]}} & alu_or) |
+ ({16{inst_alu[`ALU_XOR]}} & alu_xor) |
+ ({16{inst_alu[`ALU_SHIFT]}} & alu_shift) |
+ ({16{inst_so[`SWPB]}} & alu_swpb) |
+ ({16{inst_so[`SXT]}} & alu_sxt) |
+ ({16{alu_short_thro}} & op_src_in);
+
+
+// ALU output mux
+wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
+ inst_alu[`ALU_ADD]) ? alu_add_inc :
+ inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
+
+assign alu_out = alu_out_nxt[15:0];
+assign alu_out_add = alu_add[15:0];
+
+
+//-----------------------------------------------------------------------------
+// STATUS FLAG GENERATION
+//-----------------------------------------------------------------------------
+
+wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
+ (op_src_in[15] & op_dst_in[15]);
+
+wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
+ ( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
+ ((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
+ ( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
+
+wire N = inst_bw ? alu_out[7] : alu_out[15];
+wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
+wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
+
+assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} :
+ inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} :
+ inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
+
+assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;
+
+
+endmodule // omsp_alu
+
+`include "openMSP430_undefines.v"
actel/src/omsp_alu.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_register_file.v
===================================================================
--- actel/src/omsp_register_file.v (nonexistent)
+++ actel/src/omsp_register_file.v (revision 64)
@@ -0,0 +1,345 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_register_file.v
+//
+// *Module Description:
+// openMSP430 Register files
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_register_file (
+
+// OUTPUTs
+ cpuoff, // Turns off the CPU
+ gie, // General interrupt enable
+ oscoff, // Turns off LFXT1 clock input
+ pc_sw, // Program counter software value
+ pc_sw_wr, // Program counter software write
+ reg_dest, // Selected register destination content
+ reg_src, // Selected register source content
+ scg1, // System clock generator 1. Turns off the SMCLK
+ status, // R2 Status {V,N,Z,C}
+
+// INPUTs
+ alu_stat, // ALU Status {V,N,Z,C}
+ alu_stat_wr, // ALU Status write {V,N,Z,C}
+ inst_bw, // Decoded Inst: byte width
+ inst_dest, // Register destination selection
+ inst_src, // Register source selection
+ mclk, // Main system clock
+ pc, // Program counter
+ puc, // Main system reset
+ reg_dest_val, // Selected register destination value
+ reg_dest_wr, // Write selected register destination
+ reg_pc_call, // Trigger PC update for a CALL instruction
+ reg_sp_val, // Stack Pointer next value
+ reg_sp_wr, // Stack Pointer write
+ reg_sr_wr, // Status register update for RETI instruction
+ reg_sr_clr, // Status register clear for interrupts
+ reg_incr // Increment source register
+);
+
+// OUTPUTs
+//=========
+output cpuoff; // Turns off the CPU
+output gie; // General interrupt enable
+output oscoff; // Turns off LFXT1 clock input
+output [15:0] pc_sw; // Program counter software value
+output pc_sw_wr; // Program counter software write
+output [15:0] reg_dest; // Selected register destination content
+output [15:0] reg_src; // Selected register source content
+output scg1; // System clock generator 1. Turns off the SMCLK
+output [3:0] status; // R2 Status {V,N,Z,C}
+
+// INPUTs
+//=========
+input [3:0] alu_stat; // ALU Status {V,N,Z,C}
+input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
+input inst_bw; // Decoded Inst: byte width
+input [15:0] inst_dest; // Register destination selection
+input [15:0] inst_src; // Register source selection
+input mclk; // Main system clock
+input [15:0] pc; // Program counter
+input puc; // Main system reset
+input [15:0] reg_dest_val; // Selected register destination value
+input reg_dest_wr; // Write selected register destination
+input reg_pc_call; // Trigger PC update for a CALL instruction
+input [15:0] reg_sp_val; // Stack Pointer next value
+input reg_sp_wr; // Stack Pointer write
+input reg_sr_wr; // Status register update for RETI instruction
+input reg_sr_clr; // Status register clear for interrupts
+input reg_incr; // Increment source register
+
+
+//=============================================================================
+// 1) AUTOINCREMENT UNIT
+//=============================================================================
+
+wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002;
+wire [15:0] reg_incr_val = reg_src+incr_op;
+
+wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val;
+
+
+//=============================================================================
+// 2) SPECIAL REGISTERS (R1/R2/R3)
+//=============================================================================
+
+// Source input selection mask (for interrupt support)
+//-----------------------------------------------------
+
+wire [15:0] inst_src_in = reg_sr_clr ? 16'h0004 : inst_src;
+
+
+// R0: Program counter
+//---------------------
+
+wire [15:0] r0 = pc;
+
+wire [15:0] pc_sw = reg_dest_val_in;
+wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call;
+
+
+// R1: Stack pointer
+//-------------------
+reg [15:0] r1;
+wire r1_wr = inst_dest[1] & reg_dest_wr;
+wire r1_inc = inst_src_in[1] & reg_incr;
+
+always @(posedge mclk or posedge puc)
+ if (puc) r1 <= 16'h0000;
+ else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe;
+ else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe;
+ else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
+
+
+// R2: Status register
+//---------------------
+reg [15:0] r2;
+wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
+
+wire r2_c = alu_stat_wr[0] ? alu_stat[0] :
+ r2_wr ? reg_dest_val_in[0] : r2[0]; // C
+
+wire r2_z = alu_stat_wr[1] ? alu_stat[1] :
+ r2_wr ? reg_dest_val_in[1] : r2[1]; // Z
+
+wire r2_n = alu_stat_wr[2] ? alu_stat[2] :
+ r2_wr ? reg_dest_val_in[2] : r2[2]; // N
+
+wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3];
+
+wire r2_v = alu_stat_wr[3] ? alu_stat[3] :
+ r2_wr ? reg_dest_val_in[8] : r2[8]; // V
+
+
+always @(posedge mclk or posedge puc)
+ if (puc) r2 <= 16'h0000;
+ else if (reg_sr_clr) r2 <= 16'h0000;
+ else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c};
+
+assign status = {r2[8], r2[2:0]};
+assign gie = r2[3];
+assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr);
+assign oscoff = r2[5];
+assign scg1 = r2[7];
+
+
+// R3: Constant generator
+//------------------------
+reg [15:0] r3;
+wire r3_wr = inst_dest[3] & reg_dest_wr;
+wire r3_inc = inst_src_in[3] & reg_incr;
+
+always @(posedge mclk or posedge puc)
+ if (puc) r3 <= 16'h0000;
+ else if (r3_wr) r3 <= reg_dest_val_in;
+ else if (r3_inc) r3 <= reg_incr_val;
+
+
+//=============================================================================
+// 4) GENERAL PURPOSE REGISTERS (R4...R15)
+//=============================================================================
+
+// R4
+reg [15:0] r4;
+wire r4_wr = inst_dest[4] & reg_dest_wr;
+wire r4_inc = inst_src_in[4] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r4 <= 16'h0000;
+ else if (r4_wr) r4 <= reg_dest_val_in;
+ else if (r4_inc) r4 <= reg_incr_val;
+
+// R5
+reg [15:0] r5;
+wire r5_wr = inst_dest[5] & reg_dest_wr;
+wire r5_inc = inst_src_in[5] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r5 <= 16'h0000;
+ else if (r5_wr) r5 <= reg_dest_val_in;
+ else if (r5_inc) r5 <= reg_incr_val;
+
+// R6
+reg [15:0] r6;
+wire r6_wr = inst_dest[6] & reg_dest_wr;
+wire r6_inc = inst_src_in[6] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r6 <= 16'h0000;
+ else if (r6_wr) r6 <= reg_dest_val_in;
+ else if (r6_inc) r6 <= reg_incr_val;
+
+// R7
+reg [15:0] r7;
+wire r7_wr = inst_dest[7] & reg_dest_wr;
+wire r7_inc = inst_src_in[7] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r7 <= 16'h0000;
+ else if (r7_wr) r7 <= reg_dest_val_in;
+ else if (r7_inc) r7 <= reg_incr_val;
+
+// R8
+reg [15:0] r8;
+wire r8_wr = inst_dest[8] & reg_dest_wr;
+wire r8_inc = inst_src_in[8] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r8 <= 16'h0000;
+ else if (r8_wr) r8 <= reg_dest_val_in;
+ else if (r8_inc) r8 <= reg_incr_val;
+
+// R9
+reg [15:0] r9;
+wire r9_wr = inst_dest[9] & reg_dest_wr;
+wire r9_inc = inst_src_in[9] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r9 <= 16'h0000;
+ else if (r9_wr) r9 <= reg_dest_val_in;
+ else if (r9_inc) r9 <= reg_incr_val;
+
+// R10
+reg [15:0] r10;
+wire r10_wr = inst_dest[10] & reg_dest_wr;
+wire r10_inc = inst_src_in[10] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r10 <= 16'h0000;
+ else if (r10_wr) r10 <= reg_dest_val_in;
+ else if (r10_inc) r10 <= reg_incr_val;
+
+// R11
+reg [15:0] r11;
+wire r11_wr = inst_dest[11] & reg_dest_wr;
+wire r11_inc = inst_src_in[11] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r11 <= 16'h0000;
+ else if (r11_wr) r11 <= reg_dest_val_in;
+ else if (r11_inc) r11 <= reg_incr_val;
+
+// R12
+reg [15:0] r12;
+wire r12_wr = inst_dest[12] & reg_dest_wr;
+wire r12_inc = inst_src_in[12] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r12 <= 16'h0000;
+ else if (r12_wr) r12 <= reg_dest_val_in;
+ else if (r12_inc) r12 <= reg_incr_val;
+
+// R13
+reg [15:0] r13;
+wire r13_wr = inst_dest[13] & reg_dest_wr;
+wire r13_inc = inst_src_in[13] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r13 <= 16'h0000;
+ else if (r13_wr) r13 <= reg_dest_val_in;
+ else if (r13_inc) r13 <= reg_incr_val;
+
+// R14
+reg [15:0] r14;
+wire r14_wr = inst_dest[14] & reg_dest_wr;
+wire r14_inc = inst_src_in[14] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r14 <= 16'h0000;
+ else if (r14_wr) r14 <= reg_dest_val_in;
+ else if (r14_inc) r14 <= reg_incr_val;
+
+// R15
+reg [15:0] r15;
+wire r15_wr = inst_dest[15] & reg_dest_wr;
+wire r15_inc = inst_src_in[15] & reg_incr;
+always @(posedge mclk or posedge puc)
+ if (puc) r15 <= 16'h0000;
+ else if (r15_wr) r15 <= reg_dest_val_in;
+ else if (r15_inc) r15 <= reg_incr_val;
+
+
+//=============================================================================
+// 5) READ MUX
+//=============================================================================
+
+assign reg_src = (r0 & {16{inst_src_in[0]}}) |
+ (r1 & {16{inst_src_in[1]}}) |
+ (r2 & {16{inst_src_in[2]}}) |
+ (r3 & {16{inst_src_in[3]}}) |
+ (r4 & {16{inst_src_in[4]}}) |
+ (r5 & {16{inst_src_in[5]}}) |
+ (r6 & {16{inst_src_in[6]}}) |
+ (r7 & {16{inst_src_in[7]}}) |
+ (r8 & {16{inst_src_in[8]}}) |
+ (r9 & {16{inst_src_in[9]}}) |
+ (r10 & {16{inst_src_in[10]}}) |
+ (r11 & {16{inst_src_in[11]}}) |
+ (r12 & {16{inst_src_in[12]}}) |
+ (r13 & {16{inst_src_in[13]}}) |
+ (r14 & {16{inst_src_in[14]}}) |
+ (r15 & {16{inst_src_in[15]}});
+
+assign reg_dest = (r0 & {16{inst_dest[0]}}) |
+ (r1 & {16{inst_dest[1]}}) |
+ (r2 & {16{inst_dest[2]}}) |
+ (r3 & {16{inst_dest[3]}}) |
+ (r4 & {16{inst_dest[4]}}) |
+ (r5 & {16{inst_dest[5]}}) |
+ (r6 & {16{inst_dest[6]}}) |
+ (r7 & {16{inst_dest[7]}}) |
+ (r8 & {16{inst_dest[8]}}) |
+ (r9 & {16{inst_dest[9]}}) |
+ (r10 & {16{inst_dest[10]}}) |
+ (r11 & {16{inst_dest[11]}}) |
+ (r12 & {16{inst_dest[12]}}) |
+ (r13 & {16{inst_dest[13]}}) |
+ (r14 & {16{inst_dest[14]}}) |
+ (r15 & {16{inst_dest[15]}});
+
+
+endmodule // omsp_register_file
+
+`include "openMSP430_undefines.v"
actel/src/omsp_register_file.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_dbg_uart.v
===================================================================
--- actel/src/omsp_dbg_uart.v (nonexistent)
+++ actel/src/omsp_dbg_uart.v (revision 64)
@@ -0,0 +1,268 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_dbg_uart.v
+//
+// *Module Description:
+// Debug UART communication interface (8N1, Half-duplex)
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_dbg_uart (
+
+// OUTPUTs
+ dbg_addr, // Debug register address
+ dbg_din, // Debug register data input
+ dbg_rd, // Debug register data read
+ dbg_uart_txd, // Debug interface: UART TXD
+ dbg_wr, // Debug register data write
+
+// INPUTs
+ dbg_dout, // Debug register data output
+ dbg_rd_rdy, // Debug register data is ready for read
+ dbg_uart_rxd, // Debug interface: UART RXD
+ mclk, // Main system clock
+ mem_burst, // Burst on going
+ mem_burst_end, // End TX/RX burst
+ mem_burst_rd, // Start TX burst
+ mem_burst_wr, // Start RX burst
+ mem_bw, // Burst byte width
+ por // Power on reset
+);
+
+// OUTPUTs
+//=========
+output [5:0] dbg_addr; // Debug register address
+output [15:0] dbg_din; // Debug register data input
+output dbg_rd; // Debug register data read
+output dbg_uart_txd; // Debug interface: UART TXD
+output dbg_wr; // Debug register data write
+
+// INPUTs
+//=========
+input [15:0] dbg_dout; // Debug register data output
+input dbg_rd_rdy; // Debug register data is ready for read
+input dbg_uart_rxd; // Debug interface: UART RXD
+input mclk; // Main system clock
+input mem_burst; // Burst on going
+input mem_burst_end; // End TX/RX burst
+input mem_burst_rd; // Start TX burst
+input mem_burst_wr; // Start RX burst
+input mem_bw; // Burst byte width
+input por; // Power on reset
+
+
+//=============================================================================
+// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
+//=============================================================================
+
+// Synchronize RXD input & buffer
+//--------------------------------
+reg [3:0] rxd_sync;
+always @ (posedge mclk or posedge por)
+ if (por) rxd_sync <= 4'h0;
+ else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
+
+// Majority decision
+//------------------------
+reg rxd_maj;
+
+wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
+ {1'b0, rxd_sync[2]} +
+ {1'b0, rxd_sync[3]};
+wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
+
+always @ (posedge mclk or posedge por)
+ if (por) rxd_maj <= 1'b0;
+ else rxd_maj <= rxd_maj_nxt;
+
+wire rxd_s = rxd_maj;
+wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
+wire rxd_re = ~rxd_maj & rxd_maj_nxt;
+
+
+//=============================================================================
+// 2) UART STATE MACHINE
+//=============================================================================
+
+// Receive state
+//------------------------
+reg [2:0] uart_state;
+reg [2:0] uart_state_nxt;
+
+wire sync_done;
+wire xfer_done;
+reg [19:0] xfer_buf;
+
+// State machine definition
+parameter RX_SYNC = 3'h0;
+parameter RX_CMD = 3'h1;
+parameter RX_DATA1 = 3'h2;
+parameter RX_DATA2 = 3'h3;
+parameter TX_DATA1 = 3'h4;
+parameter TX_DATA2 = 3'h5;
+
+// State transition
+always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
+ case (uart_state)
+ RX_SYNC : uart_state_nxt = RX_CMD;
+ RX_CMD : uart_state_nxt = mem_burst_wr ?
+ (mem_bw ? RX_DATA2 : RX_DATA1) :
+ mem_burst_rd ?
+ (mem_bw ? TX_DATA2 : TX_DATA1) :
+ (xfer_buf[`DBG_UART_WR] ?
+ (xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
+ (xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
+ RX_DATA1 : uart_state_nxt = RX_DATA2;
+ RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
+ (mem_bw ? RX_DATA2 : RX_DATA1) :
+ RX_CMD;
+ TX_DATA1 : uart_state_nxt = TX_DATA2;
+ TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
+ (mem_bw ? TX_DATA2 : TX_DATA1) :
+ RX_CMD;
+ default : uart_state_nxt = RX_CMD;
+ endcase
+
+// State machine
+always @(posedge mclk or posedge por)
+ if (por) uart_state <= RX_SYNC;
+ else if (xfer_done | sync_done |
+ mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
+
+// Utility signals
+wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
+wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
+
+
+//=============================================================================
+// 3) UART SYNCHRONIZATION
+//=============================================================================
+// After POR, the host needs to fist send a synchronization character (0x80)
+// If this feature doesn't work properly, it is possible to disable it by
+// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
+
+reg sync_busy;
+always @ (posedge mclk or posedge por)
+ if (por) sync_busy <= 1'b0;
+ else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
+ else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
+
+assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
+
+`ifdef DBG_UART_AUTO_SYNC
+
+reg [14:0] sync_cnt;
+always @ (posedge mclk or posedge por)
+ if (por) sync_cnt <= 15'h7ff8;
+ else if (sync_busy) sync_cnt <= sync_cnt+15'h0001;
+
+wire [11:0] bit_cnt_max = sync_cnt[14:3];
+`else
+wire [11:0] bit_cnt_max = `DBG_UART_CNT;
+`endif
+
+
+//=============================================================================
+// 4) UART RECEIVE / TRANSMIT
+//=============================================================================
+
+// Transfer counter
+//------------------------
+reg [3:0] xfer_bit;
+reg [11:0] xfer_cnt;
+
+wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
+wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
+wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000);
+assign xfer_done = (xfer_bit==4'hb);
+
+always @ (posedge mclk or posedge por)
+ if (por) xfer_bit <= 4'h0;
+ else if (txd_start | rxd_start) xfer_bit <= 4'h1;
+ else if (xfer_done) xfer_bit <= 4'h0;
+ else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
+
+always @ (posedge mclk or posedge por)
+ if (por) xfer_cnt <= 12'h000;
+ else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]};
+ else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
+ else xfer_cnt <= xfer_cnt+12'hfff;
+
+
+// Receive/Transmit buffer
+//-------------------------
+wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
+
+always @ (posedge mclk or posedge por)
+ if (por) xfer_buf <= 18'h00000;
+ else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
+ else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
+
+
+// Generate TXD output
+//------------------------
+reg dbg_uart_txd;
+
+always @ (posedge mclk or posedge por)
+ if (por) dbg_uart_txd <= 1'b1;
+ else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
+
+
+//=============================================================================
+// 5) INTERFACE TO DEBUG REGISTERS
+//=============================================================================
+
+reg [5:0] dbg_addr;
+ always @ (posedge mclk or posedge por)
+ if (por) dbg_addr <= 6'h00;
+ else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
+
+reg dbg_bw;
+always @ (posedge mclk or posedge por)
+ if (por) dbg_bw <= 1'b0;
+ else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
+
+wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
+
+wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
+ {xfer_buf[18:11], xfer_buf[8:1]};
+wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
+wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
+ (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
+
+
+
+endmodule // omsp_dbg_uart
+
+`include "openMSP430_undefines.v"
actel/src/omsp_dbg_uart.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_dbg_hwbrk.v
===================================================================
--- actel/src/omsp_dbg_hwbrk.v (nonexistent)
+++ actel/src/omsp_dbg_hwbrk.v (revision 64)
@@ -0,0 +1,272 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_dbg_hwbrk.v
+//
+// *Module Description:
+// Hardware Breakpoint / Watchpoint module
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 57 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mo, 01 Feb 2010) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_dbg_hwbrk (
+
+// OUTPUTs
+ brk_halt, // Hardware breakpoint command
+ brk_pnd, // Hardware break/watch-point pending
+ brk_dout, // Hardware break/watch-point register data input
+
+// INPUTs
+ brk_reg_rd, // Hardware break/watch-point register read select
+ brk_reg_wr, // Hardware break/watch-point register write select
+ dbg_din, // Debug register data input
+ eu_mab, // Execution-Unit Memory address bus
+ eu_mb_en, // Execution-Unit Memory bus enable
+ eu_mb_wr, // Execution-Unit Memory bus write transfer
+ eu_mdb_in, // Memory data bus input
+ eu_mdb_out, // Memory data bus output
+ exec_done, // Execution completed
+ fe_mb_en, // Frontend Memory bus enable
+ mclk, // Main system clock
+ pc, // Program counter
+ por // Power on reset
+);
+
+// OUTPUTs
+//=========
+output brk_halt; // Hardware breakpoint command
+output brk_pnd; // Hardware break/watch-point pending
+output [15:0] brk_dout; // Hardware break/watch-point register data input
+
+// INPUTs
+//=========
+input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
+input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
+input [15:0] dbg_din; // Debug register data input
+input [15:0] eu_mab; // Execution-Unit Memory address bus
+input eu_mb_en; // Execution-Unit Memory bus enable
+input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
+input [15:0] eu_mdb_in; // Memory data bus input
+input [15:0] eu_mdb_out; // Memory data bus output
+input exec_done; // Execution completed
+input fe_mb_en; // Frontend Memory bus enable
+input mclk; // Main system clock
+input [15:0] pc; // Program counter
+input por; // Power on reset
+
+
+//=============================================================================
+// 1) WIRE & PARAMETER DECLARATION
+//=============================================================================
+
+wire range_wr_set;
+wire range_rd_set;
+wire addr1_wr_set;
+wire addr1_rd_set;
+wire addr0_wr_set;
+wire addr0_rd_set;
+
+
+parameter BRK_CTL = 0,
+ BRK_STAT = 1,
+ BRK_ADDR0 = 2,
+ BRK_ADDR1 = 3;
+
+
+//=============================================================================
+// 2) CONFIGURATION REGISTERS
+//=============================================================================
+
+// BRK_CTL Register
+//-----------------------------------------------------------------------------
+// 7 6 5 4 3 2 1 0
+// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
+//
+// ACCESS_MODE: - 00 : Disabled
+// - 01 : Detect read access
+// - 10 : Detect write access
+// - 11 : Detect read/write access
+// NOTE: '10' & '11' modes are not supported on the instruction flow
+//
+// BREAK_EN: - 0 : Watchmode enable
+// - 1 : Break enable
+//
+// INST_EN: - 0 : Checks are done on the execution unit (data flow)
+// - 1 : Checks are done on the frontend (instruction flow)
+//
+// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
+// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
+//
+//-----------------------------------------------------------------------------
+reg [4:0] brk_ctl;
+
+wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
+
+always @ (posedge mclk or posedge por)
+ if (por) brk_ctl <= 5'h00;
+ else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
+
+wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
+
+
+// BRK_STAT Register
+//-----------------------------------------------------------------------------
+// 7 6 5 4 3 2 1 0
+// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
+//-----------------------------------------------------------------------------
+reg [5:0] brk_stat;
+
+wire brk_stat_wr = brk_reg_wr[BRK_STAT];
+wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
+ range_rd_set & `HWBRK_RANGE,
+ addr1_wr_set, addr1_rd_set,
+ addr0_wr_set, addr0_rd_set};
+wire [5:0] brk_stat_clr = ~dbg_din[5:0];
+
+always @ (posedge mclk or posedge por)
+ if (por) brk_stat <= 6'h00;
+ else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
+ else brk_stat <= (brk_stat | brk_stat_set);
+
+wire [7:0] brk_stat_full = {2'b00, brk_stat};
+wire brk_pnd = |brk_stat;
+
+
+// BRK_ADDR0 Register
+//-----------------------------------------------------------------------------
+reg [15:0] brk_addr0;
+
+wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
+
+always @ (posedge mclk or posedge por)
+ if (por) brk_addr0 <= 16'h0000;
+ else if (brk_addr0_wr) brk_addr0 <= dbg_din;
+
+
+// BRK_ADDR1/DATA0 Register
+//-----------------------------------------------------------------------------
+reg [15:0] brk_addr1;
+
+wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
+
+always @ (posedge mclk or posedge por)
+ if (por) brk_addr1 <= 16'h0000;
+ else if (brk_addr1_wr) brk_addr1 <= dbg_din;
+
+
+//============================================================================
+// 3) DATA OUTPUT GENERATION
+//============================================================================
+
+wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
+wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
+wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
+wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
+
+wire [15:0] brk_dout = brk_ctl_rd |
+ brk_stat_rd |
+ brk_addr0_rd |
+ brk_addr1_rd;
+
+
+//============================================================================
+// 4) BREAKPOINT / WATCHPOINT GENERATION
+//============================================================================
+
+// Comparators
+//---------------------------
+// Note: here the comparison logic is instanciated several times in order
+// to improve the timings, at the cost of a bit more area.
+
+wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
+wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
+wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
+ brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
+
+reg fe_mb_en_buf;
+always @ (posedge mclk or posedge por)
+ if (por) fe_mb_en_buf <= 1'b0;
+ else fe_mb_en_buf <= fe_mb_en;
+
+wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
+wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
+wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
+ brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
+
+
+// Detect accesses
+//---------------------------
+
+// Detect Instruction read access
+wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
+wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
+wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
+
+// Detect Execution-Unit write access
+wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
+wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
+wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
+
+// Detect DATA read access
+// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
+// before being written back. In that case, the read flag should not be set.
+// In general, We should here make sure no write access occures during the
+// same instruction cycle before setting the read flag.
+reg [2:0] d_rd_trig;
+always @ (posedge mclk or posedge por)
+ if (por) d_rd_trig <= 3'h0;
+ else if (exec_done) d_rd_trig <= 3'h0;
+ else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
+ equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
+ equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
+
+wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
+wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
+wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
+
+
+// Set flags
+assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
+assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
+assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
+assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
+assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
+assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
+
+
+// Break CPU
+assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
+
+
+endmodule // omsp_dbg_hwbrk
+
+`include "openMSP430_undefines.v"
actel/src/omsp_dbg_hwbrk.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_sfr.v
===================================================================
--- actel/src/omsp_sfr.v (nonexistent)
+++ actel/src/omsp_sfr.v (revision 64)
@@ -0,0 +1,204 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_sfr.v
+//
+// *Module Description:
+// Processor Special function register
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_sfr (
+
+// OUTPUTs
+ nmie, // Non-maskable interrupt enable
+ per_dout, // Peripheral data output
+ wdt_irq, // Watchdog-timer interrupt
+ wdt_reset, // Watchdog-timer reset
+ wdtie, // Watchdog-timer interrupt enable
+
+// INPUTs
+ mclk, // Main system clock
+ nmi_acc, // Non-Maskable interrupt request accepted
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_en, // Peripheral enable (high active)
+ per_wen, // Peripheral write enable (high active)
+ por, // Power-on reset
+ puc, // Main system reset
+ wdtifg_clr, // Clear Watchdog-timer interrupt flag
+ wdtifg_set, // Set Watchdog-timer interrupt flag
+ wdtpw_error, // Watchdog-timer password error
+ wdttmsel // Watchdog-timer mode select
+);
+
+// OUTPUTs
+//=========
+output nmie; // Non-maskable interrupt enable
+output [15:0] per_dout; // Peripheral data output
+output wdt_irq; // Watchdog-timer interrupt
+output wdt_reset; // Watchdog-timer reset
+output wdtie; // Watchdog-timer interrupt enable
+
+// INPUTs
+//=========
+input mclk; // Main system clock
+input nmi_acc; // Non-Maskable interrupt request accepted
+input [7:0] per_addr; // Peripheral address
+input [15:0] per_din; // Peripheral data input
+input per_en; // Peripheral enable (high active)
+input [1:0] per_wen; // Peripheral write enable (high active)
+input por; // Power-on reset
+input puc; // Main system reset
+input wdtifg_clr; // Clear Watchdog-timer interrupt flag
+input wdtifg_set; // Set Watchdog-timer interrupt flag
+input wdtpw_error; // Watchdog-timer password error
+input wdttmsel; // Watchdog-timer mode select
+
+
+//=============================================================================
+// 1) PARAMETER DECLARATION
+//=============================================================================
+
+// Register addresses
+parameter IE1 = 9'h000;
+parameter IFG1 = 9'h002;
+
+// Register one-hot decoder
+parameter IE1_D = (256'h1 << (IE1 /2));
+parameter IFG1_D = (256'h1 << (IFG1 /2));
+
+
+//============================================================================
+// 2) REGISTER DECODER
+//============================================================================
+
+// Register address decode
+reg [255:0] reg_dec;
+always @(per_addr)
+ case (per_addr)
+ (IE1 /2): reg_dec = IE1_D;
+ (IFG1 /2): reg_dec = IFG1_D;
+ default : reg_dec = {256{1'b0}};
+ endcase
+
+// Read/Write probes
+wire reg_lo_write = per_wen[0] & per_en;
+wire reg_hi_write = per_wen[1] & per_en;
+wire reg_read = ~|per_wen & per_en;
+
+// Read/Write vectors
+wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
+wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
+wire [255:0] reg_rd = reg_dec & {256{reg_read}};
+
+
+//============================================================================
+// 3) REGISTERS
+//============================================================================
+
+// IE1 Register
+//--------------
+wire [7:0] ie1;
+wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
+wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
+
+reg nmie;
+always @ (posedge mclk or posedge puc)
+ if (puc) nmie <= 1'b0;
+ else if (nmi_acc) nmie <= 1'b0;
+ else if (ie1_wr) nmie <= ie1_nxt[4];
+
+reg wdtie;
+always @ (posedge mclk or posedge puc)
+ if (puc) wdtie <= 1'b0;
+ else if (ie1_wr) wdtie <= ie1_nxt[0];
+
+assign ie1 = {3'b000, nmie, 3'b000, wdtie};
+
+
+// IFG1 Register
+//---------------
+wire [7:0] ifg1;
+wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
+wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
+
+reg nmiifg;
+always @ (posedge mclk or posedge puc)
+ if (puc) nmiifg <= 1'b0;
+ else if (nmi_acc) nmiifg <= 1'b1;
+ else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
+
+reg wdtifg;
+always @ (posedge mclk or posedge por)
+ if (por) wdtifg <= 1'b0;
+ else if (wdtifg_set) wdtifg <= 1'b1;
+ else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0;
+ else if (ifg1_wr) wdtifg <= ifg1_nxt[0];
+
+assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
+
+
+//============================================================================
+// 4) DATA OUTPUT GENERATION
+//============================================================================
+
+// Data output mux
+wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}});
+wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});
+
+wire [15:0] per_dout = ie1_rd |
+ ifg1_rd;
+
+
+//=============================================================================
+// 5) WATCHDOG INTERRUPT & RESET
+//=============================================================================
+
+// Watchdog interrupt generation
+//---------------------------------
+wire wdt_irq = wdttmsel & wdtifg & wdtie;
+
+
+// Watchdog reset generation
+//-----------------------------
+reg wdt_reset;
+
+always @ (posedge mclk or posedge por)
+ if (por) wdt_reset <= 1'b0;
+ else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
+
+
+endmodule // omsp_sfr
+
+`include "openMSP430_undefines.v"
actel/src/omsp_sfr.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_dbg.v
===================================================================
--- actel/src/omsp_dbg.v (nonexistent)
+++ actel/src/omsp_dbg.v (revision 64)
@@ -0,0 +1,792 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_dbg.v
+//
+// *Module Description:
+// Debug interface
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 53 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-01-27 19:17:14 +0100 (Mi, 27 Jan 2010) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_dbg (
+
+// OUTPUTs
+ dbg_freeze, // Freeze peripherals
+ dbg_halt_cmd, // Halt CPU command
+ dbg_mem_addr, // Debug address for rd/wr access
+ dbg_mem_dout, // Debug unit data output
+ dbg_mem_en, // Debug unit memory enable
+ dbg_mem_wr, // Debug unit memory write
+ dbg_reg_wr, // Debug unit CPU register write
+ dbg_reset, // Reset CPU from debug interface
+ dbg_uart_txd, // Debug interface: UART TXD
+
+// INPUTs
+ dbg_halt_st, // Halt/Run status from CPU
+ dbg_mem_din, // Debug unit Memory data input
+ dbg_reg_din, // Debug unit CPU register data input
+ dbg_uart_rxd, // Debug interface: UART RXD
+ decode_noirq, // Frontend decode instruction
+ eu_mab, // Execution-Unit Memory address bus
+ eu_mb_en, // Execution-Unit Memory bus enable
+ eu_mb_wr, // Execution-Unit Memory bus write transfer
+ eu_mdb_in, // Memory data bus input
+ eu_mdb_out, // Memory data bus output
+ exec_done, // Execution completed
+ fe_mb_en, // Frontend Memory bus enable
+ fe_mdb_in, // Frontend Memory data bus input
+ mclk, // Main system clock
+ pc, // Program counter
+ por, // Power on reset
+ puc // Main system reset
+);
+
+// OUTPUTs
+//=========
+output dbg_freeze; // Freeze peripherals
+output dbg_halt_cmd; // Halt CPU command
+output [15:0] dbg_mem_addr; // Debug address for rd/wr access
+output [15:0] dbg_mem_dout; // Debug unit data output
+output dbg_mem_en; // Debug unit memory enable
+output [1:0] dbg_mem_wr; // Debug unit memory write
+output dbg_reg_wr; // Debug unit CPU register write
+output dbg_reset; // Reset CPU from debug interface
+output dbg_uart_txd; // Debug interface: UART TXD
+
+// INPUTs
+//=========
+input dbg_halt_st; // Halt/Run status from CPU
+input [15:0] dbg_mem_din; // Debug unit Memory data input
+input [15:0] dbg_reg_din; // Debug unit CPU register data input
+input dbg_uart_rxd; // Debug interface: UART RXD
+input decode_noirq; // Frontend decode instruction
+input [15:0] eu_mab; // Execution-Unit Memory address bus
+input eu_mb_en; // Execution-Unit Memory bus enable
+input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
+input [15:0] eu_mdb_in; // Memory data bus input
+input [15:0] eu_mdb_out; // Memory data bus output
+input exec_done; // Execution completed
+input fe_mb_en; // Frontend Memory bus enable
+input [15:0] fe_mdb_in; // Frontend Memory data bus input
+input mclk; // Main system clock
+input [15:0] pc; // Program counter
+input por; // Power on reset
+input puc; // Main system reset
+
+
+//=============================================================================
+// 1) WIRE & PARAMETER DECLARATION
+//=============================================================================
+
+// Diverse wires and registers
+wire [5:0] dbg_addr;
+wire [15:0] dbg_din;
+wire dbg_wr;
+reg mem_burst;
+wire dbg_reg_rd;
+wire dbg_mem_rd;
+reg dbg_mem_rd_dly;
+wire dbg_swbrk;
+wire dbg_rd;
+reg dbg_rd_rdy;
+wire mem_burst_rd;
+wire mem_burst_wr;
+wire brk0_halt;
+wire brk0_pnd;
+wire [15:0] brk0_dout;
+wire brk1_halt;
+wire brk1_pnd;
+wire [15:0] brk1_dout;
+wire brk2_halt;
+wire brk2_pnd;
+wire [15:0] brk2_dout;
+wire brk3_halt;
+wire brk3_pnd;
+wire [15:0] brk3_dout;
+
+// Register addresses
+parameter CPU_ID_LO = 6'h00;
+parameter CPU_ID_HI = 6'h01;
+parameter CPU_CTL = 6'h02;
+parameter CPU_STAT = 6'h03;
+parameter MEM_CTL = 6'h04;
+parameter MEM_ADDR = 6'h05;
+parameter MEM_DATA = 6'h06;
+parameter MEM_CNT = 6'h07;
+`ifdef DBG_HWBRK_0
+parameter BRK0_CTL = 6'h08;
+parameter BRK0_STAT = 6'h09;
+parameter BRK0_ADDR0 = 6'h0A;
+parameter BRK0_ADDR1 = 6'h0B;
+`endif
+`ifdef DBG_HWBRK_1
+parameter BRK1_CTL = 6'h0C;
+parameter BRK1_STAT = 6'h0D;
+parameter BRK1_ADDR0 = 6'h0E;
+parameter BRK1_ADDR1 = 6'h0F;
+`endif
+`ifdef DBG_HWBRK_2
+parameter BRK2_CTL = 6'h10;
+parameter BRK2_STAT = 6'h11;
+parameter BRK2_ADDR0 = 6'h12;
+parameter BRK2_ADDR1 = 6'h13;
+`endif
+`ifdef DBG_HWBRK_3
+parameter BRK3_CTL = 6'h14;
+parameter BRK3_STAT = 6'h15;
+parameter BRK3_ADDR0 = 6'h16;
+parameter BRK3_ADDR1 = 6'h17;
+`endif
+
+// Register one-hot decoder
+parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO);
+parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI);
+parameter CPU_CTL_D = (64'h1 << CPU_CTL);
+parameter CPU_STAT_D = (64'h1 << CPU_STAT);
+parameter MEM_CTL_D = (64'h1 << MEM_CTL);
+parameter MEM_ADDR_D = (64'h1 << MEM_ADDR);
+parameter MEM_DATA_D = (64'h1 << MEM_DATA);
+parameter MEM_CNT_D = (64'h1 << MEM_CNT);
+`ifdef DBG_HWBRK_0
+parameter BRK0_CTL_D = (64'h1 << BRK0_CTL);
+parameter BRK0_STAT_D = (64'h1 << BRK0_STAT);
+parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0);
+parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1);
+`endif
+`ifdef DBG_HWBRK_1
+parameter BRK1_CTL_D = (64'h1 << BRK1_CTL);
+parameter BRK1_STAT_D = (64'h1 << BRK1_STAT);
+parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0);
+parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1);
+`endif
+`ifdef DBG_HWBRK_2
+parameter BRK2_CTL_D = (64'h1 << BRK2_CTL);
+parameter BRK2_STAT_D = (64'h1 << BRK2_STAT);
+parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0);
+parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1);
+`endif
+`ifdef DBG_HWBRK_3
+parameter BRK3_CTL_D = (64'h1 << BRK3_CTL);
+parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
+parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
+parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
+`endif
+
+
+//============================================================================
+// 2) REGISTER DECODER
+//============================================================================
+
+// Select Data register during a burst
+wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
+
+// Register address decode
+reg [63:0] reg_dec;
+always @(dbg_addr_in)
+ case (dbg_addr_in)
+ CPU_ID_LO : reg_dec = CPU_ID_LO_D;
+ CPU_ID_HI : reg_dec = CPU_ID_HI_D;
+ CPU_CTL : reg_dec = CPU_CTL_D;
+ CPU_STAT : reg_dec = CPU_STAT_D;
+ MEM_CTL : reg_dec = MEM_CTL_D;
+ MEM_ADDR : reg_dec = MEM_ADDR_D;
+ MEM_DATA : reg_dec = MEM_DATA_D;
+ MEM_CNT : reg_dec = MEM_CNT_D;
+`ifdef DBG_HWBRK_0
+ BRK0_CTL : reg_dec = BRK0_CTL_D;
+ BRK0_STAT : reg_dec = BRK0_STAT_D;
+ BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
+ BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
+`endif
+`ifdef DBG_HWBRK_1
+ BRK1_CTL : reg_dec = BRK1_CTL_D;
+ BRK1_STAT : reg_dec = BRK1_STAT_D;
+ BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
+ BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
+`endif
+`ifdef DBG_HWBRK_2
+ BRK2_CTL : reg_dec = BRK2_CTL_D;
+ BRK2_STAT : reg_dec = BRK2_STAT_D;
+ BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
+ BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
+`endif
+`ifdef DBG_HWBRK_3
+ BRK3_CTL : reg_dec = BRK3_CTL_D;
+ BRK3_STAT : reg_dec = BRK3_STAT_D;
+ BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
+ BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
+`endif
+ default: reg_dec = {64{1'b0}};
+ endcase
+
+// Read/Write probes
+wire reg_write = dbg_wr;
+wire reg_read = 1'b1;
+
+// Read/Write vectors
+wire [511:0] reg_wr = reg_dec & {64{reg_write}};
+wire [511:0] reg_rd = reg_dec & {64{reg_read}};
+
+
+//=============================================================================
+// 3) REGISTER: CORE INTERFACE
+//=============================================================================
+
+// CPU_ID Register
+//-----------------
+
+wire [3:0] cpu_id_pmem = `PMEM_AWIDTH;
+wire [3:0] cpu_id_dmem = `DMEM_AWIDTH;
+wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem};
+
+
+// CPU_CTL Register
+//-----------------------------------------------------------------------------
+// 7 6 5 4 3 2 1 0
+// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
+//-----------------------------------------------------------------------------
+reg [6:3] cpu_ctl;
+
+wire cpu_ctl_wr = reg_wr[CPU_CTL];
+
+always @ (posedge mclk or posedge por)
+ if (por) cpu_ctl <= 4'h0;
+ else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
+
+wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
+
+wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
+wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
+wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
+
+
+// CPU_STAT Register
+//------------------------------------------------------------------------------------
+// 7 6 5 4 3 2 1 0
+// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
+//------------------------------------------------------------------------------------
+reg [3:2] cpu_stat;
+
+wire cpu_stat_wr = reg_wr[CPU_STAT];
+wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
+wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
+
+always @ (posedge mclk or posedge por)
+ if (por) cpu_stat <= 2'b00;
+ else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
+ else cpu_stat <= (cpu_stat | cpu_stat_set);
+
+wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
+ cpu_stat, 1'b0, dbg_halt_st};
+
+
+//=============================================================================
+// 4) REGISTER: MEMORY INTERFACE
+//=============================================================================
+
+// MEM_CTL Register
+//-----------------------------------------------------------------------------
+// 7 6 5 4 3 2 1 0
+// Reserved B/W MEM/REG RD/WR START
+//
+// START : - 0 : Do nothing.
+// - 1 : Initiate memory transfer.
+//
+// RD/WR : - 0 : Read access.
+// - 1 : Write access.
+//
+// MEM/REG: - 0 : Memory access.
+// - 1 : CPU Register access.
+//
+// B/W : - 0 : 16 bit access.
+// - 1 : 8 bit access (not valid for CPU Registers).
+//
+//-----------------------------------------------------------------------------
+reg [3:1] mem_ctl;
+
+wire mem_ctl_wr = reg_wr[MEM_CTL];
+
+always @ (posedge mclk or posedge por)
+ if (por) mem_ctl <= 3'h0;
+ else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
+
+wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
+
+reg mem_start;
+always @ (posedge mclk or posedge por)
+ if (por) mem_start <= 1'b0;
+ else mem_start <= mem_ctl_wr & dbg_din[0];
+
+wire mem_bw = mem_ctl[3];
+
+// MEM_DATA Register
+//------------------
+reg [15:0] mem_data;
+reg [15:0] mem_addr;
+wire mem_access;
+
+wire mem_data_wr = reg_wr[MEM_DATA];
+
+wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
+ mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
+ {8'h00, dbg_mem_din[7:0]};
+
+always @ (posedge mclk or posedge por)
+ if (por) mem_data <= 16'h0000;
+ else if (mem_data_wr) mem_data <= dbg_din;
+ else if (dbg_reg_rd) mem_data <= dbg_reg_din;
+ else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
+
+
+// MEM_ADDR Register
+//------------------
+reg [15:0] mem_cnt;
+
+wire mem_addr_wr = reg_wr[MEM_ADDR];
+wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
+wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
+
+wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
+ (dbg_mem_acc & ~mem_bw) ? 16'h0002 :
+ (dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
+
+always @ (posedge mclk or posedge por)
+ if (por) mem_addr <= 16'h0000;
+ else if (mem_addr_wr) mem_addr <= dbg_din;
+ else mem_addr <= mem_addr + mem_addr_inc;
+
+// MEM_CNT Register
+//------------------
+
+wire mem_cnt_wr = reg_wr[MEM_CNT];
+
+wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
+ (dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000;
+
+always @ (posedge mclk or posedge por)
+ if (por) mem_cnt <= 16'h0000;
+ else if (mem_cnt_wr) mem_cnt <= dbg_din;
+ else mem_cnt <= mem_cnt + mem_cnt_dec;
+
+
+//=============================================================================
+// 5) BREAKPOINTS / WATCHPOINTS
+//=============================================================================
+
+`ifdef DBG_HWBRK_0
+// Hardware Breakpoint/Watchpoint Register read select
+wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
+ reg_rd[BRK0_ADDR0],
+ reg_rd[BRK0_STAT],
+ reg_rd[BRK0_CTL]};
+
+// Hardware Breakpoint/Watchpoint Register write select
+wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
+ reg_wr[BRK0_ADDR0],
+ reg_wr[BRK0_STAT],
+ reg_wr[BRK0_CTL]};
+
+omsp_dbg_hwbrk dbg_hwbr_0 (
+
+// OUTPUTs
+ .brk_halt (brk0_halt), // Hardware breakpoint command
+ .brk_pnd (brk0_pnd), // Hardware break/watch-point pending
+ .brk_dout (brk0_dout), // Hardware break/watch-point register data input
+
+// INPUTs
+ .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
+ .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
+ .dbg_din (dbg_din), // Debug register data input
+ .eu_mab (eu_mab), // Execution-Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
+ .eu_mdb_in (eu_mdb_in), // Memory data bus input
+ .eu_mdb_out (eu_mdb_out), // Memory data bus output
+ .exec_done (exec_done), // Execution completed
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .por (por) // Power on reset
+);
+
+`else
+assign brk0_halt = 1'b0;
+assign brk0_pnd = 1'b0;
+assign brk0_dout = 16'h0000;
+`endif
+
+`ifdef DBG_HWBRK_1
+// Hardware Breakpoint/Watchpoint Register read select
+wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
+ reg_rd[BRK1_ADDR0],
+ reg_rd[BRK1_STAT],
+ reg_rd[BRK1_CTL]};
+
+// Hardware Breakpoint/Watchpoint Register write select
+wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
+ reg_wr[BRK1_ADDR0],
+ reg_wr[BRK1_STAT],
+ reg_wr[BRK1_CTL]};
+
+omsp_dbg_hwbrk dbg_hwbr_1 (
+
+// OUTPUTs
+ .brk_halt (brk1_halt), // Hardware breakpoint command
+ .brk_pnd (brk1_pnd), // Hardware break/watch-point pending
+ .brk_dout (brk1_dout), // Hardware break/watch-point register data input
+
+// INPUTs
+ .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
+ .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
+ .dbg_din (dbg_din), // Debug register data input
+ .eu_mab (eu_mab), // Execution-Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
+ .eu_mdb_in (eu_mdb_in), // Memory data bus input
+ .eu_mdb_out (eu_mdb_out), // Memory data bus output
+ .exec_done (exec_done), // Execution completed
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .por (por) // Power on reset
+);
+
+`else
+assign brk1_halt = 1'b0;
+assign brk1_pnd = 1'b0;
+assign brk1_dout = 16'h0000;
+`endif
+
+ `ifdef DBG_HWBRK_2
+// Hardware Breakpoint/Watchpoint Register read select
+wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
+ reg_rd[BRK2_ADDR0],
+ reg_rd[BRK2_STAT],
+ reg_rd[BRK2_CTL]};
+
+// Hardware Breakpoint/Watchpoint Register write select
+wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
+ reg_wr[BRK2_ADDR0],
+ reg_wr[BRK2_STAT],
+ reg_wr[BRK2_CTL]};
+
+omsp_dbg_hwbrk dbg_hwbr_2 (
+
+// OUTPUTs
+ .brk_halt (brk2_halt), // Hardware breakpoint command
+ .brk_pnd (brk2_pnd), // Hardware break/watch-point pending
+ .brk_dout (brk2_dout), // Hardware break/watch-point register data input
+
+// INPUTs
+ .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
+ .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
+ .dbg_din (dbg_din), // Debug register data input
+ .eu_mab (eu_mab), // Execution-Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
+ .eu_mdb_in (eu_mdb_in), // Memory data bus input
+ .eu_mdb_out (eu_mdb_out), // Memory data bus output
+ .exec_done (exec_done), // Execution completed
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .por (por) // Power on reset
+);
+
+`else
+assign brk2_halt = 1'b0;
+assign brk2_pnd = 1'b0;
+assign brk2_dout = 16'h0000;
+`endif
+
+`ifdef DBG_HWBRK_3
+// Hardware Breakpoint/Watchpoint Register read select
+wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
+ reg_rd[BRK3_ADDR0],
+ reg_rd[BRK3_STAT],
+ reg_rd[BRK3_CTL]};
+
+// Hardware Breakpoint/Watchpoint Register write select
+wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
+ reg_wr[BRK3_ADDR0],
+ reg_wr[BRK3_STAT],
+ reg_wr[BRK3_CTL]};
+
+omsp_dbg_hwbrk dbg_hwbr_3 (
+
+// OUTPUTs
+ .brk_halt (brk3_halt), // Hardware breakpoint command
+ .brk_pnd (brk3_pnd), // Hardware break/watch-point pending
+ .brk_dout (brk3_dout), // Hardware break/watch-point register data input
+
+// INPUTs
+ .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
+ .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
+ .dbg_din (dbg_din), // Debug register data input
+ .eu_mab (eu_mab), // Execution-Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
+ .eu_mdb_in (eu_mdb_in), // Memory data bus input
+ .eu_mdb_out (eu_mdb_out), // Memory data bus output
+ .exec_done (exec_done), // Execution completed
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .por (por) // Power on reset
+);
+
+`else
+assign brk3_halt = 1'b0;
+assign brk3_pnd = 1'b0;
+assign brk3_dout = 16'h0000;
+`endif
+
+
+//============================================================================
+// 6) DATA OUTPUT GENERATION
+//============================================================================
+
+wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
+wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
+wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
+wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
+wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
+wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
+wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
+wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
+
+wire [15:0] dbg_dout = cpu_id_lo_rd |
+ cpu_id_hi_rd |
+ cpu_ctl_rd |
+ cpu_stat_rd |
+ mem_ctl_rd |
+ mem_data_rd |
+ mem_addr_rd |
+ mem_cnt_rd |
+ brk0_dout |
+ brk1_dout |
+ brk2_dout |
+ brk3_dout;
+
+// Tell UART/JTAG interface that the data is ready to be read
+always @ (posedge mclk or posedge por)
+ if (por) dbg_rd_rdy <= 1'b0;
+ else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
+ else dbg_rd_rdy <= dbg_rd;
+
+
+//============================================================================
+// 7) CPU CONTROL
+//============================================================================
+
+// Reset CPU
+//--------------------------
+wire dbg_reset = cpu_ctl[`CPU_RST];
+
+
+// Break after reset
+//--------------------------
+wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
+
+
+// Freeze peripherals
+//--------------------------
+wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
+
+
+// Software break
+//--------------------------
+assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
+
+
+// Single step
+//--------------------------
+reg [1:0] inc_step;
+always @(posedge mclk or posedge por)
+ if (por) inc_step <= 2'b00;
+ else if (istep) inc_step <= 2'b11;
+ else inc_step <= {inc_step[0], 1'b0};
+
+
+// Run / Halt
+//--------------------------
+reg halt_flag;
+
+wire mem_halt_cpu;
+wire mem_run_cpu;
+
+wire halt_flag_clr = run_cpu | mem_run_cpu;
+wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
+ brk0_halt | brk1_halt | brk2_halt | brk3_halt;
+
+always @(posedge mclk or posedge por)
+ if (por) halt_flag <= 1'b0;
+ else if (halt_flag_clr) halt_flag <= 1'b0;
+ else if (halt_flag_set) halt_flag <= 1'b1;
+
+wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
+
+
+//============================================================================
+// 8) MEMORY CONTROL
+//============================================================================
+
+// Control Memory bursts
+//------------------------------
+
+wire mem_burst_start = (mem_start & |mem_cnt);
+wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
+
+// Detect when burst is on going
+always @(posedge mclk or posedge por)
+ if (por) mem_burst <= 1'b0;
+ else if (mem_burst_start) mem_burst <= 1'b1;
+ else if (mem_burst_end) mem_burst <= 1'b0;
+
+// Control signals for UART/JTAG interface
+assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
+assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
+
+// Trigger CPU Register or memory access during a burst
+reg mem_startb;
+always @(posedge mclk or posedge por)
+ if (por) mem_startb <= 1'b0;
+ else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
+
+// Combine single and burst memory start of sequence
+wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
+
+
+// Memory access state machine
+//------------------------------
+reg [1:0] mem_state;
+reg [1:0] mem_state_nxt;
+
+// State machine definition
+parameter M_IDLE = 2'h0;
+parameter M_SET_BRK = 2'h1;
+parameter M_ACCESS_BRK = 2'h2;
+parameter M_ACCESS = 2'h3;
+
+// State transition
+always @(mem_state or mem_seq_start or dbg_halt_st)
+ case (mem_state)
+ M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
+ dbg_halt_st ? M_ACCESS : M_SET_BRK;
+ M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
+ M_ACCESS_BRK : mem_state_nxt = M_IDLE;
+ M_ACCESS : mem_state_nxt = M_IDLE;
+ default : mem_state_nxt = M_IDLE;
+ endcase
+
+// State machine
+always @(posedge mclk or posedge por)
+ if (por) mem_state <= M_IDLE;
+ else mem_state <= mem_state_nxt;
+
+// Utility signals
+assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
+assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
+assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
+
+
+// Interface to CPU Registers and Memory bacbkone
+//------------------------------------------------
+assign dbg_mem_addr = mem_addr;
+assign dbg_mem_dout = ~mem_bw ? mem_data :
+ mem_addr[0] ? {mem_data[7:0], 8'h00} :
+ {8'h00, mem_data[7:0]};
+
+assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
+assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
+
+assign dbg_mem_en = mem_access & ~mem_ctl[2];
+assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
+
+wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
+ mem_addr[0] ? 2'b10 : 2'b01;
+assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
+
+
+// It takes one additional cycle to read from Memory as from registers
+always @(posedge mclk or posedge por)
+ if (por) dbg_mem_rd_dly <= 1'b0;
+ else dbg_mem_rd_dly <= dbg_mem_rd;
+
+
+//=============================================================================
+// 9) UART COMMUNICATION
+//=============================================================================
+`ifdef DBG_UART
+omsp_dbg_uart dbg_uart_0 (
+
+// OUTPUTs
+ .dbg_addr (dbg_addr), // Debug register address
+ .dbg_din (dbg_din), // Debug register data input
+ .dbg_rd (dbg_rd), // Debug register data read
+ .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
+ .dbg_wr (dbg_wr), // Debug register data write
+
+// INPUTs
+ .dbg_dout (dbg_dout), // Debug register data output
+ .dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
+ .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
+ .mclk (mclk), // Main system clock
+ .mem_burst (mem_burst), // Burst on going
+ .mem_burst_end(mem_burst_end), // End TX/RX burst
+ .mem_burst_rd (mem_burst_rd), // Start TX burst
+ .mem_burst_wr (mem_burst_wr), // Start RX burst
+ .mem_bw (mem_bw), // Burst byte width
+ .por (por) // Power on reset
+);
+
+`else
+assign dbg_addr = 6'h00;
+assign dbg_din = 16'h0000;
+assign dbg_rd = 1'b0;
+assign dbg_uart_txd = 1'b0;
+assign dbg_wr = 1'b0;
+`endif
+
+
+//=============================================================================
+// 10) JTAG COMMUNICATION
+//=============================================================================
+`ifdef DBG_JTAG
+JTAG INTERFACE IS NOT SUPPORTED YET
+`else
+`endif
+
+endmodule // dbg
+
+`include "openMSP430_undefines.v"
actel/src/omsp_dbg.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_clock_module.v
===================================================================
--- actel/src/omsp_clock_module.v (nonexistent)
+++ actel/src/omsp_clock_module.v (revision 64)
@@ -0,0 +1,247 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_clock_module.v
+//
+// *Module Description:
+// Basic clock module implementation.
+// Since the openMSP430 mainly targets FPGA and hobby
+// designers. The clock structure has been greatly
+// symplified in order to ease integration.
+// See online wiki for more info.
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_clock_module (
+
+// OUTPUTs
+ aclk_en, // ACLK enable
+ mclk, // Main system clock
+ per_dout, // Peripheral data output
+ por, // Power-on reset
+ puc, // Main system reset
+ smclk_en, // SMCLK enable
+
+// INPUTs
+ dbg_reset, // Reset CPU from debug interface
+ dco_clk, // Fast oscillator (fast clock)
+ lfxt_clk, // Low frequency oscillator (typ 32kHz)
+ oscoff, // Turns off LFXT1 clock input
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_en, // Peripheral enable (high active)
+ per_wen, // Peripheral write enable (high active)
+ reset_n, // Reset Pin (low active)
+ scg1, // System clock generator 1. Turns off the SMCLK
+ wdt_reset // Watchdog-timer reset
+);
+
+// OUTPUTs
+//=========
+output aclk_en; // ACLK enable
+output mclk; // Main system clock
+output [15:0] per_dout; // Peripheral data output
+output por; // Power-on reset
+output puc; // Main system reset
+output smclk_en; // SMCLK enable
+
+// INPUTs
+//=========
+input dbg_reset; // Reset CPU from debug interface
+input dco_clk; // Fast oscillator (fast clock)
+input lfxt_clk; // Low frequency oscillator (typ 32kHz)
+input oscoff; // Turns off LFXT1 clock input
+input [7:0] per_addr; // Peripheral address
+input [15:0] per_din; // Peripheral data input
+input per_en; // Peripheral enable (high active)
+input [1:0] per_wen; // Peripheral write enable (high active)
+input reset_n; // Reset Pin (low active)
+input scg1; // System clock generator 1. Turns off the SMCLK
+input wdt_reset; // Watchdog-timer reset
+
+
+//=============================================================================
+// 1) PARAMETER DECLARATION
+//=============================================================================
+
+// Register addresses
+parameter BCSCTL1 = 9'h057;
+parameter BCSCTL2 = 9'h058;
+
+// Register one-hot decoder
+parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2));
+parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2));
+
+
+//============================================================================
+// 2) REGISTER DECODER
+//============================================================================
+
+// Register address decode
+reg [255:0] reg_dec;
+always @(per_addr)
+ case (per_addr)
+ (BCSCTL1 /2): reg_dec = BCSCTL1_D;
+ (BCSCTL2 /2): reg_dec = BCSCTL2_D;
+ default : reg_dec = {256{1'b0}};
+ endcase
+
+// Read/Write probes
+wire reg_lo_write = per_wen[0] & per_en;
+wire reg_hi_write = per_wen[1] & per_en;
+wire reg_read = ~|per_wen & per_en;
+
+// Read/Write vectors
+wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
+wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
+wire [255:0] reg_rd = reg_dec & {256{reg_read}};
+
+
+//============================================================================
+// 3) REGISTERS
+//============================================================================
+
+// BCSCTL1 Register
+//--------------
+reg [7:0] bcsctl1;
+wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2];
+wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
+
+always @ (posedge mclk or posedge puc)
+ if (puc) bcsctl1 <= 8'h00;
+ else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits
+
+
+// BCSCTL2 Register
+//--------------
+reg [7:0] bcsctl2;
+wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2];
+wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0];
+
+always @ (posedge mclk or posedge puc)
+ if (puc) bcsctl2 <= 8'h00;
+ else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits
+
+
+//============================================================================
+// 4) DATA OUTPUT GENERATION
+//============================================================================
+
+// Data output mux
+wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}});
+wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}});
+
+wire [15:0] per_dout = bcsctl1_rd |
+ bcsctl2_rd;
+
+
+//=============================================================================
+// 5) CLOCK GENERATION
+//=============================================================================
+
+// Synchronize LFXT_CLK & edge detection
+//---------------------------------------
+reg [2:0] lfxt_clk_s;
+
+always @ (posedge mclk or posedge puc)
+ if (puc) lfxt_clk_s <= 3'b000;
+ else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
+
+wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
+
+
+// Generate main system clock
+//----------------------------
+
+wire mclk = dco_clk;
+wire mclk_n = !dco_clk;
+
+
+// Generate ACLK
+//----------------------------
+
+reg [2:0] aclk_div;
+
+wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
+ (bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
+ (bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
+ &aclk_div[2:0]);
+
+always @ (posedge mclk or posedge puc)
+ if (puc) aclk_div <= 3'h0;
+ else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
+
+
+// Generate SMCLK
+//----------------------------
+
+reg [2:0] smclk_div;
+
+wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
+
+wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
+ (bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
+ (bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
+ &smclk_div[2:0]);
+
+always @ (posedge mclk or posedge puc)
+ if (puc) smclk_div <= 3'h0;
+ else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
+
+
+//=============================================================================
+// 6) RESET GENERATION
+//=============================================================================
+
+// Generate synchronized POR
+wire por_reset = !reset_n;
+
+reg [1:0] por_s;
+always @(posedge mclk_n or posedge por_reset)
+ if (por_reset) por_s <= 2'b11;
+ else por_s <= {por_s[0], 1'b0};
+wire por = por_s[1];
+
+// Generate main system reset
+wire puc_reset = por_reset | wdt_reset | dbg_reset;
+
+reg [1:0] puc_s;
+always @(posedge mclk_n or posedge puc_reset)
+ if (puc_reset) puc_s <= 2'b11;
+ else puc_s <= {puc_s[0], 1'b0};
+wire puc = puc_s[1];
+
+
+endmodule // omsp_clock_module
+
+`include "openMSP430_undefines.v"
actel/src/omsp_clock_module.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_watchdog.v
===================================================================
--- actel/src/omsp_watchdog.v (nonexistent)
+++ actel/src/omsp_watchdog.v (revision 64)
@@ -0,0 +1,217 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_watchdog.v
+//
+// *Module Description:
+// Watchdog Timer
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_watchdog (
+
+// OUTPUTs
+ nmi_evt, // NMI Event
+ per_dout, // Peripheral data output
+ wdtifg_set, // Set Watchdog-timer interrupt flag
+ wdtpw_error, // Watchdog-timer password error
+ wdttmsel, // Watchdog-timer mode select
+
+// INPUTs
+ aclk_en, // ACLK enable
+ dbg_freeze, // Freeze Watchdog counter
+ mclk, // Main system clock
+ nmi, // Non-maskable interrupt (asynchronous)
+ nmie, // Non-maskable interrupt enable
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_en, // Peripheral enable (high active)
+ per_wen, // Peripheral write enable (high active)
+ puc, // Main system reset
+ smclk_en, // SMCLK enable
+ wdtie // Watchdog timer interrupt enable
+);
+
+// OUTPUTs
+//=========
+output nmi_evt; // NMI Event
+output [15:0] per_dout; // Peripheral data output
+output wdtifg_set; // Set Watchdog-timer interrupt flag
+output wdtpw_error; // Watchdog-timer password error
+output wdttmsel; // Watchdog-timer mode select
+
+// INPUTs
+//=========
+input aclk_en; // ACLK enable
+input dbg_freeze; // Freeze Watchdog counter
+input mclk; // Main system clock
+input nmi; // Non-maskable interrupt (asynchronous)
+input nmie; // Non-maskable interrupt enable
+input [7:0] per_addr; // Peripheral address
+input [15:0] per_din; // Peripheral data input
+input per_en; // Peripheral enable (high active)
+input [1:0] per_wen; // Peripheral write enable (high active)
+input puc; // Main system reset
+input smclk_en; // SMCLK enable
+input wdtie; // Watchdog timer interrupt enable
+
+
+//=============================================================================
+// 1) PARAMETER DECLARATION
+//=============================================================================
+
+// Register addresses
+parameter WDTCTL = 9'h120;
+
+
+// Register one-hot decoder
+parameter WDTCTL_D = (512'h1 << WDTCTL);
+
+
+//============================================================================
+// 2) REGISTER DECODER
+//============================================================================
+
+// Register address decode
+reg [511:0] reg_dec;
+always @(per_addr)
+ case ({per_addr,1'b0})
+ WDTCTL : reg_dec = WDTCTL_D;
+ default: reg_dec = {512{1'b0}};
+ endcase
+
+// Read/Write probes
+wire reg_write = |per_wen & per_en;
+wire reg_read = ~|per_wen & per_en;
+
+// Read/Write vectors
+wire [511:0] reg_wr = reg_dec & {512{reg_write}};
+wire [511:0] reg_rd = reg_dec & {512{reg_read}};
+
+
+//============================================================================
+// 3) REGISTERS
+//============================================================================
+
+// WDTCTL Register
+//-----------------
+// WDTNMI & WDTSSEL are not implemented and therefore masked
+
+reg [7:0] wdtctl;
+
+wire wdtctl_wr = reg_wr[WDTCTL];
+
+always @ (posedge mclk or posedge puc)
+ if (puc) wdtctl <= 8'h00;
+ else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7;
+
+wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
+wire wdttmsel = wdtctl[4];
+
+
+//============================================================================
+// 3) REGISTERS
+//============================================================================
+
+// Data output mux
+wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}};
+
+wire [15:0] per_dout = wdtctl_rd;
+
+
+//=============================================================================
+// 4) NMI GENERATION
+//=============================================================================
+
+// Synchronization state
+reg [2:0] nmi_sync;
+always @ (posedge mclk or posedge puc)
+ if (puc) nmi_sync <= 3'h0;
+ else nmi_sync <= {nmi_sync[1:0], nmi};
+
+// Edge detection
+wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
+wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
+
+// NMI event
+wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
+
+
+//=============================================================================
+// 5) WATCHDOG TIMER
+//=============================================================================
+
+// Watchdog clock source selection
+//---------------------------------
+wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
+
+
+// Watchdog 16 bit counter
+//--------------------------
+reg [15:0] wdtcnt;
+
+wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
+
+always @ (posedge mclk or posedge puc)
+ if (puc) wdtcnt <= 16'h0000;
+ else if (wdtcnt_clr) wdtcnt <= 16'h0000;
+ else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
+
+
+// Interval selection mux
+//--------------------------
+reg wdtqn;
+
+always @(wdtctl or wdtcnt)
+ case(wdtctl[1:0])
+ 2'b00 : wdtqn = wdtcnt[15];
+ 2'b01 : wdtqn = wdtcnt[13];
+ 2'b10 : wdtqn = wdtcnt[9];
+ default: wdtqn = wdtcnt[6];
+ endcase
+
+
+// Watchdog event detection
+//-----------------------------
+reg wdtqn_dly;
+
+always @ (posedge mclk or posedge puc)
+ if (puc) wdtqn_dly <= 1'b0;
+ else wdtqn_dly <= wdtqn;
+
+wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error;
+
+
+endmodule // omsp_watchdog
+
+`include "openMSP430_undefines.v"
actel/src/omsp_watchdog.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_execution_unit.v
===================================================================
--- actel/src/omsp_execution_unit.v (nonexistent)
+++ actel/src/omsp_execution_unit.v (revision 64)
@@ -0,0 +1,367 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_execution_unit.v
+//
+// *Module Description:
+// openMSP430 Execution unit
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_execution_unit (
+
+// OUTPUTs
+ cpuoff, // Turns off the CPU
+ dbg_reg_din, // Debug unit CPU register data input
+ gie, // General interrupt enable
+ mab, // Memory address bus
+ mb_en, // Memory bus enable
+ mb_wr, // Memory bus write transfer
+ mdb_out, // Memory data bus output
+ oscoff, // Turns off LFXT1 clock input
+ pc_sw, // Program counter software value
+ pc_sw_wr, // Program counter software write
+ scg1, // System clock generator 1. Turns off the SMCLK
+
+// INPUTs
+ dbg_halt_st, // Halt/Run status from CPU
+ dbg_mem_dout, // Debug unit data output
+ dbg_reg_wr, // Debug unit CPU register write
+ e_state, // Execution state
+ exec_done, // Execution completed
+ inst_ad, // Decoded Inst: destination addressing mode
+ inst_as, // Decoded Inst: source addressing mode
+ inst_alu, // ALU control signals
+ inst_bw, // Decoded Inst: byte width
+ inst_dest, // Decoded Inst: destination (one hot)
+ inst_dext, // Decoded Inst: destination extended instruction word
+ inst_irq_rst, // Decoded Inst: reset interrupt
+ inst_jmp, // Decoded Inst: Conditional jump
+ inst_sext, // Decoded Inst: source extended instruction word
+ inst_so, // Decoded Inst: Single-operand arithmetic
+ inst_src, // Decoded Inst: source (one hot)
+ inst_type, // Decoded Instruction type
+ mclk, // Main system clock
+ mdb_in, // Memory data bus input
+ pc, // Program counter
+ pc_nxt, // Next PC value (for CALL & IRQ)
+ puc // Main system reset
+);
+
+// OUTPUTs
+//=========
+output cpuoff; // Turns off the CPU
+output [15:0] dbg_reg_din; // Debug unit CPU register data input
+output gie; // General interrupt enable
+output [15:0] mab; // Memory address bus
+output mb_en; // Memory bus enable
+output [1:0] mb_wr; // Memory bus write transfer
+output [15:0] mdb_out; // Memory data bus output
+output oscoff; // Turns off LFXT1 clock input
+output [15:0] pc_sw; // Program counter software value
+output pc_sw_wr; // Program counter software write
+output scg1; // System clock generator 1. Turns off the SMCLK
+
+// INPUTs
+//=========
+input dbg_halt_st; // Halt/Run status from CPU
+input [15:0] dbg_mem_dout; // Debug unit data output
+input dbg_reg_wr; // Debug unit CPU register write
+input [3:0] e_state; // Execution state
+input exec_done; // Execution completed
+input [7:0] inst_ad; // Decoded Inst: destination addressing mode
+input [7:0] inst_as; // Decoded Inst: source addressing mode
+input [11:0] inst_alu; // ALU control signals
+input inst_bw; // Decoded Inst: byte width
+input [15:0] inst_dest; // Decoded Inst: destination (one hot)
+input [15:0] inst_dext; // Decoded Inst: destination extended instruction word
+input inst_irq_rst; // Decoded Inst: reset interrupt
+input [7:0] inst_jmp; // Decoded Inst: Conditional jump
+input [15:0] inst_sext; // Decoded Inst: source extended instruction word
+input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
+input [15:0] inst_src; // Decoded Inst: source (one hot)
+input [2:0] inst_type; // Decoded Instruction type
+input mclk; // Main system clock
+input [15:0] mdb_in; // Memory data bus input
+input [15:0] pc; // Program counter
+input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
+input puc; // Main system reset
+
+
+//=============================================================================
+// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
+//=============================================================================
+
+wire [15:0] alu_out;
+wire [15:0] alu_out_add;
+wire [3:0] alu_stat;
+wire [3:0] alu_stat_wr;
+wire [15:0] op_dst;
+wire [15:0] op_src;
+wire [15:0] reg_dest;
+wire [15:0] reg_src;
+wire [15:0] mdb_in_bw;
+wire [15:0] mdb_in_val;
+wire [3:0] status;
+
+
+//=============================================================================
+// 2) REGISTER FILE
+//=============================================================================
+
+wire reg_dest_wr = ((e_state==`E_EXEC) & (
+ (inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) |
+ (inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) |
+ inst_type[`INST_JMP])) | dbg_reg_wr;
+
+wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
+ ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]));
+
+wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
+
+wire reg_sr_clr = (e_state==`E_IRQ_2);
+
+wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) |
+ ((e_state==`E_DST_WR) & inst_so[`RETI]);
+
+wire reg_incr = (exec_done & inst_as[`INDIR_I]) |
+ ((e_state==`E_SRC_RD) & inst_so[`RETI]) |
+ ((e_state==`E_EXEC) & inst_so[`RETI]);
+
+assign dbg_reg_din = reg_dest;
+
+
+omsp_register_file register_file_0 (
+
+// OUTPUTs
+ .cpuoff (cpuoff), // Turns off the CPU
+ .gie (gie), // General interrupt enable
+ .oscoff (oscoff), // Turns off LFXT1 clock input
+ .pc_sw (pc_sw), // Program counter software value
+ .pc_sw_wr (pc_sw_wr), // Program counter software write
+ .reg_dest (reg_dest), // Selected register destination content
+ .reg_src (reg_src), // Selected register source content
+ .scg1 (scg1), // System clock generator 1. Turns off the SMCLK
+ .status (status), // R2 Status {V,N,Z,C}
+
+// INPUTs
+ .alu_stat (alu_stat), // ALU Status {V,N,Z,C}
+ .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
+ .inst_bw (inst_bw), // Decoded Inst: byte width
+ .inst_dest (inst_dest), // Register destination selection
+ .inst_src (inst_src), // Register source selection
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .puc (puc), // Main system reset
+ .reg_dest_val (alu_out), // Selected register destination value
+ .reg_dest_wr (reg_dest_wr), // Write selected register destination
+ .reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
+ .reg_sp_val (alu_out_add), // Stack Pointer next value
+ .reg_sp_wr (reg_sp_wr), // Stack Pointer write
+ .reg_sr_clr (reg_sr_clr), // Status register clear for interrupts
+ .reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction
+ .reg_incr (reg_incr) // Increment source register
+);
+
+
+//=============================================================================
+// 3) SOURCE OPERAND MUXING
+//=============================================================================
+// inst_as[`DIR] : Register direct. -> Source is in register
+// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset
+// inst_as[`INDIR] : Register indirect.
+// inst_as[`INDIR_I]: Register indirect autoincrement.
+// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x).
+// inst_as[`IMM] : Immediate (operand is next word in the instruction stream).
+// inst_as[`ABS] : Absolute (operand is in memory at address x).
+// inst_as[`CONST] : Constant.
+
+wire src_reg_src_sel = (e_state==`E_IRQ_0) |
+ (e_state==`E_IRQ_2) |
+ ((e_state==`E_SRC_RD) & ~inst_as[`ABS]) |
+ ((e_state==`E_SRC_WR) & ~inst_as[`ABS]) |
+ ((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]);
+
+wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
+ (e_state==`E_IRQ_3) |
+ ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]));
+
+wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
+ ((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
+ inst_as[`IDX] | inst_as[`SYMB] |
+ inst_as[`ABS]));
+
+wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) |
+ ((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] |
+ inst_so[`RETI]));
+
+wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] |
+ inst_as[`CONST] | inst_so[`RETI]));
+
+
+assign op_src = src_reg_src_sel ? reg_src :
+ src_reg_dest_sel ? reg_dest :
+ src_mdb_in_val_sel ? mdb_in_val :
+ src_inst_dext_sel ? inst_dext :
+ src_inst_sext_sel ? inst_sext : 16'h0000;
+
+
+//=============================================================================
+// 4) DESTINATION OPERAND MUXING
+//=============================================================================
+// inst_ad[`DIR] : Register direct.
+// inst_ad[`IDX] : Register indexed.
+// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x).
+// inst_ad[`ABS] : Absolute (operand is in memory at address x).
+
+
+wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] |
+ inst_as[`ABS])) |
+ ((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] |
+ inst_as[`ABS]));
+
+wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) |
+ ((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] |
+ inst_type[`INST_SO]) & ~inst_so[`RETI]);
+
+wire dst_fffe_sel = (e_state==`E_IRQ_0) |
+ (e_state==`E_IRQ_1) |
+ (e_state==`E_IRQ_3) |
+ ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]);
+
+wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
+ ((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
+ ((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] |
+ inst_type[`INST_SO]) & ~inst_so[`RETI]);
+
+
+assign op_dst = dbg_halt_st ? dbg_mem_dout :
+ dst_inst_sext_sel ? inst_sext :
+ dst_mdb_in_bw_sel ? mdb_in_bw :
+ dst_reg_dest_sel ? reg_dest :
+ dst_fffe_sel ? 16'hfffe : 16'h0000;
+
+
+//=============================================================================
+// 5) ALU
+//=============================================================================
+
+wire exec_cycle = (e_state==`E_EXEC);
+
+omsp_alu alu_0 (
+
+// OUTPUTs
+ .alu_out (alu_out), // ALU output value
+ .alu_out_add (alu_out_add), // ALU adder output value
+ .alu_stat (alu_stat), // ALU Status {V,N,Z,C}
+ .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
+
+// INPUTs
+ .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
+ .exec_cycle (exec_cycle), // Instruction execution cycle
+ .inst_alu (inst_alu), // ALU control signals
+ .inst_bw (inst_bw), // Decoded Inst: byte width
+ .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
+ .inst_so (inst_so), // Single-operand arithmetic
+ .op_dst (op_dst), // Destination operand
+ .op_src (op_src), // Source operand
+ .status (status) // R2 Status {V,N,Z,C}
+);
+
+
+//=============================================================================
+// 6) MEMORY INTERFACE
+//=============================================================================
+
+// Detect memory read/write access
+assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) |
+ ((e_state==`E_IRQ_3) & ~inst_irq_rst) |
+ ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) |
+ (e_state==`E_SRC_WR) |
+ ((e_state==`E_EXEC) & inst_so[`RETI]) |
+ (e_state==`E_DST_RD) |
+ (e_state==`E_DST_WR);
+
+wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :
+ ~inst_bw ? 2'b11 :
+ alu_out_add[0] ? 2'b10 : 2'b01;
+assign mb_wr = ({2{(e_state==`E_IRQ_1)}} |
+ {2{(e_state==`E_IRQ_3)}} |
+ {2{(e_state==`E_DST_WR)}} |
+ {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk;
+
+// Memory address bus
+assign mab = alu_out_add[15:0];
+
+// Memory data bus output
+reg [15:0] mdb_out_nxt;
+always @(posedge mclk or posedge puc)
+ if (puc) mdb_out_nxt <= 16'h0000;
+ else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
+ else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
+ (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
+
+assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
+
+// Format memory data bus input depending on BW
+reg mab_lsb;
+always @(posedge mclk or posedge puc)
+ if (puc) mab_lsb <= 1'b0;
+ else if (mb_en) mab_lsb <= alu_out_add[0];
+
+assign mdb_in_bw = ~inst_bw ? mdb_in :
+ mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
+
+// Memory data bus input buffer (buffer after a source read)
+reg mdb_in_buf_en;
+always @(posedge mclk or posedge puc)
+ if (puc) mdb_in_buf_en <= 1'b0;
+ else mdb_in_buf_en <= (e_state==`E_SRC_RD);
+
+reg mdb_in_buf_valid;
+always @(posedge mclk or posedge puc)
+ if (puc) mdb_in_buf_valid <= 1'b0;
+ else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
+ else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
+
+reg [15:0] mdb_in_buf;
+always @(posedge mclk or posedge puc)
+ if (puc) mdb_in_buf <= 16'h0000;
+ else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
+
+assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
+
+
+endmodule // omsp_execution_unit
+
+`include "openMSP430_undefines.v"
actel/src/omsp_execution_unit.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/omsp_mem_backbone.v
===================================================================
--- actel/src/omsp_mem_backbone.v (nonexistent)
+++ actel/src/omsp_mem_backbone.v (revision 64)
@@ -0,0 +1,244 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: omsp_mem_backbone.v
+//
+// *Module Description:
+// Memory interface backbone (decoder + arbiter)
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 34 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module omsp_mem_backbone (
+
+// OUTPUTs
+ dbg_mem_din, // Debug unit Memory data input
+ dmem_addr, // Data Memory address
+ dmem_cen, // Data Memory chip enable (low active)
+ dmem_din, // Data Memory data input
+ dmem_wen, // Data Memory write enable (low active)
+ eu_mdb_in, // Execution Unit Memory data bus input
+ fe_mdb_in, // Frontend Memory data bus input
+ fe_pmem_wait, // Frontend wait for Instruction fetch
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_wen, // Peripheral write enable (high active)
+ per_en, // Peripheral enable (high active)
+ pmem_addr, // Program Memory address
+ pmem_cen, // Program Memory chip enable (low active)
+ pmem_din, // Program Memory data input (optional)
+ pmem_wen, // Program Memory write enable (low active) (optional)
+
+// INPUTs
+ dbg_halt_st, // Halt/Run status from CPU
+ dbg_mem_addr, // Debug address for rd/wr access
+ dbg_mem_dout, // Debug unit data output
+ dbg_mem_en, // Debug unit memory enable
+ dbg_mem_wr, // Debug unit memory write
+ dmem_dout, // Data Memory data output
+ eu_mab, // Execution Unit Memory address bus
+ eu_mb_en, // Execution Unit Memory bus enable
+ eu_mb_wr, // Execution Unit Memory bus write transfer
+ eu_mdb_out, // Execution Unit Memory data bus output
+ fe_mab, // Frontend Memory address bus
+ fe_mb_en, // Frontend Memory bus enable
+ mclk, // Main system clock
+ per_dout, // Peripheral data output
+ pmem_dout, // Program Memory data output
+ puc // Main system reset
+);
+
+// OUTPUTs
+//=========
+output [15:0] dbg_mem_din; // Debug unit Memory data input
+output [`DMEM_MSB:0] dmem_addr; // Data Memory address
+output dmem_cen; // Data Memory chip enable (low active)
+output [15:0] dmem_din; // Data Memory data input
+output [1:0] dmem_wen; // Data Memory write enable (low active)
+output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
+output [15:0] fe_mdb_in; // Frontend Memory data bus input
+output fe_pmem_wait; // Frontend wait for Instruction fetch
+output [7:0] per_addr; // Peripheral address
+output [15:0] per_din; // Peripheral data input
+output [1:0] per_wen; // Peripheral write enable (high active)
+output per_en; // Peripheral enable (high active)
+output [`PMEM_MSB:0] pmem_addr; // Program Memory address
+output pmem_cen; // Program Memory chip enable (low active)
+output [15:0] pmem_din; // Program Memory data input (optional)
+output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
+
+// INPUTs
+//=========
+input dbg_halt_st; // Halt/Run status from CPU
+input [15:0] dbg_mem_addr; // Debug address for rd/wr access
+input [15:0] dbg_mem_dout; // Debug unit data output
+input dbg_mem_en; // Debug unit memory enable
+input [1:0] dbg_mem_wr; // Debug unit memory write
+input [15:0] dmem_dout; // Data Memory data output
+input [14:0] eu_mab; // Execution Unit Memory address bus
+input eu_mb_en; // Execution Unit Memory bus enable
+input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
+input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
+input [14:0] fe_mab; // Frontend Memory address bus
+input fe_mb_en; // Frontend Memory bus enable
+input mclk; // Main system clock
+input [15:0] per_dout; // Peripheral data output
+input [15:0] pmem_dout; // Program Memory data output
+input puc; // Main system reset
+
+
+//=============================================================================
+// 1) DECODER
+//=============================================================================
+
+// RAM Interface
+//------------------
+
+// Execution unit access
+wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
+ (eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
+wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
+
+// Debug interface access
+wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
+ (dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
+wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
+
+
+// RAM Interface
+wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
+wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
+wire [1:0] dmem_wen = ~(dbg_mem_wr | eu_mb_wr);
+wire [15:0] dmem_din = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
+
+
+// ROM Interface
+//------------------
+parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1);
+
+// Execution unit access (only read access are accepted)
+wire eu_pmem_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
+wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
+
+// Front-end access
+wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
+wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
+
+// Debug interface access
+wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
+wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
+
+
+// ROM Interface (Execution unit has priority)
+wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
+ ~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
+wire pmem_cen = fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
+wire [1:0] pmem_wen = ~dbg_mem_wr;
+wire [15:0] pmem_din = dbg_mem_dout;
+
+wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
+
+
+// Peripherals
+//--------------------
+wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
+wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
+
+wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
+wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
+wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
+wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
+
+reg [15:0] per_dout_val;
+always @ (posedge mclk or posedge puc)
+ if (puc) per_dout_val <= 16'h0000;
+ else per_dout_val <= per_dout;
+
+
+// Frontend data Mux
+//---------------------------------
+// Whenever the frontend doesn't access the ROM, backup the data
+
+// Detect whenever the data should be backuped and restored
+reg fe_pmem_cen_dly;
+always @(posedge mclk or posedge puc)
+ if (puc) fe_pmem_cen_dly <= 1'b0;
+ else fe_pmem_cen_dly <= fe_pmem_cen;
+
+wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
+wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
+
+reg [15:0] pmem_dout_bckup;
+always @(posedge mclk or posedge puc)
+ if (puc) pmem_dout_bckup <= 16'h0000;
+ else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
+
+// Mux between the ROM data and the backup
+reg pmem_dout_bckup_sel;
+always @(posedge mclk or posedge puc)
+ if (puc) pmem_dout_bckup_sel <= 1'b0;
+ else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
+ else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
+
+assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
+
+
+// Execution-Unit data Mux
+//---------------------------------
+
+// Select between peripherals, RAM and ROM
+reg [1:0] eu_mdb_in_sel;
+always @(posedge mclk or posedge puc)
+ if (puc) eu_mdb_in_sel <= 2'b00;
+ else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
+
+// Mux
+assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
+ eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
+
+// Debug interface data Mux
+//---------------------------------
+
+// Select between peripherals, RAM and ROM
+reg [1:0] dbg_mem_din_sel;
+always @(posedge mclk or posedge puc)
+ if (puc) dbg_mem_din_sel <= 2'b00;
+ else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
+
+// Mux
+assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
+ dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
+
+
+endmodule // omsp_mem_backbone
+
+`include "openMSP430_undefines.v"
actel/src/omsp_mem_backbone.v
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+native
\ No newline at end of property
Index: actel/src/openMSP430_defines.v
===================================================================
--- actel/src/openMSP430_defines.v (nonexistent)
+++ actel/src/openMSP430_defines.v (revision 64)
@@ -0,0 +1,300 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: openMSP430_defines.v
+//
+// *Module Description:
+// openMSP430 Configuration file
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 57 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mo, 01 Feb 2010) $
+//----------------------------------------------------------------------------
+`include "openMSP430_undefines.v"
+
+//----------------------------------------------------------------------------
+// SYSTEM CONFIGURATION
+//----------------------------------------------------------------------------
+
+// Program Memory Size:
+// 9 -> 1 kB
+// 10 -> 2 kB
+// 11 -> 4 kB
+// 12 -> 8 kB
+// 13 -> 16 kB
+// 14 -> 32 kB
+`define PMEM_AWIDTH 12
+
+// Data Memory Size:
+// 6 -> 128 B
+// 7 -> 256 B
+// 8 -> 512 B
+// 9 -> 1 kB
+// 10 -> 2 kB
+// 11 -> 4 kB
+// 12 -> 8 kB
+// 13 -> 16 kB
+// 14 -> 32 kB
+`define DMEM_AWIDTH 10
+
+//----------------------------------------------------------------------------
+// REMOTE DEBUGGING INTERFACE CONFIGURATION
+//----------------------------------------------------------------------------
+
+// Include Debug interface
+`define DBG_EN
+
+// Debug interface selection
+// `define DBG_UART -> Enable UART (8N1) debug interface
+// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
+//
+`define DBG_UART
+//`define DBG_JTAG
+
+// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
+// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
+// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
+// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
+// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
+//
+`define DBG_HWBRK_0
+`define DBG_HWBRK_1
+`define DBG_HWBRK_2
+`define DBG_HWBRK_3
+
+
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+
+// Program and Data Memory sizes
+`define PMEM_SIZE (2 << `PMEM_AWIDTH)
+`define DMEM_SIZE (2 << `DMEM_AWIDTH)
+
+// Data Memory Base Adresses
+`define DMEM_BASE 16'h0200
+
+// Program & Data Memory most significant address bit (for 16 bit words)
+`define PMEM_MSB `PMEM_AWIDTH-1
+`define DMEM_MSB `DMEM_AWIDTH-1
+
+
+// Instructions type
+`define INST_SO 0
+`define INST_JMP 1
+`define INST_TO 2
+
+// Single-operand arithmetic
+`define RRC 0
+`define SWPB 1
+`define RRA 2
+`define SXT 3
+`define PUSH 4
+`define CALL 5
+`define RETI 6
+`define IRQ 7
+
+// Conditional jump
+`define JNE 0
+`define JEQ 1
+`define JNC 2
+`define JC 3
+`define JN 4
+`define JGE 5
+`define JL 6
+`define JMP 7
+
+// Two-operand arithmetic
+`define MOV 0
+`define ADD 1
+`define ADDC 2
+`define SUBC 3
+`define SUB 4
+`define CMP 5
+`define DADD 6
+`define BIT 7
+`define BIC 8
+`define BIS 9
+`define XOR 10
+`define AND 11
+
+// Addressing modes
+`define DIR 0
+`define IDX 1
+`define INDIR 2
+`define INDIR_I 3
+`define SYMB 4
+`define IMM 5
+`define ABS 6
+`define CONST 7
+
+// Execution state machine
+`define E_IRQ_0 4'h0
+`define E_IRQ_1 4'h1
+`define E_IRQ_2 4'h2
+`define E_IRQ_3 4'h3
+`define E_IRQ_4 4'h4
+`define E_SRC_AD 4'h5
+`define E_SRC_RD 4'h6
+`define E_SRC_WR 4'h7
+`define E_DST_AD 4'h8
+`define E_DST_RD 4'h9
+`define E_DST_WR 4'hA
+`define E_EXEC 4'hB
+`define E_JUMP 4'hC
+`define E_IDLE 4'hD
+
+// ALU control signals
+`define ALU_SRC_INV 0
+`define ALU_INC 1
+`define ALU_INC_C 2
+`define ALU_ADD 3
+`define ALU_AND 4
+`define ALU_OR 5
+`define ALU_XOR 6
+`define ALU_DADD 7
+`define ALU_STAT_7 8
+`define ALU_STAT_F 9
+`define ALU_SHIFT 10
+`define EXEC_NO_WR 11
+
+// Debug interface
+`define DBG_UART_WR 18
+`define DBG_UART_BW 17
+`define DBG_UART_ADDR 16:11
+
+// Debug interface CPU_CTL register
+`define HALT 0
+`define RUN 1
+`define ISTEP 2
+`define SW_BRK_EN 3
+`define FRZ_BRK_EN 4
+`define RST_BRK_EN 5
+`define CPU_RST 6
+
+// Debug interface CPU_STAT register
+`define HALT_RUN 0
+`define PUC_PND 1
+`define SWBRK_PND 3
+`define HWBRK0_PND 4
+`define HWBRK1_PND 5
+
+// Debug interface BRKx_CTL register
+`define BRK_MODE_RD 0
+`define BRK_MODE_WR 1
+`define BRK_MODE 1:0
+`define BRK_EN 2
+`define BRK_I_EN 3
+`define BRK_RANGE 4
+
+// Basic clock module: BCSCTL1 Control Register
+`define DIVAx 5:4
+
+// Basic clock module: BCSCTL2 Control Register
+`define SELS 3
+`define DIVSx 2:1
+
+// Timer A: TACTL Control Register
+`define TASSELx 9:8
+`define TAIDx 7:6
+`define TAMCx 5:4
+`define TACLR 2
+`define TAIE 1
+`define TAIFG 0
+
+// Timer A: TACCTLx Capture/Compare Control Register
+`define TACMx 15:14
+`define TACCISx 13:12
+`define TASCS 11
+`define TASCCI 10
+`define TACAP 8
+`define TAOUTMODx 7:5
+`define TACCIE 4
+`define TACCI 3
+`define TAOUT 2
+`define TACOV 1
+`define TACCIFG 0
+
+//
+// DEBUG INTERFACE EXTRA CONFIGURATION
+//======================================
+
+// Debug interface: Software breakpoint opcode
+`define DBG_SWBRK_OP 16'h4343
+
+// Debug interface ID
+`define DBG_ID 24'h4D5350
+
+// Debug UART interface auto data synchronization
+// If the following define is commented out, then
+// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
+// defined.
+`define DBG_UART_AUTO_SYNC
+
+// Debug UART interface data rate
+// In order to properly setup the UART debug interface, you
+// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
+// the chosen BAUD rate from the UART interface.
+//
+//`define DBG_UART_BAUD 9600
+//`define DBG_UART_BAUD 19200
+//`define DBG_UART_BAUD 38400
+//`define DBG_UART_BAUD 57600
+//`define DBG_UART_BAUD 115200
+//`define DBG_UART_BAUD 230400
+//`define DBG_UART_BAUD 460800
+//`define DBG_UART_BAUD 576000
+//`define DBG_UART_BAUD 921600
+`define DBG_UART_BAUD 2000000
+`define DBG_DCO_FREQ 20000000
+`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
+
+// Enable/Disable the hardware breakpoint RANGE mode
+`define HWBRK_RANGE 1'b0
+
+// Check configuration
+`ifdef DBG_EN
+ `ifdef DBG_UART
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
+ `endif
+ `else
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
+ `else
+CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
+ `endif
+ `endif
+`endif
+
actel/src/openMSP430_defines.v
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+native
\ No newline at end of property
Index: actel/src/openMSP430_fpga.v
===================================================================
--- actel/src/openMSP430_fpga.v (nonexistent)
+++ actel/src/openMSP430_fpga.v (revision 64)
@@ -0,0 +1,161 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: openMSP430_fpga.v
+//
+// *Module Description:
+// openMSP430 FPGA Top-level for the Xilinx synthesis.
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 37 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module openMSP430_fpga (
+
+// OUTPUTs
+ aclk_en, // ACLK enable
+ dbg_freeze, // Freeze peripherals
+ dbg_uart_txd, // Debug interface: UART TXD
+ irq_acc, // Interrupt request accepted (one-hot signal)
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_wen, // Peripheral write enable (high active)
+ per_en, // Peripheral enable (high active)
+ smclk_en, // SMCLK enable
+
+// INPUTs
+ dbg_uart_rxd, // Debug interface: UART RXD
+ dco_clk, // Fast oscillator (fast clock)
+ irq, // Maskable interrupts
+ lfxt_clk, // Low frequency oscillator (typ 32kHz)
+ nmi, // Non-maskable interrupt (asynchronous)
+ per_dout, // Peripheral data output
+ reset_n // Reset Pin (low active)
+);
+
+// OUTPUTs
+//=========
+output aclk_en; // ACLK enable
+output dbg_freeze; // Freeze peripherals
+output dbg_uart_txd; // Debug interface: UART TXD
+output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
+output [7:0] per_addr; // Peripheral address
+output [15:0] per_din; // Peripheral data input
+output [1:0] per_wen; // Peripheral write enable (high active)
+output per_en; // Peripheral enable (high active)
+output smclk_en; // SMCLK enable
+
+
+// INPUTs
+//=========
+input dbg_uart_rxd; // Debug interface: UART RXD
+input dco_clk; // Fast oscillator (fast clock)
+input [13:0] irq; // Maskable interrupts
+input lfxt_clk; // Low frequency oscillator (typ 32kHz)
+input nmi; // Non-maskable interrupt (asynchronous)
+input [15:0] per_dout; // Peripheral data output
+input reset_n; // Reset Pin (active low)
+
+
+//=============================================================================
+// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
+//=============================================================================
+
+wire [`DMEM_MSB:0] dmem_addr;
+wire dmem_cen;
+wire [15:0] dmem_din;
+wire [1:0] dmem_wen;
+wire [15:0] dmem_dout;
+
+wire [`PMEM_MSB:0] pmem_addr;
+wire pmem_cen;
+wire [15:0] pmem_din;
+wire [1:0] pmem_wen;
+wire [15:0] pmem_dout;
+
+wire mclk;
+wire puc;
+
+
+//=============================================================================
+// 2) PROGRAM AND DATA MEMORIES
+//=============================================================================
+
+dmem dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(puc));
+dmem dmem_lo (.WD(dmem_din[7:0]), .RD(dmem_dout[7:0]), .WEN(dmem_wen[0] | dmem_cen), .REN(dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(puc));
+
+pmem pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(puc));
+pmem pmem_lo (.WD(pmem_din[7:0]), .RD(pmem_dout[7:0]), .WEN(pmem_wen[0] | pmem_cen), .REN(pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(puc));
+
+
+//=============================================================================
+// 3) OPENMSP430
+//=============================================================================
+
+openMSP430 openMSP430_0 (
+
+// OUTPUTs
+ .aclk_en (aclk_en), // ACLK enable
+ .dbg_freeze (dbg_freeze), // Freeze peripherals
+ .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
+ .dmem_addr (dmem_addr), // Data Memory address
+ .dmem_cen (dmem_cen), // Data Memory chip enable (low active)
+ .dmem_din (dmem_din), // Data Memory data input
+ .dmem_wen (dmem_wen), // Data Memory write enable (low active)
+ .irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
+ .mclk (mclk), // Main system clock
+ .per_addr (per_addr), // Peripheral address
+ .per_din (per_din), // Peripheral data input
+ .per_wen (per_wen), // Peripheral write enable (high active)
+ .per_en (per_en), // Peripheral enable (high active)
+ .pmem_addr (pmem_addr), // Program Memory address
+ .pmem_cen (pmem_cen), // Program Memory chip enable (low active)
+ .pmem_din (pmem_din), // Program Memory data input (optional)
+ .pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
+ .puc (puc), // Main system reset
+ .smclk_en (smclk_en), // SMCLK enable
+
+// INPUTs
+ .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
+ .dco_clk (dco_clk), // Fast oscillator (fast clock)
+ .dmem_dout (dmem_dout), // Data Memory data output
+ .irq (irq), // Maskable interrupts
+ .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
+ .nmi (nmi), // Non-maskable interrupt (asynchronous)
+ .per_dout (per_dout), // Peripheral data output
+ .pmem_dout (pmem_dout), // Program Memory data output
+ .reset_n (reset_n) // Reset Pin (low active)
+);
+
+
+
+endmodule // openMSP430_fpga
+
actel/src/openMSP430_fpga.v
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Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/timescale.v
===================================================================
--- actel/src/timescale.v (nonexistent)
+++ actel/src/timescale.v (revision 64)
@@ -0,0 +1 @@
+`timescale 1ns / 100ps
actel/src/timescale.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/openMSP430_undefines.v
===================================================================
--- actel/src/openMSP430_undefines.v (nonexistent)
+++ actel/src/openMSP430_undefines.v (revision 64)
@@ -0,0 +1,498 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: openMSP430_undefines.v
+//
+// *Module Description:
+// openMSP430 Verilog `undef file
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 23 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+// SYSTEM CONFIGURATION
+//----------------------------------------------------------------------------
+
+// Program Memory Size:
+`ifdef PMEM_AWIDTH
+`undef PMEM_AWIDTH
+`endif
+
+// Data Memory Size:
+`ifdef DMEM_AWIDTH
+`undef DMEM_AWIDTH
+`endif
+
+//----------------------------------------------------------------------------
+// REMOTE DEBUGGING INTERFACE CONFIGURATION
+//----------------------------------------------------------------------------
+
+// Include Debug interface
+`ifdef DBG_EN
+`undef DBG_EN
+`endif
+
+// Debug interface selection
+`ifdef DBG_UART
+`undef DBG_UART
+`endif
+`ifdef DBG_JTAG
+`undef DBG_JTAG
+`endif
+
+// Number of hardware breakpoints
+`ifdef DBG_HWBRK_0
+`undef DBG_HWBRK_0
+`endif
+`ifdef DBG_HWBRK_1
+`undef DBG_HWBRK_1
+`endif
+`ifdef DBG_HWBRK_2
+`undef DBG_HWBRK_2
+`endif
+`ifdef DBG_HWBRK_3
+`undef DBG_HWBRK_3
+`endif
+
+
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+
+// Program and Data Memory sizes
+`ifdef PMEM_SIZE
+`undef PMEM_SIZE
+`endif
+`ifdef DMEM_SIZE
+`undef DMEM_SIZE
+`endif
+
+// Data Memory Base Adresses
+`ifdef DMEM_BASE
+`undef DMEM_BASE
+`endif
+
+// Program & Data Memory most significant address bit (for 16 bit words)
+`ifdef PMEM_MSB
+`undef PMEM_MSB
+`endif
+`ifdef DMEM_MSB
+`undef DMEM_MSB
+`endif
+
+
+// Instructions type
+`ifdef INST_SO
+`undef INST_SO
+`endif
+`ifdef INST_JMP
+`undef INST_JMP
+`endif
+`ifdef INST_TO
+`undef INST_TO
+`endif
+
+// Single-operand arithmetic
+`ifdef RRC
+`undef RRC
+`endif
+`ifdef SWPB
+`undef SWPB
+`endif
+`ifdef RRA
+`undef RRA
+`endif
+`ifdef SXT
+`undef SXT
+`endif
+`ifdef PUSH
+`undef PUSH
+`endif
+`ifdef CALL
+`undef CALL
+`endif
+`ifdef RETI
+`undef RETI
+`endif
+`ifdef IRQ
+`undef IRQ
+`endif
+
+// Conditional jump
+`ifdef JNE
+`undef JNE
+`endif
+`ifdef JEQ
+`undef JEQ
+`endif
+`ifdef JNC
+`undef JNC
+`endif
+`ifdef JC
+`undef JC
+`endif
+`ifdef JN
+`undef JN
+`endif
+`ifdef JGE
+`undef JGE
+`endif
+`ifdef JL
+`undef JL
+`endif
+`ifdef JMP
+`undef JMP
+`endif
+
+// Two-operand arithmetic
+`ifdef MOV
+`undef MOV
+`endif
+`ifdef ADD
+`undef ADD
+`endif
+`ifdef ADDC
+`undef ADDC
+`endif
+`ifdef SUBC
+`undef SUBC
+`endif
+`ifdef SUB
+`undef SUB
+`endif
+`ifdef CMP
+`undef CMP
+`endif
+`ifdef DADD
+`undef DADD
+`endif
+`ifdef BIT
+`undef BIT
+`endif
+`ifdef BIC
+`undef BIC
+`endif
+`ifdef BIS
+`undef BIS
+`endif
+`ifdef XOR
+`undef XOR
+`endif
+`ifdef AND
+`undef AND
+`endif
+
+// Addressing modes
+`ifdef DIR
+`undef DIR
+`endif
+`ifdef IDX
+`undef IDX
+`endif
+`ifdef INDIR
+`undef INDIR
+`endif
+`ifdef INDIR_I
+`undef INDIR_I
+`endif
+`ifdef SYMB
+`undef SYMB
+`endif
+`ifdef IMM
+`undef IMM
+`endif
+`ifdef ABS
+`undef ABS
+`endif
+`ifdef CONST
+`undef CONST
+`endif
+
+// Execution state machine
+`ifdef E_IRQ_0
+`undef E_IRQ_0
+`endif
+`ifdef E_IRQ_1
+`undef E_IRQ_1
+`endif
+`ifdef E_IRQ_2
+`undef E_IRQ_2
+`endif
+`ifdef E_IRQ_3
+`undef E_IRQ_3
+`endif
+`ifdef E_IRQ_4
+`undef E_IRQ_4
+`endif
+`ifdef E_SRC_AD
+`undef E_SRC_AD
+`endif
+`ifdef E_SRC_RD
+`undef E_SRC_RD
+`endif
+`ifdef E_SRC_WR
+`undef E_SRC_WR
+`endif
+`ifdef E_DST_AD
+`undef E_DST_AD
+`endif
+`ifdef E_DST_RD
+`undef E_DST_RD
+`endif
+`ifdef E_DST_WR
+`undef E_DST_WR
+`endif
+`ifdef E_EXEC
+`undef E_EXEC
+`endif
+`ifdef E_JUMP
+`undef E_JUMP
+`endif
+`ifdef E_IDLE
+`undef E_IDLE
+`endif
+
+// ALU control signals
+`ifdef ALU_SRC_INV
+`undef ALU_SRC_INV
+`endif
+`ifdef ALU_INC
+`undef ALU_INC
+`endif
+`ifdef ALU_INC_C
+`undef ALU_INC_C
+`endif
+`ifdef ALU_ADD
+`undef ALU_ADD
+`endif
+`ifdef ALU_AND
+`undef ALU_AND
+`endif
+`ifdef ALU_OR
+`undef ALU_OR
+`endif
+`ifdef ALU_XOR
+`undef ALU_XOR
+`endif
+`ifdef ALU_DADD
+`undef ALU_DADD
+`endif
+`ifdef ALU_STAT_7
+`undef ALU_STAT_7
+`endif
+`ifdef ALU_STAT_F
+`undef ALU_STAT_F
+`endif
+`ifdef ALU_SHIFT
+`undef ALU_SHIFT
+`endif
+`ifdef EXEC_NO_WR
+`undef EXEC_NO_WR
+`endif
+
+// Debug interface
+`ifdef DBG_UART_WR
+`undef DBG_UART_WR
+`endif
+`ifdef DBG_UART_BW
+`undef DBG_UART_BW
+`endif
+`ifdef DBG_UART_ADDR
+`undef DBG_UART_ADDR
+`endif
+
+// Debug interface CPU_CTL register
+`ifdef HALT
+`undef HALT
+`endif
+`ifdef RUN
+`undef RUN
+`endif
+`ifdef ISTEP
+`undef ISTEP
+`endif
+`ifdef SW_BRK_EN
+`undef SW_BRK_EN
+`endif
+`ifdef FRZ_BRK_EN
+`undef FRZ_BRK_EN
+`endif
+`ifdef RST_BRK_EN
+`undef RST_BRK_EN
+`endif
+`ifdef CPU_RST
+`undef CPU_RST
+`endif
+
+// Debug interface CPU_STAT register
+`ifdef HALT_RUN
+`undef HALT_RUN
+`endif
+`ifdef PUC_PND
+`undef PUC_PND
+`endif
+`ifdef SWBRK_PND
+`undef SWBRK_PND
+`endif
+`ifdef HWBRK0_PND
+`undef HWBRK0_PND
+`endif
+`ifdef HWBRK1_PND
+`undef HWBRK1_PND
+`endif
+
+// Debug interface BRKx_CTL register
+`ifdef BRK_MODE_RD
+`undef BRK_MODE_RD
+`endif
+`ifdef BRK_MODE_WR
+`undef BRK_MODE_WR
+`endif
+`ifdef BRK_MODE
+`undef BRK_MODE
+`endif
+`ifdef BRK_EN
+`undef BRK_EN
+`endif
+`ifdef BRK_I_EN
+`undef BRK_I_EN
+`endif
+`ifdef BRK_RANGE
+`undef BRK_RANGE
+`endif
+
+// Basic clock module: BCSCTL1 Control Register
+`ifdef DIVAx
+`undef DIVAx
+`endif
+
+// Basic clock module: BCSCTL2 Control Register
+`ifdef SELS
+`undef SELS
+`endif
+`ifdef DIVSx
+`undef DIVSx
+`endif
+
+// Timer A: TACTL Control Register
+`ifdef TASSELx
+`undef TASSELx
+`endif
+`ifdef TAIDx
+`undef TAIDx
+`endif
+`ifdef TAMCx
+`undef TAMCx
+`endif
+`ifdef TACLR
+`undef TACLR
+`endif
+`ifdef TAIE
+`undef TAIE
+`endif
+`ifdef TAIFG
+`undef TAIFG
+`endif
+
+// Timer A: TACCTLx Capture/Compare Control Register
+`ifdef TACMx
+`undef TACMx
+`endif
+`ifdef TACCISx
+`undef TACCISx
+`endif
+`ifdef TASCS
+`undef TASCS
+`endif
+`ifdef TASCCI
+`undef TASCCI
+`endif
+`ifdef TACAP
+`undef TACAP
+`endif
+`ifdef TAOUTMODx
+`undef TAOUTMODx
+`endif
+`ifdef TACCIE
+`undef TACCIE
+`endif
+`ifdef TACCI
+`undef TACCI
+`endif
+`ifdef TAOUT
+`undef TAOUT
+`endif
+`ifdef TACOV
+`undef TACOV
+`endif
+`ifdef TACCIFG
+`undef TACCIFG
+`endif
+
+//
+// DEBUG INTERFACE EXTRA CONFIGURATION
+//======================================
+
+// Debug interface: Software breakpoint opcode
+`ifdef DBG_SWBRK_OP
+`undef DBG_SWBRK_OP
+`endif
+
+// Debug interface ID
+`ifdef DBG_ID
+`undef DBG_ID
+`endif
+
+// Debug UART interface auto data synchronization
+`ifdef DBG_UART_AUTO_SYNC
+`undef DBG_UART_AUTO_SYNC
+`endif
+
+// Debug UART interface data rate
+`ifdef DBG_UART_BAUD
+`undef DBG_UART_BAUD
+`endif
+`ifdef DBG_DCO_FREQ
+`undef DBG_DCO_FREQ
+`endif
+`ifdef DBG_UART_CNT
+`undef DBG_UART_CNT
+`endif
+
+// Enable/Disable the hardware breakpoint RANGE mode
+`ifdef HWBRK_RANGE
+`undef HWBRK_RANGE
+`endif
\ No newline at end of file
actel/src/openMSP430_undefines.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/src/openMSP430.v
===================================================================
--- actel/src/openMSP430.v (nonexistent)
+++ actel/src/openMSP430.v (revision 64)
@@ -0,0 +1,440 @@
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: openMSP430.v
+//
+// *Module Description:
+// openMSP430 Top level file
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 53 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-01-27 19:17:14 +0100 (Mi, 27 Jan 2010) $
+//----------------------------------------------------------------------------
+`include "timescale.v"
+`include "openMSP430_defines.v"
+
+module openMSP430 (
+
+// OUTPUTs
+ aclk_en, // ACLK enable
+ dbg_freeze, // Freeze peripherals
+ dbg_uart_txd, // Debug interface: UART TXD
+ dmem_addr, // Data Memory address
+ dmem_cen, // Data Memory chip enable (low active)
+ dmem_din, // Data Memory data input
+ dmem_wen, // Data Memory write enable (low active)
+ irq_acc, // Interrupt request accepted (one-hot signal)
+ mclk, // Main system clock
+ per_addr, // Peripheral address
+ per_din, // Peripheral data input
+ per_wen, // Peripheral write enable (high active)
+ per_en, // Peripheral enable (high active)
+ pmem_addr, // Program Memory address
+ pmem_cen, // Program Memory chip enable (low active)
+ pmem_din, // Program Memory data input (optional)
+ pmem_wen, // Program Memory write enable (low active) (optional)
+ puc, // Main system reset
+ smclk_en, // SMCLK enable
+
+// INPUTs
+ dbg_uart_rxd, // Debug interface: UART RXD
+ dco_clk, // Fast oscillator (fast clock)
+ dmem_dout, // Data Memory data output
+ irq, // Maskable interrupts
+ lfxt_clk, // Low frequency oscillator (typ 32kHz)
+ nmi, // Non-maskable interrupt (asynchronous)
+ per_dout, // Peripheral data output
+ pmem_dout, // Program Memory data output
+ reset_n // Reset Pin (low active)
+);
+
+// OUTPUTs
+//=========
+output aclk_en; // ACLK enable
+output dbg_freeze; // Freeze peripherals
+output dbg_uart_txd; // Debug interface: UART TXD
+output [`DMEM_MSB:0] dmem_addr; // Data Memory address
+output dmem_cen; // Data Memory chip enable (low active)
+output [15:0] dmem_din; // Data Memory data input
+output [1:0] dmem_wen; // Data Memory write enable (low active)
+output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
+output mclk; // Main system clock
+output [7:0] per_addr; // Peripheral address
+output [15:0] per_din; // Peripheral data input
+output [1:0] per_wen; // Peripheral write enable (high active)
+output per_en; // Peripheral enable (high active)
+output [`PMEM_MSB:0] pmem_addr; // Program Memory address
+output pmem_cen; // Program Memory chip enable (low active)
+output [15:0] pmem_din; // Program Memory data input (optional)
+output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
+output puc; // Main system reset
+output smclk_en; // SMCLK enable
+
+
+// INPUTs
+//=========
+input dbg_uart_rxd; // Debug interface: UART RXD
+input dco_clk; // Fast oscillator (fast clock)
+input [15:0] dmem_dout; // Data Memory data output
+input [13:0] irq; // Maskable interrupts
+input lfxt_clk; // Low frequency oscillator (typ 32kHz)
+input nmi; // Non-maskable interrupt (asynchronous)
+input [15:0] per_dout; // Peripheral data output
+input [15:0] pmem_dout; // Program Memory data output
+input reset_n; // Reset Pin (active low)
+
+
+
+//=============================================================================
+// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
+//=============================================================================
+
+wire [7:0] inst_ad;
+wire [7:0] inst_as;
+wire [11:0] inst_alu;
+wire inst_bw;
+wire [15:0] inst_dest;
+wire [15:0] inst_dext;
+wire [15:0] inst_sext;
+wire [7:0] inst_so;
+wire [15:0] inst_src;
+wire [2:0] inst_type;
+wire [3:0] e_state;
+wire exec_done;
+
+wire [15:0] eu_mab;
+wire [15:0] eu_mdb_in;
+wire [15:0] eu_mdb_out;
+wire [1:0] eu_mb_wr;
+wire [15:0] fe_mab;
+wire [15:0] fe_mdb_in;
+
+wire [15:0] pc_sw;
+wire [7:0] inst_jmp;
+wire [15:0] pc;
+wire [15:0] pc_nxt;
+
+wire [15:0] dbg_mem_addr;
+wire [15:0] dbg_mem_dout;
+wire [15:0] dbg_mem_din;
+wire [15:0] dbg_reg_din;
+wire [1:0] dbg_mem_wr;
+
+wire [15:0] per_dout_or;
+wire [15:0] per_dout_sfr;
+wire [15:0] per_dout_wdog;
+wire [15:0] per_dout_clk;
+
+
+//=============================================================================
+// 2) GLOBAL CLOCK & RESET MANAGEMENT
+//=============================================================================
+
+omsp_clock_module clock_module_0 (
+
+// OUTPUTs
+ .aclk_en (aclk_en), // ACLK enablex
+ .mclk (mclk), // Main system clock
+ .per_dout (per_dout_clk), // Peripheral data output
+ .por (por), // Power-on reset
+ .puc (puc), // Main system reset
+ .smclk_en (smclk_en), // SMCLK enable
+
+// INPUTs
+ .dbg_reset (dbg_reset), // Reset CPU from debug interface
+ .dco_clk (dco_clk), // Fast oscillator (fast clock)
+ .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
+ .oscoff (oscoff), // Turns off LFXT1 clock input
+ .per_addr (per_addr), // Peripheral address
+ .per_din (per_din), // Peripheral data input
+ .per_en (per_en), // Peripheral enable (high active)
+ .per_wen (per_wen), // Peripheral write enable (high active)
+ .reset_n (reset_n), // Reset Pin (low active)
+ .scg1 (scg1), // System clock generator 1. Turns off the SMCLK
+ .wdt_reset (wdt_reset) // Watchdog-timer reset
+);
+
+
+//=============================================================================
+// 3) FRONTEND (<=> FETCH & DECODE)
+//=============================================================================
+
+omsp_frontend frontend_0 (
+
+// OUTPUTs
+ .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
+ .decode_noirq (decode_noirq), // Frontend decode instruction
+ .e_state (e_state), // Execution state
+ .exec_done (exec_done), // Execution completed
+ .inst_ad (inst_ad), // Decoded Inst: destination addressing mode
+ .inst_as (inst_as), // Decoded Inst: source addressing mode
+ .inst_alu (inst_alu), // ALU control signals
+ .inst_bw (inst_bw), // Decoded Inst: byte width
+ .inst_dest (inst_dest), // Decoded Inst: destination (one hot)
+ .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
+ .inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
+ .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
+ .inst_sext (inst_sext), // Decoded Inst: source extended instruction word
+ .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
+ .inst_src (inst_src), // Decoded Inst: source (one hot)
+ .inst_type (inst_type), // Decoded Instruction type
+ .irq_acc (irq_acc), // Interrupt request accepted
+ .mab (fe_mab), // Frontend Memory address bus
+ .mb_en (fe_mb_en), // Frontend Memory bus enable
+ .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
+ .pc (pc), // Program counter
+ .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
+
+// INPUTs
+ .cpuoff (cpuoff), // Turns off the CPU
+ .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
+ .dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
+ .fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
+ .gie (gie), // General interrupt enable
+ .irq (irq), // Maskable interrupts
+ .mclk (mclk), // Main system clock
+ .mdb_in (fe_mdb_in), // Frontend Memory data bus input
+ .nmi_evt (nmi_evt), // Non-maskable interrupt event
+ .pc_sw (pc_sw), // Program counter software value
+ .pc_sw_wr (pc_sw_wr), // Program counter software write
+ .puc (puc), // Main system reset
+ .wdt_irq (wdt_irq) // Watchdog-timer interrupt
+);
+
+
+//=============================================================================
+// 4) EXECUTION UNIT
+//=============================================================================
+
+omsp_execution_unit execution_unit_0 (
+
+// OUTPUTs
+ .cpuoff (cpuoff), // Turns off the CPU
+ .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
+ .mab (eu_mab), // Memory address bus
+ .mb_en (eu_mb_en), // Memory bus enable
+ .mb_wr (eu_mb_wr), // Memory bus write transfer
+ .mdb_out (eu_mdb_out), // Memory data bus output
+ .oscoff (oscoff), // Turns off LFXT1 clock input
+ .pc_sw (pc_sw), // Program counter software value
+ .pc_sw_wr (pc_sw_wr), // Program counter software write
+ .scg1 (scg1), // System clock generator 1. Turns off the SMCLK
+
+// INPUTs
+ .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
+ .dbg_mem_dout (dbg_mem_dout), // Debug unit data output
+ .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
+ .e_state (e_state), // Execution state
+ .exec_done (exec_done), // Execution completed
+ .gie (gie), // General interrupt enable
+ .inst_ad (inst_ad), // Decoded Inst: destination addressing mode
+ .inst_as (inst_as), // Decoded Inst: source addressing mode
+ .inst_alu (inst_alu), // ALU control signals
+ .inst_bw (inst_bw), // Decoded Inst: byte width
+ .inst_dest (inst_dest), // Decoded Inst: destination (one hot)
+ .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
+ .inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
+ .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
+ .inst_sext (inst_sext), // Decoded Inst: source extended instruction word
+ .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
+ .inst_src (inst_src), // Decoded Inst: source (one hot)
+ .inst_type (inst_type), // Decoded Instruction type
+ .mclk (mclk), // Main system clock
+ .mdb_in (eu_mdb_in), // Memory data bus input
+ .pc (pc), // Program counter
+ .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
+ .puc (puc) // Main system reset
+);
+
+
+//=============================================================================
+// 5) MEMORY BACKBONE
+//=============================================================================
+
+omsp_mem_backbone mem_backbone_0 (
+
+// OUTPUTs
+ .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
+ .dmem_addr (dmem_addr), // Data Memory address
+ .dmem_cen (dmem_cen), // Data Memory chip enable (low active)
+ .dmem_din (dmem_din), // Data Memory data input
+ .dmem_wen (dmem_wen), // Data Memory write enable (low active)
+ .eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
+ .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
+ .fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
+ .per_addr (per_addr), // Peripheral address
+ .per_din (per_din), // Peripheral data input
+ .per_wen (per_wen), // Peripheral write enable (high active)
+ .per_en (per_en), // Peripheral enable (high active)
+ .pmem_addr (pmem_addr), // Program Memory address
+ .pmem_cen (pmem_cen), // Program Memory chip enable (low active)
+ .pmem_din (pmem_din), // Program Memory data input (optional)
+ .pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
+
+// INPUTs
+ .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
+ .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
+ .dbg_mem_dout (dbg_mem_dout), // Debug unit data output
+ .dbg_mem_en (dbg_mem_en), // Debug unit memory enable
+ .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
+ .dmem_dout (dmem_dout), // Data Memory data output
+ .eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
+ .eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
+ .fe_mab (fe_mab[15:1]), // Frontend Memory address bus
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .mclk (mclk), // Main system clock
+ .per_dout (per_dout_or), // Peripheral data output
+ .pmem_dout (pmem_dout), // Program Memory data output
+ .puc (puc) // Main system reset
+);
+
+
+//=============================================================================
+// 6) SPECIAL FUNCTION REGISTERS
+//=============================================================================
+
+omsp_sfr sfr_0 (
+
+// OUTPUTs
+ .nmie (nmie), // Non-maskable interrupt enable
+ .per_dout (per_dout_sfr), // Peripheral data output
+ .wdt_irq (wdt_irq), // Watchdog-timer interrupt
+ .wdt_reset (wdt_reset), // Watchdog-timer reset
+ .wdtie (wdtie), // Watchdog-timer interrupt enable
+
+// INPUTs
+ .mclk (mclk), // Main system clock
+ .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
+ .per_addr (per_addr), // Peripheral address
+ .per_din (per_din), // Peripheral data input
+ .per_en (per_en), // Peripheral enable (high active)
+ .per_wen (per_wen), // Peripheral write enable (high active)
+ .por (por), // Power-on reset
+ .puc (puc), // Main system reset
+ .wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
+ .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
+ .wdtpw_error (wdtpw_error), // Watchdog-timer password error
+ .wdttmsel (wdttmsel) // Watchdog-timer mode select
+);
+
+
+//=============================================================================
+// 7) WATCHDOG TIMER
+//=============================================================================
+
+omsp_watchdog watchdog_0 (
+
+// OUTPUTs
+ .nmi_evt (nmi_evt), // NMI Event
+ .per_dout (per_dout_wdog), // Peripheral data output
+ .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
+ .wdtpw_error (wdtpw_error), // Watchdog-timer password error
+ .wdttmsel (wdttmsel), // Watchdog-timer mode select
+
+// INPUTs
+ .aclk_en (aclk_en), // ACLK enable
+ .dbg_freeze (dbg_freeze), // Freeze Watchdog counter
+ .mclk (mclk), // Main system clock
+ .nmi (nmi), // Non-maskable interrupt (asynchronous)
+ .nmie (nmie), // Non-maskable interrupt enable
+ .per_addr (per_addr), // Peripheral address
+ .per_din (per_din), // Peripheral data input
+ .per_en (per_en), // Peripheral enable (high active)
+ .per_wen (per_wen), // Peripheral write enable (high active)
+ .puc (puc), // Main system reset
+ .smclk_en (smclk_en), // SMCLK enable
+ .wdtie (wdtie) // Watchdog-timer interrupt enable
+);
+
+
+//=============================================================================
+// 8) PERIPHERALS' OUTPUT BUS
+//=============================================================================
+
+assign per_dout_or = per_dout |
+ per_dout_clk |
+ per_dout_sfr |
+ per_dout_wdog;
+
+
+//=============================================================================
+// 9) DEBUG INTERFACE
+//=============================================================================
+
+`ifdef DBG_EN
+omsp_dbg dbg_0 (
+
+// OUTPUTs
+ .dbg_freeze (dbg_freeze), // Freeze peripherals
+ .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
+ .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
+ .dbg_mem_dout (dbg_mem_dout), // Debug unit data output
+ .dbg_mem_en (dbg_mem_en), // Debug unit memory enable
+ .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
+ .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
+ .dbg_reset (dbg_reset), // Reset CPU from debug interface
+ .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
+
+// INPUTs
+ .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
+ .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
+ .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
+ .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
+ .decode_noirq (decode_noirq), // Frontend decode instruction
+ .eu_mab (eu_mab), // Execution-Unit Memory address bus
+ .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
+ .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
+ .eu_mdb_in (eu_mdb_in), // Memory data bus input
+ .eu_mdb_out (eu_mdb_out), // Memory data bus output
+ .exec_done (exec_done), // Execution completed
+ .fe_mb_en (fe_mb_en), // Frontend Memory bus enable
+ .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
+ .mclk (mclk), // Main system clock
+ .pc (pc), // Program counter
+ .por (por), // Power on reset
+ .puc (puc) // Main system reset
+);
+
+`else
+assign dbg_freeze = 1'b0;
+assign dbg_halt_cmd = 1'b0;
+assign dbg_mem_addr = 16'h0000;
+assign dbg_mem_dout = 16'h0000;
+assign dbg_mem_en = 1'b0;
+assign dbg_mem_wr = 2'b00;
+assign dbg_reg_wr = 1'b0;
+assign dbg_reset = 1'b0;
+assign dbg_uart_txd = 1'b0;
+`endif
+
+
+endmodule // openMSP430
+
+`include "openMSP430_undefines.v"
actel/src/openMSP430.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/run_analysis.log
===================================================================
--- actel/run_analysis.log (nonexistent)
+++ actel/run_analysis.log (revision 64)
@@ -0,0 +1,3029 @@
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 59.496
+Frequency (MHz): 16.808
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 56.596
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 65.840
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 62.940
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3585
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3106 | 3106
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.520
+Frequency (MHz): 18.012
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.193
+External Hold (ns): 0.486
+Min Clock-To-Out (ns): 3.058
+Max Clock-To-Out (ns): 64.779
+
+ Input to Output
+Min Delay (ns): 2.046
+Max Delay (ns): 60.452
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3635
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3156 | 3156
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 44.550
+Frequency (MHz): 22.447
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 41.682
+External Hold (ns): 0.248
+Min Clock-To-Out (ns): 3.318
+Max Clock-To-Out (ns): 51.566
+
+ Input to Output
+Min Delay (ns): 2.088
+Max Delay (ns): 48.698
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3556
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3077 | 3077
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 69.886
+Frequency (MHz): 14.309
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.083
+External Hold (ns): 0.765
+Min Clock-To-Out (ns): 7.615
+Max Clock-To-Out (ns): 75.891
+
+ Input to Output
+Min Delay (ns): 4.971
+Max Delay (ns): 71.088
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3549
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3069 | 3069
+ SEQ | 480 | 480
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.165
+Frequency (MHz): 18.127
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.175
+External Hold (ns): 0.935
+Min Clock-To-Out (ns): 6.100
+Max Clock-To-Out (ns): 62.347
+
+ Input to Output
+Min Delay (ns): 4.213
+Max Delay (ns): 58.357
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3535
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3056 | 3056
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 60.713
+Frequency (MHz): 16.471
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 58.080
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 67.811
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 65.178
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3585
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3106 | 3106
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.458
+Frequency (MHz): 18.032
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 50.559
+External Hold (ns): 0.424
+Min Clock-To-Out (ns): 2.941
+Max Clock-To-Out (ns): 64.709
+
+ Input to Output
+Min Delay (ns): 1.904
+Max Delay (ns): 59.812
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3635
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3156 | 3156
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 43.859
+Frequency (MHz): 22.800
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 41.325
+External Hold (ns): 0.349
+Min Clock-To-Out (ns): 3.018
+Max Clock-To-Out (ns): 48.521
+
+ Input to Output
+Min Delay (ns): 1.893
+Max Delay (ns): 45.987
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3556
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3077 | 3077
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 60.059
+Frequency (MHz): 16.650
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 57.164
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 68.807
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 65.912
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3585
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3106 | 3106
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.859
+Frequency (MHz): 17.902
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 49.060
+External Hold (ns): 0.991
+Min Clock-To-Out (ns): 3.083
+Max Clock-To-Out (ns): 62.333
+
+ Input to Output
+Min Delay (ns): 2.212
+Max Delay (ns): 55.534
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3635
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3156 | 3156
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 44.843
+Frequency (MHz): 22.300
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 40.185
+External Hold (ns): 1.018
+Min Clock-To-Out (ns): 2.963
+Max Clock-To-Out (ns): 51.927
+
+ Input to Output
+Min Delay (ns): 2.260
+Max Delay (ns): 47.269
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3556
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3077 | 3077
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 0 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 71.404
+Frequency (MHz): 14.005
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.180
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 79.196
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 72.972
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 3646
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 3167 | 3167
+ SEQ | 479 | 479
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 71.522
+Frequency (MHz): 13.982
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 62.333
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 71.649
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 70.065
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4884
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4261 | 4261
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.799
+Frequency (MHz): 17.921
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 55.847
+External Hold (ns): 0.430
+Min Clock-To-Out (ns): 3.127
+Max Clock-To-Out (ns): 62.868
+
+ Input to Output
+Min Delay (ns): 2.070
+Max Delay (ns): 62.916
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4742
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4118 | 4118
+ SEQ | 624 | 624
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 46.678
+Frequency (MHz): 21.423
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 45.726
+External Hold (ns): 0.184
+Min Clock-To-Out (ns): 3.121
+Max Clock-To-Out (ns): 52.569
+
+ Input to Output
+Min Delay (ns): 2.125
+Max Delay (ns): 51.617
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4811
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4188 | 4188
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 66.074
+Frequency (MHz): 15.135
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.604
+External Hold (ns): 0.636
+Min Clock-To-Out (ns): 6.321
+Max Clock-To-Out (ns): 74.907
+
+ Input to Output
+Min Delay (ns): 4.750
+Max Delay (ns): 75.465
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4774
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4151 | 4151
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 62.880
+Frequency (MHz): 15.903
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 58.918
+External Hold (ns): 0.501
+Min Clock-To-Out (ns): 5.767
+Max Clock-To-Out (ns): 68.704
+
+ Input to Output
+Min Delay (ns): 4.032
+Max Delay (ns): 66.092
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4776
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4153 | 4153
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 66.554
+Frequency (MHz): 15.025
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 61.743
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 72.194
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 70.797
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4884
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4261 | 4261
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 54.375
+Frequency (MHz): 18.391
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 54.649
+External Hold (ns): 0.420
+Min Clock-To-Out (ns): 2.827
+Max Clock-To-Out (ns): 59.461
+
+ Input to Output
+Min Delay (ns): 1.902
+Max Delay (ns): 59.735
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4742
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4118 | 4118
+ SEQ | 624 | 624
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 46.154
+Frequency (MHz): 21.667
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 46.484
+External Hold (ns): 0.353
+Min Clock-To-Out (ns): 3.003
+Max Clock-To-Out (ns): 51.186
+
+ Input to Output
+Min Delay (ns): 1.940
+Max Delay (ns): 51.965
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4811
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4188 | 4188
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 70.208
+Frequency (MHz): 14.243
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 60.252
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 69.971
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 68.565
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4884
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4261 | 4261
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 56.209
+Frequency (MHz): 17.791
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 54.735
+External Hold (ns): 0.685
+Min Clock-To-Out (ns): 2.951
+Max Clock-To-Out (ns): 61.627
+
+ Input to Output
+Min Delay (ns): 2.212
+Max Delay (ns): 60.153
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4742
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4118 | 4118
+ SEQ | 624 | 624
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 48.594
+Frequency (MHz): 20.579
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 49.120
+External Hold (ns): 1.041
+Min Clock-To-Out (ns): 2.988
+Max Clock-To-Out (ns): 53.864
+
+ Input to Output
+Min Delay (ns): 2.262
+Max Delay (ns): 54.390
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4811
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4188 | 4188
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 0 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 73.462
+Frequency (MHz): 13.612
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 64.585
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 73.620
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 70.771
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 4857
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4234 | 4234
+ SEQ | 623 | 623
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 61.636
+Frequency (MHz): 16.224
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 57.137
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 67.618
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 63.463
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5014
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4348 | 4348
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 62.374
+Frequency (MHz): 16.032
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 52.661
+External Hold (ns): 0.369
+Min Clock-To-Out (ns): 3.057
+Max Clock-To-Out (ns): 60.319
+
+ Input to Output
+Min Delay (ns): 2.079
+Max Delay (ns): 57.466
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5004
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4337 | 4337
+ SEQ | 667 | 667
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 47.073
+Frequency (MHz): 21.244
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 46.714
+External Hold (ns): 0.437
+Min Clock-To-Out (ns): 3.315
+Max Clock-To-Out (ns): 52.799
+
+ Input to Output
+Min Delay (ns): 2.109
+Max Delay (ns): 52.440
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5002
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4336 | 4336
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 69.350
+Frequency (MHz): 14.420
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 66.678
+External Hold (ns): 1.139
+Min Clock-To-Out (ns): 6.759
+Max Clock-To-Out (ns): 73.782
+
+ Input to Output
+Min Delay (ns): 4.757
+Max Delay (ns): 72.203
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5012
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4345 | 4345
+ SEQ | 667 | 667
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 54.514
+Frequency (MHz): 18.344
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 52.044
+External Hold (ns): 0.934
+Min Clock-To-Out (ns): 5.679
+Max Clock-To-Out (ns): 62.000
+
+ Input to Output
+Min Delay (ns): 4.032
+Max Delay (ns): 58.639
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5032
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4366 | 4366
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 60.421
+Frequency (MHz): 16.551
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 58.594
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 69.078
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 67.251
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5014
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4348 | 4348
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 54.338
+Frequency (MHz): 18.403
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.572
+External Hold (ns): 0.643
+Min Clock-To-Out (ns): 2.515
+Max Clock-To-Out (ns): 58.728
+
+ Input to Output
+Min Delay (ns): 1.854
+Max Delay (ns): 55.962
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5004
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4337 | 4337
+ SEQ | 667 | 667
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 47.071
+Frequency (MHz): 21.245
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 47.553
+External Hold (ns): 0.528
+Min Clock-To-Out (ns): 2.730
+Max Clock-To-Out (ns): 50.373
+
+ Input to Output
+Min Delay (ns): 1.940
+Max Delay (ns): 50.855
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5002
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4336 | 4336
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 64.110
+Frequency (MHz): 15.598
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 62.268
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 75.575
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 73.733
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5014
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4348 | 4348
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.995
+Frequency (MHz): 17.859
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 53.992
+External Hold (ns): 0.998
+Min Clock-To-Out (ns): 2.999
+Max Clock-To-Out (ns): 62.056
+
+ Input to Output
+Min Delay (ns): 2.211
+Max Delay (ns): 60.053
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5004
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4337 | 4337
+ SEQ | 667 | 667
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 49.346
+Frequency (MHz): 20.265
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 46.472
+External Hold (ns): 1.023
+Min Clock-To-Out (ns): 2.997
+Max Clock-To-Out (ns): 52.969
+
+ Input to Output
+Min Delay (ns): 2.297
+Max Delay (ns): 53.522
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5002
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4336 | 4336
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 0 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 72.222
+Frequency (MHz): 13.846
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 66.967
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 79.167
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 73.912
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5016
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4350 | 4350
+ SEQ | 666 | 666
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 60.040
+Frequency (MHz): 16.656
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 56.383
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 67.070
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 63.561
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5263
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4554 | 4554
+ SEQ | 709 | 709
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 52.542
+Frequency (MHz): 19.032
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.724
+External Hold (ns): 0.390
+Min Clock-To-Out (ns): 3.241
+Max Clock-To-Out (ns): 60.476
+
+ Input to Output
+Min Delay (ns): 2.048
+Max Delay (ns): 59.658
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5246
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4538 | 4538
+ SEQ | 708 | 708
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 41.647
+Frequency (MHz): 24.011
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 40.940
+External Hold (ns): 0.393
+Min Clock-To-Out (ns): 3.373
+Max Clock-To-Out (ns): 49.023
+
+ Input to Output
+Min Delay (ns): 2.162
+Max Delay (ns): 48.316
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5210
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4503 | 4503
+ SEQ | 707 | 707
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 67.866
+Frequency (MHz): 14.735
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 67.341
+External Hold (ns): 0.633
+Min Clock-To-Out (ns): 6.638
+Max Clock-To-Out (ns): 77.183
+
+ Input to Output
+Min Delay (ns): 4.759
+Max Delay (ns): 76.658
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5183
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4474 | 4474
+ SEQ | 709 | 709
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 58.347
+Frequency (MHz): 17.139
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 53.616
+External Hold (ns): 0.484
+Min Clock-To-Out (ns): 6.148
+Max Clock-To-Out (ns): 67.071
+
+ Input to Output
+Min Delay (ns): 4.038
+Max Delay (ns): 62.340
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5174
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4466 | 4466
+ SEQ | 708 | 708
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 62.489
+Frequency (MHz): 16.003
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 59.682
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 71.122
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 68.508
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5263
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4554 | 4554
+ SEQ | 709 | 709
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 52.780
+Frequency (MHz): 18.947
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.636
+External Hold (ns): 0.644
+Min Clock-To-Out (ns): 2.870
+Max Clock-To-Out (ns): 60.087
+
+ Input to Output
+Min Delay (ns): 1.901
+Max Delay (ns): 58.974
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5246
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4538 | 4538
+ SEQ | 708 | 708
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 44.316
+Frequency (MHz): 22.565
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 42.479
+External Hold (ns): 0.407
+Min Clock-To-Out (ns): 2.509
+Max Clock-To-Out (ns): 49.750
+
+ Input to Output
+Min Delay (ns): 1.888
+Max Delay (ns): 47.909
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5210
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4503 | 4503
+ SEQ | 707 | 707
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 64.038
+Frequency (MHz): 15.616
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 64.165
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 68.333
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 69.112
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5263
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4554 | 4554
+ SEQ | 709 | 709
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 56.151
+Frequency (MHz): 17.809
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 54.045
+External Hold (ns): 0.671
+Min Clock-To-Out (ns): 2.988
+Max Clock-To-Out (ns): 65.864
+
+ Input to Output
+Min Delay (ns): 2.209
+Max Delay (ns): 63.758
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5246
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4538 | 4538
+ SEQ | 708 | 708
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 46.560
+Frequency (MHz): 21.478
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 48.940
+External Hold (ns): 0.720
+Min Clock-To-Out (ns): 2.906
+Max Clock-To-Out (ns): 56.528
+
+ Input to Output
+Min Delay (ns): 2.260
+Max Delay (ns): 58.908
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5210
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4503 | 4503
+ SEQ | 707 | 707
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 0 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 70.004
+Frequency (MHz): 14.285
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 67.782
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 76.206
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 73.984
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5214
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4505 | 4505
+ SEQ | 709 | 709
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 67.175
+Frequency (MHz): 14.886
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 66.999
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 74.967
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 74.791
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5571
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4821 | 4821
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 52.406
+Frequency (MHz): 19.082
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 49.356
+External Hold (ns): 0.399
+Min Clock-To-Out (ns): 3.024
+Max Clock-To-Out (ns): 58.778
+
+ Input to Output
+Min Delay (ns): 2.043
+Max Delay (ns): 57.661
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5345
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4595 | 4595
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 43.762
+Frequency (MHz): 22.851
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 42.914
+External Hold (ns): 0.453
+Min Clock-To-Out (ns): 2.938
+Max Clock-To-Out (ns): 52.039
+
+ Input to Output
+Min Delay (ns): 2.117
+Max Delay (ns): 50.921
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5446
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4696 | 4696
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 70.659
+Frequency (MHz): 14.152
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 69.361
+External Hold (ns): 1.104
+Min Clock-To-Out (ns): 6.284
+Max Clock-To-Out (ns): 79.935
+
+ Input to Output
+Min Delay (ns): 4.970
+Max Delay (ns): 78.637
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5453
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4703 | 4703
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 56.521
+Frequency (MHz): 17.693
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 53.598
+External Hold (ns): 0.935
+Min Clock-To-Out (ns): 5.720
+Max Clock-To-Out (ns): 64.497
+
+ Input to Output
+Min Delay (ns): 4.213
+Max Delay (ns): 61.316
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5418
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4668 | 4668
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 68.371
+Frequency (MHz): 14.626
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.231
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 75.295
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 72.138
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5571
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4821 | 4821
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 58.370
+Frequency (MHz): 17.132
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.910
+External Hold (ns): 0.260
+Min Clock-To-Out (ns): 2.311
+Max Clock-To-Out (ns): 60.896
+
+ Input to Output
+Min Delay (ns): 1.902
+Max Delay (ns): 59.108
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5345
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4595 | 4595
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 42.983
+Frequency (MHz): 23.265
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 41.687
+External Hold (ns): 0.668
+Min Clock-To-Out (ns): 2.665
+Max Clock-To-Out (ns): 50.200
+
+ Input to Output
+Min Delay (ns): 1.890
+Max Delay (ns): 48.904
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5446
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4696 | 4696
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 65.791
+Frequency (MHz): 15.200
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.369
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 77.776
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 77.354
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5571
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4821 | 4821
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 53.504
+Frequency (MHz): 18.690
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 51.043
+External Hold (ns): 1.020
+Min Clock-To-Out (ns): 2.932
+Max Clock-To-Out (ns): 63.905
+
+ Input to Output
+Min Delay (ns): 2.211
+Max Delay (ns): 61.444
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5345
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4595 | 4595
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 46.762
+Frequency (MHz): 21.385
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 45.886
+External Hold (ns): 1.039
+Min Clock-To-Out (ns): 2.882
+Max Clock-To-Out (ns): 54.605
+
+ Input to Output
+Min Delay (ns): 2.258
+Max Delay (ns): 53.727
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5446
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4696 | 4696
+ SEQ | 750 | 750
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 0
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 69.277
+Frequency (MHz): 14.435
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.839
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 77.535
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 73.236
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5467
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4716 | 4716
+ SEQ | 751 | 751
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 65.626
+Frequency (MHz): 15.238
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 62.017
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 71.036
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 68.666
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5747
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4954 | 4954
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 54.672
+Frequency (MHz): 18.291
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 49.764
+External Hold (ns): 0.328
+Min Clock-To-Out (ns): 3.161
+Max Clock-To-Out (ns): 61.785
+
+ Input to Output
+Min Delay (ns): 2.070
+Max Delay (ns): 56.877
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5713
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4920 | 4920
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3E (A3PE1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 51.406
+Frequency (MHz): 19.453
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 47.497
+External Hold (ns): 0.320
+Min Clock-To-Out (ns): 3.089
+Max Clock-To-Out (ns): 52.123
+
+ Input to Output
+Min Delay (ns): 2.089
+Max Delay (ns): 51.309
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5625
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4833 | 4833
+ SEQ | 792 | 792
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 71.166
+Frequency (MHz): 14.052
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 65.631
+External Hold (ns): 1.104
+Min Clock-To-Out (ns): 5.982
+Max Clock-To-Out (ns): 81.369
+
+ Input to Output
+Min Delay (ns): 4.759
+Max Delay (ns): 75.834
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5638
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4846 | 4846
+ SEQ | 792 | 792
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3L (A3P1000L), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 61.462
+Frequency (MHz): 16.270
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 55.362
+External Hold (ns): 0.356
+Min Clock-To-Out (ns): 5.381
+Max Clock-To-Out (ns): 64.619
+
+ Input to Output
+Min Delay (ns): 4.213
+Max Delay (ns): 62.829
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5706
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4913 | 4913
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 65.017
+Frequency (MHz): 15.381
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 61.568
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 70.734
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 67.285
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5747
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4954 | 4954
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 53.783
+Frequency (MHz): 18.593
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 50.882
+External Hold (ns): 0.475
+Min Clock-To-Out (ns): 2.731
+Max Clock-To-Out (ns): 59.354
+
+ Input to Output
+Min Delay (ns): 1.901
+Max Delay (ns): 56.114
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5713
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4920 | 4920
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# ProASIC3 (A3P1000), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 48.202
+Frequency (MHz): 20.746
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 45.292
+External Hold (ns): 0.414
+Min Clock-To-Out (ns): 2.463
+Max Clock-To-Out (ns): 53.635
+
+ Input to Output
+Min Delay (ns): 1.941
+Max Delay (ns): 51.955
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5625
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4833 | 4833
+ SEQ | 792 | 792
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 64.510
+Frequency (MHz): 15.501
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 61.904
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 75.008
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 73.237
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5747
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4954 | 4954
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -1
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 55.618
+Frequency (MHz): 17.980
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 49.363
+External Hold (ns): 1.007
+Min Clock-To-Out (ns): 3.473
+Max Clock-To-Out (ns): 63.477
+
+ Input to Output
+Min Delay (ns): 2.212
+Max Delay (ns): 59.116
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5713
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4920 | 4920
+ SEQ | 793 | 793
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# Fusion (AFS1500), speedgrade: -2
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 48.568
+Frequency (MHz): 20.590
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 45.081
+External Hold (ns): 1.026
+Min Clock-To-Out (ns): 2.608
+Max Clock-To-Out (ns): 55.077
+
+ Input to Output
+Min Delay (ns): 2.258
+Max Delay (ns): 51.590
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5625
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4833 | 4833
+ SEQ | 792 | 792
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+#####################################################################################
+# START SYNTHESIS
+#====================================================================================
+# IGLOOE (AGLE600V5), speedgrade: Std
+#====================================================================================
+# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
+# 12 10 1 1 1 1 1
+#====================================================================================
+
+
+Clock Domain: dco_clk
+Period (ns): 70.914
+Frequency (MHz): 14.102
+Required Period (ns): 40.000
+Required Frequency (MHz): 25.000
+External Setup (ns): 67.728
+External Hold (ns): 0.000
+Min Clock-To-Out (ns): 0.000
+Max Clock-To-Out (ns): 80.521
+
+ Input to Output
+Min Delay (ns): 0.000
+Max Delay (ns): 77.335
+
+
+====================================================================================
+Compile report:
+===============
+
+ CORE Used: 5739
+Core Information:
+
+ Type | Instances | Core tiles
+ --------|--------------|-----------
+ COMB | 4948 | 4948
+ SEQ | 791 | 791
+
+
+====================================================================================
+# SYNTHESIS DONE
+#####################################################################################
+
+
+#####################################################################################
+# ANALYSIS DONE
+#####################################################################################
+
actel/run_analysis.log
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/run_analysis.tcl
===================================================================
--- actel/run_analysis.tcl (nonexistent)
+++ actel/run_analysis.tcl (revision 64)
@@ -0,0 +1,274 @@
+#!/usr/bin/tclsh
+#------------------------------------------------------------------------------
+# Copyright (C) 2001 Authors
+#
+# This source file may be used and distributed without restriction provided
+# that this copyright statement is not removed from the file and that any
+# derivative work contains the original copyright notice and the associated
+# disclaimer.
+#
+# This source file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published
+# by the Free Software Foundation; either version 2.1 of the License, or
+# (at your option) any later version.
+#
+# This source is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+# License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this source; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+#------------------------------------------------------------------------------
+#
+# File Name: run_analysis.tcl
+#
+# Author(s):
+# - Olivier Girard, olgirard@gmail.com
+#
+#------------------------------------------------------------------------------
+# $Rev: 17 $
+# $LastChangedBy: olivier.girard $
+# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
+#------------------------------------------------------------------------------
+package require Tclx
+
+###############################################################################
+# SET SOME GLOBAL VARIABLES #
+###############################################################################
+
+# Set tools
+set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify.exe"
+set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe"
+
+# Set the different FPGA architectures & models to be checked (it should have a FBGA484 package)
+set fpgaConfigs {{"ProASIC3E" A3PE1500 {Std -1 -2}}
+ {"ProASIC3L" A3P1000L {Std -1}}
+ {"ProASIC3" A3P1000 {Std -1 -2}}
+ {"Fusion" AFS1500 {Std -1 -2}}
+ {"IGLOOE" AGLE600V5 {Std}}}
+
+
+# Set the different RTL configurations to be analysed
+set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3}
+set rtlConfigs {{ 12 10 0 0 0 0 0 }
+ { 12 10 1 0 0 0 0 }
+ { 12 10 1 1 0 0 0 }
+ { 12 10 1 1 1 0 0 }
+ { 12 10 1 1 1 1 0 }
+ { 12 10 1 1 1 1 1 }}
+
+
+# RTL configuration files
+set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
+set designFiles {../../rtl/verilog/openMSP430.v
+ ../../rtl/verilog/omsp_frontend.v
+ ../../rtl/verilog/omsp_execution_unit.v
+ ../../rtl/verilog/omsp_register_file.v
+ ../../rtl/verilog/omsp_alu.v
+ ../../rtl/verilog/omsp_mem_backbone.v
+ ../../rtl/verilog/omsp_clock_module.v
+ ../../rtl/verilog/omsp_sfr.v
+ ../../rtl/verilog/omsp_watchdog.v
+ ../../rtl/verilog/omsp_dbg.v
+ ../../rtl/verilog/omsp_dbg_uart.v
+ ../../rtl/verilog/omsp_dbg_hwbrk.v
+ ../../rtl/verilog/openMSP430_undefines.v
+ ../../rtl/verilog/timescale.v
+}
+
+###############################################################################
+# PERFORM ANALYSIS #
+###############################################################################
+proc sleep {time} {
+ after [expr $time*1000] set end 1
+ vwait end
+ }
+
+# Copy design files
+foreach designFile $designFiles {
+ file copy -force $designFile "./src/"
+}
+
+# Create log file
+file delete "./run_analysis.log"
+set f_logFile [open "./run_analysis.log" w]
+
+# Perform analysis
+foreach rtlConfig $rtlConfigs {
+
+ #-------------------------------------------------------------------------#
+ # Generate RTL configuration #
+ #-------------------------------------------------------------------------#
+
+ # Read original define file
+ if [catch {open $omspConfigFile r} f_omspConfigFile] {
+ puts $f_logFile "ERROR: Cannot open file $omspConfigFile"
+ close $f_logFile
+ exit 1
+ }
+ set configFile [read $f_omspConfigFile]
+ close $f_omspConfigFile
+
+
+ # Update defines
+ set idx 0
+ foreach rtlDefine $rtlDefines {
+
+ if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
+ } else {
+ if {[lindex $rtlConfig $idx]==0} {
+ regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
+ }
+ }
+ set idx [expr $idx+1]
+ }
+
+
+ # Write the new file
+ set f_configFile [open "./src/[file tail $omspConfigFile]" w]
+ puts $f_configFile $configFile
+ close $f_configFile
+
+ #-------------------------------------------------------------------------#
+ # Perform analysis for each FPGA #
+ #-------------------------------------------------------------------------#
+ foreach fpgaConfig $fpgaConfigs {
+ foreach speedGrade [lindex $fpgaConfig 2] {
+
+ # Cleanup
+ file delete -force ./WORK
+ file mkdir ./WORK
+ cd ./WORK
+
+ # Copy Synplify tcl command files
+ if [catch {open "../synplify.tcl" r} f_synplify_tcl] {
+ puts $f_logFile "ERROR: Cannot open Synplify command file file ../synplify.tcl"
+ close $f_logFile
+ exit 1
+ }
+ set synplify_tcl [read $f_synplify_tcl]
+ close $f_synplify_tcl
+
+ regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 1]]" synplify_tcl
+ regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 0]]" synplify_tcl
+ regsub -all {} $synplify_tcl "$speedGrade" synplify_tcl
+
+ set f_synplify_tcl [open "synplify.tcl" w]
+ puts $f_synplify_tcl $synplify_tcl
+ close $f_synplify_tcl
+
+ # Copy Libero Designer tcl command files
+ if [catch {open "../libero_designer.tcl" r} f_libero_designer_tcl] {
+ puts $f_logFile "ERROR: Cannot open Libero Designer command file file ../libero_designer.tcl"
+ close $f_logFile
+ exit 1
+ }
+ set libero_designer_tcl [read $f_libero_designer_tcl]
+ close $f_libero_designer_tcl
+
+ regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 1]" libero_designer_tcl
+ regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 0]" libero_designer_tcl
+ regsub -all {} $libero_designer_tcl "$speedGrade" libero_designer_tcl
+
+ set f_libero_designer_tcl [open "libero_designer.tcl" w]
+ puts $f_libero_designer_tcl $libero_designer_tcl
+ close $f_libero_designer_tcl
+
+ # Run synthesis
+ puts $f_logFile "#####################################################################################"
+ puts $f_logFile "# START SYNTHESIS"
+ puts $f_logFile "#===================================================================================="
+ puts $f_logFile "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: $speedGrade"
+ puts $f_logFile "#===================================================================================="
+ puts $f_logFile "# $rtlDefines"
+ puts $f_logFile "# $rtlConfig"
+ puts $f_logFile "#===================================================================================="
+ flush $f_logFile
+
+ # Run synthesis
+ set synplify_done 0
+ while {[string eq $synplify_done 0]} {
+
+ sleep 10
+ eval exec $SYNPLICITY synplify.tcl
+ sleep 30
+
+ # Wait until EDIF file is generated
+ set synplify_timeout 0
+
+# puts $f_logFile "START LOOP: $synplify_timeout ($synplify_done)"
+# flush $f_logFile
+
+ while {!([file exists "./rev_1/design_files.edn"] | ($synplify_timeout==100))} {
+ sleep 6
+# puts $f_logFile "YOPYOP: $synplify_timeout"
+# flush $f_logFile
+ set synplify_timeout [expr $synplify_timeout+1]
+ }
+ if ($synplify_timeout<100) {
+ set synplify_done 1
+ }
+# puts $f_logFile "DONE: $synplify_timeout ($synplify_done)"
+# flush $f_logFile
+
+ # Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
+ sleep 10
+ eval exec taskkill /IM synplify.exe
+ sleep 20
+ if {[string eq $synplify_done 0]} {
+ sleep 180
+ }
+ }
+# puts $f_logFile "SYNPLIFY DONE: $synplify_timeout ($synplify_done)"
+# flush $f_logFile
+
+ # Run place & route
+ eval exec $LIBERO_DESIGNER script:libero_designer.tcl logfile:libero_designer.log
+
+
+ # Extract timing information
+ if [catch {open "report_timing_max.txt" r} f_timing] {
+ puts $f_logFile "ERROR: Cannot open timing file"
+ close $f_logFile
+ exit 1
+ }
+ set timingFile [read $f_timing]
+ close $f_timing
+ regexp {SUMMARY(.*)END SUMMARY} $timingFile whole_match timing
+ puts $f_logFile $timing
+ puts $f_logFile "===================================================================================="
+
+ # Extract size information
+ if [catch {open "report_status.txt" r} f_area] {
+ puts $f_logFile "ERROR: Cannot open status file: report_status.txt"
+ close $f_logFile
+ exit 1
+ }
+ set areaFile [read $f_area]
+ close $f_area
+ regexp {(Compile report:.*?)Total:} $areaFile whole_match area1
+ regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2
+ puts $f_logFile $area1
+ puts $f_logFile $area2
+ puts $f_logFile "===================================================================================="
+
+ puts $f_logFile "# SYNTHESIS DONE"
+ puts $f_logFile "#####################################################################################"
+ puts $f_logFile ""
+ flush $f_logFile
+ cd ../
+ sleep 3
+ }
+ }
+
+}
+puts $f_logFile ""
+puts $f_logFile "#####################################################################################"
+puts $f_logFile "# ANALYSIS DONE"
+puts $f_logFile "#####################################################################################"
+puts $f_logFile ""
+close $f_logFile
+exit 0
actel/run_analysis.tcl
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/libero_designer.tcl
===================================================================
--- actel/libero_designer.tcl (nonexistent)
+++ actel/libero_designer.tcl (revision 64)
@@ -0,0 +1,29 @@
+
+
+new_design -name "design_fpga" -family "" -path {.} -block "off"
+
+set_device -die "" \
+ -package "484 FBGA" \
+ -speed ""
+
+import_source -format "edif" -edif_flavor "GENERIC" {./rev_1/design_files.edn} \
+ -format "sdc" -scenario "Primary" {../design_files.sdc} \
+ -merge_physical "no" -merge_timing "yes"
+
+compile -pdc_abort_on_error "on" -pdc_eco_display_unmatched_objects "off" -pdc_eco_max_warnings 10000 \
+ -demote_globals "off" -demote_globals_max_fanout 12 -promote_globals "off" \
+ -promote_globals_min_fanout 200 -promote_globals_max_limit 0 -localclock_max_shared_instances 12 \
+ -localclock_buffer_tree_max_fanout 12 -combine_register "off" -delete_buffer_tree "off" \
+ -delete_buffer_tree_max_fanout 12 -report_high_fanout_nets_limit 10
+
+layout -timing_driven -placer_high_effort "on" -seq_opt "on"
+
+report -type "timer" -format "TEXT" -analysis "max" -print_summary "yes" \
+ -use_slack_threshold "no" -print_paths "yes" -max_paths 5 -max_expanded_paths 1 \
+ -include_user_sets "no" -include_pin_to_pin "yes" -select_clock_domains "no" \
+ {./report_timing_max.txt}
+
+report -type "status" \
+ {./report_status.txt}
+
+
actel/libero_designer.tcl
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: actel/synplify.tcl
===================================================================
--- actel/synplify.tcl (nonexistent)
+++ actel/synplify.tcl (revision 64)
@@ -0,0 +1,71 @@
+
+
+
+#add_file options
+add_file -verilog "../design_files.v"
+add_file -constraint "../design_files.sdc"
+
+
+#implementation: "rev_1"
+impl -add rev_1 -type fpga
+
+#device options
+set_option -technology
+set_option -part
+set_option -package FBGA484
+set_option -speed_grade
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -default_enum_encoding default
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+set_option -top_module "openMSP430"
+
+#map options
+set_option -frequency 30.000
+set_option -vendor_xcompatible_mode 0
+set_option -vendor_xcompatible_mode 0
+set_option -run_prop_extract 1
+set_option -fanout_limit 24
+set_option -globalthreshold 50
+set_option -maxfan_hard 0
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -report_path 4000
+set_option -opcond COMWC
+set_option -update_models_cp 0
+set_option -preserve_registers 0
+
+
+#sequential_optimizations options
+set_option -symbolic_fsm_compiler 1
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "./rev_1/design_files.edn"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -dup 0
+set_option -project_relative_includes 1
+impl -active "rev_1"
+
+
+# Run synthesis
+project -run synthesis
+
+# Save and quit
+project -save rev_1.prj
+
+#exit 0
+
actel/synplify.tcl
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property