Subversion Repositories openmsp430

/actel/run_analysis.tcl

/actel/run_analysis.mpy.log

actel/run_analysis.mpy.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: altera/design_files.v =================================================================== --- altera/design_files.v (revision 64) +++ altera/design_files.v (revision 68) @@ -96,3 +96,7 @@ `include "../../../rtl/verilog/omsp_dbg_hwbrk.v" `endif `endif +`include "../src/openMSP430_defines.v" +`ifdef MULTIPLIER + `include "../../../rtl/verilog/omsp_multiplier.v" +`endif Index: altera/run_analysis.area.mpy.log =================================================================== --- altera/run_analysis.area.mpy.log (nonexistent) +++ altera/run_analysis.area.mpy.log (revision 68) @@ -0,0 +1,691 @@ +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -17.586 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 45.97 MHz ( period = 21.752 ns ) + +==================================================================================== +Total logic elements : 1,785 / 18,752 ( 10 % ) + Total combinational functions : 1,732 / 18,752 ( 9 % ) + Dedicated logic registers : 537 / 18,752 ( 3 % ) +Total registers : 537 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 2 / 52 ( 4 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.153 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.00 MHz ( period = 26.319 ns ) + +==================================================================================== +Total logic elements : 1,781 / 18,752 ( 9 % ) + Total combinational functions : 1,732 / 18,752 ( 9 % ) + Dedicated logic registers : 537 / 18,752 ( 3 % ) +Total registers : 537 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 2 / 52 ( 4 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.587 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.52 MHz ( period = 30.753 ns ) + +==================================================================================== +Total logic elements : 1,779 / 18,752 ( 9 % ) + Total combinational functions : 1,732 / 18,752 ( 9 % ) + Dedicated logic registers : 537 / 18,752 ( 3 % ) +Total registers : 537 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 2 / 52 ( 4 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 49.06 MHz ; 49.06 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,752 / 55,856 ( 3 % ) + Total combinational functions : 1,732 / 55,856 ( 3 % ) + Dedicated logic registers : 537 / 55,856 ( < 1 % ) +Total registers : 537 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 2 / 312 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.01 MHz ; 41.01 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,750 / 55,856 ( 3 % ) + Total combinational functions : 1,732 / 55,856 ( 3 % ) + Dedicated logic registers : 537 / 55,856 ( < 1 % ) +Total registers : 537 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 2 / 312 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 37.34 MHz ; 37.34 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,752 / 55,856 ( 3 % ) + Total combinational functions : 1,732 / 55,856 ( 3 % ) + Dedicated logic registers : 537 / 55,856 ( < 1 % ) +Total registers : 537 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 2 / 312 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 49.1 MHz ; 49.1 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,750 / 21,280 ( 8 % ) + Total combinational functions : 1,732 / 21,280 ( 8 % ) + Dedicated logic registers : 537 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 2 / 80 ( 3 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.92 MHz ; 42.92 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,749 / 21,280 ( 8 % ) + Total combinational functions : 1,732 / 21,280 ( 8 % ) + Dedicated logic registers : 537 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 2 / 80 ( 3 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 37.09 MHz ; 37.09 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,747 / 21,280 ( 8 % ) + Total combinational functions : 1,732 / 21,280 ( 8 % ) + Dedicated logic registers : 537 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 2 / 80 ( 3 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 45.11 MHz ; 45.11 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,160 / 40,128 ( 3 % ) + Dedicated logic registers : 539 / 40,128 ( 1 % ) +Total registers : 539 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 2 / 208 ( < 1 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 80.28 MHz ; 80.28 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,146 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 540 / 36,100 ( 1 % ) +Total registers : 540 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 2 / 232 ( < 1 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 71.11 MHz ; 71.11 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,148 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 539 / 36,100 ( 1 % ) +Total registers : 539 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 2 / 232 ( < 1 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 63.11 MHz ; 63.11 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,143 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 539 / 36,100 ( 1 % ) +Total registers : 539 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 2 / 232 ( < 1 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.846 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 43.46 MHz ( period = 23.012 ns ) + +==================================================================================== +Total logic elements : 1,730 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 2 / 48 ( 4 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.238 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.87 MHz ( period = 26.404 ns ) + +==================================================================================== +Total logic elements : 1,730 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 2 / 48 ( 4 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.875 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.29 MHz ( period = 30.041 ns ) + +==================================================================================== +Total logic elements : 1,730 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 2 / 48 ( 4 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -10.358 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 68.85 MHz ( period = 14.524 ns ) + +==================================================================================== +Logic utilization : 13 % + Combinational ALUTs : 1,145 / 12,480 ( 9 % ) + Dedicated logic registers : 540 / 12,480 ( 4 % ) +Total registers : 540 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 2 / 96 ( 2 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -12.410 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 60.33 MHz ( period = 16.576 ns ) + +==================================================================================== +Logic utilization : 13 % + Combinational ALUTs : 1,157 / 12,480 ( 9 % ) + Dedicated logic registers : 540 / 12,480 ( 4 % ) +Total registers : 540 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 2 / 96 ( 2 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.087 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 51.94 MHz ( period = 19.253 ns ) + +==================================================================================== +Logic utilization : 13 % + Combinational ALUTs : 1,155 / 12,480 ( 9 % ) + Dedicated logic registers : 541 / 12,480 ( 4 % ) +Total registers : 541 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 2 / 96 ( 2 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 87.91 MHz ; 87.91 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,147 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 538 / 38,000 ( 1 % ) +Total registers : 538 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 2 / 384 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 81.95 MHz ; 81.95 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,142 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 539 / 38,000 ( 1 % ) +Total registers : 539 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 2 / 384 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 72.61 MHz ; 72.61 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,147 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 539 / 38,000 ( 1 % ) +Total registers : 539 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 2 / 384 ( < 1 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### +

altera/run_analysis.area.mpy.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: altera/src/openMSP430_defines.v =================================================================== --- altera/src/openMSP430_defines.v (revision 64) +++ altera/src/openMSP430_defines.v (revision 68) @@ -62,6 +62,10 @@ // 14 -> 32 kB `define DMEM_AWIDTH 10 +// Include/Exclude Hardware Multiplier +`define MULTIPLIER + + //---------------------------------------------------------------------------- // REMOTE DEBUGGING INTERFACE CONFIGURATION //---------------------------------------------------------------------------- @@ -298,3 +302,12 @@ `endif `endif +// +// MULTIPLIER CONFIGURATION +//====================================== + +// If uncommented, the following define selects +// the 16x16 multiplier (1 cycle) instead of the +// default 16x8 multplier (2 cycles) +//`define MPY_16x16 +

/altera/src/megawizard

altera/src/megawizard Property changes : Added: svn:ignore ## -0,0 +1 ## +WORK Index: altera/run_analysis.tcl =================================================================== --- altera/run_analysis.tcl (revision 64) +++ altera/run_analysis.tcl (revision 68) @@ -51,18 +51,16 @@ {"Stratix" EP1S10F484C {5 6 7}} {"Stratix II" EP2S15F484C {3 4 5}} {"Stratix III" EP3SE50F484C {2 3 4}}} -set fpgaConfigs {{"Cyclone II" EP2C20F484C {7}}} - - + # Set the different RTL configurations to be analysed -set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3} -set rtlConfigs {{ 12 10 0 0 0 0 0 } - { 12 10 1 0 0 0 0 } - { 12 10 1 1 0 0 0 } - { 12 10 1 1 1 0 0 } - { 12 10 1 1 1 1 0 } - { 12 10 1 1 1 1 1 }} -set rtlConfigs {{ 12 10 0 0 0 0 0 }} +set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER} +set rtlConfigs {{ 12 10 0 0 0 0 0 0} + { 12 10 1 0 0 0 0 0} + { 12 10 1 1 0 0 0 0} + { 12 10 1 1 1 0 0 0} + { 12 10 1 1 1 1 0 0} + { 12 10 1 1 1 1 1 0}} +set rtlConfigs {{ 12 10 0 0 0 0 0 1}} # RTL configuration files

/altera/run_analysis.speed.mpy.log

altera/run_analysis.speed.mpy.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: altera =================================================================== --- altera (revision 64) +++ altera (revision 68)

altera Property changes : Added: svn:ignore ## -0,0 +1 ## +WORK Index: xilinx/src/openMSP430_defines.v =================================================================== --- xilinx/src/openMSP430_defines.v (revision 64) +++ xilinx/src/openMSP430_defines.v (revision 68) @@ -62,6 +62,10 @@ // 14 -> 32 kB `define DMEM_AWIDTH 10 +// Include/Exclude Hardware Multiplier +`define MULTIPLIER + + //---------------------------------------------------------------------------- // REMOTE DEBUGGING INTERFACE CONFIGURATION //---------------------------------------------------------------------------- @@ -298,3 +302,12 @@ `endif `endif +// +// MULTIPLIER CONFIGURATION +//====================================== + +// If uncommented, the following define selects +// the 16x16 multiplier (1 cycle) instead of the +// default 16x8 multplier (2 cycles) +//`define MPY_16x16 +

/xilinx/run_analysis.tcl

/xilinx/run_analysis.speed.mpy.log

xilinx/run_analysis.speed.mpy.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: xilinx/openMSP430_fpga.prj =================================================================== --- xilinx/openMSP430_fpga.prj (revision 64) +++ xilinx/openMSP430_fpga.prj (revision 68) @@ -96,3 +96,7 @@ `include "../../../rtl/verilog/omsp_dbg_hwbrk.v" `endif `endif +`include "../src/openMSP430_defines.v" +`ifdef MULTIPLIER + `include "../../../rtl/verilog/omsp_multiplier.v" +`endif Index: xilinx/run_analysis.area.mpy.log =================================================================== --- xilinx/run_analysis.area.mpy.log (nonexistent) +++ xilinx/run_analysis.area.mpy.log (revision 68) @@ -0,0 +1,889 @@ +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3 (xc3s400pq208), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 36.357| | | 1.641| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s400pq208-4 + + Number of Slices: 1008 out of 3584 28% + Number of Slice Flip Flops: 533 out of 7168 7% + Number of 4 input LUTs: 1811 out of 7168 25% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 141 56% + IOB Flip Flops: 10 + Number of BRAMs: 6 out of 16 37% + Number of MULT18X18s: 1 out of 16 6% + Number of GCLKs: 1 out of 8 12% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3 (xc3s400pq208), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 33.554| | | 1.468| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s400pq208-5 + + Number of Slices: 1008 out of 3584 28% + Number of Slice Flip Flops: 533 out of 7168 7% + Number of 4 input LUTs: 1811 out of 7168 25% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 141 56% + IOB Flip Flops: 10 + Number of BRAMs: 6 out of 16 37% + Number of MULT18X18s: 1 out of 16 6% + Number of GCLKs: 1 out of 8 12% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3e (xc3s500epq208), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 35.454| | | 2.328| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s500epq208-4 + + Number of Slices: 1013 out of 4656 21% + Number of Slice Flip Flops: 533 out of 9312 5% + Number of 4 input LUTs: 1816 out of 9312 19% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 158 50% + IOB Flip Flops: 10 + Number of BRAMs: 6 out of 20 30% + Number of MULT18X18SIOs: 1 out of 20 5% + Number of GCLKs: 1 out of 24 4% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3e (xc3s500epq208), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 30.742| | | 1.538| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s500epq208-5 + + Number of Slices: 1013 out of 4656 21% + Number of Slice Flip Flops: 533 out of 9312 5% + Number of 4 input LUTs: 1816 out of 9312 19% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 158 50% + IOB Flip Flops: 10 + Number of BRAMs: 6 out of 20 30% + Number of MULT18X18SIOs: 1 out of 20 5% + Number of GCLKs: 1 out of 24 4% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3a (xc3s700aft256), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 39.532| | | 1.688| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s700aft256-4 + + Number of Slices: 1022 out of 5888 17% + Number of Slice Flip Flops: 534 out of 11776 4% + Number of 4 input LUTs: 1832 out of 11776 15% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 161 49% + IOB Flip Flops: 10 + Number of BRAMs: 5 out of 20 25% + Number of MULT18X18SIOs: 1 out of 20 5% + Number of GCLKs: 1 out of 24 4% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3a (xc3s700aft256), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 30.273| | | 1.532| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3s700aft256-5 + + Number of Slices: 1020 out of 5888 17% + Number of Slice Flip Flops: 534 out of 11776 4% + Number of 4 input LUTs: 1827 out of 11776 15% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 161 49% + IOB Flip Flops: 10 + Number of BRAMs: 5 out of 20 25% + Number of MULT18X18SIOs: 1 out of 20 5% + Number of GCLKs: 1 out of 24 4% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3adsp (xc3sd1800acs484), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 36.164| | | 1.777| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3sd1800acs484-4 + + Number of Slices: 1024 out of 16640 6% + Number of Slice Flip Flops: 534 out of 33280 1% + Number of 4 input LUTs: 1831 out of 33280 5% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 309 25% + IOB Flip Flops: 10 + Number of BRAMs: 5 out of 84 5% + Number of GCLKs: 1 out of 24 4% + Number of DSP48s: 1 out of 84 1% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan3adsp (xc3sd1800acs484), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 28.990| | | 1.440| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 3sd1800acs484-5 + + Number of Slices: 1022 out of 16640 6% + Number of Slice Flip Flops: 534 out of 33280 1% + Number of 4 input LUTs: 1826 out of 33280 5% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 309 25% + IOB Flip Flops: 10 + Number of BRAMs: 5 out of 84 5% + Number of GCLKs: 1 out of 24 4% + Number of DSP48s: 1 out of 84 1% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan6 (xc6slx45tfgg484), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 29.715| 5.512| 2.728| 2.769| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6slx45tfgg484-2 + + +Slice Logic Utilization: + Number of Slice Registers: 533 out of 54576 0% + Number of Slice LUTs: 1436 out of 27288 5% + Number used as Logic: 1436 out of 27288 5% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1466 + Number with an unused Flip Flop: 933 out of 1466 63% + Number with an unused LUT: 30 out of 1466 2% + Number of fully used LUT-FF pairs: 503 out of 1466 34% + Number of unique control sets: 50 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 296 26% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 5 out of 348 1% + Number using Block RAM only: 5 + Number of BUFG/BUFGCTRLs: 1 out of 16 6% + Number of DSP48A1s: 1 out of 58 1% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan6 (xc6slx45tfgg484), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 23.010| 5.235| 2.087| 2.062| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6slx45tfgg484-3 + + +Slice Logic Utilization: + Number of Slice Registers: 533 out of 54576 0% + Number of Slice LUTs: 1425 out of 27288 5% + Number used as Logic: 1425 out of 27288 5% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1452 + Number with an unused Flip Flop: 919 out of 1452 63% + Number with an unused LUT: 27 out of 1452 1% + Number of fully used LUT-FF pairs: 506 out of 1452 34% + Number of unique control sets: 50 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 296 26% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 5 out of 348 1% + Number using Block RAM only: 5 + Number of BUFG/BUFGCTRLs: 1 out of 16 6% + Number of DSP48A1s: 1 out of 58 1% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# spartan6 (xc6slx45tfgg484), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 19.001| 4.893| 1.806| 1.570| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6slx45tfgg484-4 + + +Slice Logic Utilization: + Number of Slice Registers: 533 out of 54576 0% + Number of Slice LUTs: 1424 out of 27288 5% + Number used as Logic: 1424 out of 27288 5% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1451 + Number with an unused Flip Flop: 918 out of 1451 63% + Number with an unused LUT: 27 out of 1451 1% + Number of fully used LUT-FF pairs: 506 out of 1451 34% + Number of unique control sets: 50 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 296 26% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 5 out of 348 1% + Number using Block RAM only: 5 + Number of BUFG/BUFGCTRLs: 1 out of 16 6% + Number of DSP48A1s: 1 out of 58 1% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex4 (xc4vlx25sf363), speedgrade: -10 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 23.262| | | 0.954| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 4vlx25sf363-10 + + Number of Slices: 1021 out of 10752 9% + Number of Slice Flip Flops: 534 out of 21504 2% + Number of 4 input LUTs: 1829 out of 21504 8% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops: 10 + Number of FIFO16/RAMB16s: 5 out of 72 6% + Number used as RAMB16s: 5 + Number of GCLKs: 1 out of 32 3% + Number of DSP48s: 1 out of 48 2% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex4 (xc4vlx25sf363), speedgrade: -11 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 21.546| | | 0.850| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 4vlx25sf363-11 + + Number of Slices: 1015 out of 10752 9% + Number of Slice Flip Flops: 534 out of 21504 2% + Number of 4 input LUTs: 1810 out of 21504 8% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops: 10 + Number of FIFO16/RAMB16s: 5 out of 72 6% + Number used as RAMB16s: 5 + Number of GCLKs: 1 out of 32 3% + Number of DSP48s: 1 out of 48 2% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex4 (xc4vlx25sf363), speedgrade: -12 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 18.274| | | 0.914| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 4vlx25sf363-12 + + Number of Slices: 1018 out of 10752 9% + Number of Slice Flip Flops: 534 out of 21504 2% + Number of 4 input LUTs: 1819 out of 21504 8% + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops: 10 + Number of FIFO16/RAMB16s: 5 out of 72 6% + Number used as RAMB16s: 5 + Number of GCLKs: 1 out of 32 3% + Number of DSP48s: 1 out of 48 2% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex5 (xc5vlx30ff324), speedgrade: -1 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 16.985| | | 0.781| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 5vlx30ff324-1 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 19200 2% + Number of Slice LUTs: 1372 out of 19200 7% + Number used as Logic: 1372 out of 19200 7% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1398 + Number with an unused Flip Flop: 866 out of 1398 61% + Number with an unused LUT: 26 out of 1398 1% + Number of fully used LUT-FF pairs: 506 out of 1398 36% + Number of unique control sets: 48 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 220 35% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 32 9% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48Es: 1 out of 32 3% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex5 (xc5vlx30ff324), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 14.207| | | 0.680| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 5vlx30ff324-2 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 19200 2% + Number of Slice LUTs: 1372 out of 19200 7% + Number used as Logic: 1372 out of 19200 7% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1399 + Number with an unused Flip Flop: 867 out of 1399 61% + Number with an unused LUT: 27 out of 1399 1% + Number of fully used LUT-FF pairs: 505 out of 1399 36% + Number of unique control sets: 48 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 220 35% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 32 9% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48Es: 1 out of 32 3% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex5 (xc5vlx30ff324), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 13.429| | | 0.601| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 5vlx30ff324-3 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 19200 2% + Number of Slice LUTs: 1367 out of 19200 7% + Number used as Logic: 1367 out of 19200 7% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1395 + Number with an unused Flip Flop: 863 out of 1395 61% + Number with an unused LUT: 28 out of 1395 2% + Number of fully used LUT-FF pairs: 504 out of 1395 36% + Number of unique control sets: 48 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 220 35% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 32 9% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48Es: 1 out of 32 3% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex6 (xc6vlx75tff484), speedgrade: -1 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 14.414| 3.474| 1.579| 0.604| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6vlx75tff484-1 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 93120 0% + Number of Slice LUTs: 1390 out of 46560 2% + Number used as Logic: 1390 out of 46560 2% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1419 + Number with an unused Flip Flop: 887 out of 1419 62% + Number with an unused LUT: 29 out of 1419 2% + Number of fully used LUT-FF pairs: 503 out of 1419 35% + Number of unique control sets: 49 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 156 1% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48E1s: 1 out of 288 0% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex6 (xc6vlx75tff484), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 12.694| 3.071| 1.435| 0.508| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6vlx75tff484-2 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 93120 0% + Number of Slice LUTs: 1388 out of 46560 2% + Number used as Logic: 1388 out of 46560 2% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1418 + Number with an unused Flip Flop: 886 out of 1418 62% + Number with an unused LUT: 30 out of 1418 2% + Number of fully used LUT-FF pairs: 502 out of 1418 35% + Number of unique control sets: 49 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 156 1% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48E1s: 1 out of 288 0% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# virtex6 (xc6vlx75tff484), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER +# 12 10 0 0 0 0 0 1 +#==================================================================================== +Clock to Setup on destination clock dco_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +dco_clk | 10.953| 3.120| 1.173| 0.463| +---------------+---------+---------+---------+---------+ + +==================================================================================== +Device utilization summary: +--------------------------- + +Selected Device : 6vlx75tff484-3 + + +Slice Logic Utilization: + Number of Slice Registers: 532 out of 93120 0% + Number of Slice LUTs: 1387 out of 46560 2% + Number used as Logic: 1387 out of 46560 2% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1416 + Number with an unused Flip Flop: 884 out of 1416 62% + Number with an unused LUT: 29 out of 1416 2% + Number of fully used LUT-FF pairs: 503 out of 1416 35% + Number of unique control sets: 49 + +IO Utilization: + Number of IOs: 80 + Number of bonded IOBs: 79 out of 240 32% + IOB Flip Flops/Latches: 10 + +Specific Feature Utilization: + Number of Block RAM/FIFO: 3 out of 156 1% + Number using Block RAM only: 3 + Number of BUFG/BUFGCTRLs: 1 out of 32 3% + Number of DSP48E1s: 1 out of 288 0% + +--------------------------- + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### +

xilinx/run_analysis.area.mpy.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: xilinx =================================================================== --- xilinx (revision 64) +++ xilinx (revision 68)

xilinx Property changes : Added: svn:ignore ## -0,0 +1 ## +WORK