Subversion Repositories openmsp430

/bench/verilog/dbg_uart_tasks.v

/bench/verilog/tb_openMSP430.v

/bench/verilog/dbg_i2c_tasks.v

bench/verilog/dbg_i2c_tasks.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: bench/verilog/io_cell.v =================================================================== --- bench/verilog/io_cell.v (nonexistent) +++ bench/verilog/io_cell.v (revision 154) @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2009 , Olivier Girard +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the authors nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGE +// +//---------------------------------------------------------------------------- +// +// *File Name: io_cell.v +// +// *Module Description: +// I/O cell model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module io_cell ( + +// INOUTs + pad, // I/O Pad + +// OUTPUTs + data_in, // Input value + +// INPUTs + data_out_en, // Output enable + data_out // Output value +); + +// INOUTs +//========= +inout pad; // I/O Pad + +// OUTPUTs +//========= +output data_in; // Input value + +// INPUTs +//========= +input data_out_en; // Output enable +input data_out; // Output value + + +//============================================================================= +// 1) I/O CELL +//============================================================================= + +assign data_in = pad; +assign pad = data_out_en ? data_out : 1'bz; + + +endmodule // io_cell

bench/verilog/io_cell.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: rtl/verilog/omsp_dbg_i2c.v =================================================================== --- rtl/verilog/omsp_dbg_i2c.v (nonexistent) +++ rtl/verilog/omsp_dbg_i2c.v (revision 154) @@ -0,0 +1,466 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2009 , Olivier Girard +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the authors nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGE +// +//---------------------------------------------------------------------------- +// +// *File Name: omsp_dbg_i2c.v +// +// *Module Description: +// Debug I2C Slave communication interface +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- +`ifdef OMSP_NO_INCLUDE +`else +`include "openMSP430_defines.v" +`endif + +module omsp_dbg_i2c ( + +// OUTPUTs + dbg_addr, // Debug register address + dbg_din, // Debug register data input + dbg_i2c_sda_out, // Debug interface: I2C SDA OUT + dbg_rd, // Debug register data read + dbg_wr, // Debug register data write + +// INPUTs + dbg_clk, // Debug unit clock + dbg_dout, // Debug register data output + dbg_i2c_addr, // Debug interface: I2C ADDRESS + dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems) + dbg_i2c_scl, // Debug interface: I2C SCL + dbg_i2c_sda_in, // Debug interface: I2C SDA IN + dbg_rd_rdy, // Debug register data is ready for read + dbg_rst, // Debug unit reset + mem_burst, // Burst on going + mem_burst_end, // End TX/RX burst + mem_burst_rd, // Start TX burst + mem_burst_wr, // Start RX burst + mem_bw // Burst byte width +); + +// OUTPUTs +//========= +output [5:0] dbg_addr; // Debug register address +output [15:0] dbg_din; // Debug register data input +output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT +output dbg_rd; // Debug register data read +output dbg_wr; // Debug register data write + +// INPUTs +//========= +input dbg_clk; // Debug unit clock +input [15:0] dbg_dout; // Debug register data output +input [6:0] dbg_i2c_addr; // Debug interface: I2C ADDRESS +input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems) +input dbg_i2c_scl; // Debug interface: I2C SCL +input dbg_i2c_sda_in; // Debug interface: I2C SDA IN +input dbg_rd_rdy; // Debug register data is ready for read +input dbg_rst; // Debug unit reset +input mem_burst; // Burst on going +input mem_burst_end; // End TX/RX burst +input mem_burst_rd; // Start TX burst +input mem_burst_wr; // Start RX burst +input mem_bw; // Burst byte width + + +//============================================================================= +// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING +//============================================================================= + +// Synchronize SCL/SDA inputs +//-------------------------------- + +wire scl_sync_n; +omsp_sync_cell sync_cell_i2c_scl ( + .data_out (scl_sync_n), + .data_in (~dbg_i2c_scl), + .clk (dbg_clk), + .rst (dbg_rst) +); +wire scl_sync = ~scl_sync_n; + +wire sda_in_sync_n; +omsp_sync_cell sync_cell_i2c_sda ( + .data_out (sda_in_sync_n), + .data_in (~dbg_i2c_sda_in), + .clk (dbg_clk), + .rst (dbg_rst) +); +wire sda_in_sync = ~sda_in_sync_n; + + +// SCL/SDA input buffers +//-------------------------------- + +reg [1:0] scl_buf; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) scl_buf <= 2'h3; + else scl_buf <= {scl_buf[0], scl_sync}; + +reg [1:0] sda_in_buf; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) sda_in_buf <= 2'h3; + else sda_in_buf <= {sda_in_buf[0], sda_in_sync}; + + +// SCL/SDA Majority decision +//------------------------------ + +wire scl = (scl_sync & scl_buf[0]) | + (scl_sync & scl_buf[1]) | + (scl_buf[0] & scl_buf[1]); + +wire sda_in = (sda_in_sync & sda_in_buf[0]) | + (sda_in_sync & sda_in_buf[1]) | + (sda_in_buf[0] & sda_in_buf[1]); + + +// SCL/SDA Edge detection +//------------------------------ + +// SDA Edge detection +reg sda_in_dly; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) sda_in_dly <= 1'b1; + else sda_in_dly <= sda_in; + +wire sda_in_fe = sda_in_dly & ~sda_in; +wire sda_in_re = ~sda_in_dly & sda_in; +wire sda_in_edge = sda_in_dly ^ sda_in; + +// SCL Edge detection +reg scl_dly; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) scl_dly <= 1'b1; + else scl_dly <= scl; + +wire scl_fe = scl_dly & ~scl; +wire scl_re = ~scl_dly & scl; +wire scl_edge = scl_dly ^ scl; + + +// Delayed SCL Rising-Edge for SDA data sampling +reg [1:0] scl_re_dly; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) scl_re_dly <= 2'b00; + else scl_re_dly <= {scl_re_dly[0], scl_re}; + +wire scl_sample = scl_re_dly[1]; + + +//============================================================================= +// 2) I2C START & STOP CONDITION DETECTION +//============================================================================= + +//----------------- +// Start condition +//----------------- + +wire start_detect = sda_in_fe & scl; + +//----------------- +// Stop condition +//----------------- + + wire stop_detect = sda_in_re & scl; + +//----------------- +// I2C Slave Active +//----------------- +// The I2C logic will be activated whenever a start condition +// is detected and will be disactivated if the slave address +// doesn't match or if a stop condition is detected. + +wire i2c_addr_not_valid; + +reg i2c_active_seq; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) i2c_active_seq <= 1'b0; + else if (start_detect) i2c_active_seq <= 1'b1; + else if (stop_detect || i2c_addr_not_valid) i2c_active_seq <= 1'b0; + +wire i2c_active = i2c_active_seq & ~stop_detect; +wire i2c_init = ~i2c_active | start_detect; + + +//============================================================================= +// 3) I2C STATE MACHINE +//============================================================================= + +// State register/wires +reg [2:0] i2c_state; +reg [2:0] i2c_state_nxt; + +// Utility signals +reg [8:0] shift_buf; +wire shift_rx_done; +wire shift_tx_done; +reg dbg_rd; + +// State machine definition +parameter RX_ADDR = 3'h0; +parameter RX_ADDR_ACK = 3'h1; +parameter RX_DATA = 3'h2; +parameter RX_DATA_ACK = 3'h3; +parameter TX_DATA = 3'h4; +parameter TX_DATA_ACK = 3'h5; + +// State transition +always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in) + case (i2c_state) + RX_ADDR : i2c_state_nxt = i2c_init ? RX_ADDR : + ~shift_rx_done ? RX_ADDR : + i2c_addr_not_valid ? RX_ADDR : + RX_ADDR_ACK; + + RX_ADDR_ACK : i2c_state_nxt = i2c_init ? RX_ADDR : + ~scl_fe ? RX_ADDR_ACK : + shift_buf[0] ? TX_DATA : + RX_DATA; + + RX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR : + ~shift_rx_done ? RX_DATA : + RX_DATA_ACK; + + RX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR : + ~scl_fe ? RX_DATA_ACK : + RX_DATA; + + TX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR : + ~shift_tx_done ? TX_DATA : + TX_DATA_ACK; + + TX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR : + ~scl_fe ? TX_DATA_ACK : + ~sda_in ? TX_DATA : + RX_ADDR; + // pragma coverage off + default : i2c_state_nxt = RX_ADDR; + // pragma coverage on + endcase + +// State machine +always @(posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) i2c_state <= RX_ADDR; + else i2c_state <= i2c_state_nxt; + + +//============================================================================= +// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING) +//============================================================================= + +wire shift_rx_en = ((i2c_state==RX_ADDR) | (i2c_state ==RX_DATA) | (i2c_state ==RX_DATA_ACK)); +wire shift_tx_en = (i2c_state ==TX_DATA) | (i2c_state ==TX_DATA_ACK); +wire shift_tx_en_pre = (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK); + +assign shift_rx_done = shift_rx_en & scl_fe & shift_buf[8]; +assign shift_tx_done = shift_tx_en & scl_fe & (shift_buf==9'h100); + +wire shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) | + ((i2c_state==RX_DATA_ACK) & scl_fe); +wire shift_buf_rx_en = shift_rx_en & scl_sample; + +wire shift_buf_tx_init = ((i2c_state==RX_ADDR_ACK) & scl_re & shift_buf[0]) | + ((i2c_state==TX_DATA_ACK) & scl_re); +wire shift_buf_tx_en = shift_tx_en_pre & scl_fe & (shift_buf!=9'h100); + +wire [7:0] shift_tx_val; + +wire [8:0] shift_buf_nxt = shift_buf_rx_init ? 9'h001 : // RX Init + shift_buf_tx_init ? {shift_tx_val, 1'b1} : // TX Init + shift_buf_rx_en ? {shift_buf[7:0], sda_in} : // RX Shift + shift_buf_tx_en ? {shift_buf[7:0], 1'b0} : // TX Shift + shift_buf[8:0]; // Hold + +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) shift_buf <= 9'h001; + else shift_buf <= shift_buf_nxt; + +// Detect when the received I2C device address is not valid +assign i2c_addr_not_valid = (i2c_state == RX_ADDR) && shift_rx_done && ( +`ifdef DBG_I2C_BROADCAST + (shift_buf[7:1] != dbg_i2c_broadcast[6:0]) && +`endif + (shift_buf[7:1] != dbg_i2c_addr[6:0])); + +// Utility signals +wire shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA); +wire shift_tx_data_done = shift_tx_done; + + +//============================================================================= +// 5) I2C TRANSMIT BUFFER +//============================================================================= + +reg dbg_i2c_sda_out; + +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_i2c_sda_out <= 1'b1; + else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) || + (i2c_state_nxt==RX_DATA_ACK) || + (shift_buf_tx_en & ~shift_buf[8])); + + +//============================================================================= +// 6) DEBUG INTERFACE STATE MACHINE +//============================================================================= + +// State register/wires +reg [2:0] dbg_state; +reg [2:0] dbg_state_nxt; + +// Utility signals +reg dbg_bw; + +// State machine definition +parameter RX_CMD = 3'h0; +parameter RX_BYTE_LO = 3'h1; +parameter RX_BYTE_HI = 3'h2; +parameter TX_BYTE_LO = 3'h3; +parameter TX_BYTE_HI = 3'h4; + +// State transition +always @(dbg_state or shift_rx_data_done or shift_tx_data_done or shift_buf or dbg_bw or + mem_burst_wr or mem_burst_rd or mem_burst or mem_burst_end or mem_bw) + case (dbg_state) + RX_CMD : dbg_state_nxt = mem_burst_wr ? RX_BYTE_LO : + mem_burst_rd ? TX_BYTE_LO : + ~shift_rx_data_done ? RX_CMD : + shift_buf[7] ? RX_BYTE_LO : + TX_BYTE_LO; + + RX_BYTE_LO : dbg_state_nxt = (mem_burst & mem_burst_end) ? RX_CMD : + ~shift_rx_data_done ? RX_BYTE_LO : + (mem_burst & ~mem_burst_end) ? + (mem_bw ? RX_BYTE_LO : + RX_BYTE_HI) : + dbg_bw ? RX_CMD : + RX_BYTE_HI; + + RX_BYTE_HI : dbg_state_nxt = ~shift_rx_data_done ? RX_BYTE_HI : + (mem_burst & ~mem_burst_end) ? RX_BYTE_LO : + RX_CMD; + + TX_BYTE_LO : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_LO : + ( mem_burst & mem_bw) ? TX_BYTE_LO : + ( mem_burst & ~mem_bw) ? TX_BYTE_HI : + ~dbg_bw ? TX_BYTE_HI : + RX_CMD; + + TX_BYTE_HI : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_HI : + mem_burst ? TX_BYTE_LO : + RX_CMD; + + // pragma coverage off + default : dbg_state_nxt = RX_CMD; + // pragma coverage on + endcase + +// State machine +always @(posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_state <= RX_CMD; + else dbg_state <= dbg_state_nxt; + +// Utility signals +wire cmd_valid = (dbg_state==RX_CMD) & shift_rx_data_done; +wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done; +wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done; + + +//============================================================================= +// 7) REGISTER READ/WRITE ACCESS +//============================================================================= + +parameter MEM_DATA = 6'h06; + +// Debug register address & bit width +reg [5:0] dbg_addr; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) + begin + dbg_bw <= 1'b0; + dbg_addr <= 6'h00; + end + else if (cmd_valid) + begin + dbg_bw <= shift_buf[6]; + dbg_addr <= shift_buf[5:0]; + end + else if (mem_burst) + begin + dbg_bw <= mem_bw; + dbg_addr <= MEM_DATA; + end + + +// Debug register data input +reg [7:0] dbg_din_lo; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_din_lo <= 8'h00; + else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0]; + +reg [7:0] dbg_din_hi; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_din_hi <= 8'h00; + else if (rx_lo_valid) dbg_din_hi <= 8'h00; + else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0]; + +assign dbg_din = {dbg_din_hi, dbg_din_lo}; + + +// Debug register data write command +reg dbg_wr; +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_wr <= 1'b0; + else dbg_wr <= (mem_burst & mem_bw) ? rx_lo_valid : + (mem_burst & ~mem_bw) ? rx_hi_valid : + dbg_bw ? rx_lo_valid : + rx_hi_valid; + + +// Debug register data read command +always @ (posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) dbg_rd <= 1'b0; + else dbg_rd <= (mem_burst & mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) : + (mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) : + cmd_valid ? ~shift_buf[7] : + 1'b0; + + +// Debug register data read value +assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] : + dbg_dout[7:0]; + +endmodule

rtl/verilog/omsp_dbg_i2c.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: rtl/verilog/omsp_sfr.v =================================================================== --- rtl/verilog/omsp_sfr.v (revision 151) +++ rtl/verilog/omsp_sfr.v (revision 154) @@ -58,6 +58,8 @@ wdtifg_sw_set, // Watchdog-timer interrupt flag software set // INPUTs + cpu_nr_inst, // Current oMSP instance number + cpu_nr_total, // Total number of oMSP instances-1 mclk, // Main system clock nmi, // Non-maskable interrupt (asynchronous) nmi_acc, // Non-Maskable interrupt request accepted @@ -83,6 +85,8 @@ // INPUTs //========= +input [7:0] cpu_nr_inst; // Current oMSP instance number +input [7:0] cpu_nr_total; // Total number of oMSP instances-1 input mclk; // Main system clock input nmi; // Non-maskable interrupt (asynchronous) input nmi_acc; // Non-Maskable interrupt request accepted @@ -104,13 +108,14 @@ parameter [14:0] BASE_ADDR = 15'h0000; // Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 3; +parameter DEC_WD = 4; // Register addresses offset parameter [DEC_WD-1:0] IE1 = 'h0, IFG1 = 'h2, CPU_ID_LO = 'h4, - CPU_ID_HI = 'h6; + CPU_ID_HI = 'h6, + CPU_NR = 'h8; // Register one-hot decoder utilities parameter DEC_SZ = (1 << DEC_WD); @@ -120,7 +125,8 @@ parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1), IFG1_D = (BASE_REG << IFG1), CPU_ID_LO_D = (BASE_REG << CPU_ID_LO), - CPU_ID_HI_D = (BASE_REG << CPU_ID_HI); + CPU_ID_HI_D = (BASE_REG << CPU_ID_HI), + CPU_NR_D = (BASE_REG << CPU_NR); //============================================================================ @@ -137,7 +143,8 @@ wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) | (IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}) | (CPU_ID_LO_D & {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}}) | - (CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}}); + (CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}}) | + (CPU_NR_D & {DEC_SZ{(reg_addr==(CPU_NR >>1))}}); // Read/Write probes wire reg_lo_write = per_we[0] & reg_sel; @@ -248,6 +255,17 @@ cpu_version}; +// CPU_NR Register (READ ONLY) +//----------------------------- +// ------------------------------------------------------------------- +// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 | +// |---------------------------------+---------------------------------| +// | CPU_TOTAL_NR | CPU_INST_NR | +// ------------------------------------------------------------------- + +wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst}; + + //============================================================================ // 4) DATA OUTPUT GENERATION //============================================================================ @@ -257,11 +275,13 @@ wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}}); wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}}; wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}}; +wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}}; wire [15:0] per_dout = ie1_rd | ifg1_rd | cpu_id_lo_rd | - cpu_id_hi_rd; + cpu_id_hi_rd | + cpu_nr_rd; //=============================================================================

/rtl/verilog/omsp_dbg.v

/rtl/verilog/openMSP430_defines.v

/rtl/verilog/openMSP430.v

/rtl/verilog/openMSP430_undefines.v

/sim/rtl_sim/run/run_all

/sim/rtl_sim/run

sim/rtl_sim/run Property changes : Modified: svn:ignore ## -1,5 +1,5 ## *.log -pmem.* +pmem* stimulus.v *.vcd simv Index: sim/rtl_sim/src/dbg_rdwr.s43 =================================================================== --- sim/rtl_sim/src/dbg_rdwr.s43 (revision 151) +++ sim/rtl_sim/src/dbg_rdwr.s43 (nonexistent) @@ -1,87 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE: RD / WR */ -/*---------------------------------------------------------------------------*/ -/* Test the UART debug interface: */ -/* - Check RD/WR access to all adressable */ -/* debug registers. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 19 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - - - mov #0x0300, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_rdwr.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_onoff.s43 =================================================================== --- sim/rtl_sim/src/dbg_onoff.s43 (revision 151) +++ sim/rtl_sim/src/dbg_onoff.s43 (nonexistent) @@ -1,87 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 19 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - -main: - mov #DMEM_250, r1 ; Initialize stack - mov #0x0000, r15 - mov #0x0000, r14 - mov #0x0000, r13 - nop - eint - -test_loop: - add #0x0001, r14 - cmp #0xffff, r13 - jne test_loop - - mov #0x1000, r15 - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - -isr_1: - mov #0xffff, r13 - reti - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word isr_1 ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_onoff.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_mem.s43 =================================================================== --- sim/rtl_sim/src/dbg_mem.s43 (revision 151) +++ sim/rtl_sim/src/dbg_mem.s43 (nonexistent) @@ -1,93 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Memory RD/WR features. */ -/* */ -/* Note: The burst features are specific to the selected interface */ -/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - -WAIT_FUNC: - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - - mov #0x1122, &DMEM_210 - mov #0x3344, &DMEM_212 - - mov #0xaaaa, r5 - mov #0xbbbb, r6 - - mov #0x1200, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - /* ---------------------- SOME VARIABLES IN ROM --------------- */ -diverse_data: - .word 0x5ab7 - .word 0x6bc8 - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_mem.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_halt_irq.s43 =================================================================== --- sim/rtl_sim/src/dbg_halt_irq.s43 (revision 151) +++ sim/rtl_sim/src/dbg_halt_irq.s43 (nonexistent) @@ -1,99 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* SERIAL DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the serial debug interface: */ -/* - Interrupts when going out of halt mode. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 19 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - -main: - ; Disable interrupts - dint - mov.b #0x00, &P1IE - - - /* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */ - - mov #DMEM_250, r1 ; Initialize stack - - mov.b #0x0001, &P1IE ; Enable GPIO interrupt - - eint ; Enable Global interrupts - - mov #0x0000, r13; - mov #0x0000, r14; - mov #DMEM_200, r15; -infinite_loop: - inc r13 - bit #0x0002, &P1IN - jz infinite_loop - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT ROUTINES --------------- */ - -PORT1_VECTOR: - mov.b &P1IFG, 0(r15) - mov.b #0x00, &P1IFG - mov #0xaaaa, r14; - reti - - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word PORT1_VECTOR ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_halt_irq.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_cpu.v =================================================================== --- sim/rtl_sim/src/dbg_cpu.v (revision 151) +++ sim/rtl_sim/src/dbg_cpu.v (nonexistent) @@ -1,214 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - - - integer my_test; - integer test_var; - - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - - // STOP, FREEZE, ISTEP, RUN - //-------------------------------------------------------- - - dbg_uart_wr(CPU_STAT, 16'h00ff); // HALT - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 ====="); - - dbg_uart_wr(CPU_CTL, 16'h0001); // HALT - repeat(10) @(posedge mclk); - test_var = inst_number; - repeat(50) @(posedge mclk); - if (test_var !== inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function ====="); - - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0001) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 ====="); - - if (dbg_freeze !== 1'b0) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 ====="); - dbg_uart_wr(CPU_CTL, 16'h0010); // FREEZE WITH BREAK - repeat(10) @(posedge mclk); - if (dbg_freeze !== 1'b1) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 ====="); - - - test_var = r14; - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - repeat(12) @(posedge mclk); - if (test_var !== (r14+1)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 ====="); - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - repeat(12) @(posedge mclk); - if (test_var !== (r14+2)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 ====="); - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP - repeat(12) @(posedge mclk); - if (test_var !== (r14+3)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 ====="); - - - test_var = inst_number; - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - repeat(50) @(posedge mclk); - if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 ====="); - test_var = inst_number; - repeat(50) @(posedge mclk); - if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 ====="); - - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 ====="); - - - - // RESET / BREAK ON RESET - //-------------------------------------------------------- - - test_var = r14; - dbg_uart_wr(CPU_CTL, 16'h0040); // RESET CPU - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 ====="); - if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 ====="); - dbg_uart_wr(CPU_CTL, 16'h0000); // RELEASE RESET - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 ====="); - if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 ====="); - if (test_var >= r14) tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 ====="); - dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 ====="); - - - test_var = r14; - dbg_uart_wr(CPU_CTL, 16'h0060); // RESET & BREAK ON RESET - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 ====="); - if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 ====="); - dbg_uart_wr(CPU_CTL, 16'h0020); // RELEASE RESET - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0005) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 ====="); - if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 ====="); - repeat(10) @(posedge mclk); - test_var = inst_number; - repeat(50) @(posedge mclk); - if (test_var !== inst_number) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 ====="); - if (r0 !== irq_vect_15) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 ====="); - - dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0001) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 ====="); - - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 ====="); - - - // SOFTWARE BREAKPOINT - //-------------------------------------------------------- - - dbg_uart_wr(CPU_CTL, 16'h0048); // RESET & ENABLE SOFTWARE BREAKPOINT - dbg_uart_wr(CPU_CTL, 16'h0008); // RELEASE RESET - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h000D) tb_error("====== SOFTWARE BREAKPOINT: test 1 ====="); - if (r0 !== ('h10000-`PMEM_SIZE+'h12)) tb_error("====== SOFTWARE BREAKPOINT: test 2 ====="); - dbg_uart_wr(CPU_STAT, 16'h000C); // CLEAR STATUS - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 3 ====="); - - // Replace software breakpoint with a mov #2, r15 (opcode=0x432f) - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12)); - dbg_uart_wr(MEM_DATA, 16'h432f); - dbg_uart_wr(MEM_CTL, 16'h0003); - - // Dummy write - dbg_uart_wr(MEM_ADDR, 16'hff00); - dbg_uart_wr(MEM_DATA, 16'h1234); - dbg_uart_wr(MEM_CTL, 16'h0003); - - // RUN - dbg_uart_wr(CPU_CTL, 16'h000A); - repeat(20) @(posedge mclk); - if (r15 !== 16'h0002) tb_error("====== SOFTWARE BREAKPOINT: test 4 ====="); - - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0009) tb_error("====== SOFTWARE BREAKPOINT: test 5 ====="); - if (r0 !== ('h10000-`PMEM_SIZE+'h16)) tb_error("====== SOFTWARE BREAKPOINT: test 6 ====="); - dbg_uart_wr(CPU_STAT, 16'h0008); // CLEAR STATUS - dbg_uart_rd(CPU_STAT); // READ STATUS - if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 7 ====="); - - - // Replace software breakpoint with a mov #4, r15 (opcode=0x422f) - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16)); - dbg_uart_wr(MEM_DATA, 16'h422f); - dbg_uart_wr(MEM_CTL, 16'h0003); - - // Dummy write - dbg_uart_wr(MEM_ADDR, 16'hff00); - dbg_uart_wr(MEM_DATA, 16'h5678); - dbg_uart_wr(MEM_CTL, 16'h0003); - - // RUN - dbg_uart_wr(CPU_CTL, 16'h000A); - repeat(20) @(posedge mclk); - if (r15 !== 16'h0004) tb_error("====== SOFTWARE BREAKPOINT: test 8 ====="); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_cpu.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_onoff.v =================================================================== --- sim/rtl_sim/src/dbg_onoff.v (revision 151) +++ sim/rtl_sim/src/dbg_onoff.v (nonexistent) @@ -1,218 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 95 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ -/*===========================================================================*/ - - - integer test_nr; - integer test_var; - - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN - `ifdef ASIC - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (this test is not supported in ASIC mode) |"); - $display(" ==============================================="); - $finish; - `else - test_nr = 0; - #1 dbg_en = 0; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // Make sure the CPU always starts executing when the - // debug interface is disabled during POR. - //-------------------------------------------------------- - dbg_en = 0; - test_nr = 1; - - repeat(300) @(posedge mclk); - if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); - test_var = r14; - - - // Make sure that enabling the debug interface after the POR - // don't stop the cpu - //-------------------------------------------------------- - dbg_en = 1; - test_nr = 2; - - repeat(300) @(posedge mclk); - if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 ====="); - - - // Create POR with debug enable and observe the - // behavior depending on the DBG_RST_BRK_EN define - //-------------------------------------------------------- - dbg_en = 1; - test_nr = 3; - - @(posedge mclk); // Generate POR - reset_n = 1'b0; - @(posedge mclk); - reset_n = 1'b1; - - repeat(300) @(posedge mclk); -`ifdef DBG_RST_BRK_EN - if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); -`else - if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); -`endif - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); -`ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); -`else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); -`endif - - - // Make sure that DBG_EN resets the debug interface - //-------------------------------------------------------- - test_nr = 4; - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - repeat(300) @(posedge mclk); - dbg_uart_wr(CPU_CTL, 16'h0000); - dbg_uart_wr(MEM_DATA, 16'haa55); - dbg_uart_rd(CPU_CTL); - if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); - - - test_var = r14; // Backup the current register value - - - @(posedge mclk); // Resets the debug interface - dbg_en = 1'b0; - repeat(2) @(posedge mclk); - dbg_en = 1'b1; - - // Make sure that the register was not reseted - if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); - repeat(2) @(posedge mclk); - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); -`ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); -`else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); -`endif - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); - - - // Make sure that RESET_N resets the debug interface - //-------------------------------------------------------- - test_nr = 5; - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - repeat(300) @(posedge mclk); - dbg_uart_wr(CPU_CTL, 16'h0000); - dbg_uart_wr(MEM_DATA, 16'haa55); - dbg_uart_rd(CPU_CTL); - if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); - - test_nr = 6; - - @(posedge mclk); // Generates POR - reset_n = 1'b0; - repeat(2) @(posedge mclk); - reset_n = 1'b1; - - // Make sure that the register was reseted - if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); - repeat(2) @(posedge mclk); - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - test_nr = 7; - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); -`ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); -`else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); -`endif - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); - - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - test_nr = 8; - - // Generate IRQ to terminate the test pattern - irq[1] = 1'b1; - @(r13); - irq[1] = 1'b0; - - stimulus_done = 1; - - `endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_onoff.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_halt_irq.v =================================================================== --- sim/rtl_sim/src/dbg_halt_irq.v (revision 151) +++ sim/rtl_sim/src/dbg_halt_irq.v (nonexistent) @@ -1,92 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* SERIAL DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the serial debug interface: */ -/* - Interrupts when going out of halt mode. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 19 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ -/*===========================================================================*/ - -reg [15:0] r13_bkup; - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // Initialize the debug interface and send the CPU in halt mode - dbg_uart_tx(DBG_SYNC); - -`ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN -`endif - - // Wait until software initialization is done - if (r15!==(`PER_SIZE+16'h0000)) - @(r15==(`PER_SIZE+16'h0000)); - - - dbg_uart_wr(CPU_CTL, 16'h0001); // HALT - repeat(150) @(posedge mclk); - r13_bkup = r13; - - // Generate a GPIO interrupt - p1_din[0] = 1'b1; - repeat(150) @(posedge mclk); - - // Re-start the CPU - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - repeat(150) @(posedge mclk); - - // Make sure the interrupt was serviced - if (r14 !== 16'haaaa) tb_error("====== Interrupt was not properly serviced ====="); - - // Make sure the program resumed execution when coming back from IRQ - if (r13 === r13_bkup) tb_error("====== Program didn't properly resumed execution ====="); - - - p1_din[1] = 1'b1; - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_halt_irq.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk0.s43 =================================================================== --- sim/rtl_sim/src/dbg_hwbrk0.s43 (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk0.s43 (nonexistent) @@ -1,100 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 0. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - inc &DMEM_206 - inc &DMEM_202 - inc &DMEM_204 - inc &DMEM_200 - inc &DMEM_208 - mov &DMEM_204, r10 - mov &DMEM_208, r9 - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - - /* -------------- ACLK GENERATION ----------------- */ - - mov #0x0001, r15 - mov #0x0000, &DMEM_200 - mov #0x0001, &DMEM_202 - mov #0x0002, &DMEM_204 - mov #0x0003, &DMEM_206 - mov #0x0004, &DMEM_208 - mov #0x0080, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_hwbrk0.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk1.s43 =================================================================== --- sim/rtl_sim/src/dbg_hwbrk1.s43 (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk1.s43 (nonexistent) @@ -1,100 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later versixon. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 1. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - inc &DMEM_206 - inc &DMEM_202 - inc &DMEM_204 - inc &DMEM_200 - inc &DMEM_208 - mov &DMEM_204, r10 - mov &DMEM_208, r9 - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - - /* -------------- ACLK GENERATION ----------------- */ - - mov #0x0001, r15 - mov #0x0000, &DMEM_200 - mov #0x0001, &DMEM_202 - mov #0x0002, &DMEM_204 - mov #0x0003, &DMEM_206 - mov #0x0004, &DMEM_208 - mov #0x0080, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_hwbrk1.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk2.s43 =================================================================== --- sim/rtl_sim/src/dbg_hwbrk2.s43 (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk2.s43 (nonexistent) @@ -1,100 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later versixon. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 2. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - inc &DMEM_206 - inc &DMEM_202 - inc &DMEM_204 - inc &DMEM_200 - inc &DMEM_208 - mov &DMEM_204, r10 - mov &DMEM_208, r9 - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - - /* -------------- ACLK GENERATION ----------------- */ - - mov #0x0001, r15 - mov #0x0000, &DMEM_200 - mov #0x0001, &DMEM_202 - mov #0x0002, &DMEM_204 - mov #0x0003, &DMEM_206 - mov #0x0004, &DMEM_208 - mov #0x0080, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_hwbrk2.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk3.s43 =================================================================== --- sim/rtl_sim/src/dbg_hwbrk3.s43 (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk3.s43 (nonexistent) @@ -1,100 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later versixon. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 3. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - inc &DMEM_206 - inc &DMEM_202 - inc &DMEM_204 - inc &DMEM_200 - inc &DMEM_208 - mov &DMEM_204, r10 - mov &DMEM_208, r9 - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - - /* -------------- ACLK GENERATION ----------------- */ - - mov #0x0001, r15 - mov #0x0000, &DMEM_200 - mov #0x0001, &DMEM_202 - mov #0x0002, &DMEM_204 - mov #0x0003, &DMEM_206 - mov #0x0004, &DMEM_208 - mov #0x0080, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_hwbrk3.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_rdwr.v =================================================================== --- sim/rtl_sim/src/dbg_rdwr.v (revision 151) +++ sim/rtl_sim/src/dbg_rdwr.v (nonexistent) @@ -1,203 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE: RD / WR */ -/*---------------------------------------------------------------------------*/ -/* Test the UART debug interface: */ -/* - Check RD/WR access to all adressable */ -/* debug registers. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 95 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -reg [2:0] cpu_version; -reg cpu_asic; -reg [4:0] user_version; -reg [6:0] per_space; -reg mpy_info; -reg [8:0] dmem_size; -reg [5:0] pmem_size; -reg [31:0] dbg_id; - -integer ii; - - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN -`ifdef DBG_UART - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - // STOP CPU - dbg_uart_wr(CPU_CTL , 16'h0001); - - // TEST READ/WR TO ALL DEBUG REGISTERS - //-------------------------------------------------------- - - cpu_version = `CPU_VERSION; -`ifdef ASIC - cpu_asic = 1'b1; -`else - cpu_asic = 1'b0; -`endif - user_version = `USER_VERSION; - per_space = (`PER_SIZE >> 9); -`ifdef MULTIPLIER - mpy_info = 1'b1; -`else - mpy_info = 1'b0; -`endif - dmem_size = (`DMEM_SIZE >> 7); - pmem_size = (`PMEM_SIZE >> 10); - - dbg_id = {pmem_size, - dmem_size, - mpy_info, - per_space, - user_version, - cpu_asic, - cpu_version}; - - // Check reset value - for ( ii=0; ii < 64; ii=ii+1) - begin - dbg_uart_rd(ii[7:0]); - - case(ii) - 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 1 ERROR (CPU_ID_LO)"); - 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)"); - 2 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)"); - 3 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)"); - default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR"); - endcase - end - - // Write access - for ( ii=0; ii < 64; ii=ii+1) - begin - // Skip write for MEM_CNT - if (ii!=7) - dbg_uart_wr(ii[7:0] , 16'hffff); - end - - // Read value back - for ( ii=0; ii < 64; ii=ii+1) - begin - dbg_uart_rd(ii[7:0]); - - case(ii) - 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 2 ERROR (CPU_ID_LO)"); - 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)"); - 2 : if (dbg_uart_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)"); - 3 : if ((dbg_uart_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)"); - 4 : if (dbg_uart_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)"); - 5 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)"); - 6 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)"); - 7 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)"); -`ifdef DBG_HWBRK_0 - `ifdef DBG_HWBRK_RANGE - 8 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)"); - 9 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)"); - `else - 8 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)"); - 9 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)"); - `endif - 10 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)"); - 11 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)"); -`endif -`ifdef DBG_HWBRK_1 - `ifdef DBG_HWBRK_RANGE - 12 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)"); - 13 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)"); - `else - 12 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)"); - 13 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)"); - `endif - 14 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)"); - 15 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)"); -`endif -`ifdef DBG_HWBRK_2 - `ifdef DBG_HWBRK_RANGE - 16 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)"); - 17 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)"); - `else - 16 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)"); - 17 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)"); - `endif - 18 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)"); - 19 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)"); -`endif -`ifdef DBG_HWBRK_3 - `ifdef DBG_HWBRK_RANGE - 20 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)"); - 21 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)"); - `else - 20 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)"); - 21 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)"); - `endif - 22 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)"); - 23 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)"); -`endif - default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR"); - endcase - end - - - dbg_uart_wr(CPU_CTL , 16'h0002); - repeat(10) @(posedge mclk); - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface UART not included) |"); - $display(" ==============================================="); - $finish; -`endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_rdwr.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk0.v =================================================================== --- sim/rtl_sim/src/dbg_hwbrk0.v (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk0.v (nonexistent) @@ -1,670 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 0. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN -`ifdef DBG_HWBRK_0 - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - //---------------------------------------------------------------------- - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - - // CONFIGURE BREAKPOINT (DISABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK0_CTL, 16'h000C); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CHECK - if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK0_CTL, 16'h000D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); - - // RE-RUN - dbg_uart_wr(BRK0_ADDR0, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); - - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - //---------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CONFIGURE BREAKPOINT(ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE-'h100)); - dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h20)); - dbg_uart_wr(BRK0_CTL, 16'h001D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ - //---------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK0_CTL, 16'h0005); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); - if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE - //----------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK0_CTL, 16'h0006); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE - //---------------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK0_CTL, 16'h0007); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ - //---------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK0_CTL, 16'h0015); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); - if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE - //----------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK0_CTL, 16'h0016); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE - //---------------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK0_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK0_CTL, 16'h0017); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK0_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK0_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); - - end - - // RE-RUN UNTIL END OF PATTERN - dbg_uart_wr(BRK0_CTL, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (hardware breakpoint unit 0 not included) |"); - $display(" ==============================================="); - $finish; -`endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_hwbrk0.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk1.v =================================================================== --- sim/rtl_sim/src/dbg_hwbrk1.v (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk1.v (nonexistent) @@ -1,669 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 1. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN -`ifdef DBG_HWBRK_1 - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - //---------------------------------------------------------------------- - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - - // CONFIGURE BREAKPOINT (DISABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK1_CTL, 16'h000C); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CHECK - if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK1_CTL, 16'h000D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); - - // RE-RUN - dbg_uart_wr(BRK1_ADDR0, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); - - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - //---------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CONFIGURE BREAKPOINT(ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE-'h100)); - dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h20)); - dbg_uart_wr(BRK1_CTL, 16'h001D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ - //---------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK1_CTL, 16'h0005); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); - if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE - //----------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK1_CTL, 16'h0006); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE - //---------------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK1_CTL, 16'h0007); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ - //---------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK1_CTL, 16'h0015); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); - if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE - //----------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK1_CTL, 16'h0016); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); - end - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE - //---------------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK1_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK1_CTL, 16'h0017); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK1_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK1_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); - - end - - // RE-RUN UNTIL END OF PATTERN - dbg_uart_wr(BRK1_CTL, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (hardware breakpoint unit 1 not included) |"); - $display(" ==============================================="); - $finish; -`endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_hwbrk1.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk2.v =================================================================== --- sim/rtl_sim/src/dbg_hwbrk2.v (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk2.v (nonexistent) @@ -1,671 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 2. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN -`ifdef DBG_HWBRK_2 - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - //---------------------------------------------------------------------- - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - - // CONFIGURE BREAKPOINT (DISABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK2_CTL, 16'h000C); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CHECK - if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK2_CTL, 16'h000D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); - - // RE-RUN - dbg_uart_wr(BRK2_ADDR0, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); - - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - //---------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CONFIGURE BREAKPOINT(ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE-'h100)); - dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h20)); - dbg_uart_wr(BRK2_CTL, 16'h001D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ - //---------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK2_CTL, 16'h0005); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); - if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE - //----------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK2_CTL, 16'h0006); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE - //---------------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK2_CTL, 16'h0007); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ - //---------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK2_CTL, 16'h0015); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); - if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE - //----------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK2_CTL, 16'h0016); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE - //---------------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK2_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK2_CTL, 16'h0017); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK2_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK2_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); - - end - - // RE-RUN UNTIL END OF PATTERN - dbg_uart_wr(BRK2_CTL, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (hardware breakpoint unit 2 not included) |"); - $display(" ==============================================="); - $finish; -`endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_hwbrk2.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_hwbrk3.v =================================================================== --- sim/rtl_sim/src/dbg_hwbrk3.v (revision 151) +++ sim/rtl_sim/src/dbg_hwbrk3.v (nonexistent) @@ -1,670 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Hardware breakpoint unit 3. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN -`ifdef DBG_HWBRK_3 - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - //---------------------------------------------------------------------- - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - - // CONFIGURE BREAKPOINT (DISABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK3_CTL, 16'h000C); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RESET & BREAK - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CHECK - if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE+'h04)); - dbg_uart_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h18)); - dbg_uart_wr(BRK3_CTL, 16'h000D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); - - // RE-RUN - dbg_uart_wr(BRK3_ADDR0, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); - - - - // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - //---------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - // CONFIGURE BREAKPOINT(ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE-'h100)); - dbg_uart_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h20)); - dbg_uart_wr(BRK3_CTL, 16'h001D); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ - //---------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK3_CTL, 16'h0005); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); - if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE - //----------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK3_CTL, 16'h0006); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE - //---------------------------------------------------------------------------------- - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); - dbg_uart_wr(BRK3_CTL, 16'h0007); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0002); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0008); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0001); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0004); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ - //---------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK3_CTL, 16'h0015); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); - if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE - //----------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK3_CTL, 16'h0016); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); - end - - - // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE - //---------------------------------------------------------------------------------- - if (`HWBRK_RANGE) - begin - - // RESET, BREAK & CLEAR STATUS - dbg_uart_wr(CPU_CTL, 16'h0060); - dbg_uart_wr(CPU_CTL, 16'h0020); - dbg_uart_wr(BRK3_STAT, 16'h00ff); - dbg_uart_wr(CPU_STAT, 16'h00ff); - - - // CONFIGURE BREAKPOINT (ENABLED) & RUN - dbg_uart_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); - dbg_uart_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); - dbg_uart_wr(BRK3_CTL, 16'h0017); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); - if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); - if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); - if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0010); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); - - // RE-RUN - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - // RE-CHECK - if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); - if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); - dbg_uart_rd(BRK3_STAT); - if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); - dbg_uart_wr(BRK3_STAT, 16'h0020); - dbg_uart_rd(CPU_STAT); - if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); - - end - - // RE-RUN UNTIL END OF PATTERN - dbg_uart_wr(BRK3_CTL, 16'h0000); - dbg_uart_wr(CPU_CTL, 16'h0002); - repeat(100) @(posedge mclk); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (hardware breakpoint unit 3 not included) |"); - $display(" ==============================================="); - $finish; -`endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_hwbrk3.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_cpu.s43 =================================================================== --- sim/rtl_sim/src/dbg_cpu.s43 (revision 151) +++ sim/rtl_sim/src/dbg_cpu.s43 (nonexistent) @@ -1,93 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - - -WAIT_FUNC: - dec r14 - jnz WAIT_FUNC - ret - -main: - mov #DMEM_250, r1 ; # Initialize stack pointer - mov #0x0000, &DMEM_200 - mov #0x0000, r15 - nop - .word 0x4343 ; # Software BREAKPOINT -; nop.b - nop - .word 0x4343 ; # Software BREAKPOINT -; nop.b - - mov #2, r15 - mov #4, r15 - - mov #0x0400, r14 - call #WAIT_FUNC - - mov #0x1000, r15 - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word end_of_test ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_cpu.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_onoff_asic.v =================================================================== --- sim/rtl_sim/src/dbg_onoff_asic.v (revision 151) +++ sim/rtl_sim/src/dbg_onoff_asic.v (nonexistent) @@ -1,260 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 95 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ -/*===========================================================================*/ - - - integer test_nr; - integer test_var; - - integer dco_clk_counter; - always @ (negedge dco_clk) - dco_clk_counter <= dco_clk_counter+1; - - integer dbg_clk_counter; - always @ (negedge dbg_clk) - dbg_clk_counter <= dbg_clk_counter+1; - - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN - `ifdef ASIC - test_nr = 0; - #1 dbg_en = 0; - repeat(30) @(posedge dco_clk); - stimulus_done = 0; - - // Make sure the CPU always starts executing when the - // debug interface is disabled during POR. - // Also make sure that the debug interface clock is stopped - // and that it is under reset - //-------------------------------------------------------- - dbg_en = 0; - test_nr = 1; - - @(negedge dco_clk) dbg_clk_counter = 0; - - repeat(300) @(posedge dco_clk); - if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); - if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) ====="); - if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) ====="); - test_var = r14; - - - // Make sure that enabling the debug interface after the POR - // don't stop the cpu - // Also make sure that the debug interface clock is running - // and that its reset is released - //-------------------------------------------------------- - dbg_en = 1; - test_nr = 2; - - @(negedge dco_clk) dbg_clk_counter = 0; - - repeat(300) @(posedge dco_clk); - if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 ====="); - if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) ====="); - if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) ====="); - - - // Make sure that disabling the CPU with debug enabled - // will stop the CPU - // Also make sure that the debug interface clock is stopped - // and that it is NOT under reset - //-------------------------------------------------------- - cpu_en = 0; - dbg_en = 1; - test_nr = 3; - - #(6*50); - test_var = r14; - dbg_clk_counter = 0; - - #(300*50); - if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) ====="); - if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) ====="); - if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) ====="); - - cpu_en = 1; - repeat(6) @(negedge dco_clk); - - - // Create POR with debug enable and observe the - // behavior depending on the DBG_RST_BRK_EN define - //-------------------------------------------------------- - dbg_en = 1; - test_nr = 4; - - @(posedge dco_clk); // Generate POR - reset_n = 1'b0; - @(posedge dco_clk); - reset_n = 1'b1; - - repeat(300) @(posedge dco_clk); - `ifdef DBG_RST_BRK_EN - if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); - `else - if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); - `endif - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); - `ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); - `else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); - `endif - - - // Make sure that DBG_EN resets the debug interface - //-------------------------------------------------------- - test_nr = 5; - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - repeat(300) @(posedge dco_clk); - dbg_uart_wr(CPU_CTL, 16'h0000); - dbg_uart_wr(MEM_DATA, 16'haa55); - dbg_uart_rd(CPU_CTL); - if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); - - - test_var = r14; // Backup the current register value - - - @(posedge dco_clk); // Resets the debug interface - dbg_en = 1'b0; - repeat(2) @(posedge dco_clk); - dbg_en = 1'b1; - - // Make sure that the register was not reseted - if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); - repeat(2) @(posedge dco_clk); - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); - `ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); - `else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); - `endif - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); - - - // Make sure that RESET_N resets the debug interface - //-------------------------------------------------------- - test_nr = 6; - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - repeat(300) @(posedge dco_clk); - dbg_uart_wr(CPU_CTL, 16'h0000); - dbg_uart_wr(MEM_DATA, 16'haa55); - dbg_uart_rd(CPU_CTL); - if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); - - test_nr = 7; - - @(posedge dco_clk); // Generates POR - reset_n = 1'b0; - repeat(2) @(posedge dco_clk); - reset_n = 1'b1; - - // Make sure that the register was reseted - if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); - repeat(2) @(posedge dco_clk); - - // Send uart synchronization frame - dbg_uart_tx(DBG_SYNC); - - test_nr = 8; - - // Check CPU_CTL reset value - dbg_uart_rd(CPU_CTL); - `ifdef DBG_RST_BRK_EN - if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); - `else - if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); - `endif - dbg_uart_rd(MEM_DATA); - if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); - - - // Let the CPU run - dbg_uart_wr(CPU_CTL, 16'h0002); - - test_nr = 9; - - // Generate IRQ to terminate the test pattern - irq[1] = 1'b1; - @(r13); - irq[1] = 1'b0; - - stimulus_done = 1; - - `else - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (this test is not supported in FPGA mode) |"); - $display(" ==============================================="); - $finish; - `endif -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_onoff_asic.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_mem.v =================================================================== --- sim/rtl_sim/src/dbg_mem.v (revision 151) +++ sim/rtl_sim/src/dbg_mem.v (nonexistent) @@ -1,274 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - Check Memory RD/WR features. */ -/* */ -/* Note: The burst features are specific to the selected interface */ -/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev$ */ -/* $LastChangedBy$ */ -/* $LastChangedDate$ */ -/*===========================================================================*/ - -`define LONG_TIMEOUT - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); -`ifdef DBG_EN - #1 dbg_en = 1; - repeat(30) @(posedge mclk); - stimulus_done = 0; - - // SEND UART SYNCHRONIZATION FRAME - dbg_uart_tx(DBG_SYNC); - - `ifdef DBG_RST_BRK_EN - dbg_uart_wr(CPU_CTL, 16'h0002); // RUN - `endif - - // RD/WR ACCESS: CPU REGISTERS (16b) - //-------------------------------------------------------- - - // READ CPU REGISTERS - dbg_uart_wr(MEM_ADDR, 16'h0005); // select register - dbg_uart_wr(MEM_CTL, 16'h0005); // read register - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'haaaa) tb_error("====== CPU REGISTERS (16b): Read R5 ====="); - dbg_uart_wr(MEM_ADDR, 16'h0006); // select register - dbg_uart_wr(MEM_CTL, 16'h0005); // read register - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'hbbbb) tb_error("====== CPU REGISTERS (16b): Read R6 ====="); - - // WRITE CPU REGISTERS - dbg_uart_wr(MEM_ADDR, 16'h0005); // select register - dbg_uart_wr(MEM_DATA, 16'hed32); // write data - dbg_uart_wr(MEM_CTL, 16'h0007); // write register - repeat(20) @(posedge mclk); - if (r5 !== 16'hed32) tb_error("====== CPU REGISTERS (16b): Write R5 ====="); - dbg_uart_wr(MEM_ADDR, 16'h0006); // select register - dbg_uart_wr(MEM_DATA, 16'hcb54); // write data - dbg_uart_wr(MEM_CTL, 16'h0007); // write register - repeat(20) @(posedge mclk); - if (r6 !== 16'hcb54) tb_error("====== CPU REGISTERS (16b): Write R6 ====="); - - - // RD/WR ACCESS: RAM (16b) - //-------------------------------------------------------- - - // READ RAM - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h1122) tb_error("====== RAM (16b): Read @0x210 ====="); - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h3344) tb_error("====== RAM (16b): Read @0x212 ====="); - - // WRITE RAM - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address - dbg_uart_wr(MEM_DATA, 16'ha976); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write memory - repeat(20) @(posedge mclk); - if (mem210 !== 16'ha976) tb_error("====== RAM (16b): Write @0x210 ====="); - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select register - dbg_uart_wr(MEM_DATA, 16'h8798); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write register - repeat(20) @(posedge mclk); - if (mem212 !== 16'h8798) tb_error("====== RAM (16b): Write @0x212 ====="); - - - // RD/WR ACCESS: RAM (8b) - //-------------------------------------------------------- - - // READ RAM - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h0076) tb_error("====== RAM (8b): Read @0x210 ====="); - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h00a9) tb_error("====== RAM (8b): Read @0x211 ====="); - - // WRITE RAM - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address - dbg_uart_wr(MEM_DATA, 16'h14b3); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write memory - repeat(20) @(posedge mclk); - if (mem210 !== 16'ha9b3) tb_error("====== RAM (8b): Write @0x210 ====="); - dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select register - dbg_uart_wr(MEM_DATA, 16'h25c4); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write register - repeat(20) @(posedge mclk); - if (mem210 !== 16'hc4b3) tb_error("====== RAM (8b): Write @0x211 ====="); - - - // RD/WR ACCESS: ROM (16b) - //-------------------------------------------------------- - - // READ ROM - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h5ab7) tb_error("====== ROM (16b): Read @0xf82e ====="); - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h30)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h6bc8) tb_error("====== ROM (16b): Read @0xf830 ====="); - - // WRITE ROM - dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address - dbg_uart_wr(MEM_DATA, 16'h7cd9); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write memory - repeat(20) @(posedge mclk); - if (irq_vect_00 !== 16'h7cd9) tb_error("====== ROM (16b): Write @0xffe0 ====="); - dbg_uart_wr(MEM_ADDR, 16'hffe2); // select register - dbg_uart_wr(MEM_DATA, 16'h8dea); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write register - repeat(20) @(posedge mclk); - if (irq_vect_01 !== 16'h8dea) tb_error("====== ROM (16b): Write @0xffe2 ====="); - - - // RD/WR ACCESS: ROM (8b) - //-------------------------------------------------------- - - // READ ROM - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h00b7) tb_error("====== ROM (8b): Read @0xf82e ====="); - dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2f)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h005a) tb_error("====== ROM (8b): Read @0xf82f ====="); - - // WRITE ROM - dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address - dbg_uart_wr(MEM_DATA, 16'hb314); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write memory - repeat(20) @(posedge mclk); - if (irq_vect_00 !== 16'h7c14) tb_error("====== ROM (8b): Write @0xffe0 ====="); - dbg_uart_wr(MEM_ADDR, 16'hffe1); // select register - dbg_uart_wr(MEM_DATA, 16'hc425); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write register - repeat(20) @(posedge mclk); - if (irq_vect_00 !== 16'h2514) tb_error("====== ROM (8b): Write @0xffe1 ====="); - - - // RD/WR ACCESS: PERIPHERALS (16b) - //-------------------------------------------------------- - - // WRITE PERIPHERAL - dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address - dbg_uart_wr(MEM_DATA, 16'h9dc7); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write memory - repeat(20) @(posedge mclk); - if (timerA_0.tar !== 16'h9dc7) tb_error("====== Peripheral (16b): Write @0x0170 ====="); - dbg_uart_wr(MEM_ADDR, 16'h0172); // select register - dbg_uart_wr(MEM_DATA, 16'haed8); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write register - repeat(20) @(posedge mclk); - if (timerA_0.taccr0 !== 16'haed8) tb_error("====== Peripheral (16b): Write @0x0172 ====="); - dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address - dbg_uart_wr(MEM_DATA, 16'hdead); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write memory - repeat(20) @(posedge mclk); - if (template_periph_16b_0.cntrl2 !== 16'hdead) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0002) ====="); - dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address - dbg_uart_wr(MEM_DATA, 16'hbeef); // write data - dbg_uart_wr(MEM_CTL, 16'h0003); // write memory - repeat(20) @(posedge mclk); - if (template_periph_16b_0.cntrl4 !== 16'hbeef) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0006) ====="); - - // READ PERIPHERAL - dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h9dc7) tb_error("====== Peripheral (16b): Read @0x0170 ====="); - dbg_uart_wr(MEM_ADDR, 16'h0172); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'haed8) tb_error("====== Peripheral (16b): Read @0x0172 ====="); - dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - repeat(20) @(posedge mclk); - if (dbg_uart_buf !== 16'hdead) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0002) ====="); - dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0001); // read memory - dbg_uart_rd(MEM_DATA); // read data - repeat(20) @(posedge mclk); - if (dbg_uart_buf !== 16'hbeef) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0006) ====="); - - - // RD/WR ACCESS: PERIPHERAL (8b) - //-------------------------------------------------------- - - // WRITE PERIPHERAL - dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address - dbg_uart_wr(MEM_DATA, 16'hbfe9); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write memory - repeat(20) @(posedge mclk); - if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0022 - test 1 ====="); - if (gpio_0.p1ifg !== 8'h00) tb_error("====== Peripheral (8b): Write @0x0022 - test 2====="); - dbg_uart_wr(MEM_ADDR, 16'h0023); // select register - dbg_uart_wr(MEM_DATA, 16'hc0fa); // write data - dbg_uart_wr(MEM_CTL, 16'h000b); // write register - repeat(20) @(posedge mclk); - if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0023 - test 1 ====="); - if (gpio_0.p1ifg !== 8'hfa) tb_error("====== Peripheral (8b): Write @0x0023 - test 2====="); - - // READ PERIPHERAL - dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h00e9) tb_error("====== Peripheral (8b): Read @0x0022 ====="); - dbg_uart_wr(MEM_ADDR, 16'h0023); // select memory address - dbg_uart_wr(MEM_CTL, 16'h0009); // read memory - dbg_uart_rd(MEM_DATA); // read data - if (dbg_uart_buf !== 16'h00fa) tb_error("====== Peripheral (8b): Read @0x0023 ====="); - - - stimulus_done = 1; -`else - - $display(" ==============================================="); - $display("| SIMULATION SKIPPED |"); - $display("| (serial debug interface not included) |"); - $display(" ==============================================="); - $finish; -`endif - end -

sim/rtl_sim/src/dbg_mem.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_onoff_asic.s43 =================================================================== --- sim/rtl_sim/src/dbg_onoff_asic.s43 (revision 151) +++ sim/rtl_sim/src/dbg_onoff_asic.s43 (nonexistent) @@ -1,87 +0,0 @@ -/*===========================================================================*/ -/* Copyright (C) 2001 Authors */ -/* */ -/* This source file may be used and distributed without restriction provided */ -/* that this copyright statement is not removed from the file and that any */ -/* derivative work contains the original copyright notice and the associated */ -/* disclaimer. */ -/* */ -/* This source file is free software; you can redistribute it and/or modify */ -/* it under the terms of the GNU Lesser General Public License as published */ -/* by the Free Software Foundation; either version 2.1 of the License, or */ -/* (at your option) any later version. */ -/* */ -/* This source is distributed in the hope that it will be useful, but WITHOUT*/ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ -/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ -/* License for more details. */ -/* */ -/* You should have received a copy of the GNU Lesser General Public License */ -/* along with this source; if not, write to the Free Software Foundation, */ -/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -/* */ -/*===========================================================================*/ -/* DEBUG INTERFACE */ -/*---------------------------------------------------------------------------*/ -/* Test the debug interface: */ -/* - CPU Control features. */ -/* */ -/* Author(s): */ -/* - Olivier Girard, olgirard@gmail.com */ -/* */ -/*---------------------------------------------------------------------------*/ -/* $Rev: 19 $ */ -/* $LastChangedBy: olivier.girard $ */ -/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ -/*===========================================================================*/ - -.include "pmem_defs.asm" - -.global main - -main: - mov #DMEM_250, r1 ; Initialize stack - mov #0x0000, r15 - mov #0x0000, r14 - mov #0x0000, r13 - nop - eint - -test_loop: - add #0x0001, r14 - cmp #0xffff, r13 - jne test_loop - - mov #0x1000, r15 - - - - /* ---------------------- END OF TEST --------------- */ -end_of_test: - nop - br #0xffff - -isr_1: - mov #0xffff, r13 - reti - - - /* ---------------------- INTERRUPT VECTORS --------------- */ - -.section .vectors, "a" -.word end_of_test ; Interrupt 0 (lowest priority) -.word isr_1 ; Interrupt 1 -.word end_of_test ; Interrupt 2 -.word end_of_test ; Interrupt 3 -.word end_of_test ; Interrupt 4 -.word end_of_test ; Interrupt 5 -.word end_of_test ; Interrupt 6 -.word end_of_test ; Interrupt 7 -.word end_of_test ; Interrupt 8 -.word end_of_test ; Interrupt 9 -.word end_of_test ; Interrupt 10 Watchdog timer -.word end_of_test ; Interrupt 11 -.word end_of_test ; Interrupt 12 -.word end_of_test ; Interrupt 13 -.word end_of_test ; Interrupt 14 NMI -.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_onoff_asic.s43 Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_onoff.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_onoff.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_onoff.s43 (revision 154) @@ -0,0 +1,87 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +main: + mov #DMEM_250, r1 ; Initialize stack + mov #0x0000, r15 + mov #0x0000, r14 + mov #0x0000, r13 + nop + eint + +test_loop: + add #0x0001, r14 + cmp #0xffff, r13 + jne test_loop + + mov #0x1000, r15 + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + +isr_1: + mov #0xffff, r13 + reti + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word isr_1 ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_onoff.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/submit.prj =================================================================== --- sim/rtl_sim/src/submit.prj (revision 151) +++ sim/rtl_sim/src/submit.prj (revision 154) @@ -1,6 +1,7 @@ verilog work ../../../bench/verilog/tb_openMSP430.v verilog work ../../../bench/verilog/ram.v +verilog work ../../../bench/verilog/io_cell.v verilog work ../../../bench/verilog/msp_debug.v verilog work ../../../rtl/verilog/openMSP430_defines.v @@ -15,6 +16,7 @@ verilog work ../../../rtl/verilog/omsp_watchdog.v verilog work ../../../rtl/verilog/omsp_dbg.v verilog work ../../../rtl/verilog/omsp_dbg_uart.v +verilog work ../../../rtl/verilog/omsp_dbg_i2c.v verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v verilog work ../../../rtl/verilog/omsp_multiplier.v verilog work ../../../rtl/verilog/omsp_sync_reset.v

/sim/rtl_sim/src/dbg_i2c_mem.s43

sim/rtl_sim/src/dbg_i2c_mem.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_cpu.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_cpu.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_cpu.v (revision 154) @@ -0,0 +1,221 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + + integer my_test; + integer test_var; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + `ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // STOP, FREEZE, ISTEP, RUN + //-------------------------------------------------------- + + dbg_i2c_wr(CPU_STAT, 16'h00ff); // HALT + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0000) tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 ====="); + + dbg_i2c_wr(CPU_CTL, 16'h0001); // HALT + repeat(10) @(posedge mclk); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var !== inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function ====="); + + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0001) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 ====="); + + if (dbg_freeze !== 1'b0) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 ====="); + dbg_i2c_wr(CPU_CTL, 16'h0010); // FREEZE WITH BREAK + repeat(10) @(posedge mclk); + if (dbg_freeze !== 1'b1) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 ====="); + + + test_var = r14; + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+1)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 ====="); + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+2)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 ====="); + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+3)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 ====="); + + + test_var = inst_number; + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + repeat(50) @(posedge mclk); + if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 ====="); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 ====="); + + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0000) tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 ====="); + + + + // RESET / BREAK ON RESET + //-------------------------------------------------------- + + test_var = r14; + dbg_i2c_wr(CPU_CTL, 16'h0040); // RESET CPU + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 ====="); + if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 ====="); + dbg_i2c_wr(CPU_CTL, 16'h0000); // RELEASE RESET + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 ====="); + if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 ====="); + if (test_var >= r14) tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 ====="); + dbg_i2c_wr(CPU_STAT, 16'h0004); // CLEAR STATUS + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 ====="); + + + test_var = r14; + dbg_i2c_wr(CPU_CTL, 16'h0060); // RESET & BREAK ON RESET + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 ====="); + if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 ====="); + dbg_i2c_wr(CPU_CTL, 16'h0020); // RELEASE RESET + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0005) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 ====="); + if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 ====="); + repeat(10) @(posedge mclk); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var !== inst_number) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 ====="); + if (r0 !== irq_vect_15) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 ====="); + + dbg_i2c_wr(CPU_STAT, 16'h0004); // CLEAR STATUS + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0001) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 ====="); + + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 ====="); + + + // SOFTWARE BREAKPOINT + //-------------------------------------------------------- + + dbg_i2c_wr(CPU_CTL, 16'h0048); // RESET & ENABLE SOFTWARE BREAKPOINT + dbg_i2c_wr(CPU_CTL, 16'h0008); // RELEASE RESET + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h000D) tb_error("====== SOFTWARE BREAKPOINT: test 1 ====="); + if (r0 !== ('h10000-`PMEM_SIZE+'h12)) tb_error("====== SOFTWARE BREAKPOINT: test 2 ====="); + dbg_i2c_wr(CPU_STAT, 16'h000C); // CLEAR STATUS + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 3 ====="); + + // Replace software breakpoint with a mov #2, r15 (opcode=0x432f) + dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12)); + dbg_i2c_wr(MEM_DATA, 16'h432f); + dbg_i2c_wr(MEM_CTL, 16'h0003); + + // Dummy write + dbg_i2c_wr(MEM_ADDR, 16'hff00); + dbg_i2c_wr(MEM_DATA, 16'h1234); + dbg_i2c_wr(MEM_CTL, 16'h0003); + + // RUN + dbg_i2c_wr(CPU_CTL, 16'h000A); + repeat(20) @(posedge mclk); + if (r15 !== 16'h0002) tb_error("====== SOFTWARE BREAKPOINT: test 4 ====="); + + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0009) tb_error("====== SOFTWARE BREAKPOINT: test 5 ====="); + if (r0 !== ('h10000-`PMEM_SIZE+'h16)) tb_error("====== SOFTWARE BREAKPOINT: test 6 ====="); + dbg_i2c_wr(CPU_STAT, 16'h0008); // CLEAR STATUS + dbg_i2c_rd(CPU_STAT); // READ STATUS + if (dbg_i2c_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 7 ====="); + + + // Replace software breakpoint with a mov #4, r15 (opcode=0x422f) + dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16)); + dbg_i2c_wr(MEM_DATA, 16'h422f); + dbg_i2c_wr(MEM_CTL, 16'h0003); + + // Dummy write + dbg_i2c_wr(MEM_ADDR, 16'hff00); + dbg_i2c_wr(MEM_DATA, 16'h5678); + dbg_i2c_wr(MEM_CTL, 16'h0003); + + // RUN + dbg_i2c_wr(CPU_CTL, 16'h000A); + repeat(20) @(posedge mclk); + if (r15 !== 16'h0004) tb_error("====== SOFTWARE BREAKPOINT: test 8 ====="); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_cpu.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk3.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk3.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk3.v (revision 154) @@ -0,0 +1,676 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 3. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 86 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C +`ifdef DBG_HWBRK_3 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + `ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK3_CTL, 16'h000C); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK3_CTL, 16'h000D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_i2c_wr(BRK3_ADDR0, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_i2c_wr(BRK3_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_i2c_wr(BRK3_CTL, 16'h001D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK3_CTL, 16'h0005); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK3_CTL, 16'h0006); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK3_CTL, 16'h0007); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK3_CTL, 16'h0015); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK3_CTL, 16'h0016); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK3_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK3_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK3_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK3_CTL, 16'h0017); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK3_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_i2c_wr(BRK3_CTL, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 3 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_hwbrk3.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk1.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk1.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk1.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 1. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_hwbrk1.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk3.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk3.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk3.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 3. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_hwbrk3.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_mem.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_mem.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_mem.s43 (revision 154) @@ -0,0 +1,93 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Memory RD/WR features. */ +/* */ +/* Note: The burst features are specific to the selected interface */ +/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +WAIT_FUNC: + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + + mov #0x1122, &DMEM_210 + mov #0x3344, &DMEM_212 + + mov #0xaaaa, r5 + mov #0xbbbb, r6 + + mov #0x1200, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + /* ---------------------- SOME VARIABLES IN ROM --------------- */ +diverse_data: + .word 0x5ab7 + .word 0x6bc8 + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_mem.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk0.v =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk0.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk0.v (revision 154) @@ -0,0 +1,679 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 0. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART +`ifdef DBG_HWBRK_0 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK0_CTL, 16'h000C); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK0_CTL, 16'h000D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_uart_wr(BRK0_ADDR0, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_uart_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_uart_wr(BRK0_CTL, 16'h001D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK0_CTL, 16'h0005); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK0_CTL, 16'h0006); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK0_CTL, 16'h0007); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK0_CTL, 16'h0015); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK0_CTL, 16'h0016); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK0_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK0_CTL, 16'h0017); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK0_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK0_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_uart_wr(BRK0_CTL, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 0 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_hwbrk0.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk0.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk0.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk0.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 0. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_hwbrk0.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk2.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk2.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk2.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 2. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_hwbrk2.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_onoff_asic.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_onoff_asic.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_onoff_asic.s43 (revision 154) @@ -0,0 +1,87 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +main: + mov #DMEM_250, r1 ; Initialize stack + mov #0x0000, r15 + mov #0x0000, r14 + mov #0x0000, r13 + nop + eint + +test_loop: + add #0x0001, r14 + cmp #0xffff, r13 + jne test_loop + + mov #0x1000, r15 + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + +isr_1: + mov #0xffff, r13 + reti + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word isr_1 ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_onoff_asic.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_sync.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_sync.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_sync.v (revision 154) @@ -0,0 +1,176 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE: I2C */ +/*---------------------------------------------------------------------------*/ +/* Test the I2C debug interface: */ +/* - Check synchronization of the serial */ +/* debug interface input. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + +`define VERY_LONG_TIMEOUT + +integer ii; +reg [15:0] jj; +integer kk; + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // Enable metastablity emulation for the SCL and SDA master path + dbg_scl_master_meta = 1'b1; + dbg_sda_master_out_meta = 1'b1; + + //-------------------------------------------------------- + // TRY VARIOUS SERIAL DEBUG INTERFACE TRANSFER + // WITH DIFFERENT BAUD-RATES + //-------------------------------------------------------- + + for ( ii=0; ii < 200; ii=ii+1) + begin + #1 reset_n = 0; + repeat(1) @(posedge mclk); + #1 reset_n = 1; + repeat(10) @(posedge mclk); + + I2C_PERIOD = 600 + 1*ii; + $display("Synchronisation test for DBG_I2C_PERIOD = %5d ns / ii = %-d", I2C_PERIOD, ii); + + + // READ CPU_ID + dbg_i2c_rd(CPU_ID_LO); + if (dbg_i2c_buf !== dbg_cpu_id[15:0]) + begin + $display("CPU_ID_LO: read = 0x%-4h / expected = 0x%-4h", dbg_i2c_buf, dbg_cpu_id[15:0]); + tb_error("====== CPU_ID_LO incorrect (test 1) ====="); + force_end_of_sim; + end + dbg_i2c_rd(CPU_ID_HI); + if (dbg_i2c_buf !== dbg_cpu_id[31:16]) + begin + $display("CPU_ID_HI: read = 0x%-4h / expected = 0x%-4h", dbg_i2c_buf, dbg_cpu_id[31:16]); + tb_error("====== CPU_ID_HI incorrect (test 1) ====="); + force_end_of_sim; + end + + //----------------------------------- + // MAKE SOME READ/WRITE ACCESS + //----------------------------------- + + for ( kk=0; kk < 10; kk=kk+1) + begin + + jj = 'h4328; + dbg_i2c_wr(MEM_DATA, 16'h5555); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h5555) + begin + $display("DMEM_DATA: read = 0x%-4h / expected = 0x5555", dbg_i2c_buf); + tb_error("====== MEM_DATA incorrect (test 1) ====="); + force_end_of_sim; + end + + jj = 'h3280; + dbg_i2c_wr(MEM_DATA, 16'haaaa); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'haaaa) + begin + $display("DMEM_DATA: read = 0x%-4h / expected = 0xaaaa", dbg_i2c_buf); + tb_error("====== MEM_DATA incorrect (test 2) ====="); + force_end_of_sim; + end + end + end + + + //-------------------------------------------------------- + // END OF TEST + //-------------------------------------------------------- + + #1 reset_n = 0; + repeat(1) @(posedge mclk); + #1 reset_n = 1; + repeat(10) @(posedge mclk); + + I2C_PERIOD = 600; + $display("Synchronisation test for DBG_I2C_PERIOD = %5d ns / ii = %-d", I2C_PERIOD, ii); + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + // Generate an IRQ + wkup[0] = 1'b1; + @(negedge mclk); + irq[0] = 1'b1; + @(negedge irq_acc[0]) + @(negedge mclk); + wkup[0] = 1'b0; + irq[0] = 1'b0; + + repeat(10) @(posedge mclk); + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end + + task force_end_of_sim; + begin + repeat(10) @(posedge mclk); + $display(" ==============================================="); + $display("| SIMULATION FAILED |"); + $display("| (some verilog stimulus checks failed) |"); + $display(" ==============================================="); + $finish; + end + endtask

sim/rtl_sim/src/dbg_i2c_sync.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_rdwr.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_rdwr.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_rdwr.v (revision 154) @@ -0,0 +1,206 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE: RD / WR */ +/*---------------------------------------------------------------------------*/ +/* Test the UART debug interface: */ +/* - Check RD/WR access to all adressable */ +/* debug registers. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +reg [2:0] cpu_version; +reg cpu_asic; +reg [4:0] user_version; +reg [6:0] per_space; +reg mpy_info; +reg [8:0] dmem_size; +reg [5:0] pmem_size; +reg [31:0] dbg_id; + +// Set oMSP parameters for later check +defparam dut.INST_NR = 8'h12; +defparam dut.TOTAL_NR = 8'h34; + +integer ii; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // STOP CPU + dbg_i2c_wr(CPU_CTL , 16'h0001); + + // TEST READ/WR TO ALL DEBUG REGISTERS + //-------------------------------------------------------- + + cpu_version = `CPU_VERSION; +`ifdef ASIC + cpu_asic = 1'b1; +`else + cpu_asic = 1'b0; +`endif + user_version = `USER_VERSION; + per_space = (`PER_SIZE >> 9); +`ifdef MULTIPLIER + mpy_info = 1'b1; +`else + mpy_info = 1'b0; +`endif + dmem_size = (`DMEM_SIZE >> 7); + pmem_size = (`PMEM_SIZE >> 10); + + dbg_id = {pmem_size, + dmem_size, + mpy_info, + per_space, + user_version, + cpu_asic, + cpu_version}; + + // Check reset value + for ( ii=0; ii < 64; ii=ii+1) + begin + dbg_i2c_rd(ii[7:0]); + + case(ii) + 0 : if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("READ 1 ERROR (CPU_ID_LO)"); + 1 : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)"); + 2 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)"); + 3 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)"); + 24 : if (dbg_i2c_buf !== 16'h3412) tb_error("READ 1 ERROR (CPU_NR)"); + default : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 1 ERROR"); + endcase + end + + // Write access + for ( ii=0; ii < 64; ii=ii+1) + begin + // Skip write for MEM_CNT + if (ii!=7) + dbg_i2c_wr(ii[7:0] , 16'hffff); + end + + // Read value back + for ( ii=0; ii < 64; ii=ii+1) + begin + dbg_i2c_rd(ii[7:0]); + + case(ii) + 0 : if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("READ 2 ERROR (CPU_ID_LO)"); + 1 : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)"); + 2 : if (dbg_i2c_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)"); + 3 : if ((dbg_i2c_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)"); + 4 : if (dbg_i2c_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)"); + 5 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)"); + 6 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)"); + 7 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)"); +`ifdef DBG_HWBRK_0 + `ifdef DBG_HWBRK_RANGE + 8 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)"); + 9 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)"); + `else + 8 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)"); + 9 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)"); + `endif + 10 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)"); + 11 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)"); +`endif +`ifdef DBG_HWBRK_1 + `ifdef DBG_HWBRK_RANGE + 12 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)"); + 13 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)"); + `else + 12 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)"); + 13 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)"); + `endif + 14 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)"); + 15 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)"); +`endif +`ifdef DBG_HWBRK_2 + `ifdef DBG_HWBRK_RANGE + 16 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)"); + 17 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)"); + `else + 16 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)"); + 17 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)"); + `endif + 18 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)"); + 19 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)"); +`endif +`ifdef DBG_HWBRK_3 + `ifdef DBG_HWBRK_RANGE + 20 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)"); + 21 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)"); + `else + 20 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)"); + 21 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)"); + `endif + 22 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)"); + 23 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)"); +`endif + 24 : if (dbg_i2c_buf !== 16'h3412) tb_error("READ 2 ERROR (CPU_NR)"); + default : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR"); + endcase + end + + + dbg_i2c_wr(CPU_CTL , 16'h0002); + repeat(10) @(posedge mclk); + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_rdwr.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_rdwr.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_rdwr.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_rdwr.s43 (revision 154) @@ -0,0 +1,87 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE: RD / WR */ +/*---------------------------------------------------------------------------*/ +/* Test the UART debug interface: */ +/* - Check RD/WR access to all adressable */ +/* debug registers. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + + mov #0x0300, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_rdwr.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c.v =================================================================== --- sim/rtl_sim/src/dbg_i2c.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c.v (revision 154) @@ -0,0 +1,471 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE: I2C */ +/*---------------------------------------------------------------------------*/ +/* Test the I2C debug interface: */ +/* - Check RD/WR access to debugg registers. */ +/* - Check RD Bursts. */ +/* - Check WR Bursts. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +reg [2:0] cpu_version; +reg cpu_asic; +reg [4:0] user_version; +reg [6:0] per_space; +reg mpy_info; +reg [8:0] dmem_size; +reg [5:0] pmem_size; +reg [31:0] dbg_id; +integer step; + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + step = 0; + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + + `ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // TEST CPU REGISTERS + //-------------------------------------------------------- + step = 1; + + cpu_version = `CPU_VERSION; +`ifdef ASIC + cpu_asic = 1'b1; +`else + cpu_asic = 1'b0; +`endif + user_version = `USER_VERSION; + per_space = (`PER_SIZE >> 9); +`ifdef MULTIPLIER + mpy_info = 1'b1; +`else + mpy_info = 1'b0; +`endif + dmem_size = (`DMEM_SIZE >> 7); + pmem_size = (`PMEM_SIZE >> 10); + + dbg_id = {pmem_size, + dmem_size, + mpy_info, + per_space, + user_version, + cpu_asic, + cpu_version}; + + dbg_i2c_wr(CPU_ID_LO , 16'hffff); + dbg_i2c_rd(CPU_ID_LO); + if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect ====="); + dbg_i2c_wr(CPU_ID_LO , 16'h0000); + dbg_i2c_rd(CPU_ID_LO); + if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect ====="); + + dbg_i2c_wr(CPU_ID_HI , 16'hffff); + dbg_i2c_rd(CPU_ID_HI); + if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect ====="); + dbg_i2c_wr(CPU_ID_HI , 16'h0000); + dbg_i2c_rd(CPU_ID_HI); + if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect ====="); + + dbg_i2c_wr(CPU_STAT , 16'hffff); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect ====="); + dbg_i2c_wr(CPU_STAT , 16'h0000); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect ====="); + + dbg_i2c_wr(CPU_CTL , 16'hffff); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0078) tb_error("====== CPU_CTL uncorrect ====="); + dbg_i2c_wr(CPU_CTL , 16'h0000); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL uncorrect ====="); + + + // TEST MEMORY CONTROL REGISTERS + //-------------------------------------------------------- + step = 2; + + dbg_i2c_wr(MEM_CTL , 16'hfffe); + dbg_i2c_rd(MEM_CTL); + if (dbg_i2c_buf !== 16'h000E) tb_error("====== MEM_CTL uncorrect ====="); + dbg_i2c_wr(MEM_CTL , 16'h0000); + dbg_i2c_rd(MEM_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_CTL uncorrect ====="); + + dbg_i2c_wr(MEM_ADDR , 16'hffff); + dbg_i2c_rd(MEM_ADDR); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_ADDR uncorrect ====="); + dbg_i2c_wr(MEM_ADDR , 16'h0000); + dbg_i2c_rd(MEM_ADDR); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_ADDR uncorrect ====="); + + dbg_i2c_wr(MEM_DATA , 16'hffff); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_DATA uncorrect ====="); + dbg_i2c_wr(MEM_DATA , 16'h0000); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA uncorrect ====="); + + dbg_i2c_wr(MEM_CNT , 16'hffff); + dbg_i2c_rd(MEM_CNT); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_CNT uncorrect ====="); + dbg_i2c_wr(MEM_CNT , 16'h0000); + dbg_i2c_rd(MEM_CNT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect ====="); + + + // TEST HARDWARE BREAKPOINT 0 REGISTERS + //-------------------------------------------------------- +`ifdef DBG_HWBRK_0 + step = 3; + dbg_i2c_wr(BRK0_CTL , 16'hffff); + dbg_i2c_rd(BRK0_CTL); + if (`HWBRK_RANGE) + begin + if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect ====="); + end + else + begin + if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect ====="); + end + dbg_i2c_wr(BRK0_CTL , 16'h0000); + dbg_i2c_rd(BRK0_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect ====="); + + dbg_i2c_wr(BRK0_STAT , 16'hffff); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect ====="); + dbg_i2c_wr(BRK0_STAT , 16'h0000); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect ====="); + + dbg_i2c_wr(BRK0_ADDR0 , 16'hffff); + dbg_i2c_rd(BRK0_ADDR0); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK0_ADDR0 uncorrect ====="); + dbg_i2c_wr(BRK0_ADDR0 , 16'h0000); + dbg_i2c_rd(BRK0_ADDR0); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_ADDR0 uncorrect ====="); + + dbg_i2c_wr(BRK0_ADDR1 , 16'hffff); + dbg_i2c_rd(BRK0_ADDR1); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect ====="); + dbg_i2c_wr(BRK0_ADDR1 , 16'h0000); + dbg_i2c_rd(BRK0_ADDR1); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect ====="); +`endif + + // TEST HARDWARE BREAKPOINT 1 REGISTERS + //-------------------------------------------------------- +`ifdef DBG_HWBRK_1 + step = 4; + dbg_i2c_wr(BRK1_CTL , 16'hffff); + dbg_i2c_rd(BRK1_CTL); + if (`HWBRK_RANGE) + begin + if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect ====="); + end + else + begin + if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect ====="); + end + dbg_i2c_wr(BRK1_CTL , 16'h0000); + dbg_i2c_rd(BRK1_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect ====="); + + dbg_i2c_wr(BRK1_STAT , 16'hffff); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect ====="); + dbg_i2c_wr(BRK1_STAT , 16'h0000); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect ====="); + + dbg_i2c_wr(BRK1_ADDR0 , 16'hffff); + dbg_i2c_rd(BRK1_ADDR0); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK1_ADDR0 uncorrect ====="); + dbg_i2c_wr(BRK1_ADDR0 , 16'h0000); + dbg_i2c_rd(BRK1_ADDR0); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_ADDR0 uncorrect ====="); + + dbg_i2c_wr(BRK1_ADDR1 , 16'hffff); + dbg_i2c_rd(BRK1_ADDR1); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect ====="); + dbg_i2c_wr(BRK1_ADDR1 , 16'h0000); + dbg_i2c_rd(BRK1_ADDR1); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect ====="); +`endif + + // TEST HARDWARE BREAKPOINT 2 REGISTERS + //-------------------------------------------------------- +`ifdef DBG_HWBRK_2 + step = 5; + dbg_i2c_wr(BRK2_CTL , 16'hffff); + dbg_i2c_rd(BRK2_CTL); + if (`HWBRK_RANGE) + begin + if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect ====="); + end + else + begin + if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect ====="); + end + dbg_i2c_wr(BRK2_CTL , 16'h0000); + dbg_i2c_rd(BRK2_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect ====="); + + dbg_i2c_wr(BRK2_STAT , 16'hffff); + dbg_i2c_rd(BRK2_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect ====="); + dbg_i2c_wr(BRK2_STAT , 16'h0000); + dbg_i2c_rd(BRK2_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect ====="); + + dbg_i2c_wr(BRK2_ADDR0 , 16'hffff); + dbg_i2c_rd(BRK2_ADDR0); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK2_ADDR0 uncorrect ====="); + dbg_i2c_wr(BRK2_ADDR0 , 16'h0000); + dbg_i2c_rd(BRK2_ADDR0); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_ADDR0 uncorrect ====="); + + dbg_i2c_wr(BRK2_ADDR1 , 16'hffff); + dbg_i2c_rd(BRK2_ADDR1); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect ====="); + dbg_i2c_wr(BRK2_ADDR1 , 16'h0000); + dbg_i2c_rd(BRK2_ADDR1); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect ====="); +`endif + + // TEST HARDWARE BREAKPOINT 3 REGISTERS + //-------------------------------------------------------- +`ifdef DBG_HWBRK_3 + step = 6; + dbg_i2c_wr(BRK3_CTL , 16'hffff); + dbg_i2c_rd(BRK3_CTL); + if (`HWBRK_RANGE) + begin + if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect ====="); + end + else + begin + if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect ====="); + end + dbg_i2c_wr(BRK3_CTL , 16'h0000); + dbg_i2c_rd(BRK3_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect ====="); + + dbg_i2c_wr(BRK3_STAT , 16'hffff); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect ====="); + dbg_i2c_wr(BRK3_STAT , 16'h0000); + dbg_i2c_rd(BRK3_STAT); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect ====="); + + dbg_i2c_wr(BRK3_ADDR0 , 16'hffff); + dbg_i2c_rd(BRK3_ADDR0); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK3_ADDR0 uncorrect ====="); + dbg_i2c_wr(BRK3_ADDR0 , 16'h0000); + dbg_i2c_rd(BRK3_ADDR0); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_ADDR0 uncorrect ====="); + + dbg_i2c_wr(BRK3_ADDR1 , 16'hffff); + dbg_i2c_rd(BRK3_ADDR1); + if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect ====="); + dbg_i2c_wr(BRK3_ADDR1 , 16'h0000); + dbg_i2c_rd(BRK3_ADDR1); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect ====="); +`endif + + // TEST 16B WRITE BURSTS (MEMORY) + //-------------------------------------------------------- + step = 7; + + dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write + dbg_i2c_burst_start(0); + dbg_i2c_tx16(16'h1234, 0); // write 1st data + repeat(12) @(posedge mclk); + if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA ====="); + dbg_i2c_tx16(16'h5678, 0); // write 2nd data + repeat(12) @(posedge mclk); + if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA ====="); + dbg_i2c_tx16(16'h9abc, 0); // write 3rd data + repeat(12) @(posedge mclk); + if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA ====="); + dbg_i2c_tx16(16'hdef0, 0); // write 4th data + repeat(12) @(posedge mclk); + if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA ====="); + dbg_i2c_tx16(16'h0fed, 1); // write 5th data + repeat(12) @(posedge mclk); + if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA ====="); + + step = 8; + dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read + dbg_i2c_burst_start(1); + dbg_i2c_rx16(0); // read 1st data + if (dbg_i2c_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA ====="); + dbg_i2c_rx16(0); // read 2nd data + if (dbg_i2c_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA ====="); + dbg_i2c_rx16(0); // read 3rd data + if (dbg_i2c_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA ====="); + dbg_i2c_rx16(0); // read 4th data + if (dbg_i2c_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA ====="); + dbg_i2c_rx16(1); // read 5th data + if (dbg_i2c_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA ====="); + + + // TEST 16B WRITE BURSTS (CPU REGISTERS) + //-------------------------------------------------------- + step = 9; + + dbg_i2c_wr(MEM_ADDR, 16'h0005); // select R5 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write + dbg_i2c_burst_start(0); + dbg_i2c_tx16(16'hcba9, 0); // write 1st data + repeat(12) @(posedge mclk); + if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA ====="); + dbg_i2c_tx16(16'h8765, 0); // write 2nd data + repeat(12) @(posedge mclk); + if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA ====="); + dbg_i2c_tx16(16'h4321, 0); // write 3rd data + repeat(12) @(posedge mclk); + if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA ====="); + dbg_i2c_tx16(16'h0123, 0); // write 4th data + repeat(12) @(posedge mclk); + if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA ====="); + dbg_i2c_tx16(16'h4567, 1); // write 5th data + repeat(12) @(posedge mclk); + if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA ====="); + + step = 10; + dbg_i2c_wr(MEM_ADDR, 16'h0005); // select @0x0200 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read + dbg_i2c_burst_start(1); + dbg_i2c_rx16(0); // read 1st data + if (dbg_i2c_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA ====="); + dbg_i2c_rx16(0); // read 2nd data + if (dbg_i2c_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA ====="); + dbg_i2c_rx16(0); // read 3rd data + if (dbg_i2c_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA ====="); + dbg_i2c_rx16(0); // read 4th data + if (dbg_i2c_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA ====="); + dbg_i2c_rx16(1); // read 5th data + if (dbg_i2c_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA ====="); + + + // TEST 8B WRITE BURSTS (MEMORY) + //-------------------------------------------------------- + step = 11; + + dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write + dbg_i2c_burst_start(0); + dbg_i2c_tx8(8'h91, 0); // write 1st data + repeat(12) @(posedge mclk); + if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA ====="); + dbg_i2c_tx8(8'h82, 0); // write 2nd data + repeat(12) @(posedge mclk); + if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA ====="); + dbg_i2c_tx8(8'h73, 0); // write 3rd data + repeat(12) @(posedge mclk); + if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA ====="); + dbg_i2c_tx8(8'h64, 0); // write 4th data + repeat(12) @(posedge mclk); + if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA ====="); + dbg_i2c_tx8(8'h55, 1); // write 5th data + repeat(12) @(posedge mclk); + if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA ====="); + + step = 12; + dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200 + dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access + + dbg_i2c_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read + dbg_i2c_burst_start(1); + dbg_i2c_rx8(0); // read 1st data + if (dbg_i2c_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA ====="); + dbg_i2c_rx8(0); // read 2nd data + if (dbg_i2c_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA ====="); + dbg_i2c_rx8(1); // read 3rd data + if (dbg_i2c_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA ====="); + dbg_i2c_burst_start(1); + dbg_i2c_rx8(0); // read 4th data + if (dbg_i2c_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA ====="); + dbg_i2c_rx8(1); // read 5th data + if (dbg_i2c_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA ====="); + + + dbg_i2c_wr(CPU_CTL , 16'h0002); + repeat(10) @(posedge mclk); + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk0.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk0.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk0.v (revision 154) @@ -0,0 +1,676 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 0. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 86 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C +`ifdef DBG_HWBRK_0 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + `ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK0_CTL, 16'h000C); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK0_CTL, 16'h000D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_i2c_wr(BRK0_ADDR0, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_i2c_wr(BRK0_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_i2c_wr(BRK0_CTL, 16'h001D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK0_CTL, 16'h0005); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK0_CTL, 16'h0006); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK0_CTL, 16'h0007); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK0_CTL, 16'h0015); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK0_CTL, 16'h0016); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK0_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK0_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK0_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK0_CTL, 16'h0017); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK0_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK0_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_i2c_wr(BRK0_CTL, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 0 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_hwbrk0.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/core.f =================================================================== --- sim/rtl_sim/src/core.f (revision 151) +++ sim/rtl_sim/src/core.f (revision 154) @@ -48,6 +48,7 @@ ../../../rtl/verilog/omsp_watchdog.v ../../../rtl/verilog/omsp_dbg.v ../../../rtl/verilog/omsp_dbg_uart.v +../../../rtl/verilog/omsp_dbg_i2c.v ../../../rtl/verilog/omsp_dbg_hwbrk.v ../../../rtl/verilog/omsp_multiplier.v ../../../rtl/verilog/omsp_sync_reset.v Index: sim/rtl_sim/src/dbg_i2c_halt_irq.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_halt_irq.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_halt_irq.v (revision 154) @@ -0,0 +1,98 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* SERIAL DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the serial debug interface: */ +/* - Interrupts when going out of halt mode. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +reg [15:0] r13_bkup; + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + +`ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN +`endif + + // Wait until software initialization is done + if (r15!==(`PER_SIZE+16'h0000)) + @(r15==(`PER_SIZE+16'h0000)); + + + dbg_i2c_wr(CPU_CTL, 16'h0001); // HALT + repeat(150) @(posedge mclk); + r13_bkup = r13; + + // Generate a GPIO interrupt + p1_din[0] = 1'b1; + repeat(150) @(posedge mclk); + + // Re-start the CPU + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + repeat(150) @(posedge mclk); + + // Make sure the interrupt was serviced + if (r14 !== 16'haaaa) tb_error("====== Interrupt was not properly serviced ====="); + + // Make sure the program resumed execution when coming back from IRQ + if (r13 === r13_bkup) tb_error("====== Program didn't properly resumed execution ====="); + + + p1_din[1] = 1'b1; + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_halt_irq.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/submit.f =================================================================== --- sim/rtl_sim/src/submit.f (revision 151) +++ sim/rtl_sim/src/submit.f (revision 154) @@ -40,6 +40,7 @@ +incdir+../../../bench/verilog/ ../../../bench/verilog/tb_openMSP430.v ../../../bench/verilog/ram.v +../../../bench/verilog/io_cell.v ../../../bench/verilog/msp_debug.v

/sim/rtl_sim/src/dbg_i2c_rdwr.s43

sim/rtl_sim/src/dbg_i2c_rdwr.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_cpu.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_cpu.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_cpu.s43 (revision 154) @@ -0,0 +1,93 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + nop + .word 0x4343 ; # Software BREAKPOINT +; nop.b + nop + .word 0x4343 ; # Software BREAKPOINT +; nop.b + + mov #2, r15 + mov #4, r15 + + mov #0x0400, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_cpu.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk1.v =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk1.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk1.v (revision 154) @@ -0,0 +1,678 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 1. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART +`ifdef DBG_HWBRK_1 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK1_CTL, 16'h000C); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK1_CTL, 16'h000D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_uart_wr(BRK1_ADDR0, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_uart_wr(BRK1_CTL, 16'h001D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK1_CTL, 16'h0005); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK1_CTL, 16'h0006); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK1_CTL, 16'h0007); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK1_CTL, 16'h0015); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK1_CTL, 16'h0016); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK1_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK1_CTL, 16'h0017); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK1_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK1_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_uart_wr(BRK1_CTL, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 1 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_hwbrk1.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_mem.v =================================================================== --- sim/rtl_sim/src/dbg_uart_mem.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_mem.v (revision 154) @@ -0,0 +1,282 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Memory RD/WR features. */ +/* */ +/* Note: The burst features are specific to the selected interface */ +/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + + // RD/WR ACCESS: CPU REGISTERS (16b) + //-------------------------------------------------------- + + // READ CPU REGISTERS + dbg_uart_wr(MEM_ADDR, 16'h0005); // select register + dbg_uart_wr(MEM_CTL, 16'h0005); // read register + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'haaaa) tb_error("====== CPU REGISTERS (16b): Read R5 ====="); + dbg_uart_wr(MEM_ADDR, 16'h0006); // select register + dbg_uart_wr(MEM_CTL, 16'h0005); // read register + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'hbbbb) tb_error("====== CPU REGISTERS (16b): Read R6 ====="); + + // WRITE CPU REGISTERS + dbg_uart_wr(MEM_ADDR, 16'h0005); // select register + dbg_uart_wr(MEM_DATA, 16'hed32); // write data + dbg_uart_wr(MEM_CTL, 16'h0007); // write register + repeat(20) @(posedge mclk); + if (r5 !== 16'hed32) tb_error("====== CPU REGISTERS (16b): Write R5 ====="); + dbg_uart_wr(MEM_ADDR, 16'h0006); // select register + dbg_uart_wr(MEM_DATA, 16'hcb54); // write data + dbg_uart_wr(MEM_CTL, 16'h0007); // write register + repeat(20) @(posedge mclk); + if (r6 !== 16'hcb54) tb_error("====== CPU REGISTERS (16b): Write R6 ====="); + + + // RD/WR ACCESS: RAM (16b) + //-------------------------------------------------------- + + // READ RAM + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h1122) tb_error("====== RAM (16b): Read @0x210 ====="); + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h3344) tb_error("====== RAM (16b): Read @0x212 ====="); + + // WRITE RAM + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address + dbg_uart_wr(MEM_DATA, 16'ha976); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write memory + repeat(20) @(posedge mclk); + if (mem210 !== 16'ha976) tb_error("====== RAM (16b): Write @0x210 ====="); + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select register + dbg_uart_wr(MEM_DATA, 16'h8798); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write register + repeat(20) @(posedge mclk); + if (mem212 !== 16'h8798) tb_error("====== RAM (16b): Write @0x212 ====="); + + + // RD/WR ACCESS: RAM (8b) + //-------------------------------------------------------- + + // READ RAM + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h0076) tb_error("====== RAM (8b): Read @0x210 ====="); + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h00a9) tb_error("====== RAM (8b): Read @0x211 ====="); + + // WRITE RAM + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address + dbg_uart_wr(MEM_DATA, 16'h14b3); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write memory + repeat(20) @(posedge mclk); + if (mem210 !== 16'ha9b3) tb_error("====== RAM (8b): Write @0x210 ====="); + dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select register + dbg_uart_wr(MEM_DATA, 16'h25c4); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write register + repeat(20) @(posedge mclk); + if (mem210 !== 16'hc4b3) tb_error("====== RAM (8b): Write @0x211 ====="); + + + // RD/WR ACCESS: ROM (16b) + //-------------------------------------------------------- + + // READ ROM + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h5ab7) tb_error("====== ROM (16b): Read @0xf82e ====="); + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h30)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h6bc8) tb_error("====== ROM (16b): Read @0xf830 ====="); + + // WRITE ROM + dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address + dbg_uart_wr(MEM_DATA, 16'h7cd9); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write memory + repeat(20) @(posedge mclk); + if (irq_vect_00 !== 16'h7cd9) tb_error("====== ROM (16b): Write @0xffe0 ====="); + dbg_uart_wr(MEM_ADDR, 16'hffe2); // select register + dbg_uart_wr(MEM_DATA, 16'h8dea); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write register + repeat(20) @(posedge mclk); + if (irq_vect_01 !== 16'h8dea) tb_error("====== ROM (16b): Write @0xffe2 ====="); + + + // RD/WR ACCESS: ROM (8b) + //-------------------------------------------------------- + + // READ ROM + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h00b7) tb_error("====== ROM (8b): Read @0xf82e ====="); + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2f)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h005a) tb_error("====== ROM (8b): Read @0xf82f ====="); + + // WRITE ROM + dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address + dbg_uart_wr(MEM_DATA, 16'hb314); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write memory + repeat(20) @(posedge mclk); + if (irq_vect_00 !== 16'h7c14) tb_error("====== ROM (8b): Write @0xffe0 ====="); + dbg_uart_wr(MEM_ADDR, 16'hffe1); // select register + dbg_uart_wr(MEM_DATA, 16'hc425); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write register + repeat(20) @(posedge mclk); + if (irq_vect_00 !== 16'h2514) tb_error("====== ROM (8b): Write @0xffe1 ====="); + + + // RD/WR ACCESS: PERIPHERALS (16b) + //-------------------------------------------------------- + + // WRITE PERIPHERAL + dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address + dbg_uart_wr(MEM_DATA, 16'h9dc7); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write memory + repeat(20) @(posedge mclk); + if (timerA_0.tar !== 16'h9dc7) tb_error("====== Peripheral (16b): Write @0x0170 ====="); + dbg_uart_wr(MEM_ADDR, 16'h0172); // select register + dbg_uart_wr(MEM_DATA, 16'haed8); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write register + repeat(20) @(posedge mclk); + if (timerA_0.taccr0 !== 16'haed8) tb_error("====== Peripheral (16b): Write @0x0172 ====="); + dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address + dbg_uart_wr(MEM_DATA, 16'hdead); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write memory + repeat(20) @(posedge mclk); + if (template_periph_16b_0.cntrl2 !== 16'hdead) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0002) ====="); + dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address + dbg_uart_wr(MEM_DATA, 16'hbeef); // write data + dbg_uart_wr(MEM_CTL, 16'h0003); // write memory + repeat(20) @(posedge mclk); + if (template_periph_16b_0.cntrl4 !== 16'hbeef) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0006) ====="); + + // READ PERIPHERAL + dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h9dc7) tb_error("====== Peripheral (16b): Read @0x0170 ====="); + dbg_uart_wr(MEM_ADDR, 16'h0172); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'haed8) tb_error("====== Peripheral (16b): Read @0x0172 ====="); + dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + repeat(20) @(posedge mclk); + if (dbg_uart_buf !== 16'hdead) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0002) ====="); + dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0001); // read memory + dbg_uart_rd(MEM_DATA); // read data + repeat(20) @(posedge mclk); + if (dbg_uart_buf !== 16'hbeef) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0006) ====="); + + + // RD/WR ACCESS: PERIPHERAL (8b) + //-------------------------------------------------------- + + // WRITE PERIPHERAL + dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address + dbg_uart_wr(MEM_DATA, 16'hbfe9); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write memory + repeat(20) @(posedge mclk); + if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0022 - test 1 ====="); + if (gpio_0.p1ifg !== 8'h00) tb_error("====== Peripheral (8b): Write @0x0022 - test 2====="); + dbg_uart_wr(MEM_ADDR, 16'h0023); // select register + dbg_uart_wr(MEM_DATA, 16'hc0fa); // write data + dbg_uart_wr(MEM_CTL, 16'h000b); // write register + repeat(20) @(posedge mclk); + if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0023 - test 1 ====="); + if (gpio_0.p1ifg !== 8'hfa) tb_error("====== Peripheral (8b): Write @0x0023 - test 2====="); + + // READ PERIPHERAL + dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h00e9) tb_error("====== Peripheral (8b): Read @0x0022 ====="); + dbg_uart_wr(MEM_ADDR, 16'h0023); // select memory address + dbg_uart_wr(MEM_CTL, 16'h0009); // read memory + dbg_uart_rd(MEM_DATA); // read data + if (dbg_uart_buf !== 16'h00fa) tb_error("====== Peripheral (8b): Read @0x0023 ====="); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_mem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_cpu.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_cpu.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_cpu.s43 (revision 154) @@ -0,0 +1,93 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + nop + .word 0x4343 ; # Software BREAKPOINT +; nop.b + nop + .word 0x4343 ; # Software BREAKPOINT +; nop.b + + mov #2, r15 + mov #4, r15 + + mov #0x0400, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_cpu.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk1.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk1.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk1.v (revision 154) @@ -0,0 +1,675 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 1. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 86 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C +`ifdef DBG_HWBRK_1 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + `ifdef DBG_RST_BRK_EN + dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK1_CTL, 16'h000C); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_i2c_wr(BRK1_CTL, 16'h000D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_i2c_wr(BRK1_ADDR0, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_i2c_wr(BRK1_CTL, 16'h001D); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK1_CTL, 16'h0005); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK1_CTL, 16'h0006); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008)); + dbg_i2c_wr(BRK1_CTL, 16'h0007); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0002); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0008); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0001); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0004); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK1_CTL, 16'h0015); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK1_CTL, 16'h0016); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_i2c_wr(CPU_CTL, 16'h0060); + dbg_i2c_wr(CPU_CTL, 16'h0020); + dbg_i2c_wr(BRK1_STAT, 16'h00ff); + dbg_i2c_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001)); + dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005)); + dbg_i2c_wr(BRK1_CTL, 16'h0017); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0010); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_i2c_rd(BRK1_STAT); + if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_i2c_wr(BRK1_STAT, 16'h0020); + dbg_i2c_rd(CPU_STAT); + if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_i2c_wr(BRK1_CTL, 16'h0000); + dbg_i2c_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 1 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_hwbrk1.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk0.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk0.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk0.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 0. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_hwbrk0.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk2.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk2.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk2.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 2. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_hwbrk2.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_onoff_asic.v =================================================================== --- sim/rtl_sim/src/dbg_uart_onoff_asic.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_onoff_asic.v (revision 154) @@ -0,0 +1,269 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + + + integer test_nr; + integer test_var; + + integer dco_clk_counter; + always @ (negedge dco_clk) + dco_clk_counter <= dco_clk_counter+1; + + integer dbg_clk_counter; + always @ (negedge dbg_clk) + dbg_clk_counter <= dbg_clk_counter+1; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + `ifdef ASIC + test_nr = 0; + #1 dbg_en = 0; + repeat(30) @(posedge dco_clk); + stimulus_done = 0; + + // Make sure the CPU always starts executing when the + // debug interface is disabled during POR. + // Also make sure that the debug interface clock is stopped + // and that it is under reset + //-------------------------------------------------------- + dbg_en = 0; + test_nr = 1; + + @(negedge dco_clk) dbg_clk_counter = 0; + + repeat(300) @(posedge dco_clk); + if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); + if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) ====="); + if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) ====="); + test_var = r14; + + + // Make sure that enabling the debug interface after the POR + // don't stop the cpu + // Also make sure that the debug interface clock is running + // and that its reset is released + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 2; + + @(negedge dco_clk) dbg_clk_counter = 0; + + repeat(300) @(posedge dco_clk); + if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 ====="); + if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) ====="); + if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) ====="); + + + // Make sure that disabling the CPU with debug enabled + // will stop the CPU + // Also make sure that the debug interface clock is stopped + // and that it is NOT under reset + //-------------------------------------------------------- + cpu_en = 0; + dbg_en = 1; + test_nr = 3; + + #(6*50); + test_var = r14; + dbg_clk_counter = 0; + + #(300*50); + if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) ====="); + if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) ====="); + if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) ====="); + + cpu_en = 1; + repeat(6) @(negedge dco_clk); + + + // Create POR with debug enable and observe the + // behavior depending on the DBG_RST_BRK_EN define + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 4; + + @(posedge dco_clk); // Generate POR + reset_n = 1'b0; + @(posedge dco_clk); + reset_n = 1'b1; + + repeat(300) @(posedge dco_clk); + `ifdef DBG_RST_BRK_EN + if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); + `else + if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); + `endif + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); + `else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); + `endif + + + // Make sure that DBG_EN resets the debug interface + //-------------------------------------------------------- + test_nr = 5; + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge dco_clk); + dbg_uart_wr(CPU_CTL, 16'h0000); + dbg_uart_wr(MEM_DATA, 16'haa55); + dbg_uart_rd(CPU_CTL); + if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); + + + test_var = r14; // Backup the current register value + + + @(posedge dco_clk); // Resets the debug interface + dbg_en = 1'b0; + repeat(2) @(posedge dco_clk); + dbg_en = 1'b1; + + // Make sure that the register was not reseted + if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); + repeat(2) @(posedge dco_clk); + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `endif + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Make sure that RESET_N resets the debug interface + //-------------------------------------------------------- + test_nr = 6; + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge dco_clk); + dbg_uart_wr(CPU_CTL, 16'h0000); + dbg_uart_wr(MEM_DATA, 16'haa55); + dbg_uart_rd(CPU_CTL); + if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); + + test_nr = 7; + + @(posedge dco_clk); // Generates POR + reset_n = 1'b0; + repeat(2) @(posedge dco_clk); + reset_n = 1'b1; + + // Make sure that the register was reseted + if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); + repeat(2) @(posedge dco_clk); + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + test_nr = 8; + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `endif + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + test_nr = 9; + + // Generate IRQ to terminate the test pattern + irq[1] = 1'b1; + @(r13); + irq[1] = 1'b0; + + stimulus_done = 1; + + `else + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (this test is not supported in FPGA mode) |"); + $display(" ==============================================="); + $finish; + `endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_onoff_asic.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_halt_irq.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_halt_irq.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_halt_irq.s43 (revision 154) @@ -0,0 +1,99 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* SERIAL DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the serial debug interface: */ +/* - Interrupts when going out of halt mode. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +main: + ; Disable interrupts + dint + mov.b #0x00, &P1IE + + + /* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */ + + mov #DMEM_250, r1 ; Initialize stack + + mov.b #0x0001, &P1IE ; Enable GPIO interrupt + + eint ; Enable Global interrupts + + mov #0x0000, r13; + mov #0x0000, r14; + mov #DMEM_200, r15; +infinite_loop: + inc r13 + bit #0x0002, &P1IN + jz infinite_loop + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT ROUTINES --------------- */ + +PORT1_VECTOR: + mov.b &P1IFG, 0(r15) + mov.b #0x00, &P1IFG + mov #0xaaaa, r14; + reti + + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word PORT1_VECTOR ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_halt_irq.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_onoff.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_onoff.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_onoff.v (revision 154) @@ -0,0 +1,218 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + + + integer test_nr; + integer test_var; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + `ifdef ASIC + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (this test is not supported in ASIC mode) |"); + $display(" ==============================================="); + $finish; + `else + test_nr = 0; + #1 dbg_en = 0; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // Make sure the CPU always starts executing when the + // debug interface is disabled during POR. + //-------------------------------------------------------- + dbg_en = 0; + test_nr = 1; + + repeat(300) @(posedge mclk); + if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); + test_var = r14; + + + // Make sure that enabling the debug interface after the POR + // don't stop the cpu + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 2; + + repeat(300) @(posedge mclk); + if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 ====="); + + + // Create POR with debug enable and observe the + // behavior depending on the DBG_RST_BRK_EN define + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 3; + + @(posedge mclk); // Generate POR + reset_n = 1'b0; + @(posedge mclk); + reset_n = 1'b1; + + repeat(300) @(posedge mclk); +`ifdef DBG_RST_BRK_EN + if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); +`else + if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); +`endif + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); +`else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); +`endif + + + // Make sure that DBG_EN resets the debug interface + //-------------------------------------------------------- + test_nr = 4; + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge mclk); + dbg_i2c_wr(CPU_CTL, 16'h0000); + dbg_i2c_wr(MEM_DATA, 16'haa55); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); + + + test_var = r14; // Backup the current register value + + + @(posedge mclk); // Resets the debug interface + dbg_en = 1'b0; + repeat(2) @(posedge mclk); + dbg_en = 1'b1; + + // Make sure that the register was not reseted + if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); + repeat(2) @(posedge mclk); + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`endif + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Make sure that RESET_N resets the debug interface + //-------------------------------------------------------- + test_nr = 5; + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge mclk); + dbg_i2c_wr(CPU_CTL, 16'h0000); + dbg_i2c_wr(MEM_DATA, 16'haa55); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); + + test_nr = 6; + + @(posedge mclk); // Generates POR + reset_n = 1'b0; + repeat(2) @(posedge mclk); + reset_n = 1'b1; + + // Make sure that the register was reseted + if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); + repeat(2) @(posedge mclk); + + test_nr = 7; + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`endif + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + test_nr = 8; + + // Generate IRQ to terminate the test pattern + irq[1] = 1'b1; + @(r13); + irq[1] = 1'b0; + + stimulus_done = 1; + + `endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_onoff.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_onoff.s43 =================================================================== --- sim/rtl_sim/src/dbg_uart_onoff.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_uart_onoff.s43 (revision 154) @@ -0,0 +1,87 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +main: + mov #DMEM_250, r1 ; Initialize stack + mov #0x0000, r15 + mov #0x0000, r14 + mov #0x0000, r13 + nop + eint + +test_loop: + add #0x0001, r14 + cmp #0xffff, r13 + jne test_loop + + mov #0x1000, r15 + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + +isr_1: + mov #0xffff, r13 + reti + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word isr_1 ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_uart_onoff.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_rdwr.v =================================================================== --- sim/rtl_sim/src/dbg_uart_rdwr.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_rdwr.v (revision 154) @@ -0,0 +1,209 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE: RD / WR */ +/*---------------------------------------------------------------------------*/ +/* Test the UART debug interface: */ +/* - Check RD/WR access to all adressable */ +/* debug registers. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +reg [2:0] cpu_version; +reg cpu_asic; +reg [4:0] user_version; +reg [6:0] per_space; +reg mpy_info; +reg [8:0] dmem_size; +reg [5:0] pmem_size; +reg [31:0] dbg_id; + +// Set oMSP parameters for later check +defparam dut.INST_NR = 8'h12; +defparam dut.TOTAL_NR = 8'h34; + +integer ii; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + // STOP CPU + dbg_uart_wr(CPU_CTL , 16'h0001); + + // TEST READ/WR TO ALL DEBUG REGISTERS + //-------------------------------------------------------- + + cpu_version = `CPU_VERSION; +`ifdef ASIC + cpu_asic = 1'b1; +`else + cpu_asic = 1'b0; +`endif + user_version = `USER_VERSION; + per_space = (`PER_SIZE >> 9); +`ifdef MULTIPLIER + mpy_info = 1'b1; +`else + mpy_info = 1'b0; +`endif + dmem_size = (`DMEM_SIZE >> 7); + pmem_size = (`PMEM_SIZE >> 10); + + dbg_id = {pmem_size, + dmem_size, + mpy_info, + per_space, + user_version, + cpu_asic, + cpu_version}; + + // Check reset value + for ( ii=0; ii < 64; ii=ii+1) + begin + dbg_uart_rd(ii[7:0]); + + case(ii) + 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 1 ERROR (CPU_ID_LO)"); + 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)"); + 2 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)"); + 3 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)"); + 24 : if (dbg_uart_buf !== 16'h3412) tb_error("READ 1 ERROR (CPU_NR)"); + default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR"); + endcase + end + + // Write access + for ( ii=0; ii < 64; ii=ii+1) + begin + // Skip write for MEM_CNT + if (ii!=7) + dbg_uart_wr(ii[7:0] , 16'hffff); + end + + // Read value back + for ( ii=0; ii < 64; ii=ii+1) + begin + dbg_uart_rd(ii[7:0]); + + case(ii) + 0 : if (dbg_uart_buf !== dbg_id[15:0]) tb_error("READ 2 ERROR (CPU_ID_LO)"); + 1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)"); + 2 : if (dbg_uart_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)"); + 3 : if ((dbg_uart_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)"); + 4 : if (dbg_uart_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)"); + 5 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)"); + 6 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)"); + 7 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)"); +`ifdef DBG_HWBRK_0 + `ifdef DBG_HWBRK_RANGE + 8 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)"); + 9 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)"); + `else + 8 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)"); + 9 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)"); + `endif + 10 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)"); + 11 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)"); +`endif +`ifdef DBG_HWBRK_1 + `ifdef DBG_HWBRK_RANGE + 12 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)"); + 13 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)"); + `else + 12 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)"); + 13 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)"); + `endif + 14 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)"); + 15 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)"); +`endif +`ifdef DBG_HWBRK_2 + `ifdef DBG_HWBRK_RANGE + 16 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)"); + 17 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)"); + `else + 16 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)"); + 17 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)"); + `endif + 18 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)"); + 19 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)"); +`endif +`ifdef DBG_HWBRK_3 + `ifdef DBG_HWBRK_RANGE + 20 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)"); + 21 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)"); + `else + 20 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)"); + 21 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)"); + `endif + 22 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)"); + 23 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)"); +`endif + 24 : if (dbg_uart_buf !== 16'h3412) tb_error("READ 2 ERROR (CPU_NR)"); + default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR"); + endcase + end + + + dbg_uart_wr(CPU_CTL , 16'h0002); + repeat(10) @(posedge mclk); + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_rdwr.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_cpu.v =================================================================== --- sim/rtl_sim/src/dbg_uart_cpu.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_cpu.v (revision 154) @@ -0,0 +1,223 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + + + integer my_test; + integer test_var; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // STOP, FREEZE, ISTEP, RUN + //-------------------------------------------------------- + + dbg_uart_wr(CPU_STAT, 16'h00ff); // HALT + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 ====="); + + dbg_uart_wr(CPU_CTL, 16'h0001); // HALT + repeat(10) @(posedge mclk); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var !== inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function ====="); + + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0001) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 ====="); + + if (dbg_freeze !== 1'b0) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 ====="); + dbg_uart_wr(CPU_CTL, 16'h0010); // FREEZE WITH BREAK + repeat(10) @(posedge mclk); + if (dbg_freeze !== 1'b1) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 ====="); + + + test_var = r14; + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+1)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 ====="); + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+2)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 ====="); + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP + repeat(12) @(posedge mclk); + if (test_var !== (r14+3)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 ====="); + + + test_var = inst_number; + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + repeat(50) @(posedge mclk); + if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 ====="); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 ====="); + + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 ====="); + + + + // RESET / BREAK ON RESET + //-------------------------------------------------------- + + test_var = r14; + dbg_uart_wr(CPU_CTL, 16'h0040); // RESET CPU + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 ====="); + if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 ====="); + dbg_uart_wr(CPU_CTL, 16'h0000); // RELEASE RESET + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 ====="); + if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 ====="); + if (test_var >= r14) tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 ====="); + dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 ====="); + + + test_var = r14; + dbg_uart_wr(CPU_CTL, 16'h0060); // RESET & BREAK ON RESET + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 ====="); + if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 ====="); + dbg_uart_wr(CPU_CTL, 16'h0020); // RELEASE RESET + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0005) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 ====="); + if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 ====="); + repeat(10) @(posedge mclk); + test_var = inst_number; + repeat(50) @(posedge mclk); + if (test_var !== inst_number) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 ====="); + if (r0 !== irq_vect_15) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 ====="); + + dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0001) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 ====="); + + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 ====="); + + + // SOFTWARE BREAKPOINT + //-------------------------------------------------------- + + dbg_uart_wr(CPU_CTL, 16'h0048); // RESET & ENABLE SOFTWARE BREAKPOINT + dbg_uart_wr(CPU_CTL, 16'h0008); // RELEASE RESET + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h000D) tb_error("====== SOFTWARE BREAKPOINT: test 1 ====="); + if (r0 !== ('h10000-`PMEM_SIZE+'h12)) tb_error("====== SOFTWARE BREAKPOINT: test 2 ====="); + dbg_uart_wr(CPU_STAT, 16'h000C); // CLEAR STATUS + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 3 ====="); + + // Replace software breakpoint with a mov #2, r15 (opcode=0x432f) + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12)); + dbg_uart_wr(MEM_DATA, 16'h432f); + dbg_uart_wr(MEM_CTL, 16'h0003); + + // Dummy write + dbg_uart_wr(MEM_ADDR, 16'hff00); + dbg_uart_wr(MEM_DATA, 16'h1234); + dbg_uart_wr(MEM_CTL, 16'h0003); + + // RUN + dbg_uart_wr(CPU_CTL, 16'h000A); + repeat(20) @(posedge mclk); + if (r15 !== 16'h0002) tb_error("====== SOFTWARE BREAKPOINT: test 4 ====="); + + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0009) tb_error("====== SOFTWARE BREAKPOINT: test 5 ====="); + if (r0 !== ('h10000-`PMEM_SIZE+'h16)) tb_error("====== SOFTWARE BREAKPOINT: test 6 ====="); + dbg_uart_wr(CPU_STAT, 16'h0008); // CLEAR STATUS + dbg_uart_rd(CPU_STAT); // READ STATUS + if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 7 ====="); + + + // Replace software breakpoint with a mov #4, r15 (opcode=0x422f) + dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16)); + dbg_uart_wr(MEM_DATA, 16'h422f); + dbg_uart_wr(MEM_CTL, 16'h0003); + + // Dummy write + dbg_uart_wr(MEM_ADDR, 16'hff00); + dbg_uart_wr(MEM_DATA, 16'h5678); + dbg_uart_wr(MEM_CTL, 16'h0003); + + // RUN + dbg_uart_wr(CPU_CTL, 16'h000A); + repeat(20) @(posedge mclk); + if (r15 !== 16'h0004) tb_error("====== SOFTWARE BREAKPOINT: test 8 ====="); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_cpu.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_hwbrk2.v =================================================================== --- sim/rtl_sim/src/dbg_uart_hwbrk2.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_hwbrk2.v (revision 154) @@ -0,0 +1,680 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 2. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev$ */ +/* $LastChangedBy$ */ +/* $LastChangedDate$ */ +/*===========================================================================*/ + +`define LONG_TIMEOUT + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART +`ifdef DBG_HWBRK_2 + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // SEND UART SYNCHRONIZATION FRAME + dbg_uart_tx(DBG_SYNC); + + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES + //---------------------------------------------------------------------- + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + + // CONFIGURE BREAKPOINT (DISABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK2_CTL, 16'h000C); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RESET & BREAK + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CHECK + if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 ====="); + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04)); + dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18)); + dbg_uart_wr(BRK2_CTL, 16'h000D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 ====="); + + // RE-RUN + dbg_uart_wr(BRK2_ADDR0, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 ====="); + + + + // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE + //---------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + // CONFIGURE BREAKPOINT(ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE-'h100)); + dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h20)); + dbg_uart_wr(BRK2_CTL, 16'h001D); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ + //---------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK2_CTL, 16'h0005); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 ====="); + if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE + //----------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK2_CTL, 16'h0006); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE + //---------------------------------------------------------------------------------- + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008)); + dbg_uart_wr(BRK2_CTL, 16'h0007); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0002); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0008); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0001); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0004); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 ====="); + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ + //---------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK2_CTL, 16'h0015); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 ====="); + if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE + //----------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK2_CTL, 16'h0016); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 ====="); + end + + + // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE + //---------------------------------------------------------------------------------- + if (`HWBRK_RANGE) + begin + + // RESET, BREAK & CLEAR STATUS + dbg_uart_wr(CPU_CTL, 16'h0060); + dbg_uart_wr(CPU_CTL, 16'h0020); + dbg_uart_wr(BRK2_STAT, 16'h00ff); + dbg_uart_wr(CPU_STAT, 16'h00ff); + + + // CONFIGURE BREAKPOINT (ENABLED) & RUN + dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001)); + dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005)); + dbg_uart_wr(BRK2_CTL, 16'h0017); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 ====="); + if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 ====="); + if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 ====="); + if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0010); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 ====="); + + // RE-RUN + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + // RE-CHECK + if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 ====="); + if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 ====="); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 ====="); + dbg_uart_rd(BRK2_STAT); + if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 ====="); + dbg_uart_wr(BRK2_STAT, 16'h0020); + dbg_uart_rd(CPU_STAT); + if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 ====="); + + end + + // RE-RUN UNTIL END OF PATTERN + dbg_uart_wr(BRK2_CTL, 16'h0000); + dbg_uart_wr(CPU_CTL, 16'h0002); + repeat(100) @(posedge mclk); + + + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (hardware breakpoint unit 2 not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_hwbrk2.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_halt_irq.v =================================================================== --- sim/rtl_sim/src/dbg_uart_halt_irq.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_halt_irq.v (revision 154) @@ -0,0 +1,101 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* SERIAL DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the serial debug interface: */ +/* - Interrupts when going out of halt mode. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +reg [15:0] r13_bkup; + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + #1 dbg_en = 1; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // Initialize the debug interface and send the CPU in halt mode + dbg_uart_tx(DBG_SYNC); + +`ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN +`endif + + // Wait until software initialization is done + if (r15!==(`PER_SIZE+16'h0000)) + @(r15==(`PER_SIZE+16'h0000)); + + + dbg_uart_wr(CPU_CTL, 16'h0001); // HALT + repeat(150) @(posedge mclk); + r13_bkup = r13; + + // Generate a GPIO interrupt + p1_din[0] = 1'b1; + repeat(150) @(posedge mclk); + + // Re-start the CPU + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + repeat(150) @(posedge mclk); + + // Make sure the interrupt was serviced + if (r14 !== 16'haaaa) tb_error("====== Interrupt was not properly serviced ====="); + + // Make sure the program resumed execution when coming back from IRQ + if (r13 === r13_bkup) tb_error("====== Program didn't properly resumed execution ====="); + + + p1_din[1] = 1'b1; + stimulus_done = 1; +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_halt_irq.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk1.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk1.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk1.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 1. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_hwbrk1.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_hwbrk3.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_hwbrk3.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_hwbrk3.s43 (revision 154) @@ -0,0 +1,100 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later versixon. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - Check Hardware breakpoint unit 3. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + + +WAIT_FUNC: + inc &DMEM_206 + inc &DMEM_202 + inc &DMEM_204 + inc &DMEM_200 + inc &DMEM_208 + mov &DMEM_204, r10 + mov &DMEM_208, r9 + dec r14 + jnz WAIT_FUNC + ret + +main: + mov #DMEM_250, r1 ; # Initialize stack pointer + mov #0x0000, &DMEM_200 + mov #0x0000, r15 + + /* -------------- ACLK GENERATION ----------------- */ + + mov #0x0001, r15 + mov #0x0000, &DMEM_200 + mov #0x0001, &DMEM_202 + mov #0x0002, &DMEM_204 + mov #0x0003, &DMEM_206 + mov #0x0004, &DMEM_208 + mov #0x0080, r14 + call #WAIT_FUNC + + mov #0x1000, r15 + + + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word end_of_test ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_hwbrk3.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_uart_onoff.v =================================================================== --- sim/rtl_sim/src/dbg_uart_onoff.v (nonexistent) +++ sim/rtl_sim/src/dbg_uart_onoff.v (revision 154) @@ -0,0 +1,227 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + + + integer test_nr; + integer test_var; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_UART + `ifdef ASIC + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (this test is not supported in ASIC mode) |"); + $display(" ==============================================="); + $finish; + `else + test_nr = 0; + #1 dbg_en = 0; + repeat(30) @(posedge mclk); + stimulus_done = 0; + + // Make sure the CPU always starts executing when the + // debug interface is disabled during POR. + //-------------------------------------------------------- + dbg_en = 0; + test_nr = 1; + + repeat(300) @(posedge mclk); + if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); + test_var = r14; + + + // Make sure that enabling the debug interface after the POR + // don't stop the cpu + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 2; + + repeat(300) @(posedge mclk); + if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 ====="); + + + // Create POR with debug enable and observe the + // behavior depending on the DBG_RST_BRK_EN define + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 3; + + @(posedge mclk); // Generate POR + reset_n = 1'b0; + @(posedge mclk); + reset_n = 1'b1; + + repeat(300) @(posedge mclk); +`ifdef DBG_RST_BRK_EN + if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); +`else + if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); +`endif + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); +`else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); +`endif + + + // Make sure that DBG_EN resets the debug interface + //-------------------------------------------------------- + test_nr = 4; + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge mclk); + dbg_uart_wr(CPU_CTL, 16'h0000); + dbg_uart_wr(MEM_DATA, 16'haa55); + dbg_uart_rd(CPU_CTL); + if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); + + + test_var = r14; // Backup the current register value + + + @(posedge mclk); // Resets the debug interface + dbg_en = 1'b0; + repeat(2) @(posedge mclk); + dbg_en = 1'b1; + + // Make sure that the register was not reseted + if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); + repeat(2) @(posedge mclk); + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`endif + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Make sure that RESET_N resets the debug interface + //-------------------------------------------------------- + test_nr = 5; + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge mclk); + dbg_uart_wr(CPU_CTL, 16'h0000); + dbg_uart_wr(MEM_DATA, 16'haa55); + dbg_uart_rd(CPU_CTL); + if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); + + test_nr = 6; + + @(posedge mclk); // Generates POR + reset_n = 1'b0; + repeat(2) @(posedge mclk); + reset_n = 1'b1; + + // Make sure that the register was reseted + if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); + repeat(2) @(posedge mclk); + + // Send uart synchronization frame + dbg_uart_tx(DBG_SYNC); + + test_nr = 7; + + // Check CPU_CTL reset value + dbg_uart_rd(CPU_CTL); +`ifdef DBG_RST_BRK_EN + if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`else + if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); +`endif + dbg_uart_rd(MEM_DATA); + if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Let the CPU run + dbg_uart_wr(CPU_CTL, 16'h0002); + + test_nr = 8; + + // Generate IRQ to terminate the test pattern + irq[1] = 1'b1; + @(r13); + irq[1] = 1'b0; + + stimulus_done = 1; + + `endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface UART not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_uart_onoff.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_onoff_asic.v =================================================================== --- sim/rtl_sim/src/dbg_i2c_onoff_asic.v (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_onoff_asic.v (revision 154) @@ -0,0 +1,260 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the debug interface: */ +/* - CPU Control features. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 95 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */ +/*===========================================================================*/ + + + integer test_nr; + integer test_var; + + integer dco_clk_counter; + always @ (negedge dco_clk) + dco_clk_counter <= dco_clk_counter+1; + + integer dbg_clk_counter; + always @ (negedge dbg_clk) + dbg_clk_counter <= dbg_clk_counter+1; + + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); +`ifdef DBG_EN +`ifdef DBG_I2C + `ifdef ASIC + test_nr = 0; + #1 dbg_en = 0; + repeat(30) @(posedge dco_clk); + stimulus_done = 0; + + // Make sure the CPU always starts executing when the + // debug interface is disabled during POR. + // Also make sure that the debug interface clock is stopped + // and that it is under reset + //-------------------------------------------------------- + dbg_en = 0; + test_nr = 1; + + @(negedge dco_clk) dbg_clk_counter = 0; + + repeat(300) @(posedge dco_clk); + if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 ====="); + if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) ====="); + if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) ====="); + test_var = r14; + + + // Make sure that enabling the debug interface after the POR + // don't stop the cpu + // Also make sure that the debug interface clock is running + // and that its reset is released + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 2; + + @(negedge dco_clk) dbg_clk_counter = 0; + + repeat(300) @(posedge dco_clk); + if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 ====="); + if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) ====="); + if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) ====="); + + + // Make sure that disabling the CPU with debug enabled + // will stop the CPU + // Also make sure that the debug interface clock is stopped + // and that it is NOT under reset + //-------------------------------------------------------- + cpu_en = 0; + dbg_en = 1; + test_nr = 3; + + #(6*50); + test_var = r14; + dbg_clk_counter = 0; + + #(300*50); + if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) ====="); + if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) ====="); + if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) ====="); + + cpu_en = 1; + repeat(6) @(negedge dco_clk); + + + // Create POR with debug enable and observe the + // behavior depending on the DBG_RST_BRK_EN define + //-------------------------------------------------------- + dbg_en = 1; + test_nr = 4; + + @(posedge dco_clk); // Generate POR + reset_n = 1'b0; + @(posedge dco_clk); + reset_n = 1'b1; + + repeat(300) @(posedge dco_clk); + `ifdef DBG_RST_BRK_EN + if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 ====="); + `else + if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 ====="); + `endif + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); + `else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 ====="); + `endif + + + // Make sure that DBG_EN resets the debug interface + //-------------------------------------------------------- + test_nr = 5; + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge dco_clk); + dbg_i2c_wr(CPU_CTL, 16'h0000); + dbg_i2c_wr(MEM_DATA, 16'haa55); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 ====="); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 ====="); + + + test_var = r14; // Backup the current register value + + + @(posedge dco_clk); // Resets the debug interface + dbg_en = 1'b0; + repeat(2) @(posedge dco_clk); + dbg_en = 1'b1; + + // Make sure that the register was not reseted + if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 ====="); + repeat(2) @(posedge dco_clk); + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `endif + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Make sure that RESET_N resets the debug interface + //-------------------------------------------------------- + test_nr = 6; + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + repeat(300) @(posedge dco_clk); + dbg_i2c_wr(CPU_CTL, 16'h0000); + dbg_i2c_wr(MEM_DATA, 16'haa55); + dbg_i2c_rd(CPU_CTL); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 ====="); + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 ====="); + + test_nr = 7; + + @(posedge dco_clk); // Generates POR + reset_n = 1'b0; + repeat(2) @(posedge dco_clk); + reset_n = 1'b1; + + // Make sure that the register was reseted + if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 ====="); + repeat(2) @(posedge dco_clk); + + test_nr = 8; + + // Check CPU_CTL reset value + dbg_i2c_rd(CPU_CTL); + `ifdef DBG_RST_BRK_EN + if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `else + if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 ====="); + `endif + dbg_i2c_rd(MEM_DATA); + if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 ====="); + + + // Let the CPU run + dbg_i2c_wr(CPU_CTL, 16'h0002); + + test_nr = 9; + + // Generate IRQ to terminate the test pattern + irq[1] = 1'b1; + @(r13); + irq[1] = 1'b0; + + stimulus_done = 1; + + `else + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (this test is not supported in FPGA mode) |"); + $display(" ==============================================="); + $finish; + `endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface I2C not included) |"); + $display(" ==============================================="); + $finish; +`endif +`else + + $display(" ==============================================="); + $display("| SIMULATION SKIPPED |"); + $display("| (serial debug interface not included) |"); + $display(" ==============================================="); + $finish; +`endif + end +

sim/rtl_sim/src/dbg_i2c_onoff_asic.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/dbg_i2c_halt_irq.s43 =================================================================== --- sim/rtl_sim/src/dbg_i2c_halt_irq.s43 (nonexistent) +++ sim/rtl_sim/src/dbg_i2c_halt_irq.s43 (revision 154) @@ -0,0 +1,99 @@ +/*===========================================================================*/ +/* Copyright (C) 2001 Authors */ +/* */ +/* This source file may be used and distributed without restriction provided */ +/* that this copyright statement is not removed from the file and that any */ +/* derivative work contains the original copyright notice and the associated */ +/* disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This source is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this source; if not, write to the Free Software Foundation, */ +/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +/* */ +/*===========================================================================*/ +/* SERIAL DEBUG INTERFACE */ +/*---------------------------------------------------------------------------*/ +/* Test the serial debug interface: */ +/* - Interrupts when going out of halt mode. */ +/* */ +/* Author(s): */ +/* - Olivier Girard, olgirard@gmail.com */ +/* */ +/*---------------------------------------------------------------------------*/ +/* $Rev: 19 $ */ +/* $LastChangedBy: olivier.girard $ */ +/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ +/*===========================================================================*/ + +.include "pmem_defs.asm" + +.global main + +main: + ; Disable interrupts + dint + mov.b #0x00, &P1IE + + + /* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */ + + mov #DMEM_250, r1 ; Initialize stack + + mov.b #0x0001, &P1IE ; Enable GPIO interrupt + + eint ; Enable Global interrupts + + mov #0x0000, r13; + mov #0x0000, r14; + mov #DMEM_200, r15; +infinite_loop: + inc r13 + bit #0x0002, &P1IN + jz infinite_loop + + + /* ---------------------- END OF TEST --------------- */ +end_of_test: + nop + br #0xffff + + + /* ---------------------- INTERRUPT ROUTINES --------------- */ + +PORT1_VECTOR: + mov.b &P1IFG, 0(r15) + mov.b #0x00, &P1IFG + mov #0xaaaa, r14; + reti + + + + /* ---------------------- INTERRUPT VECTORS --------------- */ + +.section .vectors, "a" +.word end_of_test ; Interrupt 0 (lowest priority) +.word end_of_test ; Interrupt 1 +.word PORT1_VECTOR ; Interrupt 2 +.word end_of_test ; Interrupt 3 +.word end_of_test ; Interrupt 4 +.word end_of_test ; Interrupt 5 +.word end_of_test ; Interrupt 6 +.word end_of_test ; Interrupt 7 +.word end_of_test ; Interrupt 8 +.word end_of_test ; Interrupt 9 +.word end_of_test ; Interrupt 10 Watchdog timer +.word end_of_test ; Interrupt 11 +.word end_of_test ; Interrupt 12 +.word end_of_test ; Interrupt 13 +.word end_of_test ; Interrupt 14 NMI +.word main ; Interrupt 15 (highest priority) RESET

sim/rtl_sim/src/dbg_i2c_halt_irq.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: sim/rtl_sim/src/sfr.s43 =================================================================== --- sim/rtl_sim/src/sfr.s43 (revision 151) +++ sim/rtl_sim/src/sfr.s43 (revision 154) @@ -136,7 +136,23 @@ mov #0x5003, r15 + /* ------- READ/WRITE CPU_NR ------ */ + + mov #0x6000, r15 + + mov &CPU_NR, r10 + mov #0x6001, r15 + + mov 0x5554, &CPU_NR + mov &CPU_NR, r10 + mov #0x6002, r15 + mov 0xAAAA, &CPU_NR + mov &CPU_NR, r10 + mov #0x6003, r15 + + + /* ---------------------- END OF TEST --------------- */ end_of_test: nop

/sim/rtl_sim/src/dbg_i2c_hwbrk2.v