URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core
- from Rev 86 to Rev 91
- ↔ Reverse comparison
Rev 86 → Rev 91
/rtl/verilog/omsp_frontend.v
226,7 → 226,7
else if (exec_done) inst_irq_rst <= 1'b0; |
|
// Detect other interrupts |
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE)); |
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE)); |
|
// Select interrupt vector |
reg [3:0] irq_num; |
/sim/rtl_sim/run/run_all
1,4 → 1,4
!/bin/bash |
#!/bin/bash |
|
# Disable waveform dumping |
OMSP_NODUMP=1 |
60,6 → 60,7
../bin/msp430sim dbg_hwbrk1 | tee dbg_hwbrk1.log |
../bin/msp430sim dbg_hwbrk2 | tee dbg_hwbrk2.log |
../bin/msp430sim dbg_hwbrk3 | tee dbg_hwbrk3.log |
../bin/msp430sim dbg_halt_irq | tee dbg_halt_irq.log |
|
# Watchdog test patterns |
../bin/msp430sim wdt_interval | tee wdt_interval.log |
/sim/rtl_sim/src/dbg_halt_irq.v
0,0 → 1,75
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* SERIAL DEBUG INTERFACE */ |
/*---------------------------------------------------------------------------*/ |
/* Test the serial debug interface: */ |
/* - Interrupts when going out of halt mode. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
reg [15:0] r13_bkup; |
|
initial |
begin |
$display(" ==============================================="); |
$display("| START SIMULATION |"); |
$display(" ==============================================="); |
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
// Wait until software initialization is done |
@(r15==16'h0200); |
|
// Initialize the debug interface and send the CPU in halt mode |
dbg_uart_tx(DBG_SYNC); |
dbg_uart_wr(CPU_CTL, 16'h0001); // HALT |
repeat(150) @(posedge mclk); |
r13_bkup = r13; |
|
// Generate a GPIO interrupt |
p1_din[0] = 1'b1; |
repeat(150) @(posedge mclk); |
|
// Re-start the CPU |
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN |
repeat(150) @(posedge mclk); |
|
// Make sure the interrupt was serviced |
if (r14 !== 16'haaaa) tb_error("====== Interrupt was not properly serviced ====="); |
|
// Make sure the program resumed execution when coming back from IRQ |
if (r13 === r13_bkup) tb_error("====== Program didn't properly resumed execution ====="); |
|
|
p1_din[1] = 1'b1; |
stimulus_done = 1; |
end |
|
sim/rtl_sim/src/dbg_halt_irq.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: sim/rtl_sim/src/dbg_halt_irq.s43
===================================================================
--- sim/rtl_sim/src/dbg_halt_irq.s43 (nonexistent)
+++ sim/rtl_sim/src/dbg_halt_irq.s43 (revision 91)
@@ -0,0 +1,105 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* SERIAL DEBUG INTERFACE */
+/*---------------------------------------------------------------------------*/
+/* Test the serial debug interface: */
+/* - Interrupts when going out of halt mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 19 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set P1IN, 0x0020
+.set P1OUT, 0x0021
+.set P1DIR, 0x0022
+.set P1IFG, 0x0023
+.set P1IES, 0x0024
+.set P1IE, 0x0025
+.set P1SEL, 0x0026
+
+main:
+ ; Disable interrupts
+ dint
+ mov.b #0x00, &P1IE
+
+
+ /* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */
+
+ mov #0x0250, r1 ; Initialize stack
+
+ mov.b #0x0001, &P1IE ; Enable GPIO interrupt
+
+ eint ; Enable Global interrupts
+
+ mov #0x0000, r13;
+ mov #0x0000, r14;
+ mov #0x0200, r15;
+infinite_loop:
+ inc r13
+ bit #0x0002, &P1IN
+ jz infinite_loop
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+ /* ---------------------- INTERRUPT ROUTINES --------------- */
+
+PORT1_VECTOR:
+ mov.b &P1IFG, 0(r15)
+ mov.b #0x00, &P1IFG
+ mov #0xaaaa, r14;
+ reti
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word PORT1_VECTOR ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
sim/rtl_sim/src/dbg_halt_irq.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property