URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
- from Rev 80 to Rev 81
- ↔ Reverse comparison
Rev 80 → Rev 81
/verilog/smartgen/pmem_2kB.v
14,8 → 14,7
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VCC VCC_1_net(.Y(VCC)); |
GND GND_1_net(.Y(GND)); |
RAM4K9 #( .MEMORYFILE() ) |
pmem_2kB_R0C0(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
RAM4K9 pmem_2kB_R0C0(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), |
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), |
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), |
36,8 → 35,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), |
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[1]), .DOUTB0( |
RD[0])); |
RAM4K9 #( .MEMORYFILE() ) |
pmem_2kB_R0C1(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
RAM4K9 pmem_2kB_R0C1(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), |
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), |
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), |
58,8 → 56,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), |
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[3]), .DOUTB0( |
RD[2])); |
RAM4K9 #( .MEMORYFILE() ) |
pmem_2kB_R0C3(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
RAM4K9 pmem_2kB_R0C3(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), |
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), |
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), |
80,8 → 77,7
.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), |
.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[7]), .DOUTB0( |
RD[6])); |
RAM4K9 #( .MEMORYFILE() ) |
pmem_2kB_R0C2(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
RAM4K9 pmem_2kB_R0C2(.ADDRA11(GND), .ADDRA10(WADDR[10]), |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), |
.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), |
.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), |
/verilog/smartgen/dmem_128B.v
14,8 → 14,7
|
VCC VCC_1_net(.Y(VCC)); |
GND GND_1_net(.Y(GND)); |
RAM4K9 #( .MEMORYFILE() ) |
dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9( |
RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9( |
GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]), |
.ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]), |
.ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]), |
/verilog/openMSP430_fpga.v
134,16 → 134,16
|
|
parameter FCLKA = 48.0; |
parameter M = 7'd8; |
parameter N = 7'd3; |
parameter U = 5'd8; |
parameter M = 7'd6; |
parameter N = 7'd9; |
parameter U = 5'd2; |
parameter V = 5'd1; |
parameter W = 5'd1; |
|
parameter FVCO = FCLKA*M/N; // 128 MHz |
parameter FVCO = FCLKA*M/N; // 32 MHz |
parameter FGLA = FVCO/U; // 16 MHz |
parameter FGLB = FVCO/V; // 128 MHz |
parameter FGLC = FVCO/W; // 128 MHz |
parameter FGLB = FVCO/V; // 32 MHz |
parameter FGLC = FVCO/W; // 32 MHz |
|
wire [4:0] oadiv = U-5'h01; |
wire [4:0] obdiv = V-5'h01; |
257,11 → 257,35
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.XDLYSEL (1'b0), // System Delay Select (0: no dly; 1:inserts system dly) |
|
.VCOSEL0 (1'b1), // VCO gear control |
.VCOSEL1 (1'b1), |
.VCOSEL2 (1'b1) |
.VCOSEL0 (1'b1), // PLL lock acquisition time (0: Fast with high tracking jitter; 1: Slow with low tracking jitter) |
|
.VCOSEL1 (1'b1), // VCO gear control (see table below) |
.VCOSEL2 (1'b0) |
); |
|
//-------------+--------------------------------------------------------------+ |
// | VCOSEL[2:1] | |
// |---------------+---------------+--------------+---------------| |
// | 00 | 01 | 10 | 11 | |
// VOLTAGE |---------------+---------------+--------------+---------------| |
// | Min. Max. | Min. Max. | Min. Max. | Min. Max. | |
// | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) | |
//-------------+---------------+---------------+--------------+---------------| |
// IGLOO and IGLOO PLUS | |
//-------------+---------------+---------------+--------------+---------------| |
|
|
//-------------+---------------+---------------+--------------+---------------| |
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L | |
//-------------+---------------+---------------+--------------+---------------| |
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|
//-------------+---------------+---------------+--------------+---------------| |
// ProASIC3 and Fusion | |
//-------------+---------------+---------------+--------------+---------------| |
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//-------------+---------------+---------------+--------------+---------------+ |
|
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//============================================================================= |
// 3) PROGRAM AND DATA MEMORIES |