URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
- from Rev 81 to Rev 82
- ↔ Reverse comparison
Rev 81 → Rev 82
/verilog/openMSP430_fpga.v
273,17 → 273,17
//-------------+---------------+---------------+--------------+---------------| |
// IGLOO and IGLOO PLUS | |
//-------------+---------------+---------------+--------------+---------------| |
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// 1.2 V +- 5% | 24 35 | 30 70 | 60 140 | 135 160 | |
// 1.5 V +- 5% | 24 43.75 | 30 87.5 | 60 175 | 135 250 | |
//-------------+---------------+---------------+--------------+---------------| |
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L | |
//-------------+---------------+---------------+--------------+---------------| |
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// 1.2 V +- 5% | 24 35 | 30 70 | 60 140 | 135 250 | |
// 1.5 V +- 5% | 24 43.75 | 30 70 | 60 175 | 135 350 | |
//-------------+---------------+---------------+--------------+---------------| |
// ProASIC3 and Fusion | |
//-------------+---------------+---------------+--------------+---------------| |
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// 1.5 V +- 5% | 24 43.75 | 33.75 87.5 | 67.5 175 | 135 350 | |
//-------------+---------------+---------------+--------------+---------------+ |
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508,7 → 508,7
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assign p1_din = 8'h00; |
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assign led = {cntrl1, p1_dout, p1_dout, cntrl2}; |
assign led = {cntrl1, p1_dout[0], p1_dout[0], cntrl2}; |
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endmodule // openMSP430_fpga |