URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin
- from Rev 98 to Rev 136
- ↔ Reverse comparison
Rev 98 → Rev 136
/ihex2mem.tcl
89,12 → 89,15
} |
|
# MEMH Output |
if [catch {open $out w } f_out] { |
puts "ERROR Cannot create output file $out" |
exit 1 |
if { "$out"=="-"} { |
set f_out stdout |
} else { |
if [catch {open $out w } f_out] { |
puts "ERROR Cannot create output file $out" |
exit 1 |
} |
} |
|
|
#-----------------------------------------------------------------------------# |
# CONVERSION # |
#-----------------------------------------------------------------------------# |
148,6 → 151,9
} |
|
puts $f_out "\n" |
close $f_out |
|
if { "$out"!="-"} { |
close $f_out |
} |
|
exit 0 |
/msp430sim
43,7 → 43,7
echo "USAGE : msp430sim <test name>" |
echo "Example : msp430sim leds" |
echo "" |
echo "In order to switch the verilog simulator, the MYVLOG environment" |
echo "In order to switch the verilog simulator, the OMSP_SIMULATOR environment" |
echo "variable can be set to the following values:" |
echo "" |
echo " - iverilog : Icarus Verilog (default)" |
52,6 → 52,7
echo " - ncverilog : NC-Verilog" |
echo " - vcs : VCS" |
echo " - vsim : Modelsim" |
echo " - isim : Xilinx simulator" |
echo "" |
exit 1 |
fi |
/rtlsim.sh
43,7 → 43,7
echo "ERROR : wrong number of arguments" |
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>" |
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f" |
echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs" |
echo "OMSP_SIMULATOR env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs" |
exit 1 |
fi |
|
70,7 → 70,7
# Start verilog simulation # |
############################################################################### |
|
if [ "${MYVLOG:-iverilog}" = iverilog ]; then |
if [ "${OMSP_SIMULATOR:-iverilog}" = iverilog ]; then |
|
rm -rf simv |
|
92,24 → 92,31
vargs="" |
fi |
|
case $MYVLOG in |
case $OMSP_SIMULATOR in |
cver* ) |
vargs="$vargs +define+VXL" ;; |
vargs="$vargs +define+VXL +define+CVER" ;; |
verilog* ) |
vargs="$vargs +define+VXL" ;; |
ncverilog* ) |
rm -rf INCA_libs |
vargs="$vargs +access+r +define+TRN_FILE" ;; |
vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;; |
vcs* ) |
rm -rf csrc simv* |
vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;; |
vsim ) |
vsim* ) |
# Modelsim |
if [ -d work ]; then vdel -all; fi |
vlib work |
exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all" |
exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all" ;; |
isim ) |
# Xilinx simulator |
rm -rf fuse* isim* |
fuse tb_openMSP430 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/ -i ../../../rtl/verilog/periph/ |
echo "run all" > isim.tcl |
./isim.exe -tclbatch isim.tcl |
exit |
esac |
|
echo "Running: $MYVLOG -f $3 $vargs" |
exec $MYVLOG -f $3 $vargs |
echo "Running: $OMSP_SIMULATOR -f $3 $vargs" |
exec $OMSP_SIMULATOR -f $3 $vargs |
fi |