OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar
    from Rev 202 to Rev 212
    Reverse comparison

Rev 202 → Rev 212

/linker.x File deleted
linker.x Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: linker.msp430.x =================================================================== --- linker.msp430.x (nonexistent) +++ linker.msp430.x (revision 212) @@ -0,0 +1,222 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430") +OUTPUT_ARCH("msp430") +MEMORY { + sfr : ORIGIN = 0x0000, LENGTH = 0x0010 + peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0 + peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100 + ram (wx) : ORIGIN = 0x0200, LENGTH = 0x0100 + rom (rx) : ORIGIN = 0xF000, LENGTH = 0x1000-0x20 + vectors : ORIGIN = 0xffe0, LENGTH = 0x0020 +} +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +PROVIDE (__info_segment_size = 0x80); +__WDTCTL = 0x0120; +__MPY = 0x0130; +__MPYS = 0x0132; +__MAC = 0x0134; +__MACS = 0x0136; +__OP2 = 0x0138; +__RESLO = 0x013A; +__RESHI = 0x013C; +__SUMEXT = 0x013E; + +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + /* .any.{text,rodata,data,bss}{,.*} sections are treated as orphans and + * placed in output sections with available space by linker. Do not list + * them here, or the linker will not consider them orphans. */ + .text : + { + . = ALIGN(2); + KEEP(*(.init .init.*)) + KEEP(*(.init0)) /* Start here after reset. */ + KEEP(*(.init1)) /* User definable. */ + KEEP(*(.init2)) /* Initialize stack. */ + KEEP(*(.init3)) /* Initialize hardware, user definable. */ + KEEP(*(.init4)) /* Copy data to .data, clear bss. */ + KEEP(*(.init5)) /* User definable. */ + KEEP(*(.init6)) /* C++ constructors. */ + KEEP(*(.init7)) /* User definable. */ + KEEP(*(.init8)) /* User definable. */ + KEEP(*(.init9)) /* Call main(). */ + KEEP(*(.fini9)) /* Falls into here after main(). User definable. */ + KEEP(*(.fini8)) /* User definable. */ + KEEP(*(.fini7)) /* User definable. */ + KEEP(*(.fini6)) /* C++ destructors. */ + KEEP(*(.fini5)) /* User definable. */ + KEEP(*(.fini4)) /* User definable. */ + KEEP(*(.fini3)) /* User definable. */ + KEEP(*(.fini2)) /* User definable. */ + KEEP(*(.fini1)) /* User definable. */ + KEEP(*(.fini0)) /* Infinite loop after program termination. */ + KEEP(*(.fini .fini.*)) + . = ALIGN(2); + __ctors_start = .; + KEEP(*(.ctors)) + __ctors_end = .; + __dtors_start = .; + KEEP(*(.dtors)) + __dtors_end = .; + . = ALIGN(2); + *(.text .text.* .gnu.linkonce.t.*) + *(.near.text .near.text.*) + } > REGION_TEXT + .rodata : + { + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.near.rodata .near.rodata.*) + } > REGION_TEXT + . = ALIGN(2); + _etext = .; /* Past last read-only (loadable) segment */ + .data : + { + . = ALIGN(2); + PROVIDE (__data_start = .) ; + PROVIDE (__datastart = .) ; + *(.data .data.* .gnu.linkonce.d.*) + *(.near.data .near.data.*) + . = ALIGN(2); + _edata = .; /* Past last read-write (loadable) segment */ + } > REGION_DATA AT > REGION_TEXT + __data_load_start = LOADADDR(.data); + __data_size = SIZEOF(.data); + .bss : + { + __bss_start = .; + *(.bss .bss.*) + *(.near.bss .near.bss.*) + *(COMMON) + . = ALIGN(2); + __bss_end = .; + } > REGION_DATA + __bss_size = SIZEOF(.bss); + .noinit : + { + . = ALIGN(2); + __noinit_start = .; + *(.noinit .noinit.*) + . = ALIGN(2); + __noinit_end = .; + } > REGION_DATA + . = ALIGN(2); + _end = .; /* Past last write (loadable) segment */ + + /* Values placed in the first 32 entries of a 64-entry interrupt vector + * table. This exists because the FRAM chips place the BSL and JTAG + * passwords at specific offsets that technically fall within the + * interrupt table, but for which no MCU has a corresponding interrupt. + * See https://sourceforge.net/tracker/?func=detail&aid=3554291&group_id=42303&atid=432701 */ + PROVIDE(__vte_0 = 0xffff); + PROVIDE(__vte_1 = 0xffff); + PROVIDE(__vte_2 = 0xffff); + PROVIDE(__vte_3 = 0xffff); + PROVIDE(__vte_4 = 0xffff); + PROVIDE(__vte_5 = 0xffff); + PROVIDE(__vte_6 = 0xffff); + PROVIDE(__vte_7 = 0xffff); + PROVIDE(__vte_8 = 0xffff); + PROVIDE(__vte_9 = 0xffff); + PROVIDE(__vte_10 = 0xffff); + PROVIDE(__vte_11 = 0xffff); + PROVIDE(__vte_12 = 0xffff); + PROVIDE(__vte_13 = 0xffff); + PROVIDE(__vte_14 = 0xffff); + PROVIDE(__vte_15 = 0xffff); + PROVIDE(__vte_16 = 0xffff); + PROVIDE(__vte_17 = 0xffff); + PROVIDE(__vte_18 = 0xffff); + PROVIDE(__vte_19 = 0xffff); + PROVIDE(__vte_20 = 0xffff); + PROVIDE(__vte_21 = 0xffff); + PROVIDE(__vte_22 = 0xffff); + PROVIDE(__vte_23 = 0xffff); + PROVIDE(__vte_24 = 0xffff); + PROVIDE(__vte_25 = 0xffff); + PROVIDE(__vte_26 = 0xffff); + PROVIDE(__vte_27 = 0xffff); + PROVIDE(__vte_28 = 0xffff); + PROVIDE(__vte_29 = 0xffff); + PROVIDE(__vte_30 = 0xffff); + PROVIDE(__vte_31 = 0xffff); + .vectors : + { + __vectors_start = .; + KEEP(*(.vectors*)) + _vectors_end = .; + } > vectors + /* Legacy section, prefer .far.text */ + . = ALIGN(2); + _efartext = .; /* Past last read-only (loadable) segment */ + . = ALIGN(2); + _far_end = .; /* Past last write (loadable) segment */ + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* __stack is the only symbol that the user can override */ + PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram)); + PROVIDE (__data_start_rom = _etext) ; + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; + PROVIDE (__romdatastart = _etext) ; + PROVIDE (__romdataend = _etext + SIZEOF (.data)) ; + PROVIDE (__romdatacopysize = SIZEOF(.data)); +} Index: linker.msp430-elf.x =================================================================== --- linker.msp430-elf.x (nonexistent) +++ linker.msp430-elf.x (revision 212) @@ -0,0 +1,251 @@ +/* ============================================================================ */ +/* Copyright (c) 2014, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F110 devices. */ +/* Version: 1.155 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 + PERIPHERAL_8BIT : ORIGIN = 0x0010, LENGTH = 0x00F0 + PERIPHERAL_16BIT : ORIGIN = 0x0100, LENGTH = 0x0100 + RAM : ORIGIN = 0x0200, LENGTH = 0x0100 + ROM (rx) : ORIGIN = 0xF000, LENGTH = 0x1000-0x20 + VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_port1)) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_port2)) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_timera1)) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_timera0)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15 + __reset_vector : + { + KEEP (*(__interrupt_vector_16)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .rodata : { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + LONG(0); /* Sentinel. */ + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .text : + { + . = ALIGN(2); + PROVIDE (_start = .); + KEEP (*(SORT(.crt_*))) + *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .data : { + . = ALIGN(2); + PROVIDE (__datastart = .); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT>ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + .noinit (NOLOAD) : { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + end = .; + } > RAM + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .MP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* The rest are all not normally part of the runtime image. */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /DISCARD/ : { *(.note.GNU-stack) } +} Index: update.c =================================================================== --- update.c (revision 202) +++ update.c (revision 212) @@ -1,4 +1,3 @@ -#include "msp430x20x3.h" #include "spacewar.h" //************************************************************ @@ -19,7 +18,7 @@ Generates the x, y vectors for the rocket at present angle. Checks the A to D passed into function for any keys pressed. The A to D resistors are selected to generate values in between the ranges checked. If you push multiple buttons -strange results will occure. If no keys are pressed the fire flaag clears. +strange results will occure. If no keys are pressed the fire flaag clears. Rotate counter clockwise increments the angle variable. Rotate clockwise decrements the angle variable. If the thrust key is pressed a scaled value of xsize and ysize is added into the x and y velocity of the rocket @@ -36,17 +35,17 @@ void update(rkt_data *rkt, unsigned int new_a2d) { int i; - + rkt->xsize = bzsin(rkt->ang + 64); // this returns the cosine rkt->ysize = bzsin(rkt->ang); // this returns the sine if(new_a2d > 0xD000){ // rkt rotate CCW ? rkt->ang++; // yes - } + } else { // no if(new_a2d > 0xA000){ // rkt rotate CW ? rkt->ang--; // yes - } + } else { // no if(new_a2d > 0x6000) { // is rkt thrusting rkt->xvel += ((long) rkt->xsize << 6); // yes @@ -65,7 +64,7 @@ break; } } - } + } } else { rkt->flags &= ~fire_bit; // clear fire flag } @@ -83,6 +82,3 @@ } } } - - -
/omsp_system.h
87,7 → 87,8
//----------------------------------------------------------
// SPECIAL FUNCTION REGISTERS
//----------------------------------------------------------
#define IE1 (*(volatile unsigned char *) 0x0000)
#define IE1_set_wdtie() __asm__ __volatile__ ("bis.b #0x01, &0x0000")
//#define IE1 (*(volatile unsigned char *) 0x0000)
#define IFG1 (*(volatile unsigned char *) 0x0002)
 
#define CPU_ID_LO (*(volatile unsigned char *) 0x0004)
232,19 → 233,41
#define eint() __eint()
#define dint() __dint()
 
#define RESET_VECTOR (0x001E) // Vector 15 (0xFFFE) - Reset - [Highest Priority]
#define NMI_VECTOR (0x001C) // Vector 14 (0xFFFC) - Non-maskable -
#define UNUSED_13_VECTOR (0x001A) // Vector 13 (0xFFFA) - -
#define UNUSED_12_VECTOR (0x0018) // Vector 12 (0xFFF8) - -
#define UNUSED_11_VECTOR (0x0016) // Vector 11 (0xFFF6) - -
#define WDT_VECTOR (0x0014) // Vector 10 (0xFFF4) - Watchdog Timer -
#define TIMERA0_VECTOR (0x0012) // Vector 9 (0xFFF2) - Timer A CC0 -
#define TIMERA1_VECTOR (0x0010) // Vector 8 (0xFFF0) - Timer A CC1-2, TA -
#define UNUSED_07_VECTOR (0x000E) // Vector 7 (0xFFEE) - -
#define UNUSED_06_VECTOR (0x000C) // Vector 6 (0xFFEC) - -
#define UNUSED_05_VECTOR (0x000A) // Vector 5 (0xFFEA) - -
#define UNUSED_04_VECTOR (0x0008) // Vector 4 (0xFFE8) - -
#define UNUSED_03_VECTOR (0x0006) // Vector 3 (0xFFE6) - -
#define PORT1_VECTOR (0x0004) // Vector 2 (0xFFE4) - Port 1 -
#define UNUSED_01_VECTOR (0x0002) // Vector 1 (0xFFE2) - -
#define UNUSED_00_VECTOR (0x0000) // Vector 0 (0xFFE0) - - [Lowest Priority]
// Vector definition for RedHat/TI toolchain
#ifdef PFX_MSP430_ELF
#define RESET_VECTOR ("reset") // Vector 15 (0xFFFE) - Reset - [Highest Priority]
#define NMI_VECTOR (15) // Vector 14 (0xFFFC) - Non-maskable -
#define UNUSED_13_VECTOR (14) // Vector 13 (0xFFFA) - -
#define UNUSED_12_VECTOR (13) // Vector 12 (0xFFF8) - -
#define UNUSED_11_VECTOR (12) // Vector 11 (0xFFF6) - -
#define WDT_VECTOR (11) // Vector 10 (0xFFF4) - Watchdog Timer -
#define TIMERA0_VECTOR (10) // Vector 9 (0xFFF2) - Timer A CC0 -
#define TIMERA1_VECTOR (9) // Vector 8 (0xFFF0) - Timer A CC1-2, TA -
#define UNUSED_07_VECTOR (8) // Vector 7 (0xFFEE) - -
#define UNUSED_06_VECTOR (7) // Vector 6 (0xFFEC) - -
#define UNUSED_05_VECTOR (6) // Vector 5 (0xFFEA) - -
#define UNUSED_04_VECTOR (5) // Vector 4 (0xFFE8) - -
#define UNUSED_03_VECTOR (4) // Vector 4 (0xFFE8) - -
#define PORT1_VECTOR (3) // Vector 2 (0xFFE4) - Port 1 -
#define UNUSED_01_VECTOR (2) // Vector 1 (0xFFE2) - -
#define UNUSED_00_VECTOR (1) // Vector 0 (0xFFE0) - - [Lowest Priority]
 
// Vector definition for MSPGCC toolchain
#else
#define RESET_VECTOR (0x001E) // Vector 15 (0xFFFE) - Reset - [Highest Priority]
#define NMI_VECTOR (0x001C) // Vector 14 (0xFFFC) - Non-maskable -
#define UNUSED_13_VECTOR (0x001A) // Vector 13 (0xFFFA) - -
#define UNUSED_12_VECTOR (0x0018) // Vector 12 (0xFFF8) - -
#define UNUSED_11_VECTOR (0x0016) // Vector 11 (0xFFF6) - -
#define WDT_VECTOR (0x0014) // Vector 10 (0xFFF4) - Watchdog Timer -
#define TIMERA0_VECTOR (0x0012) // Vector 9 (0xFFF2) - Timer A CC0 -
#define TIMERA1_VECTOR (0x0010) // Vector 8 (0xFFF0) - Timer A CC1-2, TA -
#define UNUSED_07_VECTOR (0x000E) // Vector 7 (0xFFEE) - -
#define UNUSED_06_VECTOR (0x000C) // Vector 6 (0xFFEC) - -
#define UNUSED_05_VECTOR (0x000A) // Vector 5 (0xFFEA) - -
#define UNUSED_04_VECTOR (0x0008) // Vector 4 (0xFFE8) - -
#define UNUSED_03_VECTOR (0x0006) // Vector 3 (0xFFE6) - -
#define PORT1_VECTOR (0x0004) // Vector 2 (0xFFE4) - Port 1 -
#define UNUSED_01_VECTOR (0x0002) // Vector 1 (0xFFE2) - -
#define UNUSED_00_VECTOR (0x0000) // Vector 0 (0xFFE0) - - [Lowest Priority]
#endif
/makefile
2,16 → 2,35
NAME = spacewar
OBJECTS = bzsin.o cline.o compar.o explode.o hardware.o main.o point.o reset.o rocket1.o rocket2.o score.o update.o
 
CFLAGS = -O2 -Wall -g -mcpu=430 -mivcnt=16 -mmpy=none # Uniarch flags
# Compiler performance option (-Os / -O2 / -O3)
PORT_CFLAGS = -O2
 
#switch the compiler (for the internal make rules)
CC = msp430-gcc
# Choose GCC toolchain prefix ('msp430' for MSPGCC / 'msp430-elf' for GCC RedHat/TI)
ifndef MSPGCC_PFX
MSPGCC_PFX = msp430-elf
endif
 
# disable some warnings specific to the Dhrystone code
WARNINGS = -Wall
 
.PHONY: all FORCE clean download download-jtag download-bsl dist
# Select flags depending on selected toolchain
ifeq ($(MSPGCC_PFX),msp430-elf)
INCDIR = -I /cad/ti/gcc/include
CFLAGS = -D PFX_MSP430_ELF $(INCDIR) $(PORT_CFLAGS) ${WARNINGS} -g -mcpu=msp430 -mhwmult=none
else
CFLAGS = -D PFX_MSP430 $(PORT_CFLAGS) ${WARNINGS} -g -mcpu=430 -mmpy=none -mivcnt=16
endif
 
# Toolchain executables
CC = ${MSPGCC_PFX}-gcc
OBJCOPY = ${MSPGCC_PFX}-objcopy
OBJDUMP = ${MSPGCC_PFX}-objdump
OBJSIZE = ${MSPGCC_PFX}-size
 
.PHONY: all FORCE clean download dist
 
#all should be the first target. it's built when make is runwithout args
all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst
all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst ${NAME}.size
 
#serial download
download: download-uart
18,25 → 37,22
 
#additional rules for files
${NAME}.elf: ${OBJECTS}
${CC} -T linker.x -o $@ ${OBJECTS}
${CC} ${CFLAGS} -T linker.${MSPGCC_PFX}.x -o $@ ${OBJECTS}
 
${NAME}.a43: ${NAME}.elf
msp430-objcopy -O ihex $^ $@
${OBJCOPY} -O ihex $^ $@
 
${NAME}.lst: ${NAME}.elf
msp430-objdump -dSt $^ >$@
${OBJDUMP} -dSt $^ >$@
 
download-jtag: all
msp430-jtag -e ${NAME}.elf
${NAME}.size: ${NAME}.elf
${OBJSIZE} $^ >$@
 
download-bsl: all
msp430-bsl -e ${NAME}.elf
 
download-uart: all
openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf
 
clean:
rm -f ${NAME} ${NAME}.a43 ${NAME}.lst ${NAME}.elf *.o
rm -f ${NAME} ${NAME}.a43 ${NAME}.lst ${NAME}.elf ${NAME}.size *.o
 
#backup archive
dist:

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