URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
- from Rev 111 to Rev 136
- ↔ Reverse comparison
Rev 111 → Rev 136
/design_files.v
51,15 → 51,21
`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v" |
`include "../../../rtl/verilog/openmsp430/omsp_register_file.v" |
`include "../../../rtl/verilog/openmsp430/omsp_alu.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v" |
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v" |
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v" |
`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v" |
`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v" |
`include "../../../rtl/verilog/openmsp430/omsp_and_gate.v" |
`include "../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_gate.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_mux.v" |
`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v" |
`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v" |
|
/prepare_implementation.tcl
55,8 → 55,7
set designTop "openMSP430_fpga" |
|
# RTL include files |
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \ |
../../../rtl/verilog/openmsp430/openMSP430_defines.v \ |
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/openMSP430_defines.v \ |
../../../rtl/verilog/openmsp430/openMSP430_undefines.v \ |
../../../rtl/verilog/openmsp430/periph/omsp_timerA_defines.v \ |
../../../rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v" |