OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
    from Rev 80 to Rev 81
    ↔ Reverse comparison
  •

Rev 80 → Rev 81

/design_files.pdc
8,7 → 8,7
 
# CLOCK & RESET
#------------------------------------------------
set_io clk_osc -pinname E4
set_io oscclk -pinname E4
set_io porst_n -pinname V7
set_io pbrst_n -pinname T9
 
15,12 → 15,12
 
# GPIOA
#------------------------------------------------
set_io gpioa\[0\] -pinname D5 ;# GPIOA_0
set_io gpioa\[1\] -pinname D6 ;# GPIOA_1
set_io gpioa\[2\] -pinname D10 ;# GPIOA_2
set_io gpioa\[3\] -pinname G10 ;# GPIOA_3
set_io gpioa\[4\] -pinname G11 ;# GPIOA_4
set_io gpioa\[4\] -pinname E11 ;# GPIOA_5
set_io din_x -pinname D5 ;# GPIOA_0
set_io sclk_x -pinname D6 ;# GPIOA_1
set_io sync_n_x -pinname D10 ;# GPIOA_2
set_io din_y -pinname G10 ;# GPIOA_3
set_io sclk_y -pinname G11 ;# GPIOA_4
set_io sync_n_y -pinname E11 ;# GPIOA_5
 
 
# UART INTERFACE
/build_fpga.tcl
40,7 → 40,7
###############################################################################
 
# Set tools
set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify.exe"
set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify_pro.exe"
set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe"
 
# Set the FPGA: architecture, model, package_syn package_libero, speed-grade
49,6 → 49,10
# RTL Top Level module
set designTop "openMSP430_fpga"
 
# RTL include files
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \
../../../rtl/verilog/openmsp430/openMSP430_defines.v \
../../../rtl/verilog/openmsp430/openMSP430_undefines.v"
 
###############################################################################
# CLEANUP #
64,9 → 68,13
file mkdir ./WORK
cd ./WORK
 
 
# Copy RTL include files
foreach rtlFile $rtlIncludeFiles {
file copy $rtlFile .
}
###############################################################################
# PERFORM SYNTHESIS #
# GENERATE SYNTHESIS SCRIPT #
###############################################################################
 
# Copy Synplify tcl command files
88,39 → 96,8
puts $f_synplify_tcl $synplify_tcl
close $f_synplify_tcl
 
# Start synthesis
puts "START SYNTHESIS..."
flush stdout
set synplify_done 0
while {[string eq $synplify_done 0]} {
 
sleep 10
eval exec $SYNPLICITY synplify.tcl
sleep 30
 
# Wait until EDIF file is generated
set synplify_timeout 0
while {!([file exists "./rev_1/design_files.edn"] | ($synplify_timeout==100))} {
set synplify_timeout [expr $synplify_timeout+1]
}
if ($synplify_timeout<100) {
set synplify_done 1
}
 
# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
sleep 10
eval exec taskkill /IM synplify.exe
sleep 20
if {[string eq $synplify_done 0]} {
sleep 180
}
}
puts "SYNTHESIS DONE..."
flush stdout
 
 
###############################################################################
# PERFORM PLACE & ROUTE #
# GENERATE PLACE & ROUTE SCRIPT #
###############################################################################
 
# Copy Libero Designer tcl command files
139,8 → 116,35
set f_libero_designer_tcl [open "libero_designer.tcl" w]
puts $f_libero_designer_tcl $libero_designer_tcl
close $f_libero_designer_tcl
 
###############################################################################
# RUN SYNTHESIS #
###############################################################################
 
# Start synthesis
puts "START SYNTHESIS..."
flush stdout
sleep 10
eval exec $SYNPLICITY synplify.tcl
sleep 30
 
# Wait until EDIF file is generated
while {!([file exists "./rev_1/design_files.edn"])} {
sleep 10
}
 
# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
sleep 10
eval exec taskkill /IM synplify.exe
sleep 20
 
puts "SYNTHESIS DONE..."
flush stdout
 
###############################################################################
# RUN PLACE & ROUTE #
###############################################################################
 
# Run place & route
puts "START PLACE & ROUTE..."
flush stdout
148,7 → 152,6
puts "PLACE & ROUTE DONE..."
flush stdout
 
 
###############################################################################
# REPORT SUMMARY #
###############################################################################
175,7 → 178,7
regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2
puts $area1
puts $area2
puts $f_logFile "===================================================================================="
puts "===================================================================================="
 
cd ../
sleep 3

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