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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/fpga/altera_de0_nano_soc
    from Rev 221 to Rev 222
    ↔ Reverse comparison
  •

Rev 221 → Rev 222

/rtl/verilog/openMSP430_fpga.v
333,7 → 333,7
 
 
 
openGFX430 opengfx430_0 (
openGFX430 #(.BASE_ADDR(16'h0200)) opengfx430_0 (
 
// OUTPUTs
.irq_gfx_o (irq_gfx), // Graphic Controller interrupt
/rtl/verilog/opengfx430/ogfx_backend.v
82,7 → 82,12
refresh_active_i, // Display refresh on going
refresh_data_request_i, // Display refresh new data request
refresh_frame_base_addr_i, // Refresh frame base address
refresh_lut_select_i // Refresh LUT bank selection
 
hw_lut_palette_sel_i, // Hardware LUT palette configuration
hw_lut_bgcolor_i, // Hardware LUT background-color selection
hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
sw_lut_enable_i, // Refresh LUT-RAM enable
sw_lut_bank_select_i // Refresh LUT-RAM bank selection
);
 
// OUTPUTs
123,9 → 128,14
input refresh_active_i; // Display refresh on going
input refresh_data_request_i; // Display refresh new data request
input [`APIX_MSB:0] refresh_frame_base_addr_i; // Refresh frame base address
input [1:0] refresh_lut_select_i; // Refresh LUT bank selection
 
input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
input sw_lut_enable_i; // Refresh LUT-RAM enable
input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
 
 
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
205,7 → 215,12
 
.refresh_active_i ( refresh_active_i ), // Display refresh on going
.refresh_data_request_i ( refresh_data_request_i ), // Request for next refresh data
.refresh_lut_select_i ( refresh_lut_select_i ) // Refresh LUT bank selection
 
.hw_lut_palette_sel_i ( hw_lut_palette_sel_i ), // Hardware LUT palette configuration
.hw_lut_bgcolor_i ( hw_lut_bgcolor_i ), // Hardware LUT background-color selection
.hw_lut_fgcolor_i ( hw_lut_fgcolor_i ), // Hardware LUT foreground-color selection
.sw_lut_enable_i ( sw_lut_enable_i ), // Refresh LUT-RAM enable
.sw_lut_bank_select_i ( sw_lut_bank_select_i ) // Refresh LUT-RAM bank selection
);
 
 
/rtl/verilog/opengfx430/ogfx_backend_lut_fifo.v
69,7 → 69,12
 
refresh_active_i, // Display refresh on going
refresh_data_request_i, // Request for next refresh data
refresh_lut_select_i // Refresh LUT bank selection
 
hw_lut_palette_sel_i, // Hardware LUT palette configuration
hw_lut_bgcolor_i, // Hardware LUT background-color selection
hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
sw_lut_enable_i, // Refresh LUT-RAM enable
sw_lut_bank_select_i // Refresh LUT-RAM bank selection
);
 
// OUTPUTs
101,9 → 106,14
 
input refresh_active_i; // Display refresh on going
input refresh_data_request_i; // Request for next refresh data
input [1:0] refresh_lut_select_i; // Refresh LUT bank selection
 
input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
input sw_lut_enable_i; // Refresh LUT-RAM enable
input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
 
 
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
139,42 → 149,113
// 2) HARD CODED LOOKUP TABLE
//============================================================================
 
wire [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==1'b0 }}) | // 1 bpp: Black
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==1'b1 }}) ; // White
// 16 full CGA color selection
parameter [3:0] CGA_BLACK = 4'h0,
CGA_BLUE = 4'h1,
CGA_GREEN = 4'h2,
CGA_CYAN = 4'h3,
CGA_RED = 4'h4,
CGA_MAGENTA = 4'h5,
CGA_BROWN = 4'h6,
CGA_LIGHT_GRAY = 4'h7,
CGA_GRAY = 4'h8,
CGA_LIGHT_BLUE = 4'h9,
CGA_LIGHT_GREEN = 4'hA,
CGA_LIGHT_CYAN = 4'hB,
CGA_LIGHT_RED = 4'hC,
CGA_LIGHT_MAGENTA = 4'hD,
CGA_YELLOW = 4'hE,
CGA_WHITE = 4'hF;
 
wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00 }}) | // 2 bpp: Black
({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01 }}) | // Dark Gray
({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10 }}) | // Light Gray
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11 }}) ; // White
// Decode CGA 4 color mode (2bpp)
wire cga_palette0_hi = (hw_lut_palette_sel_i==3'h0);
wire cga_palette0_lo = (hw_lut_palette_sel_i==3'h1);
wire cga_palette1_hi = (hw_lut_palette_sel_i==3'h2);
wire cga_palette1_lo = (hw_lut_palette_sel_i==3'h3);
wire cga_palette2_hi = (hw_lut_palette_sel_i==3'h4);
wire cga_palette2_lo = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);
 
wire [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) | // 4 bpp: Black
({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) | // Dark Blue
({5'b10000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0010}}) | // Dark Red
({5'b10000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0011}}) | // Dark Magenta
({5'b00000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0100}}) | // Dark Green
({5'b00000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0101}}) | // Dark Cyan
({5'b10000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0110}}) | // Dark Yellow
({5'b10000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0111}}) | // Gray
({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1000}}) | // Black
({5'b00000, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1001}}) | // Blue
({5'b11111, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1010}}) | // Red
({5'b11111, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1011}}) | // Magenta
({5'b00000, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1100}}) | // Green
({5'b00000, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1101}}) | // Cyan
({5'b11111, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1110}}) | // Yellow
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1111}}); // White
// LUT color decoding
// 1 BPP
wire [3:0] lut_hw_sel_1bpp = ({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b0 )}} & hw_lut_bgcolor_i ) | // 1 bpp: Black (default bgcolor)
({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b1 )}} & hw_lut_fgcolor_i ) ; // White (default fgcolor)
 
// 2 BPP (Palette #0, low-intensity)
wire [3:0] lut_hw_sel_2bpp = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN ) | // Green
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN ) | // Brown
 
// 2 BPP (Palette #0, high-intensity)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN ) | // Light-Green
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW ) | // Yellow
 
// 2 BPP (Palette #1, low-intensity)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA ) | // Magenta
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
 
// 2 BPP (Palette #1, high-intensity)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) | // Light-Magenta
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) | // White
 
// 2 BPP (Palette #2, low-intensity)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
 
// 2 BPP (Palette #2, high-intensity)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) ; // White
 
// 4 BPP (full CGA 16-color palette)
wire [3:0] lut_hw_sel_4bpp = ({4{gfx_mode_4_bpp}} & frame_data_i[3:0]);
 
wire [3:0] lut_hw_color_sel = lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;
 
// Color encoding for 1-bit / 2-bit and 4-bit modes
reg [15:0] lut_hw_data_1_2_4_bpp;
always @(lut_hw_color_sel)
case(lut_hw_color_sel)
CGA_BLACK : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b00000}; // Black
CGA_BLUE : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b10101}; // Blue
CGA_GREEN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b00000}; // Green
CGA_CYAN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b10101}; // Cyan
CGA_RED : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b00000}; // Red
CGA_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b10101}; // Magenta
CGA_BROWN : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b010101, 5'b00000}; // Brown
CGA_LIGHT_GRAY : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b101011, 5'b10101}; // Light Gray
CGA_GRAY : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b01011}; // Gray
CGA_LIGHT_BLUE : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b11111}; // Light Blue
CGA_LIGHT_GREEN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b01011}; // Light Green
CGA_LIGHT_CYAN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b11111}; // Light Cyan
CGA_LIGHT_RED : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b01011}; // Light Red
CGA_LIGHT_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b11111}; // Light Magenta
CGA_YELLOW : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b01011}; // Yellow
CGA_WHITE : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b11111}; // White
// pragma coverage off
default : lut_hw_data_1_2_4_bpp = 16'h0000;
// pragma coverage on
endcase
 
// 8-bit truecolor RGB mapping (3-bit red / 3-bit green / 2-bit blue)
wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
 
wire [15:0] lut_hw_data = (lut_hw_data_1_bpp & {16{gfx_mode_1_bpp}}) |
(lut_hw_data_2_bpp & {16{gfx_mode_2_bpp}}) |
(lut_hw_data_4_bpp & {16{gfx_mode_4_bpp}}) |
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
wire [15:0] lut_hw_data = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
 
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~refresh_lut_select_i[0];
wire lut_sw_enabled = ~gfx_mode_16_bpp & refresh_lut_select_i[0];
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~sw_lut_enable_i;
wire lut_sw_enabled = ~gfx_mode_16_bpp & sw_lut_enable_i;
 
 
//============================================================================
247,7 → 328,7
reg refresh_lut_bank_select_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
else if (~refresh_active_i) refresh_lut_bank_select_sync <= refresh_lut_select_i[1];
else if (~refresh_active_i) refresh_lut_bank_select_sync <= sw_lut_bank_select_i;
 
assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
`else
/rtl/verilog/opengfx430/ogfx_reg.v
74,8 → 74,13
per_dout_o, // Peripheral data output
 
refresh_frame_addr_o, // Refresh frame base address
refresh_lut_select_o, // Refresh LUT bank selection
 
hw_lut_palette_sel_o, // Hardware LUT palette configuration
hw_lut_bgcolor_o, // Hardware LUT background-color selection
hw_lut_fgcolor_o, // Hardware LUT foreground-color selection
sw_lut_enable_o, // Refresh LUT-RAM enable
sw_lut_bank_select_o, // Refresh LUT-RAM bank selection
 
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_din_o, // LUT-RAM data
109,8 → 114,15
vid_ram_dout_i // Video-RAM data input
);
 
// PARAMETERs
//============
 
parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
// - 7 LSBs must stay cleared: 0x0080, 0x0100,
// 0x0180, 0x0200,
// 0x0280, ...
// OUTPUTs
//=========
//============
output irq_gfx_o; // Graphic Controller interrupt
 
output [15:0] gpu_data_o; // GPU data
142,8 → 154,13
output [15:0] per_dout_o; // Peripheral data output
 
output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
output [1:0] refresh_lut_select_o; // Refresh LUT bank selection
 
output [2:0] hw_lut_palette_sel_o; // Hardware LUT palette configuration
output [3:0] hw_lut_bgcolor_o; // Hardware LUT background-color selection
output [3:0] hw_lut_fgcolor_o; // Hardware LUT foreground-color selection
output sw_lut_enable_o; // Refresh LUT-RAM enable
output sw_lut_bank_select_o; // Refresh LUT-RAM bank selection
 
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output [15:0] lut_ram_din_o; // LUT-RAM data
157,7 → 174,7
output vid_ram_cen_o; // Video-RAM chip enable (active low)
 
// INPUTs
//=========
//============
input dbg_freeze_i; // Freeze address auto-incr on read
input gpu_cmd_done_evt_i; // GPU command done event
input gpu_cmd_error_evt_i; // GPU command error event
182,9 → 199,6
// 1) PARAMETER DECLARATION
//=============================================================================
 
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0200;
 
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 7;
 
208,8 → 222,9
LT24_CMD_DFILL = 'h2A,
LT24_STATUS = 'h2C,
 
LUT_RAM_ADDR = 'h30, // LUT Memory Access Gate
LUT_RAM_DATA = 'h32,
LUT_CFG = 'h30, // LUT Configuration & Memory Access Gate
LUT_RAM_ADDR = 'h32,
LUT_RAM_DATA = 'h34,
 
FRAME_SELECT = 'h3E, // Frame pointers and selection
FRAME0_PTR_LO = 'h40,
262,6 → 277,7
LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
 
LUT_CFG_D = (BASE_REG << LUT_CFG ),
LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
 
322,6 → 338,7
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
 
(LUT_CFG_D & {DEC_SZ{(reg_addr == LUT_CFG )}}) |
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
 
372,9 → 389,7
`endif
wire [`APIX_MSB:0] vid_ram0_base_addr;
wire [`APIX_MSB:0] vid_ram1_base_addr;
`ifdef WITH_EXTRA_LUT_BANK
reg lut_bank_select;
`endif
wire refr_cnt_done_evt;
wire gpu_fifo_done_evt;
wire gpu_fifo_ovfl_evt;
 
397,6 → 412,7
// Bitfield assignments
wire gfx_irq_refr_done_en = gfx_ctrl[0];
wire gfx_irq_refr_start_en = gfx_ctrl[1];
wire gfx_irq_refr_cnt_done_en = gfx_ctrl[2];
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
419,9 → 435,15
// GFX_STATUS Register
//------------------------------------------------
wire [15:0] gfx_status;
wire gpu_busy;
 
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
assign gfx_status[15:1] = 15'h0000;
assign gfx_status[3:1] = 3'b000;
assign gfx_status[4] = gpu_data_avail_o;
assign gfx_status[5] = 1'b0;
assign gfx_status[6] = gpu_busy;
assign gfx_status[7] = 1'b0;
assign gfx_status[15:8] = 15'h0000;
 
//------------------------------------------------
// GFX_IRQ Register
435,6 → 457,9
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_start_set = lt24_start_evt_i;
 
wire gfx_irq_refr_cnt_done_clr = per_din_i[2] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_cnt_done_set = refr_cnt_done_evt;
 
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
 
449,6 → 474,7
 
reg gfx_irq_refr_done;
reg gfx_irq_refr_start;
reg gfx_irq_refr_cnt_done;
reg gfx_irq_gpu_fifo_done;
reg gfx_irq_gpu_fifo_ovfl;
reg gfx_irq_gpu_cmd_done;
458,6 → 484,7
begin
gfx_irq_refr_done <= 1'b0;
gfx_irq_refr_start <= 1'b0;
gfx_irq_refr_cnt_done <= 1'b0;
gfx_irq_gpu_fifo_done <= 1'b0;
gfx_irq_gpu_fifo_ovfl <= 1'b0;
gfx_irq_gpu_cmd_done <= 1'b0;
467,6 → 494,7
begin
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
gfx_irq_refr_cnt_done <= (gfx_irq_refr_cnt_done_set | (~gfx_irq_refr_cnt_done_clr & gfx_irq_refr_cnt_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
479,6 → 507,7
 
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
(gfx_irq_refr_cnt_done & gfx_irq_refr_cnt_done_en) |
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
591,6 → 620,8
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
 
assign refr_cnt_done_evt = (display_refr_cnt==16'h0001) & display_refr_cnt_dec;
 
//------------------------------------------------
// LT24_CFG Register
//------------------------------------------------
614,7 → 645,7
reg [11:0] lt24_cfg_refr_o;
 
wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==8'h00); // Auto-clear in manual refresh mode when done
wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==12'h000); // Auto-clear in manual refresh mode when done
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_refr_o <= 1'h0;
628,7 → 659,7
wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
 
//------------------------------------------------
// LT24_REFRESH Register
// LT24_REFRESH_SYNC Register
//------------------------------------------------
reg lt24_cfg_refr_sync_en_o;
reg [9:0] lt24_cfg_refr_sync_val_o;
699,7 → 730,57
assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
assign lt24_status[15:5] = 11'h000;
 
//------------------------------------------------
// LUT_CFG Register
//------------------------------------------------
 
wire lut_cfg_wr = reg_wr[LUT_CFG];
 
`ifdef WITH_PROGRAMMABLE_LUT
reg sw_lut_enable_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_enable_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
 
reg sw_lut_ram_rmw_mode;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_ram_rmw_mode <= 1'b0;
else if (lut_cfg_wr) sw_lut_ram_rmw_mode <= per_din_i[1];
 
`ifdef WITH_EXTRA_LUT_BANK
reg sw_lut_bank_select_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_bank_select_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
`else
assign sw_lut_bank_select_o = 1'b0;
`endif
`else
assign sw_lut_bank_select_o = 1'b0;
assign sw_lut_enable_o = 1'b0;
wire sw_lut_ram_rmw_mode = 1'b0;
`endif
 
reg [2:0] hw_lut_palette_sel_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
else if (lut_cfg_wr) hw_lut_palette_sel_o <= per_din_i[6:4];
 
reg [3:0] hw_lut_bgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_bgcolor_o <= 4'h0;
else if (lut_cfg_wr) hw_lut_bgcolor_o <= per_din_i[11:8];
 
reg [3:0] hw_lut_fgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
 
wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
1'b0, hw_lut_palette_sel_o,
1'b0, sw_lut_bank_select_o,
sw_lut_ram_rmw_mode, sw_lut_enable_o};
 
//------------------------------------------------
// LUT_RAM_ADDR Register
//------------------------------------------------
706,29 → 787,39
`ifdef WITH_PROGRAMMABLE_LUT
 
reg [7:0] lut_ram_addr;
wire [7:0] lut_ram_addr_inc;
wire [8:0] lut_ram_addr_inc;
wire lut_ram_addr_inc_wr;
 
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_addr <= 8'h00;
else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc;
if (puc_rst) lut_ram_addr <= 8'h00;
else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc[7:0];
 
assign lut_ram_addr_inc = lut_ram_addr + 8'h01;
wire [15:0] lut_ram_addr_rd = {8'h00, lut_ram_addr};
`ifdef WITH_EXTRA_LUT_BANK
reg lut_bank_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_bank_select <= 1'b0;
else if (lut_ram_addr_wr) lut_bank_select <= per_din_i[8];
else if (lut_ram_addr_inc_wr) lut_bank_select <= lut_ram_addr_inc[8];
`else
wire lut_bank_select = 1'b0;
`endif
 
`ifdef WITH_EXTRA_LUT_BANK
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
`else
assign lut_ram_addr_o = lut_ram_addr;
`endif
assign lut_ram_addr_inc = {lut_bank_select, lut_ram_addr} + 9'h001;
wire [15:0] lut_ram_addr_rd = {7'h00, lut_bank_select, lut_ram_addr};
 
`ifdef WITH_EXTRA_LUT_BANK
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
`else
wire [15:0] lut_ram_addr_rd = 16'h0000;
assign lut_ram_addr_o = lut_ram_addr;
`endif
 
`else
wire [15:0] lut_ram_addr_rd = 16'h0000;
`endif
 
//------------------------------------------------
// LUT_RAM_DATA Register
//------------------------------------------------
747,7 → 838,9
else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
 
// Increment the address after a write or read access to the LUT_RAM_DATA register
assign lut_ram_addr_inc_wr = lut_ram_data_wr | lut_ram_data_rd;
// - one clock cycle after a write access
// - with the read access (if not in read-modify-write mode)
assign lut_ram_addr_inc_wr = lut_ram_data_wr | (lut_ram_data_rd & ~dbg_freeze_i & ~sw_lut_ram_rmw_mode);
 
// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
788,36 → 881,6
 
wire frame_select_wr = reg_wr[FRAME_SELECT];
 
`ifdef WITH_PROGRAMMABLE_LUT
reg refresh_sw_lut_enable;
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) refresh_sw_lut_enable <= 1'b0;
else if (frame_select_wr) refresh_sw_lut_enable <= per_din_i[2];
`else
wire refresh_sw_lut_enable = 1'b0;
`endif
 
`ifdef WITH_EXTRA_LUT_BANK
reg refresh_sw_lut_select;
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
refresh_sw_lut_select <= 1'b0;
lut_bank_select <= 1'b0;
end
else if (frame_select_wr)
begin
refresh_sw_lut_select <= per_din_i[3];
lut_bank_select <= per_din_i[15];
end
`else
assign refresh_sw_lut_select = 1'b0;
wire lut_bank_select = 1'b0;
`endif
wire [1:0] refresh_lut_select_o = {refresh_sw_lut_select, refresh_sw_lut_enable};
 
`ifdef WITH_FRAME1_POINTER
`ifdef WITH_FRAME2_POINTER
reg [1:0] refresh_frame_select;
838,7 → 901,7
vid_ram1_frame_select <= per_din_i[7:6];
end
 
wire [15:0] frame_select = {lut_bank_select, 7'h00, vid_ram1_frame_select, vid_ram0_frame_select, refresh_lut_select_o, refresh_frame_select};
wire [15:0] frame_select = {8'h00, vid_ram1_frame_select, vid_ram0_frame_select, 2'h0, refresh_frame_select};
`else
reg refresh_frame_select;
reg vid_ram0_frame_select;
858,10 → 921,10
vid_ram1_frame_select <= per_din_i[6];
end
 
wire [15:0] frame_select = {lut_bank_select, 7'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, refresh_lut_select_o, 1'h0, refresh_frame_select};
wire [15:0] frame_select = {8'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, 2'h0, 1'h0, refresh_frame_select};
`endif
`else
wire [15:0] frame_select = {lut_bank_select, 11'h000, refresh_lut_select_o, 2'h0};
wire [15:0] frame_select = 16'h0000;
`endif
 
// Frame pointer selections
1218,7 → 1281,7
 
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
 
wire gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
assign gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
 
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
1251,6 → 1314,7
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
 
wire [15:0] lut_cfg_read = lut_cfg_rd & {16{reg_rd[LUT_CFG ]}};
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
 
1318,6 → 1382,7
lt24_cmd_dfill_read |
lt24_status_read |
 
lut_cfg_read |
lut_ram_addr_read |
lut_ram_data_read |
 
/rtl/verilog/opengfx430/openGFX430.v
46,91 → 46,98
module openGFX430 (
 
// OUTPUTs
irq_gfx_o, // Graphic Controller interrupt
irq_gfx_o, // Graphic Controller interrupt
 
lt24_cs_n_o, // LT24 Chip select (Active low)
lt24_rd_n_o, // LT24 Read strobe (Active low)
lt24_wr_n_o, // LT24 Write strobe (Active low)
lt24_rs_o, // LT24 Command/Param selection (Cmd=0/Param=1)
lt24_d_o, // LT24 Data output
lt24_d_en_o, // LT24 Data output enable
lt24_reset_n_o, // LT24 Reset (Active Low)
lt24_on_o, // LT24 on/off
lt24_cs_n_o, // LT24 Chip select (Active low)
lt24_rd_n_o, // LT24 Read strobe (Active low)
lt24_wr_n_o, // LT24 Write strobe (Active low)
lt24_rs_o, // LT24 Command/Param selection (Cmd=0/Param=1)
lt24_d_o, // LT24 Data output
lt24_d_en_o, // LT24 Data output enable
lt24_reset_n_o, // LT24 Reset (Active Low)
lt24_on_o, // LT24 on/off
 
per_dout_o, // Peripheral data output
per_dout_o, // Peripheral data output
 
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_wen_o, // LUT-RAM write enable (active low)
lut_ram_cen_o, // LUT-RAM enable (active low)
lut_ram_din_o, // LUT-RAM data input
lut_ram_addr_o, // LUT-RAM address
lut_ram_wen_o, // LUT-RAM write enable (active low)
lut_ram_cen_o, // LUT-RAM enable (active low)
lut_ram_din_o, // LUT-RAM data input
`endif
 
vid_ram_addr_o, // Video-RAM address
vid_ram_wen_o, // Video-RAM write enable (active low)
vid_ram_cen_o, // Video-RAM enable (active low)
vid_ram_din_o, // Video-RAM data input
vid_ram_addr_o, // Video-RAM address
vid_ram_wen_o, // Video-RAM write enable (active low)
vid_ram_cen_o, // Video-RAM enable (active low)
vid_ram_din_o, // Video-RAM data input
 
// INPUTs
dbg_freeze_i, // Freeze address auto-incr on read
mclk, // Main system clock
per_addr_i, // Peripheral address
per_din_i, // Peripheral data input
per_en_i, // Peripheral enable (high active)
per_we_i, // Peripheral write enable (high active)
puc_rst, // Main system reset
dbg_freeze_i, // Freeze address auto-incr on read
mclk, // Main system clock
per_addr_i, // Peripheral address
per_din_i, // Peripheral data input
per_en_i, // Peripheral enable (high active)
per_we_i, // Peripheral write enable (high active)
puc_rst, // Main system reset
 
lt24_d_i, // LT24 Data input
lt24_d_i, // LT24 Data input
 
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_dout_i, // LUT-RAM data output
lut_ram_dout_i, // LUT-RAM data output
`endif
vid_ram_dout_i // Video-RAM data output
vid_ram_dout_i // Video-RAM data output
);
 
// PARAMETERs
//============
 
parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
// - 7 LSBs must stay cleared: 0x0080, 0x0100,
// 0x0180, 0x0200,
// 0x0280, ...
// OUTPUTs
//=========
output irq_gfx_o; // Graphic Controller interrupt
output irq_gfx_o; // Graphic Controller interrupt
 
output lt24_cs_n_o; // LT24 Chip select (Active low)
output lt24_rd_n_o; // LT24 Read strobe (Active low)
output lt24_wr_n_o; // LT24 Write strobe (Active low)
output lt24_rs_o; // LT24 Command/Param selection (Cmd=0/Param=1)
output [15:0] lt24_d_o; // LT24 Data output
output lt24_d_en_o; // LT24 Data output enable
output lt24_reset_n_o; // LT24 Reset (Active Low)
output lt24_on_o; // LT24 on/off
output lt24_cs_n_o; // LT24 Chip select (Active low)
output lt24_rd_n_o; // LT24 Read strobe (Active low)
output lt24_wr_n_o; // LT24 Write strobe (Active low)
output lt24_rs_o; // LT24 Command/Param selection (Cmd=0/Param=1)
output [15:0] lt24_d_o; // LT24 Data output
output lt24_d_en_o; // LT24 Data output enable
output lt24_reset_n_o; // LT24 Reset (Active Low)
output lt24_on_o; // LT24 on/off
 
output [15:0] per_dout_o; // Peripheral data output
output [15:0] per_dout_o; // Peripheral data output
 
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output lut_ram_wen_o; // LUT-RAM write enable (active low)
output lut_ram_cen_o; // LUT-RAM enable (active low)
output [15:0] lut_ram_din_o; // LUT-RAM data input
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output lut_ram_wen_o; // LUT-RAM write enable (active low)
output lut_ram_cen_o; // LUT-RAM enable (active low)
output [15:0] lut_ram_din_o; // LUT-RAM data input
`endif
 
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output vid_ram_wen_o; // Video-RAM write enable (active low)
output vid_ram_cen_o; // Video-RAM enable (active low)
output [15:0] vid_ram_din_o; // Video-RAM data input
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output vid_ram_wen_o; // Video-RAM write enable (active low)
output vid_ram_cen_o; // Video-RAM enable (active low)
output [15:0] vid_ram_din_o; // Video-RAM data input
 
// INPUTs
//=========
input dbg_freeze_i; // Freeze address auto-incr on read
input mclk; // Main system clock
input [13:0] per_addr_i; // Peripheral address
input [15:0] per_din_i; // Peripheral data input
input per_en_i; // Peripheral enable (high active)
input [1:0] per_we_i; // Peripheral write enable (high active)
input puc_rst; // Main system reset
input dbg_freeze_i; // Freeze address auto-incr on read
input mclk; // Main system clock
input [13:0] per_addr_i; // Peripheral address
input [15:0] per_din_i; // Peripheral data input
input per_en_i; // Peripheral enable (high active)
input [1:0] per_we_i; // Peripheral write enable (high active)
input puc_rst; // Main system reset
 
input [15:0] lt24_d_i; // LT24 Data input
input [15:0] lt24_d_i; // LT24 Data input
 
`ifdef WITH_PROGRAMMABLE_LUT
input [15:0] lut_ram_dout_i; // LUT-RAM data output
input [15:0] lut_ram_dout_i; // LUT-RAM data output
`endif
input [15:0] vid_ram_dout_i; // Video-RAM data output
input [15:0] vid_ram_dout_i; // Video-RAM data output
 
 
//=============================================================================
193,7 → 200,11
wire refresh_data_ready;
wire refresh_data_request;
wire [`APIX_MSB:0] refresh_frame_addr;
wire [1:0] refresh_lut_select;
wire [2:0] hw_lut_palette_sel;
wire [3:0] hw_lut_bgcolor;
wire [3:0] hw_lut_fgcolor;
wire sw_lut_enable;
wire sw_lut_bank_select;
 
wire gpu_cmd_done_evt;
wire gpu_cmd_error_evt;
208,7 → 219,7
// 2) REGISTERS
//============================================================================
 
ogfx_reg ogfx_reg_inst (
ogfx_reg #(.BASE_ADDR(BASE_ADDR)) ogfx_reg_inst (
 
// OUTPUTs
.irq_gfx_o ( irq_gfx_o ), // Graphic Controller interrupt
243,8 → 254,13
.per_dout_o ( per_dout_o ), // Peripheral data output
 
.refresh_frame_addr_o ( refresh_frame_addr ), // Refresh frame base address
.refresh_lut_select_o ( refresh_lut_select ), // Refresh LUT bank selection
 
.hw_lut_palette_sel_o ( hw_lut_palette_sel ), // Hardware LUT palette configuration
.hw_lut_bgcolor_o ( hw_lut_bgcolor ), // Hardware LUT background-color selection
.hw_lut_fgcolor_o ( hw_lut_fgcolor ), // Hardware LUT foreground-color selection
.sw_lut_enable_o ( sw_lut_enable ), // Refresh LUT-RAM enable
.sw_lut_bank_select_o ( sw_lut_bank_select ), // Refresh LUT-RAM bank selection
 
`ifdef WITH_PROGRAMMABLE_LUT
.lut_ram_addr_o ( lut_ram_sw_addr ), // LUT-RAM address
.lut_ram_din_o ( lut_ram_sw_din ), // LUT-RAM data
405,7 → 421,12
.refresh_active_i ( refresh_active ), // Display refresh on going
.refresh_data_request_i ( refresh_data_request ), // Display refresh new data request
.refresh_frame_base_addr_i ( refresh_frame_addr ), // Refresh frame base address
.refresh_lut_select_i ( refresh_lut_select ) // Refresh LUT bank selection
 
.hw_lut_palette_sel_i ( hw_lut_palette_sel ), // Hardware LUT palette configuration
.hw_lut_bgcolor_i ( hw_lut_bgcolor ), // Hardware LUT background-color selection
.hw_lut_fgcolor_i ( hw_lut_fgcolor ), // Hardware LUT foreground-color selection
.sw_lut_enable_i ( sw_lut_enable ), // Refresh LUT-RAM enable
.sw_lut_bank_select_i ( sw_lut_bank_select ) // Refresh LUT-RAM bank selection
);
 
//============================================================================
/software/apps/gfx_demo/demo_2bpp.c
11,6 → 11,8
unsigned int color = 0;
unsigned int x_coord = 0;
unsigned int y_coord = 0;
unsigned int palette = 0;
unsigned int bg_color = 0;
 
const uint16_t offset_x = 35;
const uint16_t offset_y = 95;
17,31 → 19,31
const uint16_t char_width = 7;
 
// Screen introduction
gpu_fill (PIX_ADDR(0, 0 ), 320, 480, 0x0001, DST_SWAP_NONE); // Background
gpu_fill (PIX_ADDR(0, 0 ), 320, 480, 0x0000, DST_SWAP_NONE); // Background
 
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+1*char_width, offset_y+0*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE); // 2
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+0*char_width, offset_y+1*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+4*char_width, offset_y+1*char_width), 1*char_width, 2*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+3*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+2*char_width, offset_y+4*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+1*char_width, offset_y+5*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+0*char_width, offset_y+6*char_width), 5*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+1*char_width, offset_y+0*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE); // 2
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+0*char_width, offset_y+1*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+4*char_width, offset_y+1*char_width), 1*char_width, 2*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+3*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+2*char_width, offset_y+4*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+1*char_width, offset_y+5*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+1*6*char_width+0*char_width, offset_y+6*char_width), 5*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
 
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+0*char_width, offset_y+0*char_width), 1*char_width, 6*char_width, 0x0002, DST_SWAP_NONE); // b
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+1*char_width, offset_y+6*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+1*char_width, offset_y+4*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+2*char_width, offset_y+3*char_width), 2*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+4*char_width, offset_y+4*char_width), 1*char_width, 2*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+0*char_width, offset_y+0*char_width), 1*char_width, 6*char_width, 0x0003, DST_SWAP_NONE); // b
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+1*char_width, offset_y+6*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+1*char_width, offset_y+4*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+2*char_width, offset_y+3*char_width), 2*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+3*6*char_width+4*char_width, offset_y+4*char_width), 1*char_width, 2*char_width, 0x0003, DST_SWAP_NONE);
 
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+0*char_width, offset_y+2*char_width), 1*char_width, 5*char_width, 0x0002, DST_SWAP_NONE); // p
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+1*char_width, offset_y+2*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+1*char_width, offset_y+4*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+4*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+0*char_width, offset_y+2*char_width), 1*char_width, 5*char_width, 0x0003, DST_SWAP_NONE); // p
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+1*char_width, offset_y+2*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+1*char_width, offset_y+4*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+4*6*char_width+4*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
 
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+0*char_width, offset_y+2*char_width), 1*char_width, 5*char_width, 0x0002, DST_SWAP_NONE); // p
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+1*char_width, offset_y+2*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+1*char_width, offset_y+4*char_width), 3*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+4*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0002, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+0*char_width, offset_y+2*char_width), 1*char_width, 5*char_width, 0x0003, DST_SWAP_NONE); // p
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+1*char_width, offset_y+2*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+1*char_width, offset_y+4*char_width), 3*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
gpu_fill (PIX_ADDR(offset_x+5*6*char_width+4*char_width, offset_y+3*char_width), 1*char_width, 1*char_width, 0x0003, DST_SWAP_NONE);
 
ta_wait_no_lpm(WT_500MS);
ta_wait_no_lpm(WT_500MS);
72,64 → 74,29
ta_wait_no_lpm(WT_500MS);
ta_wait_no_lpm(WT_500MS);
 
// // Initialize LFSR for random color generation
// lfsr = 0xACEB;
//
// // Loop the demo
// loop = 0;
// while (loop <4) {
//
// // Select rotation & GPU use
// switch(loop & 0x0003) {
// case 0 : DISPLAY_CFG = DST_SWAP_CL; wait_sel = 3;
// break;
// case 1 : DISPLAY_CFG = DST_SWAP_CL; wait_sel = 2;
// break;
// case 2 : DISPLAY_CFG = DST_SWAP_CL; wait_sel = 1;
// break;
// default: DISPLAY_CFG = DST_SWAP_CL; wait_sel = 0;
// break;
// }
// loop++;
// move_to_next_mode = 0;
//
// // Move the starting point of the buffer refresh
// DISPLAY_REFR_CNT = 0;
// while (!move_to_next_mode) {
//
// // Fill the screen with random colors
// x_coord = 0;
// y_coord = 0;
// for( line = 0; line <4; line = line + 1 ) {
// for( column = 0; column < 4; column = column + 1 ) {
//
// // Compute next color from LFSR
// lfsr_lsb = lfsr & 1; /* Get LSB (i.e., the output bit). */
// lfsr >>= 1; /* Shift register */
// lfsr ^= (-lfsr_lsb) & 0xB400u; /* If the output bit is 1, apply toggle mask.
// * The value has 1 at bits corresponding
// * to taps, 0 elsewhere. */
// color = lfsr & 0x000F;
//
// // Draw the box
// draw_block(PIX_ADDR(x_coord, y_coord), 77, 57, color, DST_SWAP_NONE, use_gpu);
// x_coord += 80;
// }
// y_coord += 60;
// x_coord = 0;
// }
//
// // Wait according to config
// switch(wait_sel) {
// case 0 : while(DISPLAY_REFR_CNT!=0); DISPLAY_REFR_CNT = 2;
// break;
// case 1 : while(DISPLAY_REFR_CNT!=0); DISPLAY_REFR_CNT = 4;
// break;
// case 2 : while(DISPLAY_REFR_CNT!=0); DISPLAY_REFR_CNT = 7;
// break;
// default: while(DISPLAY_REFR_CNT!=0); DISPLAY_REFR_CNT = 10;
// break;
// }
// }
// }
// For each palette, try out each background-color
for( palette = 0; palette <6; palette = palette + 1 ) {
 
LUT_CFG = (LUT_CFG & ~HW_LUT_PALETTE_MSK) | HW_LUT_BG_BLACK | (palette<<4);
ta_wait_no_lpm(WT_500MS);
ta_wait_no_lpm(WT_500MS);
 
for( bg_color = 0; bg_color < 15; bg_color = bg_color + 1 ) {
 
LUT_CFG = (LUT_CFG & ~HW_LUT_BGCOLOR_MSK) | (bg_color<<8);
 
ta_wait_no_lpm(WT_500MS);
}
 
LUT_CFG = (LUT_CFG & ~HW_LUT_BGCOLOR_MSK) | HW_LUT_BG_BLACK;
ta_wait_no_lpm(WT_500MS);
ta_wait_no_lpm(WT_500MS);
}
 
// Re-initialize LUT configuration
LUT_CFG = HW_LUT_BG_BLACK |
HW_LUT_FG_WHITE |
HW_LUT_PALETTE_0_HI |
SW_LUT_BANK0_SELECT |
SW_LUT_DISABLE;
};
/software/apps/gfx_demo/main.c
36,16 → 36,20
// LUT_RAM_DATA = palette_64k[idx];
//}
 
// LUT Configuration
LUT_CFG = HW_LUT_BG_BLACK |
HW_LUT_FG_WHITE |
HW_LUT_PALETTE_0_HI |
SW_LUT_BANK0_SELECT |
SW_LUT_DISABLE;
 
// Initialize Frame pointers
FRAME0_PTR = PIX_ADDR(0, 0);
FRAME1_PTR = PIX_ADDR(0, 0);
 
FRAME_SELECT = REFRESH_FRAME0_SELECT |
REFRESH_SW_LUT_DISABLE |
REFRESH_SW_LUT0_SELECT |
VID_RAM0_FRAME0_SELECT |
VID_RAM1_FRAME0_SELECT |
LUT_BANK0_SELECT;
VID_RAM1_FRAME0_SELECT;
 
// Start Graphic controller
start_gfx_ctrl();
/software/libs/gfx/gfx_controller.h
73,8 → 73,9
#define LT24_CMD_DFILL (*(volatile uint16_t *) 0x022A)
#define LT24_STATUS (*(volatile uint16_t *) 0x022C)
 
#define LUT_RAM_ADDR (*(volatile uint16_t *) 0x0230)
#define LUT_RAM_DATA (*(volatile uint16_t *) 0x0232)
#define LUT_CFG (*(volatile uint16_t *) 0x0230)
#define LUT_RAM_ADDR (*(volatile uint16_t *) 0x0232)
#define LUT_RAM_DATA (*(volatile uint16_t *) 0x0234)
 
#define FRAME_SELECT (*(volatile uint16_t *) 0x023E)
#define FRAME0_PTR (*(volatile uint32_t *) 0x0240)
106,6 → 107,8
#define GFX_REFR_DONE_IRQ_DIS 0x0000
#define GFX_REFR_START_IRQ_EN 0x0002
#define GFX_REFR_START_IRQ_DIS 0x0000
#define GFX_REFR_CNT_DONE_IRQ_EN 0x0004
#define GFX_REFR_CNT_DONE_IRQ_DIS 0x0000
#define GFX_GPU_FIFO_DONE_IRQ_EN 0x0010
#define GFX_GPU_FIFO_DONE_IRQ_DIS 0x0000
#define GFX_GPU_FIFO_OVFL_IRQ_EN 0x0020
124,10 → 127,13
 
// GFX_STATUS Register
#define STATUS_REFRESH_BUSY 0x0001
#define STATUS_GPU_FIFO 0x0010
#define STATUS_GPU_BUSY 0x0040
 
// GFX_IRQ Register
#define GFX_IRQ_REFRESH_DONE 0x0001
#define GFX_IRQ_REFRESH_START 0x0002
#define GFX_IRQ_REFRESH_CNT_DONE 0x0004
#define GFX_IRQ_GPU_FIFO_DONE 0x0010
#define GFX_IRQ_GPU_FIFO_OVFL 0x0020
#define GFX_IRQ_GPU_CMD_DONE 0x0040
184,6 → 190,57
#define LT24_STATUS_REFRESH_WAIT 0x0008
#define LT24_STATUS_DFILL_BUSY 0x0010
 
// LUT_CFG Register
#define SW_LUT_DISABLE 0x0000
#define SW_LUT_ENABLE 0x0001
#define SW_LUT_RAM_RMW_MODE 0x0002
#define SW_LUT_RAM_NO_RMW_MODE 0x0000
#define SW_LUT_BANK0_SELECT 0x0000
#define SW_LUT_BANK1_SELECT 0x0004
#define HW_LUT_PALETTE_0_HI 0x0000
#define HW_LUT_PALETTE_0_LO 0x0010
#define HW_LUT_PALETTE_1_HI 0x0020
#define HW_LUT_PALETTE_1_LO 0x0030
#define HW_LUT_PALETTE_2_HI 0x0040
#define HW_LUT_PALETTE_2_LO 0x0050
#define HW_LUT_PALETTE_MSK 0x0070
#define HW_LUT_BGCOLOR_MSK 0x0F00
#define HW_LUT_FGCOLOR_MSK 0xF000
 
#define HW_LUT_BG_BLACK 0x0000
#define HW_LUT_BG_BLUE 0x0100
#define HW_LUT_BG_GREEN 0x0200
#define HW_LUT_BG_CYAN 0x0300
#define HW_LUT_BG_RED 0x0400
#define HW_LUT_BG_MAGENTA 0x0500
#define HW_LUT_BG_BROWN 0x0600
#define HW_LUT_BG_LIGHT_GRAY 0x0700
#define HW_LUT_BG_GRAY 0x0800
#define HW_LUT_BG_LIGHT_BLUE 0x0900
#define HW_LUT_BG_LIGHT_GREEN 0x0A00
#define HW_LUT_BG_LIGHT_CYAN 0x0B00
#define HW_LUT_BG_LIGHT_RED 0x0C00
#define HW_LUT_BG_LIGHT_MAGENTA 0x0D00
#define HW_LUT_BG_YELLOW 0x0E00
#define HW_LUT_BG_WHITE 0x0F00
 
#define HW_LUT_FG_BLACK 0x0000
#define HW_LUT_FG_BLUE 0x1000
#define HW_LUT_FG_GREEN 0x2000
#define HW_LUT_FG_CYAN 0x3000
#define HW_LUT_FG_RED 0x4000
#define HW_LUT_FG_MAGENTA 0x5000
#define HW_LUT_FG_BROWN 0x6000
#define HW_LUT_FG_LIGHT_GRAY 0x7000
#define HW_LUT_FG_GRAY 0x8000
#define HW_LUT_FG_LIGHT_BLUE 0x9000
#define HW_LUT_FG_LIGHT_GREEN 0xA000
#define HW_LUT_FG_LIGHT_CYAN 0xB000
#define HW_LUT_FG_LIGHT_RED 0xC000
#define HW_LUT_FG_LIGHT_MAGENTA 0xD000
#define HW_LUT_FG_YELLOW 0xE000
#define HW_LUT_FG_WHITE 0xF000
 
// FRAME_SELECT Register
#define REFRESH_FRAME0_SELECT 0x0000
#define REFRESH_FRAME1_SELECT 0x0001
191,11 → 248,6
#define REFRESH_FRAME3_SELECT 0x0003
#define REFRESH_FRAME_MASK 0x0003
 
#define REFRESH_SW_LUT_DISABLE 0x0000
#define REFRESH_SW_LUT_ENABLE 0x0004
#define REFRESH_SW_LUT0_SELECT 0x0000
#define REFRESH_SW_LUT1_SELECT 0x0008
 
#define VID_RAM0_FRAME0_SELECT 0x0000
#define VID_RAM0_FRAME1_SELECT 0x0010
#define VID_RAM0_FRAME2_SELECT 0x0020
208,9 → 260,6
#define VID_RAM1_FRAME3_SELECT 0x00C0
#define VID_RAM1_FRAME_MASK 0x00C0
 
#define LUT_BANK0_SELECT 0x0000
#define LUT_BANK1_SELECT 0x8000
 
// VID_RAMx_CFG Register
#define VID_RAM_RMW_MODE 0x0010
#define VID_RAM_MSK_MODE 0x0020
/synthesis/altera/bitstreams/gfx_demo.jic Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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