URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog
- from Rev 157 to Rev 162
- ↔ Reverse comparison
Rev 157 → Rev 162
/tb_openMSP430_fpga.v
72,7 → 72,6
// UART |
wire PMOD1_P1; |
reg PMOD1_P4; |
reg PMOD1_P8; |
|
// Core debug signals |
wire [8*32-1:0] i_state; |
156,7 → 155,6
SW1 = 1'b0; |
UART_RXD = 1'b1; // UART |
PMOD1_P4 = 1'b1; |
PMOD1_P8 = 1'b0; |
end |
|
// |
318,7 → 316,7
.PMOD1_P3 (), |
.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX |
.PMOD1_P7 (), |
.PMOD1_P8 (PMOD1_P8), // Serial Debug Interface enable |
.PMOD1_P8 (), |
.PMOD1_P9 (), |
.PMOD1_P10 (), |
|