OpenCores

/registers.v File deleted

registers.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: ram_16x2k.v =================================================================== --- ram_16x2k.v (revision 162) +++ ram_16x2k.v (nonexistent) @@ -1,74 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: ram.v -// -// *Module Description: -// Scalable RAM model -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 103 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ -//---------------------------------------------------------------------------- - -module ram_16x2k( - clka, - ena, - wea, - addra, - dina, - douta -); - -input clka; -input ena; -input [1 : 0] wea; -input [10 : 0] addra; -input [15 : 0] dina; -output [15 : 0] douta; - -//============ -// RAM -//============ - -ram #(.ADDR_MSB(10), .MEM_SIZE(4096)) ram_inst ( - -// OUTPUTs - .ram_dout ( douta), // RAM data output - -// INPUTs - .ram_addr ( addra), // RAM address - .ram_cen (~ena), // RAM chip enable (low active) - .ram_clk ( clka), // RAM clock - .ram_din ( dina), // RAM data input - .ram_wen (~wea) // RAM write enable (low active) -); - - -endmodule // ram_16x512 -

ram_16x2k.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: ram_16x512.v =================================================================== --- ram_16x512.v (revision 162) +++ ram_16x512.v (nonexistent) @@ -1,75 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: ram.v -// -// *Module Description: -// Scalable RAM model -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 103 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ -//---------------------------------------------------------------------------- - -module ram_16x512( - clka, - ena, - wea, - addra, - dina, - douta -); - -input clka; -input ena; -input [1 : 0] wea; -input [8 : 0] addra; -input [15 : 0] dina; -output [15 : 0] douta; - - -//============ -// RAM -//============ - -ram #(.ADDR_MSB(8), .MEM_SIZE(1024)) ram_inst ( - -// OUTPUTs - .ram_dout ( douta), // RAM data output - -// INPUTs - .ram_addr ( addra), // RAM address - .ram_cen (~ena), // RAM chip enable (low active) - .ram_clk ( clka), // RAM clock - .ram_din ( dina), // RAM data input - .ram_wen (~wea) // RAM write enable (low active) -); - - -endmodule // ram_16x512 -

ram_16x512.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: ram.v =================================================================== --- ram.v (revision 162) +++ ram.v (nonexistent) @@ -1,91 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: ram.v -// -// *Module Description: -// Scalable RAM model -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 103 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ -//---------------------------------------------------------------------------- - -module ram ( - -// OUTPUTs - ram_dout, // RAM data output - -// INPUTs - ram_addr, // RAM address - ram_cen, // RAM chip enable (low active) - ram_clk, // RAM clock - ram_din, // RAM data input - ram_wen // RAM write enable (low active) -); - -// PARAMETERs -//============ -parameter ADDR_MSB = 6; // MSB of the address bus -parameter MEM_SIZE = 256; // Memory size in bytes - -// OUTPUTs -//============ -output [15:0] ram_dout; // RAM data output - -// INPUTs -//============ -input [ADDR_MSB:0] ram_addr; // RAM address -input ram_cen; // RAM chip enable (low active) -input ram_clk; // RAM clock -input [15:0] ram_din; // RAM data input -input [1:0] ram_wen; // RAM write enable (low active) - - -// RAM -//============ - -reg [15:0] mem [0:(MEM_SIZE/2)-1]; -reg [ADDR_MSB:0] ram_addr_reg; - -wire [15:0] mem_val = mem[ram_addr]; - - -always @(posedge ram_clk) - if (~ram_cen & ram_addr<(MEM_SIZE/2)) - begin - if (ram_wen==2'b00) mem[ram_addr] <= ram_din; - else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]}; - else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]}; - ram_addr_reg <= ram_addr; - end - -assign ram_dout = mem[ram_addr_reg]; - - -endmodule // ram

ram.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: ram_16x1k_sp.v =================================================================== --- ram_16x1k_sp.v (nonexistent) +++ ram_16x1k_sp.v (revision 167) @@ -0,0 +1,74 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ram.v +// +// *Module Description: +// Scalable RAM model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module ram_16x1k_sp ( + clka, + ena, + wea, + addra, + dina, + douta +); + +input clka; +input ena; +input [1 : 0] wea; +input [9 : 0] addra; +input [15 : 0] dina; +output [15 : 0] douta; + +//============ +// RAM +//============ + +ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst ( + +// OUTPUTs + .ram_dout ( douta), // RAM data output + +// INPUTs + .ram_addr ( addra), // RAM address + .ram_cen (~ena), // RAM chip enable (low active) + .ram_clk ( clka), // RAM clock + .ram_din ( dina), // RAM data input + .ram_wen (~wea) // RAM write enable (low active) +); + + +endmodule // ram_16x1k_sp +

ram_16x1k_sp.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: ram_16x1k_dp.v =================================================================== --- ram_16x1k_dp.v (nonexistent) +++ ram_16x1k_dp.v (revision 167) @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ram.v +// +// *Module Description: +// Scalable RAM model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module ram_16x1k_dp ( + clka, + ena, + wea, + addra, + dina, + douta, + clkb, + enb, + web, + addrb, + dinb, + doutb +); + +input clka; +input ena; +input [1 : 0] wea; +input [9 : 0] addra; +input [15 : 0] dina; +output [15 : 0] douta; +input clkb; +input enb; +input [1 : 0] web; +input [9 : 0] addrb; +input [15 : 0] dinb; +output [15 : 0] doutb; + + +//============ +// RAM +//============ + +ram_dp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_dp_inst ( + +// OUTPUTs + .ram_douta ( douta), // RAM data output (Port A) + .ram_doutb ( douta), // RAM data output (Port B) + +// INPUTs + .ram_addra ( addra), // RAM address (Port A) + .ram_cena (~ena), // RAM chip enable (low active) (Port A) + .ram_clka ( clka), // RAM clock (Port A) + .ram_dina ( dina), // RAM data input (Port A) + .ram_wena (~wea), // RAM write enable (low active) (Port A) + .ram_addrb ( addrb), // RAM address (Port B) + .ram_cenb (~enb), // RAM chip enable (low active) (Port B) + .ram_clkb ( clkb), // RAM clock (Port B) + .ram_dinb ( dinb), // RAM data input (Port B) + .ram_wenb (~web) // RAM write enable (low active) (Port B) +); + + +endmodule // ram_16x1k_dp +

ram_16x1k_dp.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: ram_sp.v =================================================================== --- ram_sp.v (nonexistent) +++ ram_sp.v (revision 167) @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ram.v +// +// *Module Description: +// Scalable Single-Port RAM model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module ram_sp ( + +// OUTPUTs + ram_dout, // RAM data output + +// INPUTs + ram_addr, // RAM address + ram_cen, // RAM chip enable (low active) + ram_clk, // RAM clock + ram_din, // RAM data input + ram_wen // RAM write enable (low active) +); + +// PARAMETERs +//============ +parameter ADDR_MSB = 6; // MSB of the address bus +parameter MEM_SIZE = 256; // Memory size in bytes + +// OUTPUTs +//============ +output [15:0] ram_dout; // RAM data output + +// INPUTs +//============ +input [ADDR_MSB:0] ram_addr; // RAM address +input ram_cen; // RAM chip enable (low active) +input ram_clk; // RAM clock +input [15:0] ram_din; // RAM data input +input [1:0] ram_wen; // RAM write enable (low active) + + +// RAM +//============ + +reg [15:0] mem [0:(MEM_SIZE/2)-1]; +reg [ADDR_MSB:0] ram_addr_reg; + +wire [15:0] mem_val = mem[ram_addr]; + + +always @(posedge ram_clk) + if (~ram_cen && (ram_addr<(MEM_SIZE/2))) + begin + if (ram_wen==2'b00) mem[ram_addr] <= ram_din; + else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]}; + else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]}; + ram_addr_reg <= ram_addr; + end + +assign ram_dout = mem[ram_addr_reg]; + + +endmodule // ram_sp

ram_sp.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: ram_dp.v =================================================================== --- ram_dp.v (nonexistent) +++ ram_dp.v (revision 167) @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ram.v +// +// *Module Description: +// Scalable Dual-Port RAM model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module ram_dp ( + +// OUTPUTs + ram_douta, // RAM data output (Port A) + ram_doutb, // RAM data output (Port B) + +// INPUTs + ram_addra, // RAM address (Port A) + ram_cena, // RAM chip enable (low active) (Port A) + ram_clka, // RAM clock (Port A) + ram_dina, // RAM data input (Port A) + ram_wena, // RAM write enable (low active) (Port A) + ram_addrb, // RAM address (Port B) + ram_cenb, // RAM chip enable (low active) (Port B) + ram_clkb, // RAM clock (Port B) + ram_dinb, // RAM data input (Port B) + ram_wenb // RAM write enable (low active) (Port B) +); + +// PARAMETERs +//============ +parameter ADDR_MSB = 6; // MSB of the address bus +parameter MEM_SIZE = 256; // Memory size in bytes + +// OUTPUTs +//============ +output [15:0] ram_douta; // RAM data output (Port A) +output [15:0] ram_doutb; // RAM data output (Port B) + +// INPUTs +//============ +input [ADDR_MSB:0] ram_addra; // RAM address (Port A) +input ram_cena; // RAM chip enable (low active) (Port A) +input ram_clka; // RAM clock (Port A) +input [15:0] ram_dina; // RAM data input (Port A) +input [1:0] ram_wena; // RAM write enable (low active) (Port A) +input [ADDR_MSB:0] ram_addrb; // RAM address (Port B) +input ram_cenb; // RAM chip enable (low active) (Port B) +input ram_clkb; // RAM clock (Port B) +input [15:0] ram_dinb; // RAM data input (Port B) +input [1:0] ram_wenb; // RAM write enable (low active) (Port B) + + +// RAM +//============ + +reg [15:0] mem [0:(MEM_SIZE/2)-1]; +reg [ADDR_MSB:0] ram_addra_reg; +reg [ADDR_MSB:0] ram_addrb_reg; + +wire [15:0] mem_vala = mem[ram_addra]; +wire [15:0] mem_valb = mem[ram_addrb]; + + +always @(posedge ram_clka) + if (~ram_cena && (ram_addra<(MEM_SIZE/2))) + begin + if (ram_wena==2'b00) mem[ram_addra] <= ram_dina; + else if (ram_wena==2'b01) mem[ram_addra] <= {ram_dina[15:8], mem_vala[7:0]}; + else if (ram_wena==2'b10) mem[ram_addra] <= {mem_vala[15:8], ram_dina[7:0]}; + ram_addra_reg <= ram_addra; + end + +assign ram_douta = mem[ram_addra_reg]; + + +always @(posedge ram_clkb) + if (~ram_cenb && (ram_addrb<(MEM_SIZE/2))) + begin + if (ram_wenb==2'b00) mem[ram_addrb] <= ram_dinb; + else if (ram_wenb==2'b01) mem[ram_addrb] <= {ram_dinb[15:8], mem_valb[7:0]}; + else if (ram_wenb==2'b10) mem[ram_addrb] <= {mem_valb[15:8], ram_dinb[7:0]}; + ram_addrb_reg <= ram_addrb; + end + +assign ram_doutb = mem[ram_addrb_reg]; + + +endmodule // ram_dp

ram_dp.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: ram_16x8k_dp.v =================================================================== --- ram_16x8k_dp.v (nonexistent) +++ ram_16x8k_dp.v (revision 167) @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ram.v +// +// *Module Description: +// Scalable RAM model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module ram_16x8k_dp ( + clka, + ena, + wea, + addra, + dina, + douta, + clkb, + enb, + web, + addrb, + dinb, + doutb +); + +input clka; +input ena; +input [1 : 0] wea; +input [12 : 0] addra; +input [15 : 0] dina; +output [15 : 0] douta; +input clkb; +input enb; +input [1 : 0] web; +input [12 : 0] addrb; +input [15 : 0] dinb; +output [15 : 0] doutb; + + +//============ +// RAM +//============ + +ram_dp #(.ADDR_MSB(12), .MEM_SIZE(16384)) ram_dp_inst ( + +// OUTPUTs + .ram_douta ( douta), // RAM data output (Port A) + .ram_doutb ( doutb), // RAM data output (Port B) + +// INPUTs + .ram_addra ( addra), // RAM address (Port A) + .ram_cena (~ena), // RAM chip enable (low active) (Port A) + .ram_clka ( clka), // RAM clock (Port A) + .ram_dina ( dina), // RAM data input (Port A) + .ram_wena (~wea), // RAM write enable (low active) (Port A) + .ram_addrb ( addrb), // RAM address (Port B) + .ram_cenb (~enb), // RAM chip enable (low active) (Port B) + .ram_clkb ( clkb), // RAM clock (Port B) + .ram_dinb ( dinb), // RAM data input (Port B) + .ram_wenb (~web) // RAM write enable (low active) (Port B) +); + + +endmodule // ram_16x8k_dp +

ram_16x8k_dp.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: msp_debug.v =================================================================== --- msp_debug.v (revision 162) +++ msp_debug.v (revision 167) @@ -52,8 +52,7 @@ inst_short, // Currently executed instruction (short version) // INPUTs - mclk, // Main system clock - puc_rst // Main system reset + core_select // Core selection ); // OUTPUTs @@ -68,8 +67,7 @@ // INPUTs //============ -input mclk; // Main system clock -input puc_rst; // Main system reset +input core_select; // Core selection //============================================================================= @@ -112,16 +110,52 @@ // 2) CONNECTIONS TO MSP430 CORE INTERNALS //============================================================================= -wire [2:0] i_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.i_state; -wire [3:0] e_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.e_state; +//------------------------- +// CPU 0 +//------------------------- +wire [2:0] omsp0_i_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.i_state; +wire [3:0] omsp0_e_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.e_state; -wire decode = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.decode; -wire [15:0] ir = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.ir; -wire irq_detect = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_detect; -wire [3:0] irq_num = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_num; -wire [15:0] pc = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.pc; +wire omsp0_decode = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.decode; +wire [15:0] omsp0_ir = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.ir; +wire omsp0_irq_detect = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_detect; +wire [3:0] omsp0_irq_num = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_num; +wire [15:0] omsp0_pc = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.pc; +wire omsp0_mclk = tb_openMSP430_fpga.dut.omsp_system_0_inst.mclk; +wire omsp0_puc_rst = tb_openMSP430_fpga.dut.omsp_system_0_inst.puc_rst; +//------------------------- +// CPU 1 +//------------------------- +wire [2:0] omsp1_i_state_bin = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.i_state; +wire [3:0] omsp1_e_state_bin = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.e_state; + +wire omsp1_decode = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.decode; +wire [15:0] omsp1_ir = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.ir; +wire omsp1_irq_detect = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.irq_detect; +wire [3:0] omsp1_irq_num = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.irq_num; +wire [15:0] omsp1_pc = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.pc; + +wire omsp1_mclk = tb_openMSP430_fpga.dut.omsp_system_1_inst.mclk; +wire omsp1_puc_rst = tb_openMSP430_fpga.dut.omsp_system_1_inst.puc_rst; + +//------------------------- +// CPU Selection +//------------------------- +wire [2:0] i_state_bin = core_select ? omsp1_i_state_bin : omsp0_i_state_bin; +wire [3:0] e_state_bin = core_select ? omsp1_e_state_bin : omsp0_e_state_bin; + +wire decode = core_select ? omsp1_decode : omsp0_decode; +wire [15:0] ir = core_select ? omsp1_ir : omsp0_ir; +wire irq_detect = core_select ? omsp1_irq_detect : omsp0_irq_detect; +wire [3:0] irq_num = core_select ? omsp1_irq_num : omsp0_irq_num; +wire [15:0] pc = core_select ? omsp1_pc : omsp0_pc; + +wire mclk = core_select ? omsp1_mclk : omsp0_mclk; +wire puc_rst = core_select ? omsp1_puc_rst : omsp0_puc_rst; + + //============================================================================= // 3) GENERATE DEBUG SIGNALS //=============================================================================

/registers_omsp0.v

0,0 → 1,167

registers_omsp0.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: registers_omsp1.v =================================================================== --- registers_omsp1.v (nonexistent) +++ registers_omsp1.v (revision 167) @@ -0,0 +1,148 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: registers.v +// +// *Module Description: +// Direct connections to internal registers & memory. +// +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 143 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2012-05-09 22:20:03 +0200 (Wed, 09 May 2012) $ +//---------------------------------------------------------------------------- + +// CPU registers +//====================== + +wire [15:0] omsp1_r0 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r0; +wire [15:0] omsp1_r1 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r1; +wire [15:0] omsp1_r2 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r2; +wire [15:0] omsp1_r3 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r3; +wire [15:0] omsp1_r4 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r4; +wire [15:0] omsp1_r5 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r5; +wire [15:0] omsp1_r6 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r6; +wire [15:0] omsp1_r7 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r7; +wire [15:0] omsp1_r8 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r8; +wire [15:0] omsp1_r9 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r9; +wire [15:0] omsp1_r10 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r10; +wire [15:0] omsp1_r11 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r11; +wire [15:0] omsp1_r12 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r12; +wire [15:0] omsp1_r13 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r13; +wire [15:0] omsp1_r14 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r14; +wire [15:0] omsp1_r15 = dut.omsp_system_1_inst.openMSP430_0.execution_unit_0.register_file_0.r15; + + +// Data Memory cells +//====================== + +wire [15:0] omsp1_mem200 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[0]; +wire [15:0] omsp1_mem202 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[1]; +wire [15:0] omsp1_mem204 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[2]; +wire [15:0] omsp1_mem206 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[3]; +wire [15:0] omsp1_mem208 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[4]; +wire [15:0] omsp1_mem20A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[5]; +wire [15:0] omsp1_mem20C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[6]; +wire [15:0] omsp1_mem20E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[7]; +wire [15:0] omsp1_mem210 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[8]; +wire [15:0] omsp1_mem212 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[9]; +wire [15:0] omsp1_mem214 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[10]; +wire [15:0] omsp1_mem216 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[11]; +wire [15:0] omsp1_mem218 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[12]; +wire [15:0] omsp1_mem21A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[13]; +wire [15:0] omsp1_mem21C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[14]; +wire [15:0] omsp1_mem21E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[15]; +wire [15:0] omsp1_mem220 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[16]; +wire [15:0] omsp1_mem222 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[17]; +wire [15:0] omsp1_mem224 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[18]; +wire [15:0] omsp1_mem226 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[19]; +wire [15:0] omsp1_mem228 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[20]; +wire [15:0] omsp1_mem22A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[21]; +wire [15:0] omsp1_mem22C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[22]; +wire [15:0] omsp1_mem22E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[23]; +wire [15:0] omsp1_mem230 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[24]; +wire [15:0] omsp1_mem232 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[25]; +wire [15:0] omsp1_mem234 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[26]; +wire [15:0] omsp1_mem236 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[27]; +wire [15:0] omsp1_mem238 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[28]; +wire [15:0] omsp1_mem23A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[29]; +wire [15:0] omsp1_mem23C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[30]; +wire [15:0] omsp1_mem23E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[31]; +wire [15:0] omsp1_mem240 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[32]; +wire [15:0] omsp1_mem242 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[33]; +wire [15:0] omsp1_mem244 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[34]; +wire [15:0] omsp1_mem246 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[35]; +wire [15:0] omsp1_mem248 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[36]; +wire [15:0] omsp1_mem24A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[37]; +wire [15:0] omsp1_mem24C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[38]; +wire [15:0] omsp1_mem24E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[39]; +wire [15:0] omsp1_mem250 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[40]; +wire [15:0] omsp1_mem252 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[41]; +wire [15:0] omsp1_mem254 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[42]; +wire [15:0] omsp1_mem256 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[43]; +wire [15:0] omsp1_mem258 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[44]; +wire [15:0] omsp1_mem25A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[45]; +wire [15:0] omsp1_mem25C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[46]; +wire [15:0] omsp1_mem25E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[47]; +wire [15:0] omsp1_mem260 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[48]; +wire [15:0] omsp1_mem262 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[49]; +wire [15:0] omsp1_mem264 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[50]; +wire [15:0] omsp1_mem266 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[51]; +wire [15:0] omsp1_mem268 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[52]; +wire [15:0] omsp1_mem26A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[53]; +wire [15:0] omsp1_mem26C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[54]; +wire [15:0] omsp1_mem26E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[55]; +wire [15:0] omsp1_mem270 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[56]; +wire [15:0] omsp1_mem272 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[57]; +wire [15:0] omsp1_mem274 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[58]; +wire [15:0] omsp1_mem276 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[59]; +wire [15:0] omsp1_mem278 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[60]; +wire [15:0] omsp1_mem27A = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[61]; +wire [15:0] omsp1_mem27C = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[62]; +wire [15:0] omsp1_mem27E = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[63]; +wire [15:0] omsp1_mem280 = dut.ram_16x1k_sp_dmem_omsp1.ram_sp_inst.mem[64]; + + +// Program Memory cells +//====================== + +// Interrupt detection +wire omsp1_nmi_detect = dut.omsp_system_1_inst.openMSP430_0.frontend_0.nmi_pnd; +wire omsp1_irq_detect = dut.omsp_system_1_inst.openMSP430_0.frontend_0.irq_detect; + +// Debug interface +wire omsp1_dbg_en = dut.omsp_system_1_inst.openMSP430_0.dbg_en; +wire omsp1_dbg_clk = dut.omsp_system_1_inst.openMSP430_0.clock_module_0.dbg_clk; +wire omsp1_dbg_rst = dut.omsp_system_1_inst.openMSP430_0.clock_module_0.dbg_rst; + + +// CPU internals +//====================== + +wire omsp1_mclk = dut.omsp_system_1_inst.openMSP430_0.mclk; +wire omsp1_puc_rst = dut.omsp_system_1_inst.openMSP430_0.puc_rst;

registers_omsp1.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: tb_openMSP430_fpga.v =================================================================== --- tb_openMSP430_fpga.v (revision 162) +++ tb_openMSP430_fpga.v (revision 167) @@ -74,14 +74,22 @@ reg PMOD1_P4; // Core debug signals -wire [8*32-1:0] i_state; -wire [8*32-1:0] e_state; -wire [31:0] inst_cycle; -wire [8*32-1:0] inst_full; -wire [31:0] inst_number; -wire [15:0] inst_pc; -wire [8*32-1:0] inst_short; +wire [8*32-1:0] omsp0_i_state; +wire [8*32-1:0] omsp0_e_state; +wire [31:0] omsp0_inst_cycle; +wire [8*32-1:0] omsp0_inst_full; +wire [31:0] omsp0_inst_number; +wire [15:0] omsp0_inst_pc; +wire [8*32-1:0] omsp0_inst_short; +wire [8*32-1:0] omsp1_i_state; +wire [8*32-1:0] omsp1_e_state; +wire [31:0] omsp1_inst_cycle; +wire [8*32-1:0] omsp1_inst_full; +wire [31:0] omsp1_inst_number; +wire [15:0] omsp1_inst_pc; +wire [8*32-1:0] omsp1_inst_short; + // Testbench variables integer i; integer error; @@ -93,7 +101,8 @@ //------------------------------ // CPU & Memory registers -`include "registers.v" +`include "registers_omsp0.v" +`include "registers_omsp1.v" // Verilog stimulus `include "stimulus.v" @@ -108,9 +117,9 @@ #10 $readmemh("./pmem.mem", pmem); // Update Xilinx memory banks - for (i=0; i<2048; i=i+1) + for (i=0; i<8192; i=i+1) begin - dut.ram_16x2k_pmem.ram_inst.mem[i] = pmem[i]; + dut.ram_16x8k_dp_pmem_shared.ram_dp_inst.mem[i] = pmem[i]; end end @@ -334,22 +343,36 @@ // Debug utility signals //---------------------------------------- -msp_debug msp_debug_0 ( +msp_debug msp_debug_omsp0 ( // OUTPUTs - .e_state (e_state), // Execution state - .i_state (i_state), // Instruction fetch state - .inst_cycle (inst_cycle), // Cycle number within current instruction - .inst_full (inst_full), // Currently executed instruction (full version) - .inst_number (inst_number), // Instruction number since last system reset - .inst_pc (inst_pc), // Instruction Program counter - .inst_short (inst_short), // Currently executed instruction (short version) + .e_state (omsp0_e_state), // Execution state + .i_state (omsp0_i_state), // Instruction fetch state + .inst_cycle (omsp0_inst_cycle), // Cycle number within current instruction + .inst_full (omsp0_inst_full), // Currently executed instruction (full version) + .inst_number (omsp0_inst_number), // Instruction number since last system reset + .inst_pc (omsp0_inst_pc), // Instruction Program counter + .inst_short (omsp0_inst_short), // Currently executed instruction (short version) // INPUTs - .mclk (mclk), // Main system clock - .puc_rst (puc_rst) // Main system reset + .core_select (0) // Core selection ); +msp_debug msp_debug_omsp1 ( + +// OUTPUTs + .e_state (omsp1_e_state), // Execution state + .i_state (omsp1_i_state), // Instruction fetch state + .inst_cycle (omsp1_inst_cycle), // Cycle number within current instruction + .inst_full (omsp1_inst_full), // Currently executed instruction (full version) + .inst_number (omsp1_inst_number), // Instruction number since last system reset + .inst_pc (omsp1_inst_pc), // Instruction Program counter + .inst_short (omsp1_inst_short), // Currently executed instruction (short version) + +// INPUTs + .core_select (1) // Core selection +); + // // Generate Waveform //---------------------------------------- @@ -385,7 +408,7 @@ initial // Normal end of test begin - @(inst_pc===16'hffff) + @(omsp0_inst_pc===16'hffff) $display(" ==============================================="); if (error!=0) begin

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