URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/sim
- from Rev 157 to Rev 162
- ↔ Reverse comparison
Rev 157 → Rev 162
rtl_sim/run
Property changes :
Added: svn:ignore
## -0,0 +1,4 ##
+pmem.*
+*.vcd
+simv
+stimulus.v
Index: rtl_sim/src/submit.f
===================================================================
--- rtl_sim/src/submit.f (revision 157)
+++ rtl_sim/src/submit.f (revision 162)
@@ -84,6 +84,7 @@
../../../rtl/verilog/openmsp430/omsp_dbg.v
../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
+../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v
../../../rtl/verilog/openmsp430/omsp_watchdog.v
../../../rtl/verilog/openmsp430/omsp_multiplier.v
../../../rtl/verilog/openmsp430/omsp_sync_reset.v
Index: rtl_sim/src/leds.v
===================================================================
--- rtl_sim/src/leds.v (revision 157)
+++ rtl_sim/src/leds.v (revision 162)
@@ -13,11 +13,11 @@
stimulus_done = 0;
repeat(100) @(posedge CLK_40MHz);
- PMOD1_P8 = 1;
+ // PMOD1_P8 = 1;
repeat(500) @(posedge CLK_40MHz);
- PMOD1_P8 = 0;
+ // PMOD1_P8 = 0;
repeat(100) @(posedge CLK_40MHz);
- PMOD1_P8 = 1;
+ // PMOD1_P8 = 1;
repeat(500) @(posedge CLK_40MHz);
/rtl_sim/src/submit.prj
29,6 → 29,7
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v |