URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/sim
- from Rev 162 to Rev 167
- ↔ Reverse comparison
Rev 162 → Rev 167
/rtl_sim/src/submit.f
41,9 → 41,11
../../../bench/verilog/tb_openMSP430_fpga.v |
../../../bench/verilog/msp_debug.v |
../../../bench/verilog/glbl.v |
../../../bench/verilog/ram_16x512.v |
../../../bench/verilog/ram_16x2k.v |
../../../bench/verilog/ram.v |
../../../bench/verilog/ram_16x8k_dp.v |
../../../bench/verilog/ram_16x1k_dp.v |
../../../bench/verilog/ram_dp.v |
../../../bench/verilog/ram_16x1k_sp.v |
../../../bench/verilog/ram_sp.v |
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//============================================================================= |
63,6 → 65,7
+incdir+../../../rtl/verilog/ |
../../../rtl/verilog/openMSP430_fpga.v |
../../../rtl/verilog/omsp_system_0.v |
../../../rtl/verilog/omsp_system_1.v |
../../../rtl/verilog/io_mux.v |
../../../rtl/verilog/omsp_uart.v |
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/rtl_sim/src/submit.prj
2,9 → 2,11
verilog work ../../../bench/verilog/tb_openMSP430_fpga.v |
verilog work ../../../bench/verilog/msp_debug.v |
verilog work ../../../bench/verilog/glbl.v |
verilog work ../../../bench/verilog/ram_16x512.v |
verilog work ../../../bench/verilog/ram_16x2k.v |
verilog work ../../../bench/verilog/ram.v |
verilog work ../../../bench/verilog/ram_16x8k_dp.v |
verilog work ../../../bench/verilog/ram_16x1k_dp.v |
verilog work ../../../bench/verilog/ram_dp.v |
verilog work ../../../bench/verilog/ram_16x1k_sp.v |
verilog work ../../../bench/verilog/ram_sp.v |
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v |
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v |
15,6 → 17,7
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verilog work ../../../rtl/verilog/openMSP430_fpga.v |
verilog work ../../../rtl/verilog/omsp_system_0.v |
verilog work ../../../rtl/verilog/omsp_system_1.v |
verilog work ../../../rtl/verilog/io_mux.v |
verilog work ../../../rtl/verilog/omsp_uart.v |
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