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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/sim
    from Rev 202 to Rev 212
    ↔ Reverse comparison
  •

Rev 202 → Rev 212

/rtl_sim/run/run_clean
0,0 → 1,3
#!/bin/bash
 
rm -rf INCA_libs *.log pmem.* stimulus.v *.dsn *.trn *.vcd simv
rtl_sim/run/run_clean Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/src/submit.f =================================================================== --- rtl_sim/src/submit.f (revision 202) +++ rtl_sim/src/submit.f (revision 212) @@ -53,9 +53,9 @@ //============================================================================= +libext+.v --y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ --y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/simprims/ --y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ +-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/ +-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/ +-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/XilinxCoreLib/ //=============================================================================
/rtl_sim/src/submit.prj
8,12 → 8,12
verilog work ../../../bench/verilog/ram_16x1k_sp.v
verilog work ../../../bench/verilog/ram_sp.v
 
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v
verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/IBUF.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/IBUFG.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/BUFG.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/OBUF.v
verilog work /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/IOBUF.v
 
verilog work ../../../rtl/verilog/openMSP430_fpga.v
verilog work ../../../rtl/verilog/omsp_system_0.v
44,4 → 44,3
verilog work ../../../rtl/verilog/openmsp430/omsp_clock_mux.v
verilog work ../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
verilog work ../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
 
/rtl_sim/bin/msp430sim
22,16 → 22,16
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#------------------------------------------------------------------------------
#
#
# File Name: msp430sim
#
#
# Author(s):
# - Olivier Girard, olgirard@gmail.com
#
#------------------------------------------------------------------------------
# $Rev: 151 $
# $Rev: 73 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
# $LastChangedDate: 2010-08-03 21:26:39 +0200 (Tue, 03 Aug 2010) $
#------------------------------------------------------------------------------
 
###############################################################################
103,6 → 103,32
echo "| Start simulation: $1"
echo " ======================================================="
 
# Make local copy of the openMSP403 configuration file
# and prepare it for MSPGCC preprocessing
cp $incfile ./pmem.h
sed -ie 's/`ifdef/#ifdef/g' ./pmem.h
sed -ie 's/`else/#else/g' ./pmem.h
sed -ie 's/`endif/#endif/g' ./pmem.h
sed -ie 's/`define/#define/g' ./pmem.h
sed -ie 's/`include/\/\/#include/g' ./pmem.h
sed -ie 's/`//g' ./pmem.h
sed -ie "s/'//g" ./pmem.h
 
# Use MSPGCC preprocessor to extract the Program, Data
# and Peripheral memory sizes
if command -v msp430-elf-gcc >/dev/null; then
msp430-elf-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
else
msp430-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
fi
 
# Source the extracted configuration file
if [[ $(uname -s) == CYGWIN* ]];
then
dos2unix pmem.sh
fi
source pmem.sh
 
# Make C program
cd $softdir
make clean
110,7 → 136,7
cd ../../sim/rtl_sim/run/
 
# Create links
if [ `uname -o` = "Cygwin" ]
if [[ $(uname -s) == CYGWIN* ]];
then
cp $elffile pmem.elf
cp $verfile stimulus.v
119,26 → 145,13
ln -s $verfile stimulus.v
fi
 
# Make local copy of the openMSP403 configuration file
# and prepare it for MSPGCC preprocessing
cp $incfile ./pmem.h
sed -i 's/`ifdef/#ifdef/g' ./pmem.h
sed -i 's/`else/#else/g' ./pmem.h
sed -i 's/`endif/#endif/g' ./pmem.h
sed -i 's/`define/#define/g' ./pmem.h
sed -i 's/`//g' ./pmem.h
sed -i "s/'//g" ./pmem.h
 
# Use MSPGCC preprocessor to extract the Program, Data
# and Peripheral memory sizes
msp430-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
 
# Source the extracted configuration file
source pmem.sh
 
# Create IHEX file from ELF
echo "Convert ELF file to IHEX format..."
msp430-objcopy -O ihex pmem.elf pmem.ihex
if command -v msp430-elf-objcopy >/dev/null; then
msp430-elf-objcopy -O ihex pmem.elf pmem.ihex
else
msp430-objcopy -O ihex pmem.elf pmem.ihex
fi
 
# Generate Program memory file
echo "Convert IHEX file to Verilog MEMH format..."
/rtl_sim/bin/rtlsim.sh
22,17 → 22,17
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#------------------------------------------------------------------------------
#
#
# File Name: rtlsim.sh
#
#
# Author(s):
# - Olivier Girard, olgirard@gmail.com
# - Mihai M., mmihai@delajii.net
#
#------------------------------------------------------------------------------
# $Rev: 138 $
# $Rev: 73 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2012-04-23 13:10:00 +0200 (Mon, 23 Apr 2012) $
# $LastChangedDate: 2010-08-03 12:26:39 -0700 (Tue, 03 Aug 2010) $
#------------------------------------------------------------------------------
 
###############################################################################
73,7 → 73,7
if [ "${OMSP_SIMULATOR:-iverilog}" = iverilog ]; then
 
rm -rf simv
 
NODUMP=${OMSP_NODUMP-0}
if [ $NODUMP -eq 1 ]
then
81,8 → 81,8
else
iverilog -o simv -c $3
fi
if [ `uname -o` = "Cygwin" ]
 
if [[ $(uname -s) == CYGWIN* ]];
then
vvp.exe ./simv
else
98,14 → 98,15
vargs=""
fi
 
case $OMSP_SIMULATOR in
cver* )
case $OMSP_SIMULATOR in
cver* )
vargs="$vargs +define+VXL +define+CVER" ;;
verilog* )
vargs="$vargs +define+VXL" ;;
ncverilog* )
rm -rf INCA_libs
vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
#vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
vargs="$vargs +access+r +nclicq +define+TRN_FILE" ;;
vcs* )
rm -rf csrc simv*
vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
117,12 → 118,12
isim )
# Xilinx simulator
rm -rf fuse* isim*
fuse tb_openMSP430_fpga glbl -mt off -v 1 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/openmsp430/ -i ../../../rtl/verilog/openmsp430/periph/
fuse tb_openMSP430 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/ -i ../../../rtl/verilog/periph/
echo "run all" > isim.tcl
./isim.exe -tclbatch isim.tcl
exit
esac
 
echo "Running: $OMSP_SIMULATOR -f $3 $vargs"
exec $OMSP_SIMULATOR -f $3 $vargs
fi

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