URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts
- from Rev 157 to Rev 167
- ↔ Reverse comparison
Rev 157 → Rev 167
/openMSP430_fpga.prj
39,11 → 39,13
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`include "../../../rtl/verilog/openMSP430_fpga.v" |
`include "../../../rtl/verilog/omsp_system_0.v" |
`include "../../../rtl/verilog/omsp_system_1.v" |
`include "../../../rtl/verilog/io_mux.v" |
//`include "../../../rtl/verilog/driver_7segment.v" |
`include "../../../rtl/verilog/omsp_uart.v" |
`include "../../../rtl/verilog/coregen/ram_16x2k.v" |
`include "../../../rtl/verilog/coregen/ram_16x512.v" |
`include "../../../rtl/verilog/coregen/ram_16x1k_sp.v" |
`include "../../../rtl/verilog/coregen/ram_16x1k_dp.v" |
`include "../../../rtl/verilog/coregen/ram_16x8k_dp.v" |
`include "../../../rtl/verilog/coregen_chipscope/chipscope_ila.v" |
`include "../../../rtl/verilog/coregen_chipscope/chipscope_icon.v" |
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/openMSP430_fpga.ucf
50,9 → 50,14
############################################################################ |
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# ROM Block Assignments |
INST "ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram" LOC = "RAMB16_X0Y20"; |
INST "ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram" LOC = "RAMB16_X0Y22"; |
#INST "ram_16x2k_pmem/B8" LOC = "RAMB16_X0Y22"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y18"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y10"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y24"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y16"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y22"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y14"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y20"; |
INST "ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram" LOC = "RAMB16_X0Y12"; |
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############################################################################ |
/memory.bmm
1,10 → 1,31
ADDRESS_SPACE blockrom RAMB16 [0x0000:0x0fff] |
ADDRESS_SPACE blockrom COMBINED [0x0000:0x3fff] |
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BUS_BLOCK |
ADDRESS_RANGE RAMB16 /* 0x0000 - 0x0FFF */ |
BUS_BLOCK |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8] LOC = X0Y18; |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [7:0] LOC = X0Y10; |
END_BUS_BLOCK; |
END_ADDRESS_RANGE; |
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ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram [7:0] LOC = X0Y22; |
ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram [15:8] LOC = X0Y20; |
ADDRESS_RANGE RAMB16 /* 0x1000 - 0x1FFF */ |
BUS_BLOCK |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8] LOC = X0Y24; |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [7:0] LOC = X0Y16; |
END_BUS_BLOCK; |
END_ADDRESS_RANGE; |
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END_BUS_BLOCK; |
ADDRESS_RANGE RAMB16 /* 0x2000 - 0x2FFF */ |
BUS_BLOCK |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8] LOC = X0Y22; |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [7:0] LOC = X0Y14; |
END_BUS_BLOCK; |
END_ADDRESS_RANGE; |
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ADDRESS_RANGE RAMB16 /* 0x3000 - 0x3FFF */ |
BUS_BLOCK |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8] LOC = X0Y20; |
ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [7:0] LOC = X0Y12; |
END_BUS_BLOCK; |
END_ADDRESS_RANGE; |
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END_ADDRESS_SPACE; |