URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench
- from Rev 104 to Rev 111
- ↔ Reverse comparison
Rev 104 → Rev 111
/verilog/msp_debug.v
53,7 → 53,7
|
// INPUTs |
mclk, // Main system clock |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
69,7 → 69,7
// INPUTs |
//============ |
input mclk; // Main system clock |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
171,13 → 171,13
//==================================== |
|
reg [31:0] inst_number; |
always @(posedge mclk or posedge puc) |
if (puc) inst_number <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_number <= 0; |
else if (decode) inst_number <= inst_number+1; |
|
reg [31:0] inst_cycle; |
always @(posedge mclk or posedge puc) |
if (puc) inst_cycle <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_cycle <= 0; |
else if (decode) inst_cycle <= 0; |
else inst_cycle <= inst_cycle+1; |
|
187,14 → 187,14
|
// Buffer opcode |
reg [15:0] opcode; |
always @(posedge mclk or posedge puc) |
if (puc) opcode <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) opcode <= 0; |
else if (decode) opcode <= ir; |
|
// Interrupts |
reg irq; |
always @(posedge mclk or posedge puc) |
if (puc) irq <= 1'b1; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) irq <= 1'b1; |
else if (decode) irq <= irq_detect; |
|
// Instruction type |
438,8 → 438,8
//================================ |
|
reg [15:0] inst_pc; |
always @(posedge mclk or posedge puc) |
if (puc) inst_pc <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_pc <= 16'h0000; |
else if (decode) inst_pc <= pc; |
|
|
/verilog/registers.v
153,5 → 153,5
// CPU internals |
//====================== |
|
wire mclk = dut.openMSP430_0.mclk; |
wire puc = dut.openMSP430_0.puc; |
wire mclk = dut.openMSP430_0.mclk; |
wire puc_rst = dut.openMSP430_0.puc_rst; |
/verilog/tb_openMSP430_fpga.v
318,7 → 318,7
|
// INPUTs |
.mclk (mclk), // Main system clock |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
// |