URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench
- from Rev 111 to Rev 136
- ↔ Reverse comparison
Rev 111 → Rev 136
/verilog/msp_debug.v
149,9 → 149,9
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always @(e_state_bin) |
case(e_state_bin) |
4'h0 : e_state = "IRQ_0"; |
4'h2 : e_state = "IRQ_0"; |
4'h1 : e_state = "IRQ_1"; |
4'h2 : e_state = "IRQ_2"; |
4'h0 : e_state = "IRQ_2"; |
4'h3 : e_state = "IRQ_3"; |
4'h4 : e_state = "IRQ_4"; |
4'h5 : e_state = "SRC_AD"; |
/verilog/registers.v
25,8 → 25,9
// *File Name: registers.v |
// |
// *Module Description: |
// openMSP430 testbench |
// Direct connections to internal registers & memory. |
// |
// |
// *Author(s): |
// - Olivier Girard, olgirard@gmail.com |
// |
150,6 → 151,16
wire [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0 |
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// Interrupt detection |
wire nmi_detect = dut.openMSP430_0.frontend_0.nmi_pnd; |
wire irq_detect = dut.openMSP430_0.frontend_0.irq_detect; |
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// Debug interface |
wire dbg_en = dut.openMSP430_0.dbg_en; |
wire dbg_clk = dut.openMSP430_0.clock_module_0.dbg_clk; |
wire dbg_rst = dut.openMSP430_0.clock_module_0.dbg_rst; |
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// CPU internals |
//====================== |
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