URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
- from Rev 155 to Rev 176
- ↔ Reverse comparison
Rev 155 → Rev 176
/omsp_dbg_hwbrk.v
58,13 → 58,10
dbg_clk, // Debug unit clock |
dbg_din, // Debug register data input |
dbg_rst, // Debug unit reset |
decode_noirq, // Frontend decode instruction |
eu_mab, // Execution-Unit Memory address bus |
eu_mb_en, // Execution-Unit Memory bus enable |
eu_mb_wr, // Execution-Unit Memory bus write transfer |
eu_mdb_in, // Memory data bus input |
eu_mdb_out, // Memory data bus output |
exec_done, // Execution completed |
fe_mb_en, // Frontend Memory bus enable |
pc // Program counter |
); |
|
81,13 → 78,10
input dbg_clk; // Debug unit clock |
input [15:0] dbg_din; // Debug register data input |
input dbg_rst; // Debug unit reset |
input decode_noirq; // Frontend decode instruction |
input [15:0] eu_mab; // Execution-Unit Memory address bus |
input eu_mb_en; // Execution-Unit Memory bus enable |
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer |
input [15:0] eu_mdb_in; // Memory data bus input |
input [15:0] eu_mdb_out; // Memory data bus output |
input exec_done; // Execution completed |
input fe_mb_en; // Frontend Memory bus enable |
input [15:0] pc; // Program counter |
|
|
219,14 → 213,10
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
|
reg fe_mb_en_buf; |
always @ (posedge dbg_clk or posedge dbg_rst) |
if (dbg_rst) fe_mb_en_buf <= 1'b0; |
else fe_mb_en_buf <= fe_mb_en; |
|
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & |
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
|
|
244,23 → 234,10
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; |
|
// Detect DATA read access |
// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read |
// before being written back. In that case, the read flag should not be set. |
// In general, We should here make sure no write access occures during the |
// same instruction cycle before setting the read flag. |
reg [2:0] d_rd_trig; |
always @ (posedge dbg_clk or posedge dbg_rst) |
if (dbg_rst) d_rd_trig <= 3'h0; |
else if (exec_done) d_rd_trig <= 3'h0; |
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, |
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, |
equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr}; |
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr; |
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr; |
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr; |
|
wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr; |
wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr; |
wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr; |
|
|
// Set flags |
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd); |
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr; |
/omsp_dbg.v
79,10 → 79,6
eu_mab, // Execution-Unit Memory address bus |
eu_mb_en, // Execution-Unit Memory bus enable |
eu_mb_wr, // Execution-Unit Memory bus write transfer |
eu_mdb_in, // Memory data bus input |
eu_mdb_out, // Memory data bus output |
exec_done, // Execution completed |
fe_mb_en, // Frontend Memory bus enable |
fe_mdb_in, // Frontend Memory data bus input |
pc, // Program counter |
puc_pnd_set // PUC pending set for the serial debug interface |
122,10 → 118,6
input [15:0] eu_mab; // Execution-Unit Memory address bus |
input eu_mb_en; // Execution-Unit Memory bus enable |
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer |
input [15:0] eu_mdb_in; // Memory data bus input |
input [15:0] eu_mdb_out; // Memory data bus output |
input exec_done; // Execution completed |
input fe_mb_en; // Frontend Memory bus enable |
input [15:0] fe_mdb_in; // Frontend Memory data bus input |
input [15:0] pc; // Program counter |
input puc_pnd_set; // PUC pending set for the serial debug interface |
434,9 → 426,9
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2])); |
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2])); |
|
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 : |
(dbg_mem_acc & ~mem_bw) ? 16'h0002 : |
(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000; |
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 : |
(mem_burst & dbg_mem_acc & ~mem_bw) ? 16'h0002 : |
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000; |
|
always @ (posedge dbg_clk or posedge dbg_rst) |
if (dbg_rst) mem_addr <= 16'h0000; |
477,24 → 469,21
omsp_dbg_hwbrk dbg_hwbr_0 ( |
|
// OUTPUTs |
.brk_halt (brk0_halt), // Hardware breakpoint command |
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending |
.brk_dout (brk0_dout), // Hardware break/watch-point register data input |
.brk_halt (brk0_halt), // Hardware breakpoint command |
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending |
.brk_dout (brk0_dout), // Hardware break/watch-point register data input |
|
// INPUTs |
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.eu_mdb_in (eu_mdb_in), // Memory data bus input |
.eu_mdb_out (eu_mdb_out), // Memory data bus output |
.exec_done (exec_done), // Execution completed |
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.pc (pc) // Program counter |
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.pc (pc) // Program counter |
); |
|
`else |
519,24 → 508,21
omsp_dbg_hwbrk dbg_hwbr_1 ( |
|
// OUTPUTs |
.brk_halt (brk1_halt), // Hardware breakpoint command |
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending |
.brk_dout (brk1_dout), // Hardware break/watch-point register data input |
.brk_halt (brk1_halt), // Hardware breakpoint command |
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending |
.brk_dout (brk1_dout), // Hardware break/watch-point register data input |
|
// INPUTs |
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.eu_mdb_in (eu_mdb_in), // Memory data bus input |
.eu_mdb_out (eu_mdb_out), // Memory data bus output |
.exec_done (exec_done), // Execution completed |
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.pc (pc) // Program counter |
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.pc (pc) // Program counter |
); |
|
`else |
561,24 → 547,21
omsp_dbg_hwbrk dbg_hwbr_2 ( |
|
// OUTPUTs |
.brk_halt (brk2_halt), // Hardware breakpoint command |
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending |
.brk_dout (brk2_dout), // Hardware break/watch-point register data input |
.brk_halt (brk2_halt), // Hardware breakpoint command |
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending |
.brk_dout (brk2_dout), // Hardware break/watch-point register data input |
|
// INPUTs |
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.eu_mdb_in (eu_mdb_in), // Memory data bus input |
.eu_mdb_out (eu_mdb_out), // Memory data bus output |
.exec_done (exec_done), // Execution completed |
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.pc (pc) // Program counter |
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.pc (pc) // Program counter |
); |
|
`else |
603,24 → 586,21
omsp_dbg_hwbrk dbg_hwbr_3 ( |
|
// OUTPUTs |
.brk_halt (brk3_halt), // Hardware breakpoint command |
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending |
.brk_dout (brk3_dout), // Hardware break/watch-point register data input |
.brk_halt (brk3_halt), // Hardware breakpoint command |
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending |
.brk_dout (brk3_dout), // Hardware break/watch-point register data input |
|
// INPUTs |
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.eu_mdb_in (eu_mdb_in), // Memory data bus input |
.eu_mdb_out (eu_mdb_out), // Memory data bus output |
.exec_done (exec_done), // Execution completed |
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.pc (pc) // Program counter |
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select |
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select |
.dbg_clk (dbg_clk), // Debug unit clock |
.dbg_din (dbg_din), // Debug register data input |
.dbg_rst (dbg_rst), // Debug unit reset |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.pc (pc) // Program counter |
); |
|
`else |
/omsp_execution_unit.v
324,23 → 324,26
//============================================================================= |
|
// Detect memory read/write access |
assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | |
((e_state==`E_IRQ_3) & ~inst_irq_rst) | |
((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | |
(e_state==`E_SRC_WR) | |
wire mb_rd_det = ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | |
((e_state==`E_EXEC) & inst_so[`RETI]) | |
((e_state==`E_DST_RD) & ~inst_type[`INST_SO] |
& ~inst_mov) | |
(e_state==`E_DST_WR); |
& ~inst_mov); |
|
wire mb_wr_det = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | |
((e_state==`E_IRQ_3) & ~inst_irq_rst) | |
((e_state==`E_DST_WR) & ~inst_so[`RETI]) | |
(e_state==`E_SRC_WR); |
|
wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 : |
~inst_bw ? 2'b11 : |
alu_out_add[0] ? 2'b10 : 2'b01; |
assign mb_wr = ({2{(e_state==`E_IRQ_1)}} | |
{2{(e_state==`E_IRQ_3)}} | |
{2{(e_state==`E_DST_WR)}} | |
{2{(e_state==`E_SRC_WR)}}) & mb_wr_msk; |
|
assign mb_en = mb_rd_det | mb_wr_det; |
|
assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk; |
|
|
|
// Memory address bus |
assign mab = alu_out_add[15:0]; |
|
/openMSP430.v
580,10 → 580,6
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
.eu_mdb_in (eu_mdb_in), // Memory data bus input |
.eu_mdb_out (eu_mdb_out), // Memory data bus output |
.exec_done (exec_done), // Execution completed |
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable |
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input |
.pc (pc), // Program counter |
.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface |