URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
- from Rev 176 to Rev 181
- ↔ Reverse comparison
Rev 176 → Rev 181
/omsp_register_file.v
209,7 → 209,7
wire mclk_r2 = mclk; |
`endif |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef CPUOFF_EN |
wire [15:0] cpuoff_mask = 16'h0010; |
`else |
/omsp_sfr.v
299,7 → 299,7
// Pulse capture and synchronization |
//----------------------------------- |
`ifdef SYNC_NMI |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
// Glitch free reset for the event capture |
reg nmi_capture_rst; |
always @(posedge mclk or posedge puc_rst) |
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie; |
|
// NMI wakeup |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
wire nmi_wkup; |
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie)); |
`else |
/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1]; |
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef ACLK_DIVIDER |
wire [7:0] divax_mask = 8'h30; |
`else |
225,7 → 225,7
`else |
wire [7:0] divmx_mask = 8'h00; |
`endif |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
wire [7:0] sels_mask = 8'h08; |
`else |
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...) |
//============================================================================= |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
wire cpuoff_and_mclk_enable; |
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable)); |
`endif |
376,7 → 376,7
// Note: unlike the original MSP430 specification, |
// we allow to switch off the LFXT even |
// if it is selected by MCLK or SMCLK. |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
`ifdef OSCOFF_EN |
|
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain |
//---------------------------------------------- |
// Note: the synchronizer is only required if there is a SMCLK_MUX |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
wire cpu_en_sm_s; |
omsp_sync_cell sync_cell_cpu_sm_en ( |
625,7 → 625,7
|
// ASIC MODE |
//---------------------------- |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
`ifdef ACLK_DIVIDER |
`ifdef LFXT_DOMAIN |
758,7 → 758,7
|
// ASIC MODE |
//---------------------------- |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
|
// Synchronizers |
916,7 → 916,7
// Serial Debug Interface Clock gate |
//------------------------------------------------ |
`ifdef DBG_EN |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
omsp_clock_gate clock_gate_dbg_clk ( |
.gclk (dbg_clk), |
.clk (mclk), |
/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00; |
`endif |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
parameter [7:0] WDTSSEL_MASK = 8'h04; |
`else |
229,7 → 229,7
//============================================================================= |
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION) |
//============================================================================= |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// Watchdog clock source selection |
//--------------------------------- |
/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG |
|
|
///------------------------------------------------------- |
//------------------------------------------------------- |
// Include/Exclude Non-Maskable-Interrupt support |
//------------------------------------------------------- |
`define NMI |
315,6 → 315,20
|
|
//=============================================================== |
// ASIC CLOCKING |
//=============================================================== |
|
//------------------------------------------------------- |
// When uncommented, this define will enable the ASIC |
// architectural clock gating as well as the advanced low |
// power modes support (most common). |
// Comment this out in order to get FPGA-like clocking. |
//------------------------------------------------------- |
`define ASIC_CLOCKING |
|
|
`ifdef ASIC_CLOCKING |
//=============================================================== |
// LFXT CLOCK DOMAIN |
//=============================================================== |
|
437,8 → 451,8
`define OSCOFF_EN |
|
|
|
`endif |
`endif |
|
//==========================================================================// |
//==========================================================================// |
/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) |
//---------------------------------------------------------------------------- |
|
// ASIC/FPGA-like clocking |
`ifdef ASIC_CLOCKING |
`undef ASIC_CLOCKING |
`endif |
|
// Fine grained clock gating |
`ifdef CLOCK_GATING |
`undef CLOCK_GATING |