URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430
- from Rev 79 to Rev 84
- ↔ Reverse comparison
Rev 79 → Rev 84
/omsp_dbg.v
202,7 → 202,14
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1); |
`endif |
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// PUC is localy used as a data. |
reg [1:0] puc_sync; |
always @ (posedge mclk or posedge por) |
if (por) puc_sync <= 2'b11; |
else puc_sync <= {puc_sync[0] , puc}; |
wire puc_s = puc_sync[1]; |
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//============================================================================ |
// 2) REGISTER DECODER |
//============================================================================ |
298,7 → 305,7
reg [3:2] cpu_stat; |
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wire cpu_stat_wr = reg_wr[CPU_STAT]; |
wire [3:2] cpu_stat_set = {dbg_swbrk, puc}; |
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s}; |
wire [3:2] cpu_stat_clr = ~dbg_din[3:2]; |
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always @ (posedge mclk or posedge por) |
616,7 → 623,7
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// Break after reset |
//-------------------------- |
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc; |
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s; |
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// Freeze peripherals |
/omsp_watchdog.v
160,8 → 160,8
else nmi_sync <= {nmi_sync[1:0], nmi}; |
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// Edge detection |
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie; |
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie; |
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie; |
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie; |
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// NMI event |
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re; |