OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim
    from Rev 94 to Rev 98
    Reverse comparison

Rev 94 → Rev 98

/bin/msp430sim
42,6 → 42,17
echo "ERROR : wrong number of arguments"
echo "USAGE : msp430sim <test name>"
echo "Example : msp430sim leds"
echo ""
echo "In order to switch the verilog simulator, the MYVLOG environment"
echo "variable can be set to the following values:"
echo ""
echo " - iverilog : Icarus Verilog (default)"
echo " - cver : CVer"
echo " - verilog : Verilog-XL"
echo " - ncverilog : NC-Verilog"
echo " - vcs : VCS"
echo " - vsim : Modelsim"
echo ""
exit 1
fi
 
73,6 → 84,10
# Cleanup #
###############################################################################
echo "Cleanup..."
rm -rf *.vcd
rm -rf *.vpd
rm -rf *.trn
rm -rf *.dsn
rm -rf pmem.*
rm -rf stimulus.v
 
/bin/rtlsim.sh
43,7 → 43,7
echo "ERROR : wrong number of arguments"
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog"
echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs"
exit 1
fi
 
98,7 → 98,11
verilog* )
vargs="$vargs +define+VXL" ;;
ncverilog* )
vargs="$vargs +access+r" ;;
rm -rf INCA_libs
vargs="$vargs +access+r +define+TRN_FILE" ;;
vcs* )
rm -rf csrc simv*
vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
vsim )
# Modelsim
if [ -d work ]; then vdel -all; fi

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