URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim
- from Rev 28 to Rev 37
- ↔ Reverse comparison
Rev 28 → Rev 37
/rtl_sim/run/pmem.elf
0,0 → 1,?rev2len?
link ../../../software/ta_uart/ta_uart.elf |
rtl_sim/run/pmem.elf
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/run/pmem.inc
===================================================================
--- rtl_sim/run/pmem.inc (nonexistent)
+++ rtl_sim/run/pmem.inc (revision 37)
@@ -0,0 +1,296 @@
+
+
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+
+
+`include "openMSP430_undefines.v"
+
+
+
+
+
+
+
+
+
+
+
+
+`define PMEM_AWIDTH 11
+
+
+
+
+
+
+
+
+
+
+
+`define DMEM_AWIDTH 9
+
+
+
+
+
+
+`define DBG_EN
+
+
+
+
+
+`define DBG_UART
+
+
+
+
+
+
+
+
+`define DBG_HWBRK_0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`define PMEM_SIZE (2 << `PMEM_AWIDTH)
+`define DMEM_SIZE (2 << `DMEM_AWIDTH)
+
+
+`define DMEM_BASE 16'h0200
+
+
+`define PMEM_MSB `PMEM_AWIDTH-1
+`define DMEM_MSB `DMEM_AWIDTH-1
+
+
+
+`define INST_SO 0
+`define INST_JMP 1
+`define INST_TO 2
+
+
+`define RRC 0
+`define SWPB 1
+`define RRA 2
+`define SXT 3
+`define PUSH 4
+`define CALL 5
+`define RETI 6
+`define IRQ 7
+
+
+`define JNE 0
+`define JEQ 1
+`define JNC 2
+`define JC 3
+`define JN 4
+`define JGE 5
+`define JL 6
+`define JMP 7
+
+
+`define MOV 0
+`define ADD 1
+`define ADDC 2
+`define SUBC 3
+`define SUB 4
+`define CMP 5
+`define DADD 6
+`define BIT 7
+`define BIC 8
+`define BIS 9
+`define XOR 10
+`define AND 11
+
+
+`define DIR 0
+`define IDX 1
+`define INDIR 2
+`define INDIR_I 3
+`define SYMB 4
+`define IMM 5
+`define ABS 6
+`define CONST 7
+
+
+`define E_IRQ_0 4'h0
+`define E_IRQ_1 4'h1
+`define E_IRQ_2 4'h2
+`define E_IRQ_3 4'h3
+`define E_IRQ_4 4'h4
+`define E_SRC_AD 4'h5
+`define E_SRC_RD 4'h6
+`define E_SRC_WR 4'h7
+`define E_DST_AD 4'h8
+`define E_DST_RD 4'h9
+`define E_DST_WR 4'hA
+`define E_EXEC 4'hB
+`define E_JUMP 4'hC
+`define E_IDLE 4'hD
+
+
+`define ALU_SRC_INV 0
+`define ALU_INC 1
+`define ALU_INC_C 2
+`define ALU_ADD 3
+`define ALU_AND 4
+`define ALU_OR 5
+`define ALU_XOR 6
+`define ALU_DADD 7
+`define ALU_STAT_7 8
+`define ALU_STAT_F 9
+`define ALU_SHIFT 10
+`define EXEC_NO_WR 11
+
+
+`define DBG_UART_WR 18
+`define DBG_UART_BW 17
+`define DBG_UART_ADDR 16:11
+
+
+`define HALT 0
+`define RUN 1
+`define ISTEP 2
+`define SW_BRK_EN 3
+`define FRZ_BRK_EN 4
+`define RST_BRK_EN 5
+`define CPU_RST 6
+
+
+`define HALT_RUN 0
+`define PUC_PND 1
+`define SWBRK_PND 3
+`define HWBRK0_PND 4
+`define HWBRK1_PND 5
+
+
+`define BRK_MODE_RD 0
+`define BRK_MODE_WR 1
+`define BRK_MODE 1:0
+`define BRK_EN 2
+`define BRK_I_EN 3
+`define BRK_RANGE 4
+
+
+`define DIVAx 5:4
+
+
+`define SELS 3
+`define DIVSx 2:1
+
+
+`define TASSELx 9:8
+`define TAIDx 7:6
+`define TAMCx 5:4
+`define TACLR 2
+`define TAIE 1
+`define TAIFG 0
+
+
+`define TACMx 15:14
+`define TACCISx 13:12
+`define TASCS 11
+`define TASCCI 10
+`define TACAP 8
+`define TAOUTMODx 7:5
+`define TACCIE 4
+`define TACCI 3
+`define TAOUT 2
+`define TACOV 1
+`define TACCIFG 0
+
+
+
+
+
+
+`define DBG_SWBRK_OP 16'h4343
+
+
+`define DBG_ID 24'h4D5350
+
+
+
+
+
+`define DBG_UART_AUTO_SYNC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`define DBG_UART_BAUD 2000000
+`define DBG_DCO_FREQ 20000000
+`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
+
+
+`ifdef DBG_EN
+ `ifdef DBG_UART
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
+ `endif
+ `else
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
+ `else
+CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
+ `endif
+ `endif
+`endif
rtl_sim/run/pmem.inc
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/run/pmem.ihex
===================================================================
--- rtl_sim/run/pmem.ihex (nonexistent)
+++ rtl_sim/run/pmem.ihex (revision 37)
@@ -0,0 +1,157 @@
+:10F0000031400003B240805A20013F4002000F937C
+:10F0100005242F839F4F7EF90002FB233F4007000A
+:10F020000F9304241F83CF430202FC23304096F049
+:10F03000304034F000133F533F9305240343034310
+:10F040003F533F93FB2330410D0A3D3D3D3D3D3D48
+:10F05000206F70656E4D535034333020696E2061DF
+:10F060006374696F6E203D3D3D3D3D3D0D000D0AD1
+:10F0700053696D706C65204C696E652045646974D8
+:10F080006F722052656164790D003E20000D003AD8
+:10F0900025730D0A00003140D80204410A430B4396
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+:10F0B0002200C2432400C2432500C2432900E24289
+:10F0C0002E00F240FBFF2A00C2432C00C2432D0059
+:10F0D000F2431A00F24319003F43B01236F03F43A7
+:10F0E000B01236F0C2431900B24004026001B240CF
+:10F0F000109962018243640182436601B2D020000C
+:10F10000600132D23F4048F0B01200F93F406EF04B
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+:10F1200032D010001B533B9009003D241F430E4B6F
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+:02F97E00000087
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+:10FFF00030F0B2F130F030F030F030F030F000F0AE
+:040000030000F00009
+:00000001FF
rtl_sim/run/pmem.ihex
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/run/pmem.mem
===================================================================
--- rtl_sim/run/pmem.mem (nonexistent)
+++ rtl_sim/run/pmem.mem (revision 37)
@@ -0,0 +1,130 @@
+
+@0000 4031 0300 40B2 5A80 0120 403F 0002 930F 2405 832F 4F9F F97E 0200 23FB 403F 0007
+@0010 930F 2404 831F 43CF 0202 23FC 4030 F096 4030 F034 1300 533F 933F 2405 4303 4303
+@0020 533F 933F 23FB 4130 0A0D 3D3D 3D3D 3D3D 6F20 6570 4D6E 5053 3334 2030 6E69 6120
+@0030 7463 6F69 206E 3D3D 3D3D 3D3D 000D 0A0D 6953 706D 656C 4C20 6E69 2065 6445 7469
+@0040 726F 5220 6165 7964 000D 203E 0D00 3A00 7325 0A0D 0000 4031 02D8 4104 430A 430B
+@0050 40B2 5A80 0120 43E2 0021 43C2 0026 43E2 0022 43C2 0024 43C2 0025 43C2 0029 42E2
+@0060 002E 40F2 FFFB 002A 43C2 002C 43C2 002D 43F2 001A 43F2 0019 433F 12B0 F036 433F
+@0070 12B0 F036 43C2 0019 40B2 0204 0160 40B2 9910 0162 4382 0164 4382 0166 D0B2 0020
+@0080 0160 D232 403F F048 12B0 F900 403F F06E 12B0 F900 1230 F08A 12B0 F2D4 4319 5321
+@0090 D032 0010 531B 903B 0009 243D 431F 4B0E 930E 2403 5F0F 831E 23FD 4FC2 0019 425F
+@00a0 0208 118F 923F 2421 903F 000D 240E 903A 0028 2C08 12B0 F210 4A0F 540F 42DF 0208
+@00b0 0000 531A 9309 23DC 3FD5 403F F08D 12B0 F900 540A 43CA 0000 1204 1230 F08F 12B0
+@00c0 F2D4 4309 430A 5221 3FED 931A 3BEB 533A 423F 12B0 F210 403F 0020 12B0 F210 423F
+@00d0 12B0 F210 3FDF 430B 3FC1 5031 0028 4030 F97C 5010 1052 3C18 3C20 3C1F 3C1E 3C1D
+@00e0 3C1C 3C1B 3C1A B0B2 0400 0162 1050 1036 4380 1034 40B2 9910 0162 40D0 1028 102A
+@00f0 C0B1 00F0 0000 1300 4380 101A 50B2 0057 0172 40B2 1810 0162 3C05 B0B2 0400 0162
+@0100 1050 1002 50B2 00AE 0172 53A0 0FFA 1300 4382 0164 403D 000A 5F0F D03F 0200 4292
+@0110 0170 0174 50B2 00AE 0174 100F 2C03 C3E2 0021 3C03 D3E2 0021 3C00 B392 0164 27FD
+@0120 C392 0164 831D 23EE 4130 40F2 00A5 0057 43C2 0058 40B2 0204 0160 D0B2 0020 0160
+@0130 40B2 5100 0166 B392 0166 27FD 421F 0176 C392 0166 B392 0166 27FD C392 0166 425E
+@0140 0057 C07E 00F8 425D 0056 907D 00FF 2006 907E 0007 341C 53D2 0057 3C06 934D 2008
+@0150 934E 2415 83D2 0057 40F2 003C 0056 3FDB 421C 0176 8F0C 421F 0176 903C 00BB 3804
+@0160 2406 83D2 0056 3FCF 53D2 0056 3FCC 4382 0166 4130 432F 510F 4F3E 4F0D 403F F210
+@0170 12B0 F34A 4130 120B 120A 4F0A 4E0B 930E 2002 431F 3C0D 4A6F 118F 531A 1292 0202
+@0180 930F 3805 5392 0200 533B 23F5 3FF2 433F 413A 413B 4130 120B 120A 1209 4F49 4E4B
+@0190 935E 380C 4F4A 118A 4A0F 1292 0202 930F 3807 5392 0200 537B 935B 37F6 494F 3C01
+@01a0 433F 4139 413A 413B 4130 120B 120A 1209 1208 1207 1206 1205 1204 8031 003C 4D05
+@01b0 4381 0030 4381 0032 4382 0200 4F82 0202 4E06 460F 4667 9347 240A 9077 0025 2407
+@01c0 5316 4667 9347 2403 9077 0025 23F9 460D 8F0D 2402 4030 F8D8 9347 2002 4030 F8E6
+@01d0 5316 43C1 002E 43C1 0035 43C1 002F 437B 43C1 002A 4667 5316 9077 0075 2002 4030
+@01e0 F8B2 474F D07F 0020 907F 0078 2002 4030 F8B2 9077 0020 2002 4030 F89E 9077 0023
+@01f0 2002 4030 F896 9077 002A 2002 4030 F87A 9077 002D 2002 4030 F86A 9077 002B 2002
+@0200 4030 F860 9077 002E 2002 4030 F7FA 9077 0030 2002 4030 F7E4 474F 507F FFCF 907F
+@0210 0009 2C1A 430D 4D0F 5F0F 5F0F 4D0E 5E0E 4F0D 5E0D 5E0D 5E0D 474F 118F 5F0D 503D
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+@02f0 002A 4BC1 0035 934B 3803 F0F1 FFDF 002E 410F 503F 0028 4F81 002C 9381 0030 2006
+@0300 9381 0032 2003 93C1 0035 243E 41D1 0034 0038 43C1 0039 4381 003A 43C1 0036 411E
+@0310 0030 411F 0032 811E 0038 711F 003A 2802 43D1 0036 411C 0030 411D 0032 411A 0038
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+@0330 411C 0030 411D 0032 411A 0038 411B 003A 12B0 F952 4C81 0030 4D81 0032 93C1 0036
+@0340 23CC 92F1 0034 2406 4149 8159 002C 5079 0028 3F1A B2F1 002E 27F7 9074 0030 27F4
+@0350 53B1 002C 411F 002C 40FF 0030 0000 3FEC 5074 0057 9077 0058 23CD F074 FFDF 3FCA
+@0360 40F1 000A 0034 3F8B D3D1 002E 3FF9 450F 5325 4FA1 002C 9381 002C 241E 934B 3811
+@0370 4B4F 118F 4F0D 430E 411F 002C 12B0 F92E 930F 2405 4F49 8159 002C 994B 36E3 4B49
+@0380 3EE1 411F 002C 831F 531F 93CF 0000 23FC 4F49 8159 002C 3ED6 4181 002C 40F1 0028
+@0390 0000 40F1 006E 0001 40F1 0075 0002 40F1 006C 0003 40F1 006C 0004 40F1 0029 0005
+@03a0 43C1 0006 3FCB 450F 5325 4FA1 0030 4381 0032 40F1 0010 0034 D0F1 0040 002E 4077
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+@03c0 0032 9381 0032 3804 40F1 000A 0034 3F29 E3B1 0030 E3B1 0032 5391 0030 6381 0032
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+@03e0 0032 E3B1 0032 3FDD D3D1 002E 3FD1 4181 002C 450F 5325 4FE1 0000 3E73 D2E1 002E
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+@07d0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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+@07f0 F030 F030 F030 F030 F030 F030 F030 F030 F030 F1B2 F030 F030 F030 F030 F030 F000
+
rtl_sim/run/pmem.mem
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: rtl_sim/src/submit.f
===================================================================
--- rtl_sim/src/submit.f (revision 28)
+++ rtl_sim/src/submit.f (revision 37)
@@ -63,19 +63,19 @@
+incdir+../../../rtl/verilog/openmsp430/
../../../rtl/verilog/openmsp430/openMSP430.v
-../../../rtl/verilog/openmsp430/frontend.v
-../../../rtl/verilog/openmsp430/execution_unit.v
-../../../rtl/verilog/openmsp430/register_file.v
-../../../rtl/verilog/openmsp430/alu.v
-../../../rtl/verilog/openmsp430/mem_backbone.v
-../../../rtl/verilog/openmsp430/clock_module.v
-../../../rtl/verilog/openmsp430/sfr.v
-../../../rtl/verilog/openmsp430/dbg.v
-../../../rtl/verilog/openmsp430/dbg_hwbrk.v
-../../../rtl/verilog/openmsp430/dbg_uart.v
-../../../rtl/verilog/openmsp430/watchdog.v
-../../../rtl/verilog/openmsp430/periph/gpio.v
-../../../rtl/verilog/openmsp430/periph/timerA.v
+../../../rtl/verilog/openmsp430/omsp_frontend.v
+../../../rtl/verilog/openmsp430/omsp_execution_unit.v
+../../../rtl/verilog/openmsp430/omsp_register_file.v
+../../../rtl/verilog/openmsp430/omsp_alu.v
+../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
+../../../rtl/verilog/openmsp430/omsp_clock_module.v
+../../../rtl/verilog/openmsp430/omsp_sfr.v
+../../../rtl/verilog/openmsp430/omsp_dbg.v
+../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
+../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
+../../../rtl/verilog/openmsp430/omsp_watchdog.v
+../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
+../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
//=============================================================================
/rtl_sim/bin/msp430sim
73,7 → 73,7
# Cleanup # |
############################################################################### |
echo "Cleanup..." |
rm -rf rom.* |
rm -rf pmem.* |
rm -rf stimulus.v |
|
|
90,26 → 90,26
cd ../../sim/rtl_sim/run/ |
|
# Create links |
ln -s $elffile rom.elf |
ln -s $elffile pmem.elf |
ln -s $verfile stimulus.v |
|
# Make local copy of the openMSP403 configuration file and remove comments |
cp $incfile ./rom.inc |
sed -i "/^\/\// s,.*,," rom.inc |
cp $incfile ./pmem.inc |
sed -i "/^\/\// s,.*,," pmem.inc |
|
# Get ROM size |
romsize=`grep ROM_AWIDTH rom.inc | grep -v ROM_MSB | grep -v ROM_SIZE` |
romsize=${romsize##* } |
romsize=$((2<<$romsize)) |
# Get Program memory size |
pmemsize=`grep PMEM_AWIDTH pmem.inc | grep -v PMEM_MSB | grep -v PMEM_SIZE` |
pmemsize=${pmemsize##* } |
pmemsize=$((2<<$pmemsize)) |
|
# Create IHEX file from ELF |
echo "Convert ELF file to IHEX format..." |
msp430-objcopy -O ihex rom.elf rom.ihex |
msp430-objcopy -O ihex pmem.elf pmem.ihex |
|
# Generate ROM memory file |
# Generate Program memory file |
echo "Convert IHEX file to Verilog MEMH format..." |
../bin/ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size $romsize |
../bin/ihex2mem.tcl -ihex pmem.ihex -out pmem.mem -mem_size $pmemsize |
|
# Start verilog simulation |
echo "Start Verilog simulation..." |
../bin/rtlsim.sh stimulus.v rom.mem $submitfile |
../bin/rtlsim.sh stimulus.v pmem.mem $submitfile |
/rtl_sim/bin/rtlsim.sh
40,8 → 40,8
EXPECTED_ARGS=3 |
if [ $# -ne $EXPECTED_ARGS ]; then |
echo "ERROR : wrong number of arguments" |
echo "USAGE : rtlsim.sh <verilog stimulus file> <rom file> <submit file>" |
echo "Example : rtlsim.sh ./stimulus.v rom.mem ../src/submit.f" |
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>" |
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f" |
exit 1 |
fi |
|
55,7 → 55,7
exit 1 |
fi |
if [ ! -e $2 ]; then |
echo "ROM memory file $2 doesn't exist" |
echo "Memory file $2 doesn't exist" |
exit 1 |
fi |
if [ ! -e $3 ]; then |