URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart
- from Rev 136 to Rev 143
- ↔ Reverse comparison
Rev 136 → Rev 143
/hardware.h
1,33 → 1,18
#ifndef HARDWARE_H |
#define HARDWARE_H |
|
#define __msp430_have_port3 |
#define __MSP430_HAS_PORT3__ |
|
#include <io.h> |
#include <signal.h> |
#include <iomacros.h> |
|
//-------------------------------------------------- |
// Hardware UART register address mapping |
//-------------------------------------------------- |
|
#define UART_CTL_ 0x0080 // UART Control register (8bit) |
sfrb(UART_CTL,UART_CTL_); |
#define UART_CTL (*(volatile unsigned char *) 0x0080) // UART Control register (8bit) |
#define UART_STAT (*(volatile unsigned char *) 0x0081) // UART Status register (8bit) |
#define UART_BAUD (*(volatile unsigned int *) 0x0082) // UART Baud rate configuration (16bit) |
#define UART_TXD (*(volatile unsigned char *) 0x0084) // UART Transmit data register (8bit) |
#define UART_RXD (*(volatile unsigned char *) 0x0085) // UART Receive data register (8bit) |
|
#define UART_STAT_ 0x0081 // UART Status register (8bit) |
sfrb(UART_STAT,UART_STAT_); |
|
#define UART_BAUD_ 0x0082 // UART Baud rate configuration (16bit) |
sfrw(UART_BAUD,UART_BAUD_); |
|
#define UART_TXD_ 0x0084 // UART Transmit data register (8bit) |
sfrb(UART_TXD,UART_TXD_); |
|
#define UART_RXD_ 0x0085 // UART Receive data register (8bit) |
sfrb(UART_RXD,UART_RXD_); |
|
|
//-------------------------------------------------- |
// Hardware UART register field mapping |
//-------------------------------------------------- |
/main.c
1,3 → 1,4
#include "omsp_system.h" |
#include "hardware.h" |
#include <stdlib.h> |
#include <stdio.h> |
/omsp_system.h
0,0 → 1,250
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* OMSP_SYSTEM HEADER FILE */ |
/*---------------------------------------------------------------------------*/ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 19 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
#include <in430.h> |
|
//============================================================================= |
// STATUS REGISTER BITS |
//============================================================================= |
|
// Flags |
#define C (0x0001) |
#define Z (0x0002) |
#define N (0x0004) |
#define V (0x0100) |
#define GIE (0x0008) |
#define CPUOFF (0x0010) |
#define OSCOFF (0x0020) |
#define SCG0 (0x0040) |
#define SCG1 (0x0080) |
|
// Low Power Modes coded with Bits 4-7 in SR |
#define LPM0_bits (CPUOFF) |
#define LPM1_bits (SCG0+CPUOFF) |
#define LPM2_bits (SCG1+CPUOFF) |
#define LPM3_bits (SCG1+SCG0+CPUOFF) |
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) |
|
#define LPM0 _BIS_SR(LPM0_bits) // Enter Low Power Mode 0 |
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) // Exit Low Power Mode 0 |
#define LPM1 _BIS_SR(LPM1_bits) // Enter Low Power Mode 1 |
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) // Exit Low Power Mode 1 |
#define LPM2 _BIS_SR(LPM2_bits) // Enter Low Power Mode 2 |
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) // Exit Low Power Mode 2 |
#define LPM3 _BIS_SR(LPM3_bits) // Enter Low Power Mode 3 |
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) // Exit Low Power Mode 3 |
#define LPM4 _BIS_SR(LPM4_bits) // Enter Low Power Mode 4 |
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) // Exit Low Power Mode 4 |
|
|
//============================================================================= |
// PERIPHERALS REGISTER DEFINITIONS |
//============================================================================= |
|
//---------------------------------------------------------- |
// SPECIAL FUNCTION REGISTERS |
//---------------------------------------------------------- |
#define IE1 (*(volatile unsigned char *) 0x0000) |
#define IFG1 (*(volatile unsigned char *) 0x0002) |
|
#define CPU_ID_LO (*(volatile unsigned char *) 0x0004) |
#define CPU_ID_HI (*(volatile unsigned char *) 0x0006) |
|
|
//---------------------------------------------------------- |
// GPIOs |
//---------------------------------------------------------- |
#define P1IN (*(volatile unsigned char *) 0x0020) |
#define P1OUT (*(volatile unsigned char *) 0x0021) |
#define P1DIR (*(volatile unsigned char *) 0x0022) |
#define P1IFG (*(volatile unsigned char *) 0x0023) |
#define P1IES (*(volatile unsigned char *) 0x0024) |
#define P1IE (*(volatile unsigned char *) 0x0025) |
#define P1SEL (*(volatile unsigned char *) 0x0026) |
|
#define P2IN (*(volatile unsigned char *) 0x0028) |
#define P2OUT (*(volatile unsigned char *) 0x0029) |
#define P2DIR (*(volatile unsigned char *) 0x002A) |
#define P2IFG (*(volatile unsigned char *) 0x002B) |
#define P2IES (*(volatile unsigned char *) 0x002C) |
#define P2IE (*(volatile unsigned char *) 0x002D) |
#define P2SEL (*(volatile unsigned char *) 0x002E) |
|
#define P3IN (*(volatile unsigned char *) 0x0018) |
#define P3OUT (*(volatile unsigned char *) 0x0019) |
#define P3DIR (*(volatile unsigned char *) 0x001A) |
#define P3SEL (*(volatile unsigned char *) 0x001B) |
|
#define P4IN (*(volatile unsigned char *) 0x001C) |
#define P4OUT (*(volatile unsigned char *) 0x001D) |
#define P4DIR (*(volatile unsigned char *) 0x001E) |
#define P4SEL (*(volatile unsigned char *) 0x001F) |
|
#define P5IN (*(volatile unsigned char *) 0x0030) |
#define P5OUT (*(volatile unsigned char *) 0x0031) |
#define P5DIR (*(volatile unsigned char *) 0x0032) |
#define P5SEL (*(volatile unsigned char *) 0x0033) |
|
#define P6IN (*(volatile unsigned char *) 0x0034) |
#define P6OUT (*(volatile unsigned char *) 0x0035) |
#define P6DIR (*(volatile unsigned char *) 0x0036) |
#define P6SEL (*(volatile unsigned char *) 0x0037) |
|
|
//---------------------------------------------------------- |
// BASIC CLOCK MODULE |
//---------------------------------------------------------- |
#define DCOCTL (*(volatile unsigned char *) 0x0056) |
#define BCSCTL1 (*(volatile unsigned char *) 0x0057) |
#define BCSCTL2 (*(volatile unsigned char *) 0x0058) |
|
|
//---------------------------------------------------------- |
// WATCHDOG TIMER |
//---------------------------------------------------------- |
|
// Addresses |
#define WDTCTL (*(volatile unsigned int *) 0x0120) |
|
// Bit masks |
#define WDTIS0 (0x0001) |
#define WDTIS1 (0x0002) |
#define WDTSSEL (0x0004) |
#define WDTCNTCL (0x0008) |
#define WDTTMSEL (0x0010) |
#define WDTNMI (0x0020) |
#define WDTNMIES (0x0040) |
#define WDTHOLD (0x0080) |
#define WDTPW (0x5A00) |
|
|
//---------------------------------------------------------- |
// HARDWARE MULTIPLIER |
//---------------------------------------------------------- |
#define OP1_MPY (*(volatile unsigned int *) 0x0130) |
#define OP1_MPYS (*(volatile unsigned int *) 0x0132) |
#define OP1_MAC (*(volatile unsigned int *) 0x0134) |
#define OP1_MACS (*(volatile unsigned int *) 0x0136) |
#define OP2 (*(volatile unsigned int *) 0x0138) |
|
#define RESLO (*(volatile unsigned int *) 0x013A) |
#define RESHI (*(volatile unsigned int *) 0x013C) |
#define SUMEXT (*(volatile unsigned int *) 0x013E) |
|
|
//---------------------------------------------------------- |
// TIMER A |
//---------------------------------------------------------- |
#define TACTL (*(volatile unsigned int *) 0x0160) |
#define TAR (*(volatile unsigned int *) 0x0170) |
#define TACCTL0 (*(volatile unsigned int *) 0x0162) |
#define TACCR0 (*(volatile unsigned int *) 0x0172) |
#define TACCTL1 (*(volatile unsigned int *) 0x0164) |
#define TACCR1 (*(volatile unsigned int *) 0x0174) |
#define TACCTL2 (*(volatile unsigned int *) 0x0166) |
#define TACCR2 (*(volatile unsigned int *) 0x0176) |
#define TAIV (*(volatile unsigned int *) 0x012E) |
|
// Alternate register names |
#define CCTL0 TACCTL0 |
#define CCTL1 TACCTL1 |
#define CCR0 TACCR0 |
#define CCR1 TACCR1 |
|
// Bit-masks |
#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ |
#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ |
#define ID1 (0x0080) /* Timer A clock input divider 1 */ |
#define ID0 (0x0040) /* Timer A clock input divider 0 */ |
#define MC1 (0x0020) /* Timer A mode control 1 */ |
#define MC0 (0x0010) /* Timer A mode control 0 */ |
#define TACLR (0x0004) /* Timer A counter clear */ |
#define TAIE (0x0002) /* Timer A counter interrupt enable */ |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */ |
|
#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ |
#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ |
#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ |
#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ |
#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ |
#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ |
#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ |
#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ |
#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ |
#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ |
#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ |
#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ |
|
#define CM1 (0x8000) /* Capture mode 1 */ |
#define CM0 (0x4000) /* Capture mode 0 */ |
#define CCIS1 (0x2000) /* Capture input select 1 */ |
#define CCIS0 (0x1000) /* Capture input select 0 */ |
#define SCS (0x0800) /* Capture sychronize */ |
#define SCCI (0x0400) /* Latched capture signal (read) */ |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ |
#define OUTMOD2 (0x0080) /* Output mode 2 */ |
#define OUTMOD1 (0x0040) /* Output mode 1 */ |
#define OUTMOD0 (0x0020) /* Output mode 0 */ |
#define CCIE (0x0010) /* Capture/compare interrupt enable */ |
#define CCI (0x0008) /* Capture input signal (read) */ |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */ |
#define COV (0x0002) /* Capture/compare overflow flag */ |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */ |
|
|
//============================================================================= |
// INTERRUPT VECTORS |
//============================================================================= |
#define interrupt(x) void __attribute__((interrupt (x))) |
#define wakeup __attribute__((wakeup)) |
#define eint() __eint() |
#define dint() __dint() |
|
#define RESET_VECTOR (0x001E) // Vector 15 (0xFFFE) - Reset - [Highest Priority] |
#define NMI_VECTOR (0x001C) // Vector 14 (0xFFFC) - Non-maskable - |
#define UNUSED_13_VECTOR (0x001A) // Vector 13 (0xFFFA) - - |
#define UNUSED_12_VECTOR (0x0018) // Vector 12 (0xFFF8) - - |
#define UNUSED_11_VECTOR (0x0016) // Vector 11 (0xFFF6) - - |
#define WDT_VECTOR (0x0014) // Vector 10 (0xFFF4) - Watchdog Timer - |
#define TIMERA0_VECTOR (0x0012) // Vector 9 (0xFFF2) - Timer A CC0 - |
#define TIMERA1_VECTOR (0x0010) // Vector 8 (0xFFF0) - Timer A CC1-2, TA - |
#define UNUSED_07_VECTOR (0x000E) // Vector 7 (0xFFEE) - - |
#define UNUSED_06_VECTOR (0x000C) // Vector 6 (0xFFEC) - - |
#define UNUSED_05_VECTOR (0x000A) // Vector 5 (0xFFEA) - - |
#define UNUSED_04_VECTOR (0x0008) // Vector 4 (0xFFE8) - - |
#define UNUSED_03_VECTOR (0x0006) // Vector 3 (0xFFE6) - - |
#define PORT1_VECTOR (0x0004) // Vector 2 (0xFFE4) - Port 1 - |
#define UNUSED_01_VECTOR (0x0002) // Vector 1 (0xFFE2) - - |
#define UNUSED_00_VECTOR (0x0000) // Vector 0 (0xFFE0) - - [Lowest Priority] |
omsp_system.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: linker.x
===================================================================
--- linker.x (nonexistent)
+++ linker.x (revision 143)
@@ -0,0 +1,179 @@
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430")
+OUTPUT_ARCH("msp430")
+MEMORY
+{
+ text (rx) : ORIGIN = 0xF000, LENGTH = 0x1000
+ data (rwx) : ORIGIN = 0x0200, LENGTH = 0x400
+ vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20
+}
+__WDTCTL = 0x0120;
+
+SECTIONS
+{
+ PROVIDE (__stack = 0x600) ;
+
+ /* Read-only sections, merged into text segment. */
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.text :
+ {
+ *(.rel.text)
+ *(.rel.text.*)
+ *(.rel.gnu.linkonce.t*)
+ }
+ .rela.text :
+ {
+ *(.rela.text)
+ *(.rela.text.*)
+ *(.rela.gnu.linkonce.t*)
+ }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.rodata :
+ {
+ *(.rel.rodata)
+ *(.rel.rodata.*)
+ *(.rel.gnu.linkonce.r*)
+ }
+ .rela.rodata :
+ {
+ *(.rela.rodata)
+ *(.rela.rodata.*)
+ *(.rela.gnu.linkonce.r*)
+ }
+ .rel.data :
+ {
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.gnu.linkonce.d*)
+ }
+ .rela.data :
+ {
+ *(.rela.data)
+ *(.rela.data.*)
+ *(.rela.gnu.linkonce.d*)
+ }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ /* Internal text space. */
+ .text :
+ {
+ . = ALIGN(2);
+ *(.init)
+ *(.init0) /* Start here after reset. */
+ *(.init1)
+ *(.init2) /* Copy data loop */
+ *(.init3)
+ *(.init4) /* Clear bss */
+ *(.init5)
+ *(.init6) /* C++ constructors. */
+ *(.init7)
+ *(.init8)
+ *(.init9) /* Call main(). */
+ __ctors_start = . ;
+ *(.ctors)
+ __ctors_end = . ;
+ __dtors_start = . ;
+ *(.dtors)
+ __dtors_end = . ;
+ . = ALIGN(2);
+ *(.text)
+ . = ALIGN(2);
+ *(.text.*)
+ . = ALIGN(2);
+ *(.fini9) /* */
+ *(.fini8)
+ *(.fini7)
+ *(.fini6) /* C++ destructors. */
+ *(.fini5)
+ *(.fini4)
+ *(.fini3)
+ *(.fini2)
+ *(.fini1)
+ *(.fini0) /* Infinite loop after program termination. */
+ *(.fini)
+ _etext = . ;
+ } > text
+ .data : AT (ADDR (.text) + SIZEOF (.text))
+ {
+ PROVIDE (__data_start = .) ;
+ . = ALIGN(2);
+ *(.data)
+ . = ALIGN(2);
+ *(.gnu.linkonce.d*)
+ . = ALIGN(2);
+ _edata = . ;
+ } > data
+ PROVIDE (__data_load_start = LOADADDR(.data) );
+ PROVIDE (__data_size = SIZEOF(.data) );
+ .bss SIZEOF(.data) + ADDR(.data) :
+ {
+ PROVIDE (__bss_start = .) ;
+ *(.bss)
+ *(COMMON)
+ PROVIDE (__bss_end = .) ;
+ _end = . ;
+ } > data
+ PROVIDE (__bss_size = SIZEOF(.bss) );
+ .noinit SIZEOF(.bss) + ADDR(.bss) :
+ {
+ PROVIDE (__noinit_start = .) ;
+ *(.noinit)
+ *(COMMON)
+ PROVIDE (__noinit_end = .) ;
+ _end = . ;
+ } > data
+ .vectors :
+ {
+ PROVIDE (__vectors_start = .) ;
+ *(.vectors*)
+ _vectors_end = . ;
+ } > vectors
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ PROVIDE (__data_start_rom = _etext) ;
+ PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ;
+ PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ;
+ PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ;
+}
linker.x
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: makefile
===================================================================
--- makefile (revision 136)
+++ makefile (revision 143)
@@ -1,14 +1,11 @@
# makfile configuration
NAME = hw_uart
OBJECTS = main.o
-CPU = msp430x1121
-ASFLAGS = -mmcu=${CPU} -mforce-hwmul -x assembler-with-cpp -D_GNU_ASSEMBLER_ -c
-CFLAGS = -mmcu=${CPU} -mforce-hwmul -O2 -Wall -g
+CFLAGS = -O2 -Wall -g -mcpu=430 -mivcnt=16 -mmpy=16 # Uniarch flags
#switch the compiler (for the internal make rules)
CC = msp430-gcc
-AS = msp430-gcc
.PHONY: all FORCE clean download download-jtag download-bsl dist
@@ -22,7 +19,7 @@
#additional rules for files
${NAME}.elf: ${OBJECTS}
- ${CC} -mmcu=${CPU} -o $@ ${OBJECTS}
+ ${CC} -Tlinker.x -o $@ ${OBJECTS}
${NAME}.a43: ${NAME}.elf
msp430-objcopy -O ihex $^ $@