URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis
- from Rev 111 to Rev 136
- ↔ Reverse comparison
Rev 111 → Rev 136
/xilinx/openMSP430_fpga.prj
40,6 → 40,7
`include "../../../rtl/verilog/openMSP430_fpga.v" |
`include "../../../rtl/verilog/io_mux.v" |
`include "../../../rtl/verilog/driver_7segment.v" |
`include "../../../rtl/verilog/omsp_uart.v" |
`include "../../../rtl/verilog/coregen/ram_8x512_hi.v" |
`include "../../../rtl/verilog/coregen/ram_8x512_lo.v" |
`include "../../../rtl/verilog/coregen/rom_8x2k_hi.v" |
55,14 → 56,20
`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v" |
`include "../../../rtl/verilog/openmsp430/omsp_register_file.v" |
`include "../../../rtl/verilog/openmsp430/omsp_alu.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v" |
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v" |
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v" |
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v" |
`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v" |
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v" |
`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v" |
`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v" |
`include "../../../rtl/verilog/openmsp430/omsp_and_gate.v" |
`include "../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_gate.v" |
`include "../../../rtl/verilog/openmsp430/omsp_clock_mux.v" |
`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v" |
`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v" |
/xilinx/xst_verilog.opt
5,8 → 5,8
## Verilog Option File for XST targeted for speed |
## This works for FPGA devices. |
## |
## Version: 11.1 |
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_verilog_speed.opt,v 1.14 2008/10/20 23:47:14 rvklair Exp $ |
## Version: 13.1 |
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_verilog_speed.opt,v 1.15.4.1 2011/01/11 22:40:31 rvklair Exp $ |
######################################################### |
# |
# Options for XST |
28,11 → 28,11
"-ifn <synthdesign>"; # Input/Project File Name |
"-ifmt Verilog"; # Input Format |
"-ofn <design>"; # Output File Name |
"-ofmt ngc"; # Output File Format |
"-ofmt ngc"; # Output File Format |
"-p <partname>"; # Target Device |
"-verilog2001 YES"; # Enables the use of Verilog 2001 Constructs |
# YES, NO |
|
"-top openMSP430_fpga"; |
"-vlgincdir ../../../rtl/verilog/openmsp430/"; |
|
"-opt_mode SPEED"; # Optimization Criteria |