URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board
- from Rev 40 to Rev 54
- ↔ Reverse comparison
Rev 40 → Rev 54
/rtl/verilog/openmsp430/omsp_frontend.v
42,7 → 42,7
|
// OUTPUTs |
dbg_halt_st, // Halt/Run status from CPU |
decode, // Frontend decode instruction |
decode_noirq, // Frontend decode instruction |
e_state, // Execution state |
exec_done, // Execution completed |
inst_ad, // Decoded Inst: destination addressing mode |
83,7 → 83,7
// OUTPUTs |
//========= |
output dbg_halt_st; // Halt/Run status from CPU |
output decode; // Frontend decode instruction |
output decode_noirq; // Frontend decode instruction |
output [3:0] e_state; // Execution state |
output exec_done; // Execution completed |
output [7:0] inst_ad; // Decoded Inst: destination addressing mode |
173,8 → 173,9
else i_state <= i_state_nxt; |
|
// Utility signals |
wire decode = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))) | irq_detect; |
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE); |
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))); |
wire decode = decode_noirq | irq_detect; |
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE); |
|
// Debug interface cpu status |
reg dbg_halt_st; |
/rtl/verilog/openmsp430/omsp_dbg.v
56,7 → 56,7
dbg_mem_din, // Debug unit Memory data input |
dbg_reg_din, // Debug unit CPU register data input |
dbg_uart_rxd, // Debug interface: UART RXD |
decode, // Frontend decode instruction |
decode_noirq, // Frontend decode instruction |
eu_mab, // Execution-Unit Memory address bus |
eu_mb_en, // Execution-Unit Memory bus enable |
eu_mb_wr, // Execution-Unit Memory bus write transfer |
89,7 → 89,7
input [15:0] dbg_mem_din; // Debug unit Memory data input |
input [15:0] dbg_reg_din; // Debug unit CPU register data input |
input dbg_uart_rxd; // Debug interface: UART RXD |
input decode; // Frontend decode instruction |
input decode_noirq; // Frontend decode instruction |
input [15:0] eu_mab; // Execution-Unit Memory address bus |
input eu_mb_en; // Execution-Unit Memory bus enable |
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer |
626,7 → 626,7
|
// Software break |
//-------------------------- |
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode & cpu_ctl[`SW_BRK_EN]; |
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN]; |
|
|
// Single step |
/rtl/verilog/openmsp430/openMSP430.v
188,7 → 188,7
|
// OUTPUTs |
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU |
.decode (decode), // Frontend decode instruction |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.e_state (e_state), // Execution state |
.exec_done (exec_done), // Execution completed |
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode |
407,7 → 407,7
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input |
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input |
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD |
.decode (decode), // Frontend decode instruction |
.decode_noirq (decode_noirq), // Frontend decode instruction |
.eu_mab (eu_mab), // Execution-Unit Memory address bus |
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable |
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer |
/sim/rtl_sim/run/run_disassemble
1,7 → 407,7
msp430-objdump -D rom.elf |
msp430-objdump -D pmem.elf |