URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk/fpga/xilinx_diligent_s3board
- from Rev 73 to Rev 74
- ↔ Reverse comparison
Rev 73 → Rev 74
/rtl/verilog/openmsp430/periph/template_periph_8b.v
1,25 → 1,30
//---------------------------------------------------------------------------- |
// Copyright (C) 2001 Authors |
// Copyright (C) 2009 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions |
// are met: |
// * Redistributions of source code must retain the above copyright |
// notice, this list of conditions and the following disclaimer. |
// * Redistributions in binary form must reproduce the above copyright |
// notice, this list of conditions and the following disclaimer in the |
// documentation and/or other materials provided with the distribution. |
// * Neither the name of the authors nor the names of its contributors |
// may be used to endorse or promote products derived from this software |
// without specific prior written permission. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, |
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
// THE POSSIBILITY OF SUCH DAMAGE |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//---------------------------------------------------------------------------- |
// |
// *File Name: template_periph_8b.v |
/rtl/verilog/openmsp430/periph/template_periph_16b.v
1,25 → 1,30
//---------------------------------------------------------------------------- |
// Copyright (C) 2001 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions |
// are met: |
// * Redistributions of source code must retain the above copyright |
// notice, this list of conditions and the following disclaimer. |
// * Redistributions in binary form must reproduce the above copyright |
// notice, this list of conditions and the following disclaimer in the |
// documentation and/or other materials provided with the distribution. |
// * Neither the name of the authors nor the names of its contributors |
// may be used to endorse or promote products derived from this software |
// without specific prior written permission. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, |
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
// THE POSSIBILITY OF SUCH DAMAGE |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//---------------------------------------------------------------------------- |
// |
// *File Name: template_periph_16b.v |
/rtl/verilog/openmsp430/omsp_dbg_uart.v
182,14 → 182,14
|
`ifdef DBG_UART_AUTO_SYNC |
|
reg [14:0] sync_cnt; |
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt; |
always @ (posedge mclk or posedge por) |
if (por) sync_cnt <= 15'h7ff8; |
else if (sync_busy) sync_cnt <= sync_cnt+15'h0001; |
if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000}; |
else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1}; |
|
wire [11:0] bit_cnt_max = sync_cnt[14:3]; |
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3]; |
`else |
wire [11:0] bit_cnt_max = `DBG_UART_CNT; |
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT; |
`endif |
|
|
199,12 → 199,12
|
// Transfer counter |
//------------------------ |
reg [3:0] xfer_bit; |
reg [11:0] xfer_cnt; |
reg [3:0] xfer_bit; |
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt; |
|
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1)); |
wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC)); |
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000); |
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}}); |
assign xfer_done = (xfer_bit==4'hb); |
|
always @ (posedge mclk or posedge por) |
214,10 → 214,10
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1; |
|
always @ (posedge mclk or posedge por) |
if (por) xfer_cnt <= 12'h000; |
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]}; |
if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}}; |
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]}; |
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max; |
else xfer_cnt <= xfer_cnt+12'hfff; |
else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}}; |
|
|
// Receive/Transmit buffer |
/rtl/verilog/openmsp430/omsp_dbg.v
265,9 → 265,9
// CPU_ID Register |
//----------------- |
|
wire [3:0] cpu_id_pmem = `PMEM_AWIDTH; |
wire [3:0] cpu_id_dmem = `DMEM_AWIDTH; |
wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem}; |
wire [15:0] cpu_id_pmem = `PMEM_SIZE; |
wire [15:0] cpu_id_dmem = `DMEM_SIZE; |
wire [31:0] cpu_id = {cpu_id_pmem, cpu_id_dmem}; |
|
|
// CPU_CTL Register |
/rtl/verilog/openmsp430/openMSP430_defines.v
391,9 → 391,6
// Debug interface: Software breakpoint opcode |
`define DBG_SWBRK_OP 16'h4343 |
|
// Debug interface ID |
`define DBG_ID 24'h4D5350 |
|
// Debug UART interface auto data synchronization |
// If the following define is commented out, then |
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly |
421,6 → 418,9
// Enable/Disable the hardware breakpoint RANGE mode |
`define HWBRK_RANGE 1'b0 |
|
// Counter width for the debug interface UART |
`define DBG_UART_XFER_CNT_W 16 |
|
// Check configuration |
`ifdef DBG_EN |
`ifdef DBG_UART |
/rtl/verilog/openmsp430/openMSP430_undefines.v
563,11 → 563,6
`undef DBG_SWBRK_OP |
`endif |
|
// Debug interface ID |
`ifdef DBG_ID |
`undef DBG_ID |
`endif |
|
// Debug UART interface auto data synchronization |
`ifdef DBG_UART_AUTO_SYNC |
`undef DBG_UART_AUTO_SYNC |
589,6 → 584,11
`undef HWBRK_RANGE |
`endif |
|
// Counter width for the debug interface UART |
`ifdef DBG_UART_XFER_CNT_W |
`undef DBG_UART_XFER_CNT_W |
`endif |
|
// |
// MULTIPLIER CONFIGURATION |
//====================================== |