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Rev 204 → Rev 205

/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_mux.v
121,9 → 121,21
 
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in0_scan_fix_inv;
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in1;
 
//-----------------------------------------------------------------------------
// Optional scan repair for neg-edge clocked FF
//-----------------------------------------------------------------------------
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
`else
assign clk_in0_scan_fix_inv = ~clk_in0;
assign clk_in1_scan_fix_inv = ~clk_in1;
`endif
 
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
131,11 → 143,11
 
assign in0_select = ~select_in & ~in1_select_ss;
 
always @ (posedge clk_in0_inv or posedge reset)
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
 
always @ (posedge clk_in0 or posedge reset)
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
 
148,7 → 160,7
 
assign in1_select = select_in & ~in0_select_ss;
 
always @ (posedge clk_in1_inv or posedge reset)
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
 
175,7 → 187,6
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
 
 
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
161,7 → 161,6
 
// Local wire declarations
wire nodiv_mclk;
wire nodiv_mclk_n;
wire nodiv_smclk;
 
 
317,14 → 316,14
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
 
wire scg0_and_mclk_dma_enable;
334,13 → 333,13
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
`endif
 
wire scg1_and_mclk_dma_enable;
350,13 → 349,13
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
`endif
 
wire oscoff_and_mclk_dma_enable;
366,19 → 365,19
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup= mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
 
 
418,12 → 417,25
 
// Register to prevent glitch propagation
reg dco_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1'b1;
else dco_disable <= ~dco_enable_nxt;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
 
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
 
// Note that a synchronizer is required if the MCLK mux is included
wire dco_clk_n = ~dco_clk;
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
432,7 → 444,24
.rst (por)
);
`else
assign dco_enable = ~dco_disable;
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
 
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1'b0;
else dco_enable <= ~dco_disable;
`endif
 
// The DCO oscillator will get an asynchronous wakeup if:
455,19 → 484,18
);
 
// Scan MUX to increase coverage
wire dco_wkup_clear;
omsp_scan_mux scan_mux_dco_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b1),
.data_out (dco_wkup_clear)
);
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b0),
.data_out (dco_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (dco_wkup_clear),
.data_in (1'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
512,12 → 540,25
 
// Register to prevent glitch propagation
reg lfxt_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1'b1;
else lfxt_disable <= ~lfxt_enable_nxt;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
 
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
 
// Synchronize the OSCOFF control signal to the LFXT clock domain
wire lfxt_clk_n = ~lfxt_clk;
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
545,19 → 586,18
);
 
// Scan MUX to increase coverage
wire lfxt_wkup_clear;
omsp_scan_mux scan_mux_lfxt_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b1),
.data_out (lfxt_wkup_clear)
);
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (lfxt_wkup_clear),
.data_in (1'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
677,7 → 717,6
`else
assign nodiv_mclk = dco_clk;
`endif
assign nodiv_mclk_n = ~nodiv_mclk;
 
 
// Wakeup synchronizer
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_mem_backbone.v
323,16 → 323,17
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
 
`ifdef CLOCK_GATING
wire mclk_bckup;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_bckup = mclk;
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
 
reg [15:0] pmem_dout_bckup;
always @(posedge mclk_bckup or posedge puc_rst)
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
467,6 → 467,18
//-------------------------------------------------------
`define OSCOFF_EN
 
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
 
`endif
`endif
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_mux.v
121,9 → 121,21
 
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in0_scan_fix_inv;
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in1;
 
//-----------------------------------------------------------------------------
// Optional scan repair for neg-edge clocked FF
//-----------------------------------------------------------------------------
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
`else
assign clk_in0_scan_fix_inv = ~clk_in0;
assign clk_in1_scan_fix_inv = ~clk_in1;
`endif
 
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
131,11 → 143,11
 
assign in0_select = ~select_in & ~in1_select_ss;
 
always @ (posedge clk_in0_inv or posedge reset)
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
 
always @ (posedge clk_in0 or posedge reset)
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
 
148,7 → 160,7
 
assign in1_select = select_in & ~in0_select_ss;
 
always @ (posedge clk_in1_inv or posedge reset)
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
 
175,7 → 187,6
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
 
 
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
161,7 → 161,6
 
// Local wire declarations
wire nodiv_mclk;
wire nodiv_mclk_n;
wire nodiv_smclk;
 
 
317,14 → 316,14
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
 
wire scg0_and_mclk_dma_enable;
334,13 → 333,13
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
`endif
 
wire scg1_and_mclk_dma_enable;
350,13 → 349,13
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
`endif
 
wire oscoff_and_mclk_dma_enable;
366,19 → 365,19
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup= mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
 
 
418,12 → 417,25
 
// Register to prevent glitch propagation
reg dco_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1'b1;
else dco_disable <= ~dco_enable_nxt;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
 
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
 
// Note that a synchronizer is required if the MCLK mux is included
wire dco_clk_n = ~dco_clk;
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
432,7 → 444,24
.rst (por)
);
`else
assign dco_enable = ~dco_disable;
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
 
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1'b0;
else dco_enable <= ~dco_disable;
`endif
 
// The DCO oscillator will get an asynchronous wakeup if:
455,19 → 484,18
);
 
// Scan MUX to increase coverage
wire dco_wkup_clear;
omsp_scan_mux scan_mux_dco_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b1),
.data_out (dco_wkup_clear)
);
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b0),
.data_out (dco_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (dco_wkup_clear),
.data_in (1'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
512,12 → 540,25
 
// Register to prevent glitch propagation
reg lfxt_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1'b1;
else lfxt_disable <= ~lfxt_enable_nxt;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
 
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
 
// Synchronize the OSCOFF control signal to the LFXT clock domain
wire lfxt_clk_n = ~lfxt_clk;
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
545,19 → 586,18
);
 
// Scan MUX to increase coverage
wire lfxt_wkup_clear;
omsp_scan_mux scan_mux_lfxt_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b1),
.data_out (lfxt_wkup_clear)
);
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (lfxt_wkup_clear),
.data_in (1'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
677,7 → 717,6
`else
assign nodiv_mclk = dco_clk;
`endif
assign nodiv_mclk_n = ~nodiv_mclk;
 
 
// Wakeup synchronizer
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v
323,16 → 323,17
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
 
`ifdef CLOCK_GATING
wire mclk_bckup;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_bckup = mclk;
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
 
reg [15:0] pmem_dout_bckup;
always @(posedge mclk_bckup or posedge puc_rst)
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
467,6 → 467,18
//-------------------------------------------------------
`define OSCOFF_EN
 
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
 
`endif
`endif
/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_mux.v
121,9 → 121,21
 
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in0_scan_fix_inv;
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in1;
 
//-----------------------------------------------------------------------------
// Optional scan repair for neg-edge clocked FF
//-----------------------------------------------------------------------------
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
`else
assign clk_in0_scan_fix_inv = ~clk_in0;
assign clk_in1_scan_fix_inv = ~clk_in1;
`endif
 
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
131,11 → 143,11
 
assign in0_select = ~select_in & ~in1_select_ss;
 
always @ (posedge clk_in0_inv or posedge reset)
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
 
always @ (posedge clk_in0 or posedge reset)
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
 
148,7 → 160,7
 
assign in1_select = select_in & ~in0_select_ss;
 
always @ (posedge clk_in1_inv or posedge reset)
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
 
175,7 → 187,6
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
 
 
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
161,7 → 161,6
 
// Local wire declarations
wire nodiv_mclk;
wire nodiv_mclk_n;
wire nodiv_smclk;
 
 
317,14 → 316,14
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
 
wire scg0_and_mclk_dma_enable;
334,13 → 333,13
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
`endif
 
wire scg1_and_mclk_dma_enable;
350,13 → 349,13
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
`endif
 
wire oscoff_and_mclk_dma_enable;
366,19 → 365,19
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup= mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
 
 
418,12 → 417,25
 
// Register to prevent glitch propagation
reg dco_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1'b1;
else dco_disable <= ~dco_enable_nxt;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
 
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
 
// Note that a synchronizer is required if the MCLK mux is included
wire dco_clk_n = ~dco_clk;
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
432,7 → 444,24
.rst (por)
);
`else
assign dco_enable = ~dco_disable;
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
 
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1'b0;
else dco_enable <= ~dco_disable;
`endif
 
// The DCO oscillator will get an asynchronous wakeup if:
455,19 → 484,18
);
 
// Scan MUX to increase coverage
wire dco_wkup_clear;
omsp_scan_mux scan_mux_dco_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b1),
.data_out (dco_wkup_clear)
);
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b0),
.data_out (dco_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (dco_wkup_clear),
.data_in (1'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
512,12 → 540,25
 
// Register to prevent glitch propagation
reg lfxt_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1'b1;
else lfxt_disable <= ~lfxt_enable_nxt;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
 
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
 
// Synchronize the OSCOFF control signal to the LFXT clock domain
wire lfxt_clk_n = ~lfxt_clk;
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
545,19 → 586,18
);
 
// Scan MUX to increase coverage
wire lfxt_wkup_clear;
omsp_scan_mux scan_mux_lfxt_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b1),
.data_out (lfxt_wkup_clear)
);
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (lfxt_wkup_clear),
.data_in (1'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
677,7 → 717,6
`else
assign nodiv_mclk = dco_clk;
`endif
assign nodiv_mclk_n = ~nodiv_mclk;
 
 
// Wakeup synchronizer
/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
323,16 → 323,17
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
 
`ifdef CLOCK_GATING
wire mclk_bckup;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_bckup = mclk;
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
 
reg [15:0] pmem_dout_bckup;
always @(posedge mclk_bckup or posedge puc_rst)
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
467,6 → 467,18
//-------------------------------------------------------
`define OSCOFF_EN
 
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
 
`endif
`endif
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_mux.v
121,9 → 121,21
 
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in0_scan_fix_inv;
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in1;
 
//-----------------------------------------------------------------------------
// Optional scan repair for neg-edge clocked FF
//-----------------------------------------------------------------------------
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
`else
assign clk_in0_scan_fix_inv = ~clk_in0;
assign clk_in1_scan_fix_inv = ~clk_in1;
`endif
 
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
131,11 → 143,11
 
assign in0_select = ~select_in & ~in1_select_ss;
 
always @ (posedge clk_in0_inv or posedge reset)
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
 
always @ (posedge clk_in0 or posedge reset)
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
 
148,7 → 160,7
 
assign in1_select = select_in & ~in0_select_ss;
 
always @ (posedge clk_in1_inv or posedge reset)
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
 
175,7 → 187,6
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
 
 
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
161,7 → 161,6
 
// Local wire declarations
wire nodiv_mclk;
wire nodiv_mclk_n;
wire nodiv_smclk;
 
 
317,14 → 316,14
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
 
wire scg0_and_mclk_dma_enable;
334,13 → 333,13
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
`endif
 
wire scg1_and_mclk_dma_enable;
350,13 → 349,13
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
`endif
 
wire oscoff_and_mclk_dma_enable;
366,19 → 365,19
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup= mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
 
 
418,12 → 417,25
 
// Register to prevent glitch propagation
reg dco_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1'b1;
else dco_disable <= ~dco_enable_nxt;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
 
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
 
// Note that a synchronizer is required if the MCLK mux is included
wire dco_clk_n = ~dco_clk;
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
432,7 → 444,24
.rst (por)
);
`else
assign dco_enable = ~dco_disable;
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
 
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1'b0;
else dco_enable <= ~dco_disable;
`endif
 
// The DCO oscillator will get an asynchronous wakeup if:
455,19 → 484,18
);
 
// Scan MUX to increase coverage
wire dco_wkup_clear;
omsp_scan_mux scan_mux_dco_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b1),
.data_out (dco_wkup_clear)
);
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b0),
.data_out (dco_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (dco_wkup_clear),
.data_in (1'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
512,12 → 540,25
 
// Register to prevent glitch propagation
reg lfxt_disable;
always @(posedge nodiv_mclk_n or posedge por)
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1'b1;
else lfxt_disable <= ~lfxt_enable_nxt;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
 
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
 
// Synchronize the OSCOFF control signal to the LFXT clock domain
wire lfxt_clk_n = ~lfxt_clk;
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
545,19 → 586,18
);
 
// Scan MUX to increase coverage
wire lfxt_wkup_clear;
omsp_scan_mux scan_mux_lfxt_wkup_clear (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b1),
.data_out (lfxt_wkup_clear)
);
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
 
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (lfxt_wkup_clear),
.data_in (1'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
677,7 → 717,6
`else
assign nodiv_mclk = dco_clk;
`endif
assign nodiv_mclk_n = ~nodiv_mclk;
 
 
// Wakeup synchronizer
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
323,16 → 323,17
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
 
`ifdef CLOCK_GATING
wire mclk_bckup;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_bckup = mclk;
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
 
reg [15:0] pmem_dout_bckup;
always @(posedge mclk_bckup or posedge puc_rst)
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
467,6 → 467,18
//-------------------------------------------------------
`define OSCOFF_EN
 
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
 
`endif
`endif

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