URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
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/openmsp430/trunk
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- ↔ Reverse comparison
Rev 100 → Rev 99
fpga/altera_de1_board/software/memledtest
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Index: doc/openMSP430.pdf
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Index: doc/html/overview.html
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@@ -31,7 +31,7 @@
To keep yourself informed about project updates, you can subscribe to the following RSS feed.
Documentation
-The online documentation is available as pdf. +The online documentation is available as pdf.Features & Limitations
Features
-
@@ -79,7 +79,7 @@
- Icarus Verilog : Verilog simulator.
- GTKWave Analyzer : Waveform viewer. -
- MSPGCC4 : GCC toolchain for the Texas Instruments MSP430 MCUs. +
- MSPGCC : GCC toolchain for the Texas Instruments MSP430 MCUs.
- ISE WebPACK : Xilinx's FPGA synthesis tool.
- (1) Connect to the openMSP430 Serial Debug Interface -
- (2) Load the program memory with an ELF or Intel-HEX file -
- (3) Control the CPU: Reset, Stop, Start and Single-Step -
- (4) Read/Write individual status bits -
- (5) Read/Write access of the CPU registers -
- (6) Read/Write access of the whole memory range (program, data, peripherals) -
- (7) Source a custom external TCL script -
- (8) Basic disassembled view of the loaded program (current PC location is highlighted in yellow) -
- (9) Choose the disassembled view type +
- (1) Load the program memory with an ELF file +
- (2) Reset the CPU +
- (3) Stop/Start the program execution +
- (4) Read/Write access of the CPU registers +
- (5) Read/Write access of the whole memory range (program, data, peripherals)
2. openmsp430-loader
This simple program allows the user to load the openMSP430 program -memory with an executable file (ELF or Intel-HEX format) provided as argument.+memory with an executable file (ELF format) provided as argument.
It is typically used in conjunction with 'make' in order to automatically load the program after the compile step (see 'Makefile' from software examples provided with the project's FPGA implementation).
The program can be called with the following syntax:
@@ -48,10 +48,10 @@
openmsp430-loader.tcl [-device <communication device>] [-baudrate <communication speed>] <elf/ihex-file>
+ openmsp430-loader.tcl [-device <communication device>] [-baudrate <communication speed>] <elf-file>
Examples: openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 9600 leds.elf
openmsp430-loader.tcl
--device COM2: -baudrate 38400 ta_uart.ihex
+-device COM2: -baudrate 38400 ta_uart.elf
3. openmsp430-minidebug
This small program provides a minimalistic graphical interface enabling simple interaction with the openMSP430:- +
As you can see from the screenshot, it allows the following actions:
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/doc/html/images/spacewar.png
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-openMSP430 File & Directory description
+
+
+openMSP430 File & Directory description
+
+
+
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+actel Actel synthesis setup for area & speed analysis
+ altera Altera synthesis setup for area & speed analysis
+ xilinx Xilinx synthesis setup for area & speed analysis
+
+
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Table of content
-
-
- 1. Introduction -
- 2. Directory structure: openMSP430 core -
- 3. Directory structure: FGPA projects +
- 1. Introduction +
- 2. Directory structure: openMSP430 core +
- 3. Directory structure: FGPA projects -
- 4. Directory structure: Software Development Tools +
- 4. Directory structure: Software Development Tools
1. Introduction
To simplify the integration of this IP, the directory structure is based on the OpenCores recommendations. -+
- +
2. Directory structure: openMSP430 core
core | openMSP430 Core top level directory | ||||
core | openMSP430 Core top level directory | ||||
abcd | bench | Top level testbench directory | |||
abcd | verilog | - | |||
abcd | tb_openMSP430.v | Testbench top level module | |||
abcd | verilog | ||||
abcd | tb_openMSP430.v | Testbench top level module | |||
ram.v | RAM verilog model | ||||
registers.v | Connections to Core internals for easy debugging | ||||
dbg_uart_tasks.v | UART tasks for the serial debug interface | ||||
doc | Diverse documentation | ||||
abcd | slau049f.pdf | MSP430x1xx Family User's Guide | |||
rtl | RTL sources | ||||
abcd | verilog | - | |||
abcd | verilog | ||||
abcd | openMSP430_defines.v | openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration) | |||
openMSP430_undefines.v | openMSP430 Verilog `undef file | ||||
openMSP430.v | openMSP430 top level | ||||
sim | Top level simulations directory | ||||
abcd | rtl_sim | RTL simulations | |||
abcd | bin | RTL simulation scripts | |||
abcd | msp430sim | Main simulation script | |||
abcd | msp430sim | Main simulation script | |||
asm2ihex.sh | Assembly file compilation (Intel HEX file generation) | ||||
ihex2mem.tcl | Verilog program memory file generation | ||||
rtlsim.sh | Verilog Icarus simulation script | ||||
template.def | ASM linker definition file template | ||||
run | For running RTL simulations | ||||
abcd | run | Run single simulation of a given vector | |||
abcd | run | Run single simulation of a given vector | |||
run_all | Run regression of all vectors | ||||
run_disassemble | Disassemble the program memory content of the latest simulation | ||||
load_waveform.sav | SAV file for gtkWave | ||||
read.tcl | Read RTL | ||||
constraints.tcl | Set design constrains | ||||
results | Results directory | ||||
actel | Actel synthesis setup for area & speed analysis | ||||
altera | Altera synthesis setup for area & speed analysis | ||||
xilinx | Xilinx synthesis setup for area & speed analysis |
+
- +
3. Directory structure: FGPA projects
@@ -118,12 +119,11 @@3.1 Xilinx Spartan 3 example
fpga | openMSP430 FPGA Projects top level directory | ||||||
fpga | openMSP430 FPGA Projects top level directory | ||||||
abcd | xilinx_diligent_s3_board | Xilinx FPGA Project based on the Diligent Spartan-3 board | |||||
abcd | bench | Top level testbench directory | |||||
abcd | verilog | - | |||||
abcd | tb_openMSP430_fpga.v | FPGA testbench top level module | |||||
abcd | verilog | ||||||
abcd | tb_openMSP430_fpga.v | FPGA testbench top level module | |||||
registers.v | Connections to Core internals for easy debugging | ||||||
msp_debug.v | Testbench instruction decoder and ASCII chain generator for easy debugging | ||||||
glbl.v | Xilinx "glbl.v" file | ||||||
msp430f1121a.pdf | msp430f1121a Specification | ||||||
xapp462.pdf | Xilinx Digital Clock Managers (DCMs) user guide | ||||||
rtl | RTL sources | ||||||
abcd | verilog | - | |||||
abcd | verilog | ||||||
abcd | openMSP430_fpga.v | FPGA top level file | |||||
driver_7segment.v | Four-Digit, Seven-Segment LED Display driver | ||||||
io_mux.v | I/O mux for port function selection. | ||||||
sim | Top level simulations directory | ||||||
abcd | rtl_sim | RTL simulations | |||||
abcd | bin | RTL simulation scripts | |||||
abcd | msp430sim | Main simulation script | |||||
abcd | msp430sim | Main simulation script | |||||
ihex2mem.tcl | Verilog program memory file generation | ||||||
rtlsim.sh | Verilog Icarus simulation script | ||||||
run | For running RTL simulations | ||||||
*.v | Stimulus vector for the corresponding software project | ||||||
software | Software C programs to be loaded in the program memory | ||||||
abcd | leds | LEDs blinking application (from the CDK4MSP project) | |||||
abcd | makefile | - | |||||
hardware.h | - | ||||||
main.c | - | ||||||
7seg.h | - | ||||||
7seg.c | - | ||||||
abcd | makefile | ||||||
hardware.h | |||||||
main.c | |||||||
7seg.h | |||||||
7seg.c | |||||||
ta_uart | Software UART with Timer_A (from the CDK4MSP project) | ||||||
synthesis | Top level synthesis directory | ||||||
abcd | xilinx | - | |||||
abcd | xilinx | ||||||
abcd | create_bitstream.sh | Run Xilinx ISE synthesis in a Linux environment | |||||
create_bitstream.bat | Run Xilinx ISE synthesis in a Windows environment | ||||||
openMSP430_fpga.ucf | UCF file | ||||||
load_rom.sh | Update bitstream's program memory with a given software ELF file in a Linux environment | ||||||
load_rom.bat | Update bitstream's program memory with a given software ELF file in a Windows environment | ||||||
memory.bmm | FPGA memory description for bitstream's program memory update |
+ +
- +
3.2 Altera Cyclone II example
fpga | openMSP430 FPGA Projects top level directory | ||||||
fpga | openMSP430 FPGA Projects top level directory | ||||||
abcd | altera_de1_board | Altera FPGA Project based on Cyclone II Starter Development Board | |||||
abcd | README | README file | |||||
bench | Top level testbench directory | ||||||
abcd | verilog | - | |||||
abcd | tb_openMSP430_fpga.v | FPGA testbench top level module | |||||
abcd | verilog | ||||||
abcd | tb_openMSP430_fpga.v | FPGA testbench top level module | |||||
registers.v | Connections to Core internals for easy debugging | ||||||
msp_debug.v | Testbench instruction decoder and ASCII chain generator for easy debugging | ||||||
altsyncram.v | Altera verilog model of the altsyncram module. | ||||||
DE1_Reference_Manual.pdf | Cyclone II FPGA Starter Development Board Reference Manual | ||||||
DE1_User_Guide.pdf | Cyclone II FPGA Starter Development Board User Guide | ||||||
rtl | RTL sources | ||||||
abcd | verilog | - | |||||
abcd | verilog | ||||||
abcd | OpenMSP430_fpga.v | FPGA top level file | |||||
driver_7segment.v | Four-Digit, Seven-Segment LED Display driver | ||||||
io_mux.v | I/O mux for port function selection. | ||||||
sim | Top level simulations directory | ||||||
abcd | rtl_sim | RTL simulations | |||||
abcd | bin | RTL simulation scripts | |||||
abcd | msp430sim | Main simulation script | |||||
abcd | msp430sim | Main simulation script | |||||
ihex2mem.tcl | Verilog program memory file generation | ||||||
rtlsim.sh | Verilog Icarus simulation script | ||||||
run | For running RTL simulations | ||||||
*.v | Stimulus vector for the corresponding software project | ||||||
software | Software C programs to be loaded in the program memory | ||||||
abcd | bin | Specific binaries required for software development. | |||||
abcd | mifwrite.cpp | This -prog is taken from -http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly -changed to satisfy quartus6.1 *.mif eating engine. | |||||
abcd | mifwrite.cpp | This prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly changed to satisfy quartus6.1 *.mif eating engine. | |||||
mifwrite.exe | Windows executable. | ||||||
mifwrite | Linux executable. | ||||||
memledtest | LEDs blinking application (from the CDK4MSP project) | ||||||
synthesis | Top level synthesis directory | ||||||
abcd | altera | - | |||||
abcd | altera | ||||||
abcd | main.qsf | Global Assignments file | |||||
main.sof | SOF file | ||||||
OpenMSP430_fpga.qpf | Quartus II project file | ||||||
openMSP430_fpga_top.v | RTL file list to be synthesized |
- - - -
3.3 Actel ProASIC3 example
- -fpga | openMSP430 FPGA Projects top level directory | |||||
abcd | actel_m1a3pl_dev_kit | Actel FPGA Project based on the ProASIC3 M1A3PL development kit - | ||||
abcd | -bench | Top level testbench directory | ||||
abcd | verilog | - | ||||
abcd | tb_openMSP430_fpga.v | -FPGA testbench top level module | ||||
registers.v | -Connections to Core internals for easy debugging | |||||
msp_debug.v | -Testbench instruction decoder and ASCII chain generator for easy debugging | |||||
proasic3l.v | -Actel ProASIC3L library file. - | |||||
DAC121S101.v - |
- Verilog model of National's DAC121S101 12 bit DAC. | -|||||
doc | Diverse documentation | |||||
abcd | M1A3PL_DEV_KIT_QS.pdf | Development Kit Quickstart Card. | ||||
M1IGLOO_StarterKit_v1_5_UG.pdf | Development Kit User's Guide. | |||||
rtl | RTL sources | |||||
abcd | verilog | - | ||||
abcd | openMSP430_fpga.v | -FPGA top level file | ||||
dac_spi_if.v | -SPI interface to National's DAC121S101 12 bit DAC. - | |||||
smartgen - |
- Actel's smartgen directory. | |||||
abcd | -dmem_128B.v | 128 Byte RAM (for data memory). - | ||||
- |
-pmem_2kB.v | 2 kByte RAM (for program memory). - | ||||
openmsp430 | -Local copy of the openMSP430 core. The *define.v file has been adjusted to the requirements of the project. | |||||
sim | Top level simulations directory | |||||
abcd | rtl_sim | RTL simulations | ||||
- |
- bin - |
-RTL simulation scripts - | ||||
- |
- msp430sim - |
- Main simulation script - |
- ||||
ihex2mem.tcl - |
- Verilog program memory file generation - |
- |||||
rtlsim.sh - |
- Verilog Icarus simulation script - |
- |||||
run | -For running RTL simulations | |||||
- |
- run - |
-Run simulation of a given software project - | ||||
run_disassemble - |
- Disassemble the program memory content of the latest simulation | -|||||
src | -RTL simulation verilog stimulus | |||||
- |
- submit.f - |
- Verilog simulator command file - |
- ||||
*.v - |
-Stimulus vector for the corresponding software project | |||||
software | Software C programs to be loaded in the program memory | |||||
- |
-spacewar - | SpaceWar oscilloscope game. - | ||||
- |
- - |
- |||||
synthesis | Top level synthesis directory | |||||
abcd | actel | - | ||||
abcd | prepare_implementation.tcl - |
- Generate required files prior synthesis and P&R. - | ||||
synplify.tcl - |
- Synplify template for the synthesis run. - | |||||
libero_designer.tcl - |
- Libero Designer template for the P&R run. - | |||||
design_files.v - |
- RTL file list to be synthesized. - |
- |||||
design_constraints.pre.sdc - |
- Synthesis timing constraints. - |
- |||||
design_constraints.post.sdc - |
- P&R timing constraints. - |
- |||||
design_constraints.pdc - |
- P&R physical constraints. - |
+ +
- +
4. Directory structure: Software Development Tools
tools | openMSP430 Software Development Tools top level directory | ||||
tools | openMSP430 Software Development Tools top level directory | ||||
abcd | bin | Contains the executable files | |||
abcd | openmsp430-loader.tcl | Simple command line boot loader: TCL Script | |||
abcd | openmsp430-loader.tcl | Simple command line boot loader: TCL Script | |||
openmsp430-loader.exe | Simple command line boot loader: Windows executable | ||||
openmsp430-minidebug.tcl | Minimalistic debugger with simple GUI: TCL Script | ||||
openmsp430-minidebug.exe | Minimalistic debugger with simple GUI: Windows executable | ||||
abcd | ew_GDB_RSP.pdf | Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol | |||
Howto-GDB_Remote_Serial_Protocol.pdf | Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server | ||||
freewrap642 | The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows. | ||||
abcd | freewrap.exe | freeWrap executable to run on TCL/TK scripts (i.e. with GUI) | |||
abcd | freewrap.exe | freeWrap executable to run on TCL/TK scripts (i.e. with GUI) | |||
freewrapTCLSH.exe | freeWrap executable to run on pure TCL scripts (i.e. command line) | ||||
tclpip85s.dll | freeWrap mandatory DLL | ||||
generate_exec.bat | Simple Batch file for auto generation of the tools' windows executables |
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