Subversion Repositories openmsp430

/fpga/diligent_s3board/bench/verilog/msp_debug.v

fpga/diligent_s3board/bench/verilog/msp_debug.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/bench/verilog/registers.v =================================================================== --- fpga/diligent_s3board/bench/verilog/registers.v (revision 15) +++ fpga/diligent_s3board/bench/verilog/registers.v (revision 16) @@ -31,6 +31,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- // CPU registers //======================

fpga/diligent_s3board/bench/verilog/registers.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v =================================================================== --- fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v (revision 15) +++ fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v (revision 16) @@ -31,6 +31,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- `timescale 1ns / 100ps

fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/openMSP430.inc =================================================================== --- fpga/diligent_s3board/rtl/verilog/openMSP430.inc (revision 15) +++ fpga/diligent_s3board/rtl/verilog/openMSP430.inc (revision 16) @@ -31,6 +31,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- //----------------------------------------------------------------------------

fpga/diligent_s3board/rtl/verilog/openMSP430.inc Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/io_mux.v =================================================================== --- fpga/diligent_s3board/rtl/verilog/io_mux.v (revision 15) +++ fpga/diligent_s3board/rtl/verilog/io_mux.v (revision 16) @@ -31,6 +31,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- `timescale 1ns / 100ps module io_mux (

fpga/diligent_s3board/rtl/verilog/io_mux.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/driver_7segment.v =================================================================== --- fpga/diligent_s3board/rtl/verilog/driver_7segment.v (revision 15) +++ fpga/diligent_s3board/rtl/verilog/driver_7segment.v (revision 16) @@ -31,6 +31,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- `timescale 1ns / 100ps module driver_7segment (

fpga/diligent_s3board/rtl/verilog/driver_7segment.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v =================================================================== --- fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v (revision 15) +++ fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v (revision 16) @@ -32,6 +32,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- `timescale 1ns / 100ps module openMSP430_fpga (

fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/sim/rtl_sim/src/submit.f =================================================================== --- fpga/diligent_s3board/sim/rtl_sim/src/submit.f (revision 15) +++ fpga/diligent_s3board/sim/rtl_sim/src/submit.f (revision 16) @@ -1,4 +1,39 @@ //============================================================================= +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//----------------------------------------------------------------------------- +// +// File Name: submit.f +// +// Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//----------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//============================================================================= + +//============================================================================= // Xilinx library //============================================================================= +libext+.v

fpga/diligent_s3board/sim/rtl_sim/src/submit.f Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl =================================================================== --- fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl (revision 15) +++ fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl (revision 16) @@ -25,7 +25,14 @@ # # File Name: ihex2mem.tcl # +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# #------------------------------------------------------------------------------ +# $Rev$ +# $LastChangedBy$ +# $LastChangedDate$ +#------------------------------------------------------------------------------ ############################################################################### # PARAMETER CHECK #

fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim =================================================================== --- fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim (revision 15) +++ fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim (revision 16) @@ -25,7 +25,14 @@ # # File Name: msp430sim # +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# #------------------------------------------------------------------------------ +# $Rev$ +# $LastChangedBy$ +# $LastChangedDate$ +#------------------------------------------------------------------------------ ############################################################################### # Parameter Check #

fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh =================================================================== --- fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh (revision 15) +++ fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh (revision 16) @@ -25,7 +25,14 @@ # # File Name: rtlsim.sh # +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# #------------------------------------------------------------------------------ +# $Rev$ +# $LastChangedBy$ +# $LastChangedDate$ +#------------------------------------------------------------------------------ ############################################################################### # Parameter Check #

fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf =================================================================== --- fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf (revision 15) +++ fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf (revision 16) @@ -1,3 +1,38 @@ +#============================================================================= +# Copyright (C) 2001 Authors +# +# This source file may be used and distributed without restriction provided +# that this copyright statement is not removed from the file and that any +# derivative work contains the original copyright notice and the associated +# disclaimer. +# +# This source file is free software; you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation; either version 2.1 of the License, or +# (at your option) any later version. +# +# This source is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +# License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this source; if not, write to the Free Software Foundation, +# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#----------------------------------------------------------------------------- +# +# File Name: openMSP430_fpga_top.ucf +# +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# +#----------------------------------------------------------------------------- +# $Rev$ +# $LastChangedBy$ +# $LastChangedDate$ +#============================================================================= + #-----------------------------------------------------------------------------# # Clock configuration & ROM Block Assignments # #-----------------------------------------------------------------------------#

fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v =================================================================== --- fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v (revision 15) +++ fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v (revision 16) @@ -1,3 +1,38 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_fpga_top.v +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- + //============================================================================= // FPGA Specific modules //=============================================================================

fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v Property changes : Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property