URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/core/bench/verilog/dbg_uart_tasks.v
31,6 → 31,10
// - Olivier Girard, olgirard@gmail.com |
// |
//---------------------------------------------------------------------------- |
// $Rev$ |
// $LastChangedBy$ |
// $LastChangedDate$ |
//---------------------------------------------------------------------------- |
|
// Register B/W and addresses |
parameter CPU_ID_LO = (8'h00 | 8'h00); |
core/bench/verilog/dbg_uart_tasks.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/bench/verilog/tb_openMSP430.v
===================================================================
--- core/bench/verilog/tb_openMSP430.v (revision 16)
+++ core/bench/verilog/tb_openMSP430.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
core/bench/verilog/tb_openMSP430.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/bench/verilog/ram.v
===================================================================
--- core/bench/verilog/ram.v (revision 16)
+++ core/bench/verilog/ram.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module ram (
core/bench/verilog/ram.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/bench/verilog/msp_debug.v
===================================================================
--- core/bench/verilog/msp_debug.v (revision 16)
+++ core/bench/verilog/msp_debug.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module msp_debug (
core/bench/verilog/msp_debug.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/bench/verilog/registers.v
===================================================================
--- core/bench/verilog/registers.v (revision 16)
+++ core/bench/verilog/registers.v (revision 17)
@@ -32,6 +32,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
// CPU registers
//======================
core/bench/verilog/registers.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/dbg.v
===================================================================
--- core/rtl/verilog/dbg.v (revision 16)
+++ core/rtl/verilog/dbg.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module dbg (
core/rtl/verilog/dbg.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/openMSP430.inc
===================================================================
--- core/rtl/verilog/openMSP430.inc (revision 16)
+++ core/rtl/verilog/openMSP430.inc (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
core/rtl/verilog/openMSP430.inc
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/frontend.v
===================================================================
--- core/rtl/verilog/frontend.v (revision 16)
+++ core/rtl/verilog/frontend.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module frontend (
core/rtl/verilog/frontend.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/clock_module.v
===================================================================
--- core/rtl/verilog/clock_module.v (revision 16)
+++ core/rtl/verilog/clock_module.v (revision 17)
@@ -35,6 +35,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module clock_module (
core/rtl/verilog/clock_module.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/watchdog.v
===================================================================
--- core/rtl/verilog/watchdog.v (revision 16)
+++ core/rtl/verilog/watchdog.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module watchdog (
core/rtl/verilog/watchdog.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/alu.v
===================================================================
--- core/rtl/verilog/alu.v (revision 16)
+++ core/rtl/verilog/alu.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module alu (
core/rtl/verilog/alu.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/execution_unit.v
===================================================================
--- core/rtl/verilog/execution_unit.v (revision 16)
+++ core/rtl/verilog/execution_unit.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module execution_unit (
core/rtl/verilog/execution_unit.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/mem_backbone.v
===================================================================
--- core/rtl/verilog/mem_backbone.v (revision 16)
+++ core/rtl/verilog/mem_backbone.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module mem_backbone (
core/rtl/verilog/mem_backbone.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/periph/template_periph_8b.v
===================================================================
--- core/rtl/verilog/periph/template_periph_8b.v (revision 16)
+++ core/rtl/verilog/periph/template_periph_8b.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module template_periph_8b (
core/rtl/verilog/periph/template_periph_8b.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/periph/gpio.v
===================================================================
--- core/rtl/verilog/periph/gpio.v (revision 16)
+++ core/rtl/verilog/periph/gpio.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module gpio (
core/rtl/verilog/periph/gpio.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/periph/timerA.v
===================================================================
--- core/rtl/verilog/periph/timerA.v (revision 16)
+++ core/rtl/verilog/periph/timerA.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module timerA (
core/rtl/verilog/periph/timerA.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/periph/template_periph_16b.v
===================================================================
--- core/rtl/verilog/periph/template_periph_16b.v (revision 16)
+++ core/rtl/verilog/periph/template_periph_16b.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module template_periph_16b (
core/rtl/verilog/periph/template_periph_16b.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/register_file.v
===================================================================
--- core/rtl/verilog/register_file.v (revision 16)
+++ core/rtl/verilog/register_file.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module register_file (
core/rtl/verilog/register_file.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/dbg_uart.v
===================================================================
--- core/rtl/verilog/dbg_uart.v (revision 16)
+++ core/rtl/verilog/dbg_uart.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module dbg_uart (
core/rtl/verilog/dbg_uart.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/openMSP430.v
===================================================================
--- core/rtl/verilog/openMSP430.v (revision 16)
+++ core/rtl/verilog/openMSP430.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module openMSP430 (
core/rtl/verilog/openMSP430.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/dbg_hwbrk.v
===================================================================
--- core/rtl/verilog/dbg_hwbrk.v (revision 16)
+++ core/rtl/verilog/dbg_hwbrk.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module dbg_hwbrk (
core/rtl/verilog/dbg_hwbrk.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/rtl/verilog/sfr.v
===================================================================
--- core/rtl/verilog/sfr.v (revision 16)
+++ core/rtl/verilog/sfr.v (revision 17)
@@ -31,6 +31,10 @@
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
+// $Rev$
+// $LastChangedBy$
+// $LastChangedDate$
+//----------------------------------------------------------------------------
`timescale 1ns / 100ps
module sfr (
core/rtl/verilog/sfr.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/src/wdt_watchdog.v
===================================================================
--- core/sim/rtl_sim/src/wdt_watchdog.v (revision 16)
+++ core/sim/rtl_sim/src/wdt_watchdog.v (revision 17)
@@ -25,6 +25,11 @@
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Watchdog mode. */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev$ */
+/* $LastChangedBy$ */
+/* $LastChangedDate$ */
/*===========================================================================*/
`define LONG_TIMEOUT
core/sim/rtl_sim/src/wdt_watchdog.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/src/wdt_watchdog.s43
===================================================================
--- core/sim/rtl_sim/src/wdt_watchdog.s43 (revision 16)
+++ core/sim/rtl_sim/src/wdt_watchdog.s43 (revision 17)
@@ -25,6 +25,11 @@
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Watchdog mode. */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev$ */
+/* $LastChangedBy$ */
+/* $LastChangedDate$ */
/*===========================================================================*/
.global main
core/sim/rtl_sim/src/wdt_watchdog.s43
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/bin/ihex2mem.tcl
===================================================================
--- core/sim/rtl_sim/bin/ihex2mem.tcl (revision 16)
+++ core/sim/rtl_sim/bin/ihex2mem.tcl (revision 17)
@@ -25,7 +25,14 @@
#
# File Name: ihex2mem.tcl
#
+# Author(s):
+# - Olivier Girard, olgirard@gmail.com
+#
#------------------------------------------------------------------------------
+# $Rev$
+# $LastChangedBy$
+# $LastChangedDate$
+#------------------------------------------------------------------------------
###############################################################################
# PARAMETER CHECK #
core/sim/rtl_sim/bin/ihex2mem.tcl
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/bin/msp430sim
===================================================================
--- core/sim/rtl_sim/bin/msp430sim (revision 16)
+++ core/sim/rtl_sim/bin/msp430sim (revision 17)
@@ -25,7 +25,14 @@
#
# File Name: msp430sim
#
+# Author(s):
+# - Olivier Girard, olgirard@gmail.com
+#
#------------------------------------------------------------------------------
+# $Rev$
+# $LastChangedBy$
+# $LastChangedDate$
+#------------------------------------------------------------------------------
###############################################################################
# Parameter Check #
core/sim/rtl_sim/bin/msp430sim
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/bin/rtlsim.sh
===================================================================
--- core/sim/rtl_sim/bin/rtlsim.sh (revision 16)
+++ core/sim/rtl_sim/bin/rtlsim.sh (revision 17)
@@ -25,7 +25,14 @@
#
# File Name: rtlsim.sh
#
+# Author(s):
+# - Olivier Girard, olgirard@gmail.com
+#
#------------------------------------------------------------------------------
+# $Rev$
+# $LastChangedBy$
+# $LastChangedDate$
+#------------------------------------------------------------------------------
###############################################################################
# Parameter Check #
core/sim/rtl_sim/bin/rtlsim.sh
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property
Index: core/sim/rtl_sim/bin/asm2ihex.sh
===================================================================
--- core/sim/rtl_sim/bin/asm2ihex.sh (revision 16)
+++ core/sim/rtl_sim/bin/asm2ihex.sh (revision 17)
@@ -25,7 +25,14 @@
#
# File Name: asm2ihex.sh
#
+# Author(s):
+# - Olivier Girard, olgirard@gmail.com
+#
#------------------------------------------------------------------------------
+# $Rev$
+# $LastChangedBy$
+# $LastChangedDate$
+#------------------------------------------------------------------------------
###############################################################################
# Parameter Check #
core/sim/rtl_sim/bin/asm2ihex.sh
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Revision Author
\ No newline at end of property