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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/core/sim/rtl_sim/src/c-jump_jc.s43
24,6 → 24,14
/* CONDITIONAL JUMP: JC INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JC instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/sing-op_swpb.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: SWPB INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SWPB instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/dbg_hwbrk3.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 3. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/wdt_watchdog.v
26,6 → 26,9
/* Test the Watdog timer: */
/* - Watchdog mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/core/sim/rtl_sim/src/sing-op_sxt.s43
21,9 → 21,17
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */
/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SXT instruction. */
/* Test the SXT instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/template_periph_8b.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the 8 bit peripheral template: */
/* - Read/Write register access. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/c-jump_jge.v
24,6 → 24,14
/* CONDITIONAL JUMP: JGE INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JGE instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_rra.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: RRA[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RRA[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_rrc.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: RRC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RRC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/tA_output.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer output unit. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer my_counter;
/core/sim/rtl_sim/src/c-jump_jl.s43
24,6 → 24,14
/* CONDITIONAL JUMP: JL INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JL instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_bis.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIS[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/c-jump_jn.s43
24,6 → 24,14
/* CONDITIONAL JUMP: JN INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JN instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_bit.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIT[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIT[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/tA_clkmux.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer clock input mux. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer my_counter;
/core/sim/rtl_sim/src/two-op_mov-b.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: MOV.B INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the MOV.B instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/template_periph_16b.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the 16 bit peripheral template: */
/* - Read/Write register access. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/tA_capture.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer capture unit. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_uart.s43
27,6 → 27,14
/* - Check RD/WR access to debugg registers. */
/* - Check RD Bursts. */
/* - Check WR Bursts. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_mem.s43
28,6 → 28,14
/* */
/* Note: The burst features are specific to the selected interface */
/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/tA_modes.s43
27,6 → 27,14
/* - Check RD/WR register access. */
/* - Check the clock divider. */
/* - Check the timer modes. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/gpio_rdwr.s43
26,6 → 26,14
/* Test the Digital I/O interface: */
/* - Read/Write register access. */
/* - I/O Functionality. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/c-jump_jmp.v
24,6 → 24,14
/* CONDITIONAL JUMP: JMP INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JMP instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_add.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADD INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADD instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_bic.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/wdt_interval.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Interval timer mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/sing-op_reti.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the CALL instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_dadd.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: DADD[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the DADD[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_subc.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: SUBC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SUBC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/op_modes.s43
27,6 → 27,14
/* - CPUOFF (<=> R2[4]): turn off CPU. */
/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
/* - SCG1 (<=> R2[7]): turn off SMCLK. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/gpio_irq.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface: */
/* - Interrupts. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_mov.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the MOV instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/sing-op_sxt.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SXT instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_push.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: PUSH INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jl.v
24,6 → 24,14
/* CONDITIONAL JUMP: JL INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JL instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/wdt_clkmux.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Clock source selection. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/two-op_bis.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIS[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jn.v
24,6 → 24,14
/* CONDITIONAL JUMP: JN INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JN instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jnc.v
24,6 → 24,14
/* CONDITIONAL JUMP: JNC INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JNC instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jne.v
24,6 → 24,14
/* CONDITIONAL JUMP: JNE INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JNE instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/dbg_mem.v
28,6 → 28,14
/* */
/* Note: The burst features are specific to the selected interface */
/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/sing-op_push_rom-rd.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/tA_clkmux.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer clock input mux. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/gpio_rdwr.v
26,6 → 26,14
/* Test the Digital I/O interface: */
/* - Read/Write register access. */
/* - I/O Functionality. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jeq.s43
21,9 → 21,17
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CONDITIONAL JUMP: JEQ INSTRUCTION */
/* CONDITIONAL JUMP: JEQ INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JEQ instruction. */
/* Test the JEQ instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_addc.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADDC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/clock_module.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the ACLK and SMCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/c-jump_jmp.s43
24,6 → 24,14
/* CONDITIONAL JUMP: JMP INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JMP instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_mov.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: MOV INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the MOV instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_and.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: AND[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the AND[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_call.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the CALL instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/dbg_hwbrk0.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 0. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/dbg_hwbrk2.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 2. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/two-op_xor.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: XOR[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the XOR[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_add_rom-rd.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the ADD instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/gpio_irq.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface: */
/* - Interrupts. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/tA_compare.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer compare features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/sing-op_push.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: PUSH INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_add-b.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADD.B INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADD.B instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/wdt_clkmux.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Clock source selection. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/sing-op_call_rom-rd.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the CALL instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_cmp.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: CMP[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the CMP[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/c-jump_jnc.s43
21,9 → 21,17
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CONDITIONAL JUMP: JNC INSTRUCTION */
/* CONDITIONAL JUMP: JNC INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JNC instruction. */
/* Test the JNC instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/c-jump_jeq.v
24,6 → 24,14
/* CONDITIONAL JUMP: JEQ INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JEQ instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jne.s43
21,9 → 21,17
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CONDITIONAL JUMP: JNE INSTRUCTION */
/* CONDITIONAL JUMP: JNE INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JNE instruction. */
/* Test the JNE instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/clock_module.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the ACLK and SMCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/two-op_addc.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADDC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_sub.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: SUB[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SUB[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/dbg_cpu.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/sing-op_swpb.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: SWPB INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SWPB instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/c-jump_jc.v
24,6 → 24,14
/* CONDITIONAL JUMP: JC INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JC instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/tA_compare.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer compare features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer my_counter;
/core/sim/rtl_sim/src/sing-op_call.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the CALL instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/template_periph_8b.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the 8 bit peripheral template: */
/* - Read/Write register access. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_and.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: AND[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the AND[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_add-b.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADD.B INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADD.B instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/dbg_hwbrk0.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 0. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_hwbrk1.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 1. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_hwbrk2.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 2. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_hwbrk3.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 3. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/two-op_add_rom-rd.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the ADD instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_xor.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: XOR[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the XOR[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/wdt_watchdog.s43
26,6 → 26,9
/* Test the Watdog timer: */
/* - Watchdog mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/core/sim/rtl_sim/src/submit.f
1,4 → 1,39
//=============================================================================
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//-----------------------------------------------------------------------------
//
// File Name: submit.f
//
// Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//-----------------------------------------------------------------------------
// $Rev: 16 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $
//=============================================================================
 
//=============================================================================
// Module specific modules
//=============================================================================
 
/core/sim/rtl_sim/src/two-op_bit.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIT[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIT[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_rra.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: RRA[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RRA[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/c-jump_jge.s43
21,9 → 21,17
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CONDITIONAL JUMP: JGE INSTRUCTION */
/* CONDITIONAL JUMP: JGE INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the JGE instruction. */
/* Test the JGE instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/two-op_cmp.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: CMP[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the CMP[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_mov-b.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: MOV.B INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the MOV.B instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_rrc.s43
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: RRC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RRC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/tA_capture.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer capture unit. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer my_counter;
/core/sim/rtl_sim/src/dbg_uart.v
27,6 → 27,14
/* - Check RD/WR access to debugg registers. */
/* - Check RD Bursts. */
/* - Check WR Bursts. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT
/core/sim/rtl_sim/src/tA_output.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer output unit. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the CALL instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/tA_modes.v
27,6 → 27,14
/* - Check RD/WR register access. */
/* - Check the clock divider. */
/* - Check the timer modes. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer my_counter;
/core/sim/rtl_sim/src/two-op_add.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: ADD INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the ADD instruction with all addressing modes */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/template_periph_16b.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the 16 bit peripheral template: */
/* - Read/Write register access. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/two-op_sub.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: SUB[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SUB[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/sing-op_reti.v
24,6 → 24,14
/* SINGLE-OPERAND ARITHMETIC: RETI INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RETI instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer i;
/core/sim/rtl_sim/src/two-op_dadd.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: DADD[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the DADD[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/two-op_subc.v
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: SUBC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SUBC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
initial
/core/sim/rtl_sim/src/op_modes.v
27,6 → 27,14
/* - CPUOFF (<=> R2[4]): turn off CPU. */
/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
/* - SCG1 (<=> R2[7]): turn off SMCLK. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
integer smclk_cnt;
/core/sim/rtl_sim/src/two-op_bic.s43
24,6 → 24,14
/* TWO-OPERAND ARITHMETIC: BIC[.B] INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the BIC[.B] instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
 
/core/sim/rtl_sim/src/wdt_interval.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Interval timer mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_cpu.s43
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
/core/sim/rtl_sim/src/dbg_hwbrk1.v
25,6 → 25,14
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - Check Hardware breakpoint unit 1. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
`define LONG_TIMEOUT

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