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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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Rev 22 → Rev 23

/doc/openMSP430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/html/serial_debug_interface.html
663,7 → 663,7
<a name="2.4 Hardware Breakpoint Unit Registers"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h2>2.4 Hardware Breakpoint Unit Registers</h2>
Depending on the <a href="http://www.opencores.org/project/openmsp430/core#2.1.3 Configuration">defines</a> located in the "openmsp430.inc" file, up to four hardware breakpoint units can be included in the design. These units can be individually controlled with the following registers.
Depending on the <a href="http://www.opencores.org/project/openmsp430/core#2.1.3 Configuration">defines</a> located in the "openmsp430_defines.v" file, up to four hardware breakpoint units can be included in the design. These units can be individually controlled with the following registers.
<a name="2.4.1 BRKx_CTL"></a>
<h3>2.4.1 BRKx_CTL</h3>
 
/doc/html/core.html
81,7 → 81,7
<a name="2.1.3 Configuration"></a>
<h3>2.1.3 Configuration</h3>
 
It is possible to configure the openMSP430 core through the "openMSP320.inc" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
Two parameters can be adjusted by the user in order to define the ROM and RAM sizes:
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
195,7 → 195,7
<tr> <td> dbg_uart_rxd </td> <td> Input </td> <td> 1 </td> <td> Debug interface: UART RXD </td> </tr>
</table>
<br />
<sup>1</sup>: This parameter is declared in the "openMSP320.inc" file and defines the RAM/ROM size.
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.
<br /><br />
 
<a name="2.1.5 Instruction Cycles and Lengths"></a>
/doc/html/files_directory_description.html
35,7 → 35,7
<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
<tr><td rowspan="19" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr>
<tr><td rowspan="18" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430.inc</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition, Debug Interface configuration)</i></td></tr>
<tr><td rowspan="18" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition, Debug Interface configuration)</i></td></tr>
<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
<tr><td colspan="2">frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
<tr><td colspan="2">execution_unit.v</td> <td><i>Execution unit</i></td></tr>
117,7 → 117,7
<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr>
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i></td></tr>
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430.inc</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition)</i></td></tr>
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition)</i></td></tr>
<tr><td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
/doc/openMSP430.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/core/bench/verilog/tb_openMSP430.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
 
module tb_openMSP430;
/core/bench/verilog/ram.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module ram (
 
/core/bench/verilog/msp_debug.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module msp_debug (
 
/core/rtl/verilog/openMSP430.inc File deleted
core/rtl/verilog/openMSP430.inc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: core/rtl/verilog/dbg.v =================================================================== --- core/rtl/verilog/dbg.v (revision 22) +++ core/rtl/verilog/dbg.v (revision 23) @@ -35,7 +35,8 @@ // $LastChangedBy$ // $LastChangedDate$ //---------------------------------------------------------------------------- -`timescale 1ns / 100ps +`include "timescale.v" +`include "openMSP430_defines.v" module dbg (
/core/rtl/verilog/frontend.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module frontend (
 
/core/rtl/verilog/clock_module.v
39,7 → 39,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module clock_module (
 
/core/rtl/verilog/watchdog.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module watchdog (
 
/core/rtl/verilog/alu.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module alu (
 
/core/rtl/verilog/execution_unit.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module execution_unit (
 
/core/rtl/verilog/mem_backbone.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module mem_backbone (
 
/core/rtl/verilog/periph/template_periph_8b.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module template_periph_8b (
 
/core/rtl/verilog/periph/gpio.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module gpio (
 
/core/rtl/verilog/periph/timerA.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module timerA (
 
/core/rtl/verilog/periph/template_periph_16b.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module template_periph_16b (
 
/core/rtl/verilog/register_file.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module register_file (
 
/core/rtl/verilog/openMSP430_defines.v
0,0 → 1,296
`ifdef OPENMSP430_DEFINES
`else
`define OPENMSP430_DEFINES
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// ROM Size:
// 9 -> 1kB
// 10 -> 2kB
// 11 -> 4kB
// 12 -> 8kB
// 13 -> 16kB
`define ROM_AWIDTH 10
 
// RAM Size:
// 6 -> 128 B
// 7 -> 256 B
// 8 -> 512 B
// 9 -> 1 kB
// 10 -> 2 kB
`define RAM_AWIDTH 6
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`define DBG_EN
 
// Debug interface selection
// `define DBG_UART -> Enable UART (8N1) debug interface
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
`define DBG_HWBRK_0
`define DBG_HWBRK_1
`define DBG_HWBRK_2
`define DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// ROM and RAM sizes
`define ROM_SIZE (2 << `ROM_AWIDTH)
`define RAM_SIZE (2 << `RAM_AWIDTH)
 
// RAM Base Adresses
`define RAM_BASE 16'h0200 // RAM base address
 
// ROM & RAM most significant address bit (for 16 bit words)
`define ROM_MSB `ROM_AWIDTH-1
`define RAM_MSB `RAM_AWIDTH-1
 
 
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
 
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
 
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
 
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
 
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
 
// Execution state machine
`define E_IRQ_0 4'h0
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h2
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
 
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
 
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
 
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS 3
`define DIVSx 2:1
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug interface ID
`define DBG_ID 24'h4D5350
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET
`else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
 
 
`endif
core/rtl/verilog/openMSP430_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: core/rtl/verilog/timescale.v =================================================================== --- core/rtl/verilog/timescale.v (nonexistent) +++ core/rtl/verilog/timescale.v (revision 23) @@ -0,0 +1 @@ +`timescale 1ns / 100ps
core/rtl/verilog/timescale.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: core/rtl/verilog/dbg_uart.v =================================================================== --- core/rtl/verilog/dbg_uart.v (revision 22) +++ core/rtl/verilog/dbg_uart.v (revision 23) @@ -35,7 +35,8 @@ // $LastChangedBy$ // $LastChangedDate$ //---------------------------------------------------------------------------- -`timescale 1ns / 100ps +`include "timescale.v" +`include "openMSP430_defines.v" module dbg_uart (
/core/rtl/verilog/openMSP430.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module openMSP430 (
 
/core/rtl/verilog/dbg_hwbrk.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module dbg_hwbrk (
 
/core/rtl/verilog/sfr.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module sfr (
 
/core/sim/rtl_sim/src/submit.f
38,7 → 38,6
//=============================================================================
 
+incdir+../../../rtl/verilog/
../../../rtl/verilog/openMSP430.inc
../../../rtl/verilog/openMSP430.v
../../../rtl/verilog/frontend.v
../../../rtl/verilog/execution_unit.v
/core/sim/rtl_sim/bin/msp430sim
52,7 → 52,7
asmfile=../src/$1.s43;
verfile=../src/$1.v;
submitfile=../src/submit.f;
incfile=../../../rtl/verilog/openMSP430.inc;
incfile=../../../rtl/verilog/openMSP430_defines.v;
deffile=../bin/template.def;
 
if [ ! -e $asmfile ]; then
/fpga/diligent_s3board/bench/verilog/msp_debug.v
35,7 → 35,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module msp_debug (
 
/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
35,9 → 35,9
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
 
module tb_openMSP430_fpga;
 
//
/fpga/diligent_s3board/rtl/verilog/openMSP430.inc File deleted
fpga/diligent_s3board/rtl/verilog/openMSP430.inc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/io_mux.v =================================================================== --- fpga/diligent_s3board/rtl/verilog/io_mux.v (revision 22) +++ fpga/diligent_s3board/rtl/verilog/io_mux.v (revision 23) @@ -35,7 +35,7 @@ // $LastChangedBy$ // $LastChangedDate$ //---------------------------------------------------------------------------- -`timescale 1ns / 100ps +`include "timescale.v" module io_mux (
/fpga/diligent_s3board/rtl/verilog/driver_7segment.v
35,7 → 35,7
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
 
module driver_7segment (
 
/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v
36,7 → 36,8
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
`include "openMSP430_defines.v"
 
module openMSP430_fpga (
 
/fpga/diligent_s3board/rtl/verilog/openMSP430_defines.v
0,0 → 1,297
`ifdef OPENMSP430_DEFINES
`else
`define OPENMSP430_DEFINES
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
 
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// ROM Size:
// 9 -> 1kB
// 10 -> 2kB
// 11 -> 4kB
// 12 -> 8kB
// 13 -> 16kB
`define ROM_AWIDTH 11
 
// RAM Size:
// 6 -> 128 B
// 7 -> 256 B
// 8 -> 512 B
// 9 -> 1 kB
// 10 -> 2 kB
`define RAM_AWIDTH 9
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`define DBG_EN
 
// Debug interface selection
// `define DBG_UART -> Enable UART (8N1) debug interface
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// ROM and RAM sizes
`define ROM_SIZE (2 << `ROM_AWIDTH)
`define RAM_SIZE (2 << `RAM_AWIDTH)
 
// RAM Base Adresses
`define RAM_BASE 16'h0200 // RAM base address
 
// ROM & RAM most significant address bit (for 16 bit words)
`define ROM_MSB `ROM_AWIDTH-1
`define RAM_MSB `RAM_AWIDTH-1
 
 
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
 
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
 
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
 
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
 
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
 
// Execution state machine
`define E_IRQ_0 4'h0
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h2
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
 
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
 
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
 
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS 3
`define DIVSx 2:1
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug interface ID
`define DBG_ID 24'h4D5350
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET
`else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
 
 
`endif
fpga/diligent_s3board/rtl/verilog/openMSP430_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: fpga/diligent_s3board/rtl/verilog/timescale.v =================================================================== --- fpga/diligent_s3board/rtl/verilog/timescale.v (nonexistent) +++ fpga/diligent_s3board/rtl/verilog/timescale.v (revision 23) @@ -0,0 +1 @@ +`timescale 1ns / 100ps
fpga/diligent_s3board/rtl/verilog/timescale.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: fpga/diligent_s3board/sim/rtl_sim/src/submit.f =================================================================== --- fpga/diligent_s3board/sim/rtl_sim/src/submit.f (revision 22) +++ fpga/diligent_s3board/sim/rtl_sim/src/submit.f (revision 23) @@ -48,7 +48,6 @@ //============================================================================= +incdir+../../../rtl/verilog/ -../../../rtl/verilog/openMSP430.inc ../../../rtl/verilog/openMSP430_fpga.v ../../../rtl/verilog/io_mux.v ../../../rtl/verilog/driver_7segment.v
/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim
53,7 → 53,7
elffile=../../../software/$1/$1.elf;
verfile=../src/$1.v;
submitfile=../src/submit.f;
incfile=../../../rtl/verilog/openMSP430.inc;
incfile=../../../rtl/verilog/openMSP430_defines.v;
 
if [ ! -e $softdir ]; then
echo "Software directory doesn't exist: $softdir"
/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v
37,7 → 37,6
// FPGA Specific modules
//=============================================================================
 
`include "../../../rtl/verilog/openMSP430.inc"
`include "../../../rtl/verilog/openMSP430_fpga.v"
`include "../../../rtl/verilog/io_mux.v"
`include "../../../rtl/verilog/driver_7segment.v"
/fpga/diligent_s3board/synthesis/xilinx/create_bitstream
10,6 → 10,12
ln -s ../../../rtl/verilog/coregen/ram_8x512_lo.ngc .
ln -s ../../../rtl/verilog/coregen/rom_8x2k_hi.ngc .
ln -s ../../../rtl/verilog/coregen/rom_8x2k_lo.ngc .
 
# Create links for the timescale and the openMSP430 configuration
ln -s ../../../rtl/verilog/timescale.v .
ln -s ../../../rtl/verilog/openMSP430_defines.v .
 
# Create link to the Xilinx constraints file
ln -s ../openMSP430_fpga_top.ucf .
 
 

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