URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/doc/openMSP430.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/doc/html/images/cpu_structure.odg
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/doc/html/images/cpu_structure.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/doc/html/overview.html
59,7 → 59,7
<ul> |
<li><b>Core:</b> |
<ul> |
<li>Instructions can't be executed from RAM.</li> |
<li>Instructions can't be executed from the data memory.</li> |
</ul> |
</li> |
<br /> |
/doc/html/core.html
55,13 → 55,13
|
The following diagram shows the openMSP430 design structure: |
<br /><br /> |
<img src="getimg.php?1246433777" alt="CPU Structure" title="CPU Structure" /> |
<img src="getimg.php?1261910416" alt="CPU Structure" title="CPU Structure" /> |
<br /> |
<ul> |
<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li> |
<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li> |
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li> |
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for ROM and RAM access.</li> |
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for instruction and data memory access.</li> |
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li> |
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li> |
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li> |
73,7 → 73,7
The known core limitations are the following: |
<br /> |
<ul> |
<li>Instructions can't be executed from RAM.</li> |
<li>Instructions can't be executed from the data memory.</li> |
<li>SCG0 is not implemented (turns off DCO).</li> |
<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li> |
</ul> |
/doc/html/files_directory_description.html
7,10 → 7,15
<a name="TOC"></a> |
<h3>Table of content</h3> |
<ul> |
<li><a href="#1. Introduction"> 1. Introduction</a></li> |
<li><a href="#2. Directory structure: openMSP430 core"> 2. Directory structure: openMSP430 core</a></li> |
<li><a href="#3. Directory structure: FGPA projects"> 3. Directory structure: FGPA projects</a></li> |
<li><a href="#4. Directory structure: Software Development Tools"> 4. Directory structure: Software Development Tools</a></li> |
<li><a href="#1. Introduction"> 1. Introduction</a></li> |
<li><a href="#2. Directory structure: openMSP430 core"> 2. Directory structure: openMSP430 core</a></li> |
<li><a href="#3. Directory structure: FGPA projects"> 3. Directory structure: FGPA projects</a> |
<ul> |
<li><a href="#3.1 Xilinx Spartan 3 example"> 3.1 Xilinx Spartan 3 example</a></li> |
<li><a href="#3.2 Altera Cyclone II example"> 3.2 Altera Cyclone II example</a></li> |
</ul> |
</li> |
<li><a href="#4. Directory structure: Software Development Tools">4. Directory structure: Software Development Tools</a></li> |
</ul> |
|
<a name="1. Introduction"></a> |
34,8 → 39,8
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr> |
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="19" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="18" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition, Debug Interface configuration)</i></td></tr> |
<tr><td rowspan="20" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="19" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition, Debug Interface configuration)</i></td></tr> |
<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr> |
<tr><td colspan="2">frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr> |
<tr><td colspan="2">execution_unit.v</td> <td><i>Execution unit</i></td></tr> |
48,6 → 53,7
<tr><td colspan="2">dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr> |
<tr><td colspan="2">dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr> |
<tr><td colspan="2">dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr> |
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale defintion for simulation.</i></td></tr> |
<tr><td colspan="2"><b>periph</b></td> <td><i><b>Peripherals directory</b></i></td></tr> |
<tr><td rowspan="4"><font color="white">abcd</font></td> <td>gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr> |
<tr><td colspan="1">timerA.v</td> <td><i>Timer A</i></td></tr> |
102,10 → 108,13
<div style="text-align: right"><a href="#TOC">Top</a></div> |
<h1>3. Directory structure: FGPA projects</h1> |
|
<a name="3.1 Xilinx Spartan 3 example"></a> |
<h2>3.1 Xilinx Spartan 3 example</h2> |
|
<table border="1"> |
<tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr> |
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>diligent_s3board</b></td> <td><i><b>FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr> |
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr> |
<tr><td rowspan="51" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr> |
117,10 → 126,10
<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr> |
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition)</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr> |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr> |
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr> |
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr> |
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr> |
<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">ram_8x512_hi.*</td> <td><i>512 Byte RAM (upper byte)</i></td></tr> |
<tr><td colspan="2">ram_8x512_lo.*</td> <td><i>512 Byte RAM (lower byte)</i></td></tr> |
147,14 → 156,72
<tr><td colspan="3">7seg.c</td> <td><i></i></td></tr> |
<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr> |
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream</td> <td><i>Run Xilinx ISE synthesis</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga_top.ucf</td> <td><i>UCF file</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga_top.v</td> <td><i>RTL file list to be synthesized</i></td></tr> |
<tr><td colspan="3">load_rom</td> <td><i>Update bitstream's ROM with a given software ELF file</i></td></tr> |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i></td></tr> |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr> |
<tr><td colspan="3">create_bitstream.bat</td> <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr> |
<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr> |
<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's ROM with a given software ELF file in a Linux environment</i></td></tr> |
<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's ROM with a given software ELF file in a Windows environment</i></td></tr> |
<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's ROM update</i></td></tr> |
</table> |
<br /> |
|
<a name="3.2 Altera Cyclone II example"></a> |
<div style="text-align: right"><a href="#TOC">Top</a></div> |
<h2>3.2 Altera Cyclone II example</h2> |
|
|
<table border="1"> |
<tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr> |
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr> |
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr> |
<tr><td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr> |
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr> |
<tr><td colspan="3">altsyncram.v</td> <td><i>Altera verilog model of the altsyncram module.</i></td></tr> |
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr> |
<tr><td colspan="4">DE1_Reference_Manual.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr> |
<tr><td colspan="4">DE1_User_Guide.pdf</td> <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr> |
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i></td></tr> |
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr> |
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr> |
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr> |
<tr><td colspan="3">ext_de1_sram.v</td> <td><i>Interface with altera DE1's external async SRAM (256kwords x 16bits)</i></td></tr> |
<tr><td colspan="3">ram16x512.v</td> <td><i>Single port RAM generated with the megafunction wizard</i></td></tr> |
<tr><td colspan="3">rom16x2048.v</td> <td><i>Single port ROM generated with the megafunction wizard</i></td></tr> |
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr> |
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr> |
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr> |
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr> |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr> |
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog ROM memory file generation</i></td></tr> |
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr> |
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr> |
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr> |
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble ROM content of the latest simulation</i></td></tr> |
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr> |
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr> |
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr> |
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in ROM</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td> <td><i>Specific binaries required for software development.</i></td></tr> |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td> <td><i>This prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr> |
<tr><td colspan="3">mifwrite.exe</td> <td><i>Windows executable.</i></td></tr> |
<tr><td colspan="3">mifwrite</td> <td><i>Linux executable.</i></td></tr> |
<tr><td colspan="4"><b>memledtest</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr> |
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>altera</b></td> <td><i></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">main.qsf</td> <td><i>Global Assignments file</i></td></tr> |
<tr><td colspan="3">main.sof</td> <td><i>SOF file</i></td></tr> |
<tr><td colspan="3">OpenMSP430_fpga.qpf</td> <td><i>Quartus II project file</i></td></tr> |
<tr><td colspan="3">openMSP430_fpga_top.v</td> <td><i>RTL file list to be synthesized</i></td></tr> |
</table> |
<br /> |
<a name="4. Directory structure: Software Development Tools"></a> |
<div style="text-align: right"><a href="#TOC">Top</a></div> |
<h1>4. Directory structure: Software Development Tools</h1> |
/doc/openMSP430.odt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream