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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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    /openmsp430/trunk
    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/tools/bin/openmsp430-gdbproxy.tcl
160,8 → 160,8
# Display info
puts "INFO: Sucessfully connected with the openMSP430 target."
set sizes [GetCPU_ID_SIZE]
puts "INFO: ROM Size - [lindex $sizes 0] B"
puts "INFO: RAM Size - [lindex $sizes 1] B"
puts "INFO: Program Memory Size - [lindex $sizes 0] B"
puts "INFO: Data Memory Size - [lindex $sizes 1] B"
puts "INFO: $hw_break(num) Hardware Brea/Watch-point unit(s) detected"
puts ""
 
/tools/bin/openmsp430-minidebug.tcl
165,7 → 165,7
# Reset & Stop CPU
ExecutePOR_Halt
 
# Load ROM
# Load Program Memory
set StartAddr [format "0x%04x" [expr 0x10000-$byte_size]]
.load.fb.l configure -text "Load..." -fg yellow
update
378,11 → 378,11
pack .cpu.l4 -side right
label .cpu.l5 -text "--" -anchor w
pack .cpu.l5 -side right
label .cpu.l6 -text "B; RAM size:" -anchor w
label .cpu.l6 -text "B; Data Memory size:" -anchor w
pack .cpu.l6 -side right
label .cpu.l7 -text "--" -anchor w
pack .cpu.l7 -side right
label .cpu.l8 -text "(ROM size:" -anchor w
label .cpu.l8 -text "(Program Memory size:" -anchor w
pack .cpu.l8 -side right
 
 
/tools/bin/openmsp430-loader.tcl
143,18 → 143,18
ExecutePOR_Halt
puts "done"
set sizes [GetCPU_ID_SIZE]
puts "Connected: target device has [lindex $sizes 0]B ROM and [lindex $sizes 1]B RAM"
puts "Connected: target device has [lindex $sizes 0]B Program Memory and [lindex $sizes 1]B Data Memory"
puts ""
 
# Load ROM
# Load Program Memory
set StartAddr [format "0x%04x" [expr 0x10000-$byte_size]]
puts -nonewline "Load ROM... "
puts -nonewline "Load Program Memory... "
flush stdout
WriteMemQuick $StartAddr $DataArray
puts "done"
 
# Check Data
puts -nonewline "Verify ROM... "
puts -nonewline "Verify Program Memory... "
flush stdout
if {[VerifyMem $StartAddr $DataArray]} {
puts "done"
/doc/openMSP430.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/html/software_development_tools.html
114,10 → 114,11
<h2>5.2 CPU selection for msp430-gcc</h2>
 
The following table aims to help selecting the proper <b>-mmcu</b> option for the <b>msp430-gcc</b> call.<br />
Note that only the ROM size should imperatively match the openMSP430 configuration.
Note that the program memory size should imperatively match the openMSP430 configuration.
<br /><br />
<table align="center" border="1">
<tr align="center"><td colspan="3"><b>ROM Size: 1 kB</b></td></tr>
<tr align="center"><td><b>-mmcu option</b></td><td><b>&nbsp;&nbsp;Program&nbsp;&nbsp;<br />Memory</b></td><td><b>Data<br />&nbsp;&nbsp;&nbsp;Memory&nbsp;&nbsp;&nbsp;</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 1 kB</i></b></td></tr>
<tr align="center"><td>msp430x110 </td><td> 1 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x1101 </td><td> 1 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2001 </td><td> 1 kB</td><td> 128 B</td></tr>
124,7 → 125,7
<tr align="center"><td>msp430x2002 </td><td> 1 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2003 </td><td> 1 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2101 </td><td> 1 kB</td><td> 128 B</td></tr>
<tr align="center"><td colspan="3"><b>ROM Size: 2 kB</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 2 kB</i></b></td></tr>
<tr align="center"><td>msp430x1111 </td><td> 2 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2011 </td><td> 2 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2012 </td><td> 2 kB</td><td> 128 B</td></tr>
132,7 → 133,7
<tr align="center"><td>msp430x2111 </td><td> 2 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x2112 </td><td> 2 kB</td><td> 128 B</td></tr>
<tr align="center"><td>msp430x311 </td><td> 2 kB</td><td> 128 B</td></tr>
<tr align="center"><td colspan="3"><b>ROM Size: 4 kB</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 4 kB</i></b></td></tr>
<tr align="center"><td>msp430x112 </td><td> 4 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x1121 </td><td> 4 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x1122 </td><td> 4 kB</td><td> 256 B</td></tr>
142,7 → 143,7
<tr align="center"><td>msp430x2121 </td><td> 4 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x312 </td><td> 4 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x412 </td><td> 4 kB</td><td> 256 B</td></tr>
<tr align="center"><td colspan="3"><b>ROM Size: 8 kB</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 8 kB</i></b></td></tr>
<tr align="center"><td>msp430x123 </td><td> 8 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x133 </td><td> 8 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x313 </td><td> 8 kB</td><td> 256 B</td></tr>
161,7 → 162,7
<tr align="center"><td>msp430x2234 </td><td> 8 kB</td><td> 512 B</td></tr>
<tr align="center"><td>msp430x233 </td><td> 8 kB</td><td> 1024 B</td></tr>
<tr align="center"><td>msp430x2330 </td><td> 8 kB</td><td> 1024 B</td></tr>
<tr align="center"><td colspan="3"><b>ROM Size: 16 kB</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 16 kB</i></b></td></tr>
<tr align="center"><td>msp430x4250 </td><td>16 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430xG4250</td><td>16 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x135 </td><td>16 kB</td><td> 512 B</td></tr>
180,7 → 181,7
<tr align="center"><td>msp430x4351 </td><td>16 kB</td><td> 512 B</td></tr>
<tr align="center"><td>msp430x235 </td><td>16 kB</td><td> 2048 B</td></tr>
<tr align="center"><td>msp430x2350 </td><td>16 kB</td><td> 2048 B</td></tr>
<tr align="center"><td colspan="3"><b>ROM Size: 32 kB</b></td></tr>
<tr align="center"><td colspan="3"><b><i>Program Memory Size: 32 kB</i></b></td></tr>
<tr align="center"><td>msp430x4270 </td><td>32 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430xG4270</td><td>32 kB</td><td> 256 B</td></tr>
<tr align="center"><td>msp430x147 </td><td>32 kB</td><td> 1024 B</td></tr>
/doc/html/images/cpu_structure.odg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/html/images/cpu_structure.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/html/serial_debug_interface.html
93,8 → 93,8
<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_LO</a></font></td>
<td><font size="-1">0x00</font></td>
<td colspan="8"><font size="-5">CPU_ID[7:0]</font></td>
<td colspan="4"><font size="-5">ROM_AWIDTH</font></td>
<td colspan="4"><font size="-5">RAM_AWIDTH</font></td>
<td colspan="4"><font size="-5">PMEM_AWIDTH</font></td>
<td colspan="4"><font size="-5">DMEM_AWIDTH</font></td>
</tr>
<tr align="center">
<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_HI</a></font></td>
278,7 → 278,7
 
<a name="2.2.1 CPU_ID"></a>
<h3>2.2.1 CPU_ID</h3>
This 32 bit read-only register holds the ID of the implemented openMSP430 as well as the RAM and ROM size information.
This 32 bit read-only register holds the ID of the implemented openMSP430 as well as the program and data memory size information.
<br /><br />
<table border="1">
<tr align="center">
300,8 → 300,8
<td><font size="-1">CPU_ID_LO</font></td>
<td><font size="-1">0x00</font></td>
<td colspan="8"><font size="-5">CPU_ID[7:0]</font></td>
<td colspan="4"><font size="-5">ROM_AWIDTH</font></td>
<td colspan="4"><font size="-5">RAM_AWIDTH</font></td>
<td colspan="4"><font size="-5">PMEM_AWIDTH</font></td>
<td colspan="4"><font size="-5">DMEM_AWIDTH</font></td>
</tr>
<tr align="center">
<td><font size="-1">CPU_ID_HI</font></td>
316,12 → 316,12
<td>: Set by default to 0x4D5350 (ascii code for "MSP")</td>
</tr>
<tr>
<td>&nbsp;</td><td valign="top"><li><b>ROM_AWIDTH</b></li></td>
<td>: Program memory address width for the current implementation. The ROM size is then equal to 2<sup><font size="-3">ROM_AWIDTH</font></sup></td>
<td>&nbsp;</td><td valign="top"><li><b>PMEM_AWIDTH</b></li></td>
<td>: Program memory address width for the current implementation. The ROM or RAM size is then equal to 2<sup><font size="-3">PMEM_AWIDTH</font></sup></td>
</tr>
<tr>
<td>&nbsp;</td><td valign="top"><li><b>RAM_AWIDTH</b></li></td>
<td>: Data memory address width for the current implementation. The RAM size is then equal to 2<sup><font size="-3">RAM_AWIDTH</font></sup></td>
<td>&nbsp;</td><td valign="top"><li><b>DMEM_AWIDTH</b></li></td>
<td>: Data memory address width for the current implementation. The RAM size is then equal to 2<sup><font size="-3">DMEM_AWIDTH</font></sup></td>
</tr>
</table>
 
/doc/html/overview.html
28,8 → 28,7
</tr>
</table>
<h3>Documentation</h3>
The online documentation is available as <a href="getdoc.php?1261950709" title="openMSP430 PDF Documentation (R1.2)">pdf</a>
 
The online documentation is available as <a href="getdoc.php?1262114052" title="openMSP430 PDF Doc (R 1.3))">pdf</a>
<h1>Features & Limitations</h1>
<h2>Features</h2>
<ul>
39,7 → 38,7
<li>All addressing modes are supported.</li>
<li>IRQ and NMI support.</li>
<li>Power saving modes functionality is supported.</li>
<li>Configurable ROM and RAM size.</li>
<li>Configurable memory size for both program and data.</li>
<li>Serial Debug Interface (Nexus class 3).</li>
<li>FPGA friendly (single clock domain, no clock gate).</li>
<li>Small size (uses ~43% of a XC3S200 Xilinx Spartan-3).</li>
/doc/html/core.html
38,8 → 38,8
<br /><br />
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
<br /><br />
This IP doesn't contain the program and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
However the core is fully configurable in regard to the supported RAM and ROM sizes.
This IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
<br /><br />
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
<br /><br />
55,13 → 55,13
 
The following diagram shows the openMSP430 design structure:
<br /><br />
<img src="getimg.php?1261910416" width="100%" height="100%" alt="CPU Structure" title="CPU Structure" />
<img src="getimg.php?1262105776" width="100%" height="100%" alt="CPU Structure" title="CPU Structure" />
<br />
<ul>
<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for instruction and data memory access.</li>
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
82,7 → 82,7
<h3>2.1.3 Configuration</h3>
 
It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
Two parameters can be adjusted by the user in order to define the ROM and RAM sizes:
Two parameters can be adjusted by the user in order to define the program and data memory sizes:
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
91,27 → 91,35
<td width="15"></td>
<td>
<code>
// ROM Size
<br />// 9 -> 1kB
<br />// 10 -> 2kB
<br />// 11 -> 4kB
<br />// 12 -> 8kB
<br />// 13 -> 16kB
<br />`define ROM_AWIDTH 10
// Program Memory Size
<br />// 9 -> 1 kB
<br />// 10 -> 2 kB
<br />// 11 -> 4 kB
<br />// 12 -> 8 kB
<br />// 13 -> 16 kB
<br />// 14 -> 32 kB
<br />`define PMEM_AWIDTH 10
<br />
<br />// RAM Size
<br />// Data Memory Size
<br />// 6 -> 128 B
<br />// 7 -> 256 B
<br />// 8 -> 512 B
<br />// 9 -> 1 kB
<br />// 10 -> 2 kB
<br />`define RAM_AWIDTH 6
<br />// 11 -> 4 kB
<br />// 12 -> 8 kB
<br />// 13 -> 16 kB
<br />// 14 -> 32 kB
<br />`define DMEM_AWIDTH 6
</code>
</td>
</tr>
</table>
<br /><br />
The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included:
<b>Note:</b> Program and data memories <b>SHOULD NOT</b> be both set to 32 kB
<br /><br /><br />
The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included.
 
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
129,7 → 137,7
<br />
<br />// Debug interface selection
<br />// `define DBG_UART -> Enable UART (8N1) debug interface
<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
<br />//
<br />`define DBG_UART
<br />//`define DBG_JTAG
149,6 → 157,8
</tr>
</table>
<br /><br />
<b>Note:</b> Since the hardware breakpoint units are relatively big, it is recommended to include as many as you plan to use. These units are particularly useful if your instruction memory is a ROM (i.e. when you can't use software breakpoints) or if you want to be able to stop the CPU whenever some particular data addresses are accessed.
<br /><br /><br />
All remaining defines located in this file are system constants and should not be edited.
 
<a name="2.1.4 Pinout"></a>
177,18 → 187,18
<tr> <td> per_dout </td> <td> Input </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Output </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Output </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>RAM interface</i></b> </td></tr>
<tr> <td> ram_addr </td> <td> Output </td> <td> `RAM_AWIDTH<sup>1</sup> </td> <td> RAM address </td> </tr>
<tr> <td> ram_cen </td> <td> Output </td> <td> 1 </td> <td> RAM chip enable (low active) </td> </tr>
<tr> <td> ram_din </td> <td> Output </td> <td> 16 </td> <td> RAM data input </td> </tr>
<tr> <td> ram_dout </td> <td> Input </td> <td> 16 </td> <td> RAM data output </td> </tr>
<tr> <td> ram_wen </td> <td> Output </td> <td> 2 </td> <td> RAM write enable (low active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>ROM interface</i></b> </td></tr>
<tr> <td> rom_addr </td> <td> Output </td> <td> `ROM_AWIDTH<sup>1</sup> </td> <td> ROM address </td> </tr>
<tr> <td> rom_cen </td> <td> Output </td> <td> 1 </td> <td> ROM chip enable (low active) </td> </tr>
<tr> <td> rom_din_dbg </td> <td> Output </td> <td> 16 </td> <td> ROM data input --FOR DEBUG INTERFACE-- </td> </tr>
<tr> <td> rom_dout </td> <td> Input </td> <td> 16 </td> <td> ROM data output </td> </tr>
<tr> <td> rom_wen_dbg </td> <td> Output </td> <td> 2 </td> <td> ROM write enable (low active) --FOR DEBUG INTERFACE--</td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
<tr> <td> dmem_addr </td> <td> Output </td> <td> `DMEM_AWIDTH<sup>1</sup> </td> <td> Data Memory address </td> </tr>
<tr> <td> dmem_cen </td> <td> Output </td> <td> 1 </td> <td> Data Memory chip enable (low active) </td> </tr>
<tr> <td> dmem_din </td> <td> Output </td> <td> 16 </td> <td> Data Memory data input </td> </tr>
<tr> <td> dmem_dout </td> <td> Input </td> <td> 16 </td> <td> Data Memory data output </td> </tr>
<tr> <td> dmem_wen </td> <td> Output </td> <td> 2 </td> <td> Data Memory write enable (low active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
<tr> <td> pmem_addr </td> <td> Output </td> <td> `PMEM_AWIDTH<sup>1</sup> </td> <td> Program Memory address </td> </tr>
<tr> <td> pmem_cen </td> <td> Output </td> <td> 1 </td> <td> Program Memory chip enable (low active) </td> </tr>
<tr> <td> pmem_din </td> <td> Output </td> <td> 16 </td> <td> Program Memory data input (optional<sup>2</sup>) </td> </tr>
<tr> <td> pmem_dout </td> <td> Input </td> <td> 16 </td> <td> Program Memory data output </td> </tr>
<tr> <td> pmem_wen </td> <td> Output </td> <td> 2 </td> <td> Program Memory write enable (low active) (optional<sup>2</sup>)</td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
<tr> <td> dbg_freeze </td> <td> Output </td> <td> 1 </td> <td> Freeze peripherals </td> </tr>
<tr> <td> dbg_uart_txd </td> <td> Output </td> <td> 1 </td> <td> Debug interface: UART TXD </td> </tr>
195,7 → 205,8
<tr> <td> dbg_uart_rxd </td> <td> Input </td> <td> 1 </td> <td> Debug interface: UART RXD </td> </tr>
</table>
<br />
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
<sup>2</sup>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
<br /><br />
 
<a name="2.1.5 Instruction Cycles and Lengths"></a>
/doc/html/files_directory_description.html
39,24 → 39,25
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
<tr><td rowspan="20" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr>
<tr><td rowspan="19" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (ROM and RAM size definition, Debug Interface configuration)</i></td></tr>
<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr>
<tr><td rowspan="20" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration)</i></td></tr>
<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
<tr><td colspan="2">frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
<tr><td colspan="2">execution_unit.v</td> <td><i>Execution unit</i></td></tr>
<tr><td colspan="2">alu.v</td> <td><i>ALU</i></td></tr>
<tr><td colspan="2">register_file.v</td> <td><i>Register file</i></td></tr>
<tr><td colspan="2">mem_backbone.v</td> <td><i>Memory backbone</i></td></tr>
<tr><td colspan="2">clock_module.v</td> <td><i>Basic Clock Module</i></td></tr>
<tr><td colspan="2">sfr.v</td> <td><i>Special function registers</i></td></tr>
<tr><td colspan="2">watchdog.v</td> <td><i>Watchdog Timer</i></td></tr>
<tr><td colspan="2">dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr>
<tr><td colspan="2">dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
<tr><td colspan="2">dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr>
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale defintion for simulation.</i></td></tr>
<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
<tr><td colspan="2">omsp_alu.v</td> <td><i>ALU</i></td></tr>
<tr><td colspan="2">omsp_register_file.v</td> <td><i>Register file</i></td></tr>
<tr><td colspan="2">omsp_mem_backbone.v</td> <td><i>Memory backbone</i></td></tr>
<tr><td colspan="2">omsp_clock_module.v</td> <td><i>Basic Clock Module</i></td></tr>
<tr><td colspan="2">omsp_sfr.v</td> <td><i>Special function registers</i></td></tr>
<tr><td colspan="2">omsp_watchdog.v</td> <td><i>Watchdog Timer</i></td></tr>
<tr><td colspan="2">omsp_dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr>
<tr><td colspan="2">omsp_dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
<tr><td colspan="2">omsp_dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr>
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr>
<tr><td colspan="2"><b>periph</b></td> <td><i><b>Peripherals directory</b></i></td></tr>
<tr><td rowspan="4"><font color="white">abcd</font></td> <td>gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr>
<tr><td colspan="1">timerA.v</td> <td><i>Timer A</i></td></tr>
<tr><td rowspan="4"><font color="white">abcd</font></td> <td>omsp_gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr>
<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr>
<tr><td colspan="1">template_periph_16b.v</td> <td><i>Verilog template for 16 bit peripherals</i></td></tr>
<tr><td colspan="1">template_periph_8b.v</td> <td><i>Verilog template for 8 bit peripherals</i></td></tr>
<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
64,13 → 65,13
<tr><td rowspan="33" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td> <td><i>Main simulation script</i></td></tr>
<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr>
<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog ROM memory file generation</i></td></tr>
<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
<tr><td colspan="1">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
<tr><td colspan="1">template.def</td> <td><i>ASM linker definition file template</i></td></tr>
<tr><td colspan="2"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">run</td> <td><i>Run single simulation of a given vector</i></td></tr>
<tr><td colspan="1">run_all</td> <td><i>Run regression of all vectors</i></td></tr>
<tr><td colspan="1">run_disassemble</td> <td><i>Disassemble ROM content of the latest simulation</i></td></tr>
<tr><td colspan="1">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
<tr><td colspan="1">load_waveform.sav</td> <td><i>SAV file for gtkWave</i></td></tr>
<tr><td colspan="2"><b>src</b></td> <td><i><b>RTL simulation vectors sources</b></i></td></tr>
<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
133,21 → 134,21
<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">ram_8x512_hi.*</td> <td><i>512 Byte RAM (upper byte)</i></td></tr>
<tr><td colspan="2">ram_8x512_lo.*</td> <td><i>512 Byte RAM (lower byte)</i></td></tr>
<tr><td colspan="2">rom_8x2k_hi.*</td> <td><i>2 kByte ROM (upper byte)</i></td></tr>
<tr><td colspan="2">rom_8x2k_lo.*</td> <td><i>2 kByte ROM (lower byte)</i></td></tr>
<tr><td colspan="2">ram_8x2k_hi.*</td> <td><i>2 kByte RAM (upper byte)</i></td></tr>
<tr><td colspan="2">ram_8x2k_lo.*</td> <td><i>2 kByte RAM (lower byte)</i></td></tr>
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr>
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog ROM memory file generation</i></td></tr>
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr>
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble ROM content of the latest simulation</i></td></tr>
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in ROM</b></i></td></tr>
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><i></i></td></tr>
<tr><td colspan="3">hardware.h</td> <td><i></i></td></tr>
162,9 → 163,9
<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr>
<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr>
<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's ROM with a given software ELF file in a Linux environment</i></td></tr>
<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's ROM with a given software ELF file in a Windows environment</i></td></tr>
<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's ROM update</i></td></tr>
<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
</table>
<br />
 
200,15 → 201,15
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr>
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog ROM memory file generation</i></td></tr>
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr>
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble ROM content of the latest simulation</i></td></tr>
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in ROM</b></i></td></tr>
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td> <td><i>Specific binaries required for software development.</i></td></tr>
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td> <td><i>This prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr>
<tr><td colspan="3">mifwrite.exe</td> <td><i>Windows executable.</i></td></tr>
/doc/openMSP430.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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