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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk
    from Rev 78 to Rev 79
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  •

Rev 78 → Rev 79

/core/rtl/verilog/periph/omsp_gpio.v
264,11 → 264,20
 
// P1IN Register
//---------------
reg [7:0] p1in_s;
reg [7:0] p1in;
 
always @ (posedge mclk or posedge puc)
if (puc) p1in <= 8'h00;
else p1in <= p1_din & P1_EN_MSK;
if (puc)
begin
p1in_s <= 8'h00;
p1in <= 8'h00;
end
else
begin
p1in_s <= p1_din & P1_EN_MSK;
p1in <= p1in_s & P1_EN_MSK;
end
 
 
// P1OUT Register
352,11 → 361,20
// P2IN Register
//---------------
reg [7:0] p2in_s;
reg [7:0] p2in;
 
always @ (posedge mclk or posedge puc)
if (puc) p2in <= 8'h00;
else p2in <= p2_din & P2_EN_MSK;
if (puc)
begin
p2in_s <= 8'h00;
p2in <= 8'h00;
end
else
begin
p2in_s <= p2_din & P2_EN_MSK;
p2in <= p2in_s & P2_EN_MSK;
end
 
 
// P2OUT Register
441,11 → 459,20
// P3IN Register
//---------------
reg [7:0] p3in_s;
reg [7:0] p3in;
 
always @ (posedge mclk or posedge puc)
if (puc) p3in <= 8'h00;
else p3in <= p3_din & P3_EN_MSK;
if (puc)
begin
p3in_s <= 8'h00;
p3in <= 8'h00;
end
else
begin
p3in_s <= p3_din & P3_EN_MSK;
p3in <= p3in_s & P3_EN_MSK;
end
 
 
// P3OUT Register
492,11 → 519,20
// P4IN Register
//---------------
reg [7:0] p4in_s;
reg [7:0] p4in;
 
always @ (posedge mclk or posedge puc)
if (puc) p4in <= 8'h00;
else p4in <= p4_din & P4_EN_MSK;
if (puc)
begin
p4in_s <= 8'h00;
p4in <= 8'h00;
end
else
begin
p4in_s <= p4_din & P4_EN_MSK;
p4in <= p4in_s & P4_EN_MSK;
end
 
 
// P4OUT Register
543,11 → 579,20
// P5IN Register
//---------------
reg [7:0] p5in_s;
reg [7:0] p5in;
 
always @ (posedge mclk or posedge puc)
if (puc) p5in <= 8'h00;
else p5in <= p5_din & P5_EN_MSK;
if (puc)
begin
p5in_s <= 8'h00;
p5in <= 8'h00;
end
else
begin
p5in_s <= p5_din & P5_EN_MSK;
p5in <= p5in_s & P5_EN_MSK;
end
 
 
// P5OUT Register
594,11 → 639,20
// P6IN Register
//---------------
reg [7:0] p6in_s;
reg [7:0] p6in;
 
always @ (posedge mclk or posedge puc)
if (puc) p6in <= 8'h00;
else p6in <= p6_din & P6_EN_MSK;
if (puc)
begin
p6in_s <= 8'h00;
p6in <= 8'h00;
end
else
begin
p6in_s <= p6_din & P6_EN_MSK;
p6in <= p6in_s & P6_EN_MSK;
end
 
 
// P6OUT Register
/core/sim/rtl_sim/src/gpio_rdwr.s43
290,6 → 290,7
/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0200, r15 ;# Test Input path
nop
p1_din_loop:
mov.b &P1IN, 0(r15)
inc r15
332,6 → 333,7
/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0210, r15 ;# Test Input path
nop
p2_din_loop:
mov.b &P2IN, 0(r15)
inc r15
374,6 → 376,7
/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0220, r15 ;# Test Input path
nop
p3_din_loop:
mov.b &P3IN, 0(r15)
inc r15
416,6 → 419,7
/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0230, r15 ;# Test Input path
nop
p4_din_loop:
mov.b &P4IN, 0(r15)
inc r15
458,6 → 462,7
/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0240, r15 ;# Test Input path
nop
p5_din_loop:
mov.b &P5IN, 0(r15)
inc r15
500,6 → 505,7
/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
mov #0x0250, r15 ;# Test Input path
nop
p6_din_loop:
mov.b &P6IN, 0(r15)
inc r15
/core/sim/rtl_sim/src/op_modes.v
161,8 → 161,8
@(negedge mclk);
inst_cnt = 0;
repeat (80) @(negedge mclk);
if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
 
if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
@(r1==16'h0250);
repeat (3) @(negedge mclk);
inst_cnt = 0;
176,7 → 176,7
@(negedge mclk);
inst_cnt = 0;
repeat (80) @(negedge mclk);
if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
 
@(r15==16'h3003);
@(negedge mclk);
/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v
264,11 → 264,20
 
// P1IN Register
//---------------
reg [7:0] p1in_s;
reg [7:0] p1in;
 
always @ (posedge mclk or posedge puc)
if (puc) p1in <= 8'h00;
else p1in <= p1_din & P1_EN_MSK;
if (puc)
begin
p1in_s <= 8'h00;
p1in <= 8'h00;
end
else
begin
p1in_s <= p1_din & P1_EN_MSK;
p1in <= p1in_s & P1_EN_MSK;
end
 
 
// P1OUT Register
352,11 → 361,20
// P2IN Register
//---------------
reg [7:0] p2in_s;
reg [7:0] p2in;
 
always @ (posedge mclk or posedge puc)
if (puc) p2in <= 8'h00;
else p2in <= p2_din & P2_EN_MSK;
if (puc)
begin
p2in_s <= 8'h00;
p2in <= 8'h00;
end
else
begin
p2in_s <= p2_din & P2_EN_MSK;
p2in <= p2in_s & P2_EN_MSK;
end
 
 
// P2OUT Register
441,11 → 459,20
// P3IN Register
//---------------
reg [7:0] p3in_s;
reg [7:0] p3in;
 
always @ (posedge mclk or posedge puc)
if (puc) p3in <= 8'h00;
else p3in <= p3_din & P3_EN_MSK;
if (puc)
begin
p3in_s <= 8'h00;
p3in <= 8'h00;
end
else
begin
p3in_s <= p3_din & P3_EN_MSK;
p3in <= p3in_s & P3_EN_MSK;
end
 
 
// P3OUT Register
492,11 → 519,20
// P4IN Register
//---------------
reg [7:0] p4in_s;
reg [7:0] p4in;
 
always @ (posedge mclk or posedge puc)
if (puc) p4in <= 8'h00;
else p4in <= p4_din & P4_EN_MSK;
if (puc)
begin
p4in_s <= 8'h00;
p4in <= 8'h00;
end
else
begin
p4in_s <= p4_din & P4_EN_MSK;
p4in <= p4in_s & P4_EN_MSK;
end
 
 
// P4OUT Register
543,11 → 579,20
// P5IN Register
//---------------
reg [7:0] p5in_s;
reg [7:0] p5in;
 
always @ (posedge mclk or posedge puc)
if (puc) p5in <= 8'h00;
else p5in <= p5_din & P5_EN_MSK;
if (puc)
begin
p5in_s <= 8'h00;
p5in <= 8'h00;
end
else
begin
p5in_s <= p5_din & P5_EN_MSK;
p5in <= p5in_s & P5_EN_MSK;
end
 
 
// P5OUT Register
594,11 → 639,20
// P6IN Register
//---------------
reg [7:0] p6in_s;
reg [7:0] p6in;
 
always @ (posedge mclk or posedge puc)
if (puc) p6in <= 8'h00;
else p6in <= p6_din & P6_EN_MSK;
if (puc)
begin
p6in_s <= 8'h00;
p6in <= 8'h00;
end
else
begin
p6in_s <= p6_din & P6_EN_MSK;
p6in <= p6in_s & P6_EN_MSK;
end
 
 
// P6OUT Register
/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v
264,11 → 264,20
 
// P1IN Register
//---------------
reg [7:0] p1in_s;
reg [7:0] p1in;
 
always @ (posedge mclk or posedge puc)
if (puc) p1in <= 8'h00;
else p1in <= p1_din & P1_EN_MSK;
if (puc)
begin
p1in_s <= 8'h00;
p1in <= 8'h00;
end
else
begin
p1in_s <= p1_din & P1_EN_MSK;
p1in <= p1in_s & P1_EN_MSK;
end
 
 
// P1OUT Register
352,11 → 361,20
// P2IN Register
//---------------
reg [7:0] p2in_s;
reg [7:0] p2in;
 
always @ (posedge mclk or posedge puc)
if (puc) p2in <= 8'h00;
else p2in <= p2_din & P2_EN_MSK;
if (puc)
begin
p2in_s <= 8'h00;
p2in <= 8'h00;
end
else
begin
p2in_s <= p2_din & P2_EN_MSK;
p2in <= p2in_s & P2_EN_MSK;
end
 
 
// P2OUT Register
441,11 → 459,20
// P3IN Register
//---------------
reg [7:0] p3in_s;
reg [7:0] p3in;
 
always @ (posedge mclk or posedge puc)
if (puc) p3in <= 8'h00;
else p3in <= p3_din & P3_EN_MSK;
if (puc)
begin
p3in_s <= 8'h00;
p3in <= 8'h00;
end
else
begin
p3in_s <= p3_din & P3_EN_MSK;
p3in <= p3in_s & P3_EN_MSK;
end
 
 
// P3OUT Register
492,11 → 519,20
// P4IN Register
//---------------
reg [7:0] p4in_s;
reg [7:0] p4in;
 
always @ (posedge mclk or posedge puc)
if (puc) p4in <= 8'h00;
else p4in <= p4_din & P4_EN_MSK;
if (puc)
begin
p4in_s <= 8'h00;
p4in <= 8'h00;
end
else
begin
p4in_s <= p4_din & P4_EN_MSK;
p4in <= p4in_s & P4_EN_MSK;
end
 
 
// P4OUT Register
543,11 → 579,20
// P5IN Register
//---------------
reg [7:0] p5in_s;
reg [7:0] p5in;
 
always @ (posedge mclk or posedge puc)
if (puc) p5in <= 8'h00;
else p5in <= p5_din & P5_EN_MSK;
if (puc)
begin
p5in_s <= 8'h00;
p5in <= 8'h00;
end
else
begin
p5in_s <= p5_din & P5_EN_MSK;
p5in <= p5in_s & P5_EN_MSK;
end
 
 
// P5OUT Register
594,11 → 639,20
// P6IN Register
//---------------
reg [7:0] p6in_s;
reg [7:0] p6in;
 
always @ (posedge mclk or posedge puc)
if (puc) p6in <= 8'h00;
else p6in <= p6_din & P6_EN_MSK;
if (puc)
begin
p6in_s <= 8'h00;
p6in <= 8'h00;
end
else
begin
p6in_s <= p6_din & P6_EN_MSK;
p6in <= p6in_s & P6_EN_MSK;
end
 
 
// P6OUT Register

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