OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk
    from Rev 83 to Rev 84
    ↔ Reverse comparison
  •

Rev 83 → Rev 84

/core/bench/verilog/ram.v
72,7 → 72,7
// RAM
//============
 
reg [15:0] mem [(MEM_SIZE/2)-1:0];
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
 
wire [15:0] mem_val = mem[ram_addr];
/core/rtl/verilog/omsp_dbg.v
202,7 → 202,14
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
// 2) REGISTER DECODER
//============================================================================
298,7 → 305,7
reg [3:2] cpu_stat;
 
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
616,7 → 623,7
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
 
// Freeze peripherals
/core/rtl/verilog/omsp_watchdog.v
160,8 → 160,8
else nmi_sync <= {nmi_sync[1:0], nmi};
 
// Edge detection
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie;
 
// NMI event
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v
202,7 → 202,14
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
// 2) REGISTER DECODER
//============================================================================
298,7 → 305,7
reg [3:2] cpu_stat;
 
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
616,7 → 623,7
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
 
// Freeze peripherals
/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
160,8 → 160,8
else nmi_sync <= {nmi_sync[1:0], nmi};
 
// Edge detection
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie;
 
// NMI event
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
/fpga/xilinx_diligent_s3board/software/leds/main.c
5,7 → 5,7
Delay function.
*/
void delay(unsigned int c, unsigned int d) {
int i, j;
volatile int i, j;
for (i = 0; i<c; i++) {
for (j = 0; j<d; j++) {
nop();
19,7 → 19,7
it shoule be a clock ;-)
it does not count days, but i think you'll get the idea.
*/
int irq_counter, offset;
volatile int irq_counter, offset;
 
wakeup interrupt (WDT_VECTOR) INT_Watchdog(void) {
 
/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
202,7 → 202,14
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
// 2) REGISTER DECODER
//============================================================================
298,7 → 305,7
reg [3:2] cpu_stat;
 
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
616,7 → 623,7
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
 
// Freeze peripherals
/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
160,8 → 160,8
else nmi_sync <= {nmi_sync[1:0], nmi};
 
// Edge detection
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie;
 
// NMI event
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
202,7 → 202,14
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
// 2) REGISTER DECODER
//============================================================================
298,7 → 305,7
reg [3:2] cpu_stat;
 
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
616,7 → 623,7
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
 
// Freeze peripherals
/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
160,8 → 160,8
else nmi_sync <= {nmi_sync[1:0], nmi};
 
// Edge detection
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie;
 
// NMI event
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
/fpga/actel_m1a3pl_dev_kit/software/spacewar/hardware.c
35,9 → 35,12
P1DIR |= 0x01+0x04; // P1.0=LED, P1.2=TLV5618A_cs
P1SEL = 0x08; // P1.3 = VREF
 
//BCSCTL2 = 0x00; // SMCLK divider = 1
//BCSCTL2 = 0x02; // SMCLK divider = 2
//BCSCTL2 = 0x04; // SMCLK divider = 4
BCSCTL2 = 0x06; // SMCLK divider = 8
CCTL0 = CCIE; // CCR0 interrupt enabled
CCR0 = 23500;
//CCR0 = 500;
TACTL = TASSEL_2 + MC_1; // SMCLK, upmode
_BIS_SR(GIE); // enable interrupts

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.