URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

This comparison shows the changes necessary to convert path
```
/openmsp430
```
from Rev 155 to Rev 156
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 155 → Rev 156

/trunk/fpga/xilinx_avnet_lx9microbard/README File deleted

trunk/fpga/xilinx_avnet_lx9microbard/README Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise (nonexistent) @@ -1,469 +0,0 @@ - - - -

- - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v (nonexistent) @@ -1,111 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: io_mux.v -// -// *Module Description: -// I/O mux for port function selection. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 104 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $ -//---------------------------------------------------------------------------- - -module io_mux ( - -// Function A (typically GPIO) - a_din, - a_dout, - a_dout_en, - -// Function B (Timer A, ...) - b_din, - b_dout, - b_dout_en, - -// IO Cell - io_din, - io_dout, - io_dout_en, - -// Function selection (0=A, 1=B) - sel -); - -// PARAMETERs -//============ -parameter WIDTH = 8; - -// Function A (typically GPIO) -//=============================== -output [WIDTH-1:0] a_din; -input [WIDTH-1:0] a_dout; -input [WIDTH-1:0] a_dout_en; - -// Function B (Timer A, ...) -//=============================== -output [WIDTH-1:0] b_din; -input [WIDTH-1:0] b_dout; -input [WIDTH-1:0] b_dout_en; - -// IO Cell -//=============================== -input [WIDTH-1:0] io_din; -output [WIDTH-1:0] io_dout; -output [WIDTH-1:0] io_dout_en; - -// Function selection (0=A, 1=B) -//=============================== -input [WIDTH-1:0] sel; - - -//============================================================================= -// 1) I/O FUNCTION SELECTION MUX -//============================================================================= - -function [WIDTH-1:0] mux ( - input [WIDTH-1:0] A, - input [WIDTH-1:0] B, - input [WIDTH-1:0] SEL -); - integer i; - begin - mux = {WIDTH{1'b0}}; - for (i = 0; i < WIDTH; i = i + 1) - mux[i] = sel[i] ? B[i] : A[i]; - end -endfunction - - -assign a_din = mux( io_din, {WIDTH{1'b0}}, sel); -assign b_din = mux({WIDTH{1'b0}}, io_din, sel); -assign io_dout = mux( a_dout, b_dout, sel); -assign io_dout_en = mux( a_dout_en, b_dout_en, sel); - - -endmodule // io_mux

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v (nonexistent) @@ -1,245 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_watchdog.v -// -// *Module Description: -// Watchdog Timer -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_watchdog ( - -// OUTPUTs - nmi_evt, // NMI Event - per_dout, // Peripheral data output - wdtifg_set, // Set Watchdog-timer interrupt flag - wdtpw_error, // Watchdog-timer password error - wdttmsel, // Watchdog-timer mode select - -// INPUTs - aclk_en, // ACLK enable - dbg_freeze, // Freeze Watchdog counter - mclk, // Main system clock - nmi, // Non-maskable interrupt (asynchronous) - nmie, // Non-maskable interrupt enable - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst, // Main system reset - smclk_en, // SMCLK enable - wdtie // Watchdog timer interrupt enable -); - -// OUTPUTs -//========= -output nmi_evt; // NMI Event -output [15:0] per_dout; // Peripheral data output -output wdtifg_set; // Set Watchdog-timer interrupt flag -output wdtpw_error; // Watchdog-timer password error -output wdttmsel; // Watchdog-timer mode select - -// INPUTs -//========= -input aclk_en; // ACLK enable -input dbg_freeze; // Freeze Watchdog counter -input mclk; // Main system clock -input nmi; // Non-maskable interrupt (asynchronous) -input nmie; // Non-maskable interrupt enable -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset -input smclk_en; // SMCLK enable -input wdtie; // Watchdog timer interrupt enable - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0120; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 2; - -// Register addresses offset -parameter [DEC_WD-1:0] WDTCTL = 'h0; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}}); - -// Read/Write probes -wire reg_write = |per_we & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// WDTCTL Register -//----------------- -// WDTNMI & WDTSSEL are not implemented and therefore masked - -reg [7:0] wdtctl; - -wire wdtctl_wr = reg_wr[WDTCTL]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) wdtctl <= 8'h00; - else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7; - -wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a); -wire wdttmsel = wdtctl[4]; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// Data output mux -wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}}; - -wire [15:0] per_dout = wdtctl_rd; - - -//============================================================================= -// 4) NMI GENERATION -//============================================================================= - -// Synchronization -wire nmi_s; -`ifdef SYNC_NMI -omsp_sync_cell sync_cell_nmi ( - .data_out (nmi_s), - .clk (mclk), - .data_in (nmi), - .rst (puc_rst) -); -`else -assign nmi_s = nmi; -`endif - -// Delay -reg nmi_dly; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) nmi_dly <= 1'b0; - else nmi_dly <= nmi_s; - -// Edge detection -wire nmi_re = ~nmi_dly & nmi_s & nmie; -wire nmi_fe = nmi_dly & ~nmi_s & nmie; - -// NMI event -wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re; - - -//============================================================================= -// 5) WATCHDOG TIMER -//============================================================================= - -// Watchdog clock source selection -//--------------------------------- -wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en; - - -// Watchdog 16 bit counter -//-------------------------- -reg [15:0] wdtcnt; - -wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) wdtcnt <= 16'h0000; - else if (wdtcnt_clr) wdtcnt <= 16'h0000; - else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001; - - -// Interval selection mux -//-------------------------- -reg wdtqn; - -always @(wdtctl or wdtcnt) - case(wdtctl[1:0]) - 2'b00 : wdtqn = wdtcnt[15]; - 2'b01 : wdtqn = wdtcnt[13]; - 2'b10 : wdtqn = wdtcnt[9]; - default: wdtqn = wdtcnt[6]; - endcase - - -// Watchdog event detection -//----------------------------- -reg wdtqn_dly; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) wdtqn_dly <= 1'b0; - else wdtqn_dly <= wdtqn; - -wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error; - - -endmodule // omsp_watchdog - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v (nonexistent) @@ -1,339 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_clock_module.v -// -// *Module Description: -// Basic clock module implementation. -// Since the openMSP430 mainly targets FPGA and hobby -// designers. The clock structure has been greatly -// symplified in order to ease integration. -// See online wiki for more info. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_clock_module ( - -// OUTPUTs - aclk_en, // ACLK enable - cpu_en_s, // Enable CPU code execution (synchronous) - dbg_clk, // Debug unit clock - dbg_en_s, // Debug interface enable (synchronous) - dbg_rst, // Debug unit reset - mclk, // Main system clock - per_dout, // Peripheral data output - por, // Power-on reset - puc_rst, // Main system reset - smclk_en, // SMCLK enable - -// INPUTs - cpu_en, // Enable CPU code execution (asynchronous) - dbg_cpu_reset, // Reset CPU from debug interface - dbg_en, // Debug interface enable (asynchronous) - dco_clk, // Fast oscillator (fast clock) - lfxt_clk, // Low frequency oscillator (typ 32kHz) - oscoff, // Turns off LFXT1 clock input - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - reset_n, // Reset Pin (low active, asynchronous) - scg1, // System clock generator 1. Turns off the SMCLK - wdt_reset // Watchdog-timer reset -); - -// OUTPUTs -//========= -output aclk_en; // ACLK enable -output cpu_en_s; // Enable CPU code execution (synchronous) -output dbg_clk; // Debug unit clock -output dbg_en_s; // Debug unit enable (synchronous) -output dbg_rst; // Debug unit reset -output mclk; // Main system clock -output [15:0] per_dout; // Peripheral data output -output por; // Power-on reset -output puc_rst; // Main system reset -output smclk_en; // SMCLK enable - -// INPUTs -//========= -input cpu_en; // Enable CPU code execution (asynchronous) -input dbg_cpu_reset;// Reset CPU from debug interface -input dbg_en; // Debug interface enable (asynchronous) -input dco_clk; // Fast oscillator (fast clock) -input lfxt_clk; // Low frequency oscillator (typ 32kHz) -input oscoff; // Turns off LFXT1 clock input -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input reset_n; // Reset Pin (low active, asynchronous) -input scg1; // System clock generator 1. Turns off the SMCLK -input wdt_reset; // Watchdog-timer reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0050; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 4; - -// Register addresses offset -parameter [DEC_WD-1:0] BCSCTL1 = 'h7, - BCSCTL2 = 'h8; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] BCSCTL1_D = (BASE_REG << BCSCTL1), - BCSCTL2_D = (BASE_REG << BCSCTL2); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (BCSCTL1_D & {DEC_SZ{(reg_addr==(BCSCTL1 >>1))}}) | - (BCSCTL2_D & {DEC_SZ{(reg_addr==(BCSCTL2 >>1))}}); - -// Read/Write probes -wire reg_lo_write = per_we[0] & reg_sel; -wire reg_hi_write = per_we[1] & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; -wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// BCSCTL1 Register -//-------------- -reg [7:0] bcsctl1; -wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1]; -wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) bcsctl1 <= 8'h00; - else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits - - -// BCSCTL2 Register -//-------------- -reg [7:0] bcsctl2; -wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2] : reg_lo_wr[BCSCTL2]; -wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) bcsctl2 <= 8'h00; - else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] bcsctl1_rd = {8'h00, (bcsctl1 & {8{reg_rd[BCSCTL1]}})} << (8 & {4{BCSCTL1[0]}}); -wire [15:0] bcsctl2_rd = {8'h00, (bcsctl2 & {8{reg_rd[BCSCTL2]}})} << (8 & {4{BCSCTL2[0]}}); - -wire [15:0] per_dout = bcsctl1_rd | - bcsctl2_rd; - - -//============================================================================= -// 5) CLOCK GENERATION -//============================================================================= - -// Synchronize CPU_EN signal -//--------------------------------------- -`ifdef SYNC_CPU_EN -omsp_sync_cell sync_cell_cpu_en ( - .data_out (cpu_en_s), - .clk (mclk), - .data_in (cpu_en), - .rst (por) -); -`else - assign cpu_en_s = cpu_en; -`endif - -// Synchronize LFXT_CLK & edge detection -//--------------------------------------- -wire lfxt_clk_s; - -omsp_sync_cell sync_cell_lfxt_clk ( - .data_out (lfxt_clk_s), - .clk (mclk), - .data_in (lfxt_clk), - .rst (por) -); - -reg lfxt_clk_dly; - -always @ (posedge mclk or posedge por) - if (por) lfxt_clk_dly <= 1'b0; - else lfxt_clk_dly <= lfxt_clk_s; - -wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & ~(oscoff & ~bcsctl2[`SELS]); - - -// Generate main system clock -//---------------------------- - -wire mclk = dco_clk; -wire mclk_n = !dco_clk; - - -// Generate ACLK -//---------------------------- - -reg aclk_en; -reg [2:0] aclk_div; - -wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 : - (bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] : - (bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] : - &aclk_div[2:0]); - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) aclk_en <= 1'b0; - else aclk_en <= aclk_en_nxt & cpu_en_s; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) aclk_div <= 3'h0; - else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1; - - -// Generate SMCLK -//---------------------------- - -reg smclk_en; -reg [2:0] smclk_div; - -wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1); - -wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 : - (bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] : - (bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] : - &smclk_div[2:0]); - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) smclk_en <= 1'b0; - else smclk_en <= smclk_en_nxt & cpu_en_s; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) smclk_div <= 3'h0; - else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1; - - -// Generate DBG_CLK -//---------------------------- - -assign dbg_clk = mclk; - - -//============================================================================= -// 6) RESET GENERATION -//============================================================================= - -// Generate synchronized POR -wire por_n; -wire por_reset_a = !reset_n; - -omsp_sync_cell sync_cell_por ( - .data_out (por_n), - .clk (mclk), - .data_in (1'b1), - .rst (por_reset_a) -); - -wire por = ~por_n; - - -// Generate main system reset -wire puc_rst_comb = por | wdt_reset | dbg_cpu_reset; -reg puc_rst; -always @(posedge mclk or posedge puc_rst_comb) - if (puc_rst_comb) puc_rst <= 1'b1; - else puc_rst <= 1'b0; - - -// Generate debug unit reset -`ifdef DBG_EN -wire dbg_rst_n; - - `ifdef SYNC_DBG_EN - omsp_sync_cell sync_cell_dbg_en ( - .data_out (dbg_rst_n), - .clk (mclk), - .data_in (dbg_en), - .rst (por) - ); - `else -assign dbg_rst_n = dbg_en; - `endif - -`else -wire dbg_rst_n = 1'b0; -`endif - -wire dbg_en_s = dbg_rst_n; -wire dbg_rst = ~dbg_rst_n; - - -endmodule // omsp_clock_module - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v (nonexistent) @@ -1,382 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_execution_unit.v -// -// *Module Description: -// openMSP430 Execution unit -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_execution_unit ( - -// OUTPUTs - cpuoff, // Turns off the CPU - dbg_reg_din, // Debug unit CPU register data input - gie, // General interrupt enable - mab, // Memory address bus - mb_en, // Memory bus enable - mb_wr, // Memory bus write transfer - mdb_out, // Memory data bus output - oscoff, // Turns off LFXT1 clock input - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - scg1, // System clock generator 1. Turns off the SMCLK - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_dout, // Debug unit data output - dbg_reg_wr, // Debug unit CPU register write - e_state, // Execution state - exec_done, // Execution completed - inst_ad, // Decoded Inst: destination addressing mode - inst_as, // Decoded Inst: source addressing mode - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_dest, // Decoded Inst: destination (one hot) - inst_dext, // Decoded Inst: destination extended instruction word - inst_irq_rst, // Decoded Inst: reset interrupt - inst_jmp, // Decoded Inst: Conditional jump - inst_mov, // Decoded Inst: mov instruction - inst_sext, // Decoded Inst: source extended instruction word - inst_so, // Decoded Inst: Single-operand arithmetic - inst_src, // Decoded Inst: source (one hot) - inst_type, // Decoded Instruction type - mclk, // Main system clock - mdb_in, // Memory data bus input - pc, // Program counter - pc_nxt, // Next PC value (for CALL & IRQ) - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output cpuoff; // Turns off the CPU -output [15:0] dbg_reg_din; // Debug unit CPU register data input -output gie; // General interrupt enable -output [15:0] mab; // Memory address bus -output mb_en; // Memory bus enable -output [1:0] mb_wr; // Memory bus write transfer -output [15:0] mdb_out; // Memory data bus output -output oscoff; // Turns off LFXT1 clock input -output [15:0] pc_sw; // Program counter software value -output pc_sw_wr; // Program counter software write -output scg1; // System clock generator 1. Turns off the SMCLK - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_dout; // Debug unit data output -input dbg_reg_wr; // Debug unit CPU register write -input [3:0] e_state; // Execution state -input exec_done; // Execution completed -input [7:0] inst_ad; // Decoded Inst: destination addressing mode -input [7:0] inst_as; // Decoded Inst: source addressing mode -input [11:0] inst_alu; // ALU control signals -input inst_bw; // Decoded Inst: byte width -input [15:0] inst_dest; // Decoded Inst: destination (one hot) -input [15:0] inst_dext; // Decoded Inst: destination extended instruction word -input inst_irq_rst; // Decoded Inst: reset interrupt -input [7:0] inst_jmp; // Decoded Inst: Conditional jump -input inst_mov; // Decoded Inst: mov instruction -input [15:0] inst_sext; // Decoded Inst: source extended instruction word -input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic -input [15:0] inst_src; // Decoded Inst: source (one hot) -input [2:0] inst_type; // Decoded Instruction type -input mclk; // Main system clock -input [15:0] mdb_in; // Memory data bus input -input [15:0] pc; // Program counter -input [15:0] pc_nxt; // Next PC value (for CALL & IRQ) -input puc_rst; // Main system reset - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -wire [15:0] alu_out; -wire [15:0] alu_out_add; -wire [3:0] alu_stat; -wire [3:0] alu_stat_wr; -wire [15:0] op_dst; -wire [15:0] op_src; -wire [15:0] reg_dest; -wire [15:0] reg_src; -wire [15:0] mdb_in_bw; -wire [15:0] mdb_in_val; -wire [3:0] status; - - -//============================================================================= -// 2) REGISTER FILE -//============================================================================= - -wire reg_dest_wr = ((e_state==`E_EXEC) & ( - (inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) | - (inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) | - inst_type[`INST_JMP])) | dbg_reg_wr; - -wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) | - ((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] & - ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) | - inst_so[`CALL])) | - ((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) | - ((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))); - -wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI]; - -wire reg_sr_clr = (e_state==`E_IRQ_2); - -wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) | - ((e_state==`E_DST_WR) & inst_so[`RETI]); - -wire reg_incr = (exec_done & inst_as[`INDIR_I]) | - ((e_state==`E_SRC_RD) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & inst_so[`RETI]); - -assign dbg_reg_din = reg_dest; - - -omsp_register_file register_file_0 ( - -// OUTPUTs - .cpuoff (cpuoff), // Turns off the CPU - .gie (gie), // General interrupt enable - .oscoff (oscoff), // Turns off LFXT1 clock input - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .reg_dest (reg_dest), // Selected register destination content - .reg_src (reg_src), // Selected register source content - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - .status (status), // R2 Status {V,N,Z,C} - -// INPUTs - .alu_stat (alu_stat), // ALU Status {V,N,Z,C} - .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Register destination selection - .inst_src (inst_src), // Register source selection - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .puc_rst (puc_rst), // Main system reset - .reg_dest_val (alu_out), // Selected register destination value - .reg_dest_wr (reg_dest_wr), // Write selected register destination - .reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction - .reg_sp_val (alu_out_add), // Stack Pointer next value - .reg_sp_wr (reg_sp_wr), // Stack Pointer write - .reg_sr_clr (reg_sr_clr), // Status register clear for interrupts - .reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction - .reg_incr (reg_incr) // Increment source register -); - - -//============================================================================= -// 3) SOURCE OPERAND MUXING -//============================================================================= -// inst_as[`DIR] : Register direct. -> Source is in register -// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset -// inst_as[`INDIR] : Register indirect. -// inst_as[`INDIR_I]: Register indirect autoincrement. -// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x). -// inst_as[`IMM] : Immediate (operand is next word in the instruction stream). -// inst_as[`ABS] : Absolute (operand is in memory at address x). -// inst_as[`CONST] : Constant. - -wire src_reg_src_sel = (e_state==`E_IRQ_0) | - (e_state==`E_IRQ_2) | - ((e_state==`E_SRC_RD) & ~inst_as[`ABS]) | - ((e_state==`E_SRC_WR) & ~inst_as[`ABS]) | - ((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]); - -wire src_reg_dest_sel = (e_state==`E_IRQ_1) | - (e_state==`E_IRQ_3) | - ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) | - ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]); - -wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] | - inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])); - -wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) | - ((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] | - inst_so[`RETI])); - -wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] | - inst_as[`CONST] | inst_so[`RETI])); - - -assign op_src = src_reg_src_sel ? reg_src : - src_reg_dest_sel ? reg_dest : - src_mdb_in_val_sel ? mdb_in_val : - src_inst_dext_sel ? inst_dext : - src_inst_sext_sel ? inst_sext : 16'h0000; - - -//============================================================================= -// 4) DESTINATION OPERAND MUXING -//============================================================================= -// inst_ad[`DIR] : Register direct. -// inst_ad[`IDX] : Register indexed. -// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x). -// inst_ad[`ABS] : Absolute (operand is in memory at address x). - - -wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])) | - ((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])); - -wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] | - inst_type[`INST_SO]) & ~inst_so[`RETI]); - -wire dst_fffe_sel = (e_state==`E_IRQ_0) | - (e_state==`E_IRQ_1) | - (e_state==`E_IRQ_3) | - ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) | - ((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) | - ((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]); - -wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) | - ((e_state==`E_DST_WR) & ~inst_ad[`ABS]) | - ((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] | - inst_type[`INST_SO]) & ~inst_so[`RETI]); - - -assign op_dst = dbg_halt_st ? dbg_mem_dout : - dst_inst_sext_sel ? inst_sext : - dst_mdb_in_bw_sel ? mdb_in_bw : - dst_reg_dest_sel ? reg_dest : - dst_fffe_sel ? 16'hfffe : 16'h0000; - - -//============================================================================= -// 5) ALU -//============================================================================= - -wire exec_cycle = (e_state==`E_EXEC); - -omsp_alu alu_0 ( - -// OUTPUTs - .alu_out (alu_out), // ALU output value - .alu_out_add (alu_out_add), // ALU adder output value - .alu_stat (alu_stat), // ALU Status {V,N,Z,C} - .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .exec_cycle (exec_cycle), // Instruction execution cycle - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_so (inst_so), // Single-operand arithmetic - .op_dst (op_dst), // Destination operand - .op_src (op_src), // Source operand - .status (status) // R2 Status {V,N,Z,C} -); - - -//============================================================================= -// 6) MEMORY INTERFACE -//============================================================================= - -// Detect memory read/write access -assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | - ((e_state==`E_IRQ_3) & ~inst_irq_rst) | - ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | - (e_state==`E_SRC_WR) | - ((e_state==`E_EXEC) & inst_so[`RETI]) | - ((e_state==`E_DST_RD) & ~inst_type[`INST_SO] - & ~inst_mov) | - (e_state==`E_DST_WR); - -wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 : - ~inst_bw ? 2'b11 : - alu_out_add[0] ? 2'b10 : 2'b01; -assign mb_wr = ({2{(e_state==`E_IRQ_1)}} | - {2{(e_state==`E_IRQ_3)}} | - {2{(e_state==`E_DST_WR)}} | - {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk; - -// Memory address bus -assign mab = alu_out_add[15:0]; - -// Memory data bus output -reg [15:0] mdb_out_nxt; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) mdb_out_nxt <= 16'h0000; - else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt; - else if ((e_state==`E_EXEC & ~inst_so[`CALL]) | - (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out; - -assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt; - -// Format memory data bus input depending on BW -reg mab_lsb; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) mab_lsb <= 1'b0; - else if (mb_en) mab_lsb <= alu_out_add[0]; - -assign mdb_in_bw = ~inst_bw ? mdb_in : - mab_lsb ? {2{mdb_in[15:8]}} : mdb_in; - -// Memory data bus input buffer (buffer after a source read) -reg mdb_in_buf_en; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) mdb_in_buf_en <= 1'b0; - else mdb_in_buf_en <= (e_state==`E_SRC_RD); - -reg mdb_in_buf_valid; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) mdb_in_buf_valid <= 1'b0; - else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0; - else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1; - -reg [15:0] mdb_in_buf; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) mdb_in_buf <= 16'h0000; - else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw; - -assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw; - - -endmodule // omsp_execution_unit - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v (nonexistent) @@ -1,256 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_mem_backbone.v -// -// *Module Description: -// Memory interface backbone (decoder + arbiter) -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_mem_backbone ( - -// OUTPUTs - dbg_mem_din, // Debug unit Memory data input - dmem_addr, // Data Memory address - dmem_cen, // Data Memory chip enable (low active) - dmem_din, // Data Memory data input - dmem_wen, // Data Memory write enable (low active) - eu_mdb_in, // Execution Unit Memory data bus input - fe_mdb_in, // Frontend Memory data bus input - fe_pmem_wait, // Frontend wait for Instruction fetch - per_addr, // Peripheral address - per_din, // Peripheral data input - per_we, // Peripheral write enable (high active) - per_en, // Peripheral enable (high active) - pmem_addr, // Program Memory address - pmem_cen, // Program Memory chip enable (low active) - pmem_din, // Program Memory data input (optional) - pmem_wen, // Program Memory write enable (low active) (optional) - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_addr, // Debug address for rd/wr access - dbg_mem_dout, // Debug unit data output - dbg_mem_en, // Debug unit memory enable - dbg_mem_wr, // Debug unit memory write - dmem_dout, // Data Memory data output - eu_mab, // Execution Unit Memory address bus - eu_mb_en, // Execution Unit Memory bus enable - eu_mb_wr, // Execution Unit Memory bus write transfer - eu_mdb_out, // Execution Unit Memory data bus output - fe_mab, // Frontend Memory address bus - fe_mb_en, // Frontend Memory bus enable - mclk, // Main system clock - per_dout, // Peripheral data output - pmem_dout, // Program Memory data output - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output [15:0] dbg_mem_din; // Debug unit Memory data input -output [`DMEM_MSB:0] dmem_addr; // Data Memory address -output dmem_cen; // Data Memory chip enable (low active) -output [15:0] dmem_din; // Data Memory data input -output [1:0] dmem_wen; // Data Memory write enable (low active) -output [15:0] eu_mdb_in; // Execution Unit Memory data bus input -output [15:0] fe_mdb_in; // Frontend Memory data bus input -output fe_pmem_wait; // Frontend wait for Instruction fetch -output [13:0] per_addr; // Peripheral address -output [15:0] per_din; // Peripheral data input -output [1:0] per_we; // Peripheral write enable (high active) -output per_en; // Peripheral enable (high active) -output [`PMEM_MSB:0] pmem_addr; // Program Memory address -output pmem_cen; // Program Memory chip enable (low active) -output [15:0] pmem_din; // Program Memory data input (optional) -output [1:0] pmem_wen; // Program Memory write enable (low active) (optional) - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_addr; // Debug address for rd/wr access -input [15:0] dbg_mem_dout; // Debug unit data output -input dbg_mem_en; // Debug unit memory enable -input [1:0] dbg_mem_wr; // Debug unit memory write -input [15:0] dmem_dout; // Data Memory data output -input [14:0] eu_mab; // Execution Unit Memory address bus -input eu_mb_en; // Execution Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer -input [15:0] eu_mdb_out; // Execution Unit Memory data bus output -input [14:0] fe_mab; // Frontend Memory address bus -input fe_mb_en; // Frontend Memory bus enable -input mclk; // Main system clock -input [15:0] per_dout; // Peripheral data output -input [15:0] pmem_dout; // Program Memory data output -input puc_rst; // Main system reset - - -//============================================================================= -// 1) DECODER -//============================================================================= - -// RAM Interface -//------------------ - -// Execution unit access -wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) & - (eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1))); -wire [15:0] eu_dmem_addr = {1'b0, eu_mab}-(`DMEM_BASE>>1); - -// Debug interface access -wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) & - (dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1))); -wire [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(`DMEM_BASE>>1); - - -// RAM Interface -wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0]; -wire dmem_cen = dbg_dmem_cen & eu_dmem_cen; -wire [1:0] dmem_wen = ~(dbg_mem_wr | eu_mb_wr); -wire [15:0] dmem_din = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out; - - -// ROM Interface -//------------------ -parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1); - -// Execution unit access (only read access are accepted) -wire eu_pmem_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1))); -wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1); - -// Front-end access -wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1))); -wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1); - -// Debug interface access -wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1))); -wire [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1); - - -// ROM Interface (Execution unit has priority) -wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] : - ~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0]; -wire pmem_cen = fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen; -wire [1:0] pmem_wen = ~dbg_mem_wr; -wire [15:0] pmem_din = dbg_mem_dout; - -wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen); - - -// Peripherals -//-------------------- -wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:`PER_AWIDTH+1]=={15-`PER_AWIDTH{1'b0}}); -wire eu_per_en = eu_mb_en & (eu_mab[14:`PER_AWIDTH] =={15-`PER_AWIDTH{1'b0}}); - -wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out; -wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr; -wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en; -wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0]; -wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1'b0}}, per_addr_mux}; -wire [13:0] per_addr = per_addr_ful[13:0]; - -reg [15:0] per_dout_val; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) per_dout_val <= 16'h0000; - else per_dout_val <= per_dout; - - -// Frontend data Mux -//--------------------------------- -// Whenever the frontend doesn't access the ROM, backup the data - -// Detect whenever the data should be backuped and restored -reg fe_pmem_cen_dly; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) fe_pmem_cen_dly <= 1'b0; - else fe_pmem_cen_dly <= fe_pmem_cen; - -wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st; -wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st; - -reg [15:0] pmem_dout_bckup; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) pmem_dout_bckup <= 16'h0000; - else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout; - -// Mux between the ROM data and the backup -reg pmem_dout_bckup_sel; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) pmem_dout_bckup_sel <= 1'b0; - else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1; - else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0; - -assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout; - - -// Execution-Unit data Mux -//--------------------------------- - -// Select between peripherals, RAM and ROM -reg [1:0] eu_mdb_in_sel; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) eu_mdb_in_sel <= 2'b00; - else eu_mdb_in_sel <= {~eu_pmem_cen, per_en}; - -// Mux -assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout : - eu_mdb_in_sel[0] ? per_dout_val : dmem_dout; - -// Debug interface data Mux -//--------------------------------- - -// Select between peripherals, RAM and ROM -`ifdef DBG_EN -reg [1:0] dbg_mem_din_sel; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) dbg_mem_din_sel <= 2'b00; - else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en}; - -`else -wire [1:0] dbg_mem_din_sel = 2'b00; -`endif - -// Mux -assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout : - dbg_mem_din_sel[0] ? per_dout_val : dmem_dout; - - -endmodule // omsp_mem_backbone - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v (nonexistent) @@ -1,579 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_defines.v -// -// *Module Description: -// openMSP430 Configuration file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 112 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-21 22:39:47 +0200 (Sat, 21 May 2011) $ -//---------------------------------------------------------------------------- -//`define OMSP_NO_INCLUDE -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif - -//============================================================================ -//============================================================================ -// BASIC SYSTEM CONFIGURATION -//============================================================================ -//============================================================================ -// -// Note: the sum of program, data and peripheral memory spaces must not -// exceed 64 kB -// - -// Program Memory Size: -// Uncomment the required memory size -//------------------------------------------------------- -//`define PMEM_SIZE_59_KB -//`define PMEM_SIZE_55_KB -//`define PMEM_SIZE_54_KB -//`define PMEM_SIZE_51_KB -//`define PMEM_SIZE_48_KB -//`define PMEM_SIZE_41_KB -//`define PMEM_SIZE_32_KB -//`define PMEM_SIZE_24_KB -//`define PMEM_SIZE_16_KB -//`define PMEM_SIZE_12_KB -//`define PMEM_SIZE_8_KB -`define PMEM_SIZE_4_KB -//`define PMEM_SIZE_2_KB -//`define PMEM_SIZE_1_KB - - -// Data Memory Size: -// Uncomment the required memory size -//------------------------------------------------------- -//`define DMEM_SIZE_32_KB -//`define DMEM_SIZE_24_KB -//`define DMEM_SIZE_16_KB -//`define DMEM_SIZE_10_KB -//`define DMEM_SIZE_8_KB -//`define DMEM_SIZE_5_KB -//`define DMEM_SIZE_4_KB -//`define DMEM_SIZE_2p5_KB -//`define DMEM_SIZE_2_KB -`define DMEM_SIZE_1_KB -//`define DMEM_SIZE_512_B -//`define DMEM_SIZE_256_B -//`define DMEM_SIZE_128_B - - -// Include/Exclude Hardware Multiplier -`define MULTIPLIER - - -// Include/Exclude Serial Debug interface -`define DBG_EN - - -//============================================================================ -//============================================================================ -// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS) -//============================================================================ -//============================================================================ - -//------------------------------------------------------- -// Peripheral Memory Space: -//------------------------------------------------------- -// The original MSP430 architecture map the peripherals -// from 0x0000 to 0x01FF (i.e. 512B of the memory space). -// The following defines allow you to expand this space -// up to 32 kB (i.e. from 0x0000 to 0x7fff). -// As a consequence, the data memory mapping will be -// shifted up and a custom linker script will therefore -// be required by the GCC compiler. -//------------------------------------------------------- -//`define PER_SIZE_32_KB -//`define PER_SIZE_16_KB -//`define PER_SIZE_8_KB -//`define PER_SIZE_4_KB -//`define PER_SIZE_2_KB -//`define PER_SIZE_1_KB -`define PER_SIZE_512_B - - -//------------------------------------------------------- -// Defines the debugger CPU_CTL.RST_BRK_EN reset value -// (CPU break on PUC reset) -//------------------------------------------------------- -// When defined, the CPU will automatically break after -// a PUC occurrence by default. This is typically usefull -// when the program memory can only be initialized through -// the serial debug interface. -//------------------------------------------------------- -//`define DBG_RST_BRK_EN - - -//------------------------------------------------------- -// Custom user version number -//------------------------------------------------------- -// This 5 bit field can be freely used in order to allow -// custom identification of the system through the debug -// interface. -// (see CPU_ID.USER_VERSION field in the documentation) -//------------------------------------------------------- -`define USER_VERSION 5'b00001 - - -//============================================================================ -//============================================================================ -// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) -//============================================================================ -//============================================================================ -// -// IMPORTANT NOTE: Please update following configuration options ONLY if -// you have a good reason to do so... and if you know what -// you are doing :-P -// -//============================================================================ - -//------------------------------------------------------- -// Number of hardware breakpoint units (each unit contains -// two hardware address breakpoints): -// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0 -// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1 -// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2 -// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3 -//------------------------------------------------------- -// Please keep in mind that hardware breakpoints only -// make sense whenever the program memory is not an SRAM -// (i.e. Flash/OTP/ROM/...) or when you are interested -// in data breakpoints (btw. not supported by GDB). -//------------------------------------------------------- -`define DBG_HWBRK_0 -//`define DBG_HWBRK_1 -//`define DBG_HWBRK_2 -//`define DBG_HWBRK_3 - - -//------------------------------------------------------- -// Enable/Disable the hardware breakpoint RANGE mode -//------------------------------------------------------- -// When enabled this feature allows the hardware breakpoint -// units to stop the cpu whenever an instruction or data -// access lays within an address range. -// Note that this feature is not supported by GDB. -//------------------------------------------------------- -//`define DBG_HWBRK_RANGE - - -//------------------------------------------------------- -// Input synchronizers -//------------------------------------------------------- -// In some cases, the asynchronous input ports might -// already be synchronized externally. -// If an extensive CDC design review showed that this -// is really the case, the individual synchronizers -// can be disabled with the following defines. -// -// Notes: -// - the dbg_en signal will reset the debug interface -// when 0. Therefore make sure it is glitch free. -// -// - the dbg_uart_rxd synchronizer must be set to 1 -// when its reset is active. -//------------------------------------------------------- -`define SYNC_CPU_EN -`define SYNC_DBG_EN -`define SYNC_DBG_UART_RXD -`define SYNC_NMI - - - -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// - -// -// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION -//================================================== - -// Program Memory Size -`ifdef PMEM_SIZE_59_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 60416 -`endif -`ifdef PMEM_SIZE_55_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 56320 -`endif -`ifdef PMEM_SIZE_54_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 55296 -`endif -`ifdef PMEM_SIZE_51_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 52224 -`endif -`ifdef PMEM_SIZE_48_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 49152 -`endif -`ifdef PMEM_SIZE_41_KB - `define PMEM_AWIDTH 15 - `define PMEM_SIZE 41984 -`endif -`ifdef PMEM_SIZE_32_KB - `define PMEM_AWIDTH 14 - `define PMEM_SIZE 32768 -`endif -`ifdef PMEM_SIZE_24_KB - `define PMEM_AWIDTH 14 - `define PMEM_SIZE 24576 -`endif -`ifdef PMEM_SIZE_16_KB - `define PMEM_AWIDTH 13 - `define PMEM_SIZE 16384 -`endif -`ifdef PMEM_SIZE_12_KB - `define PMEM_AWIDTH 13 - `define PMEM_SIZE 12288 -`endif -`ifdef PMEM_SIZE_8_KB - `define PMEM_AWIDTH 12 - `define PMEM_SIZE 8192 -`endif -`ifdef PMEM_SIZE_4_KB - `define PMEM_AWIDTH 11 - `define PMEM_SIZE 4096 -`endif -`ifdef PMEM_SIZE_2_KB - `define PMEM_AWIDTH 10 - `define PMEM_SIZE 2048 -`endif -`ifdef PMEM_SIZE_1_KB - `define PMEM_AWIDTH 9 - `define PMEM_SIZE 1024 -`endif - -// Data Memory Size -`ifdef DMEM_SIZE_32_KB - `define DMEM_AWIDTH 14 - `define DMEM_SIZE 32768 -`endif -`ifdef DMEM_SIZE_24_KB - `define DMEM_AWIDTH 14 - `define DMEM_SIZE 24576 -`endif -`ifdef DMEM_SIZE_16_KB - `define DMEM_AWIDTH 13 - `define DMEM_SIZE 16384 -`endif -`ifdef DMEM_SIZE_10_KB - `define DMEM_AWIDTH 13 - `define DMEM_SIZE 10240 -`endif -`ifdef DMEM_SIZE_8_KB - `define DMEM_AWIDTH 12 - `define DMEM_SIZE 8192 -`endif -`ifdef DMEM_SIZE_5_KB - `define DMEM_AWIDTH 12 - `define DMEM_SIZE 5120 -`endif -`ifdef DMEM_SIZE_4_KB - `define DMEM_AWIDTH 11 - `define DMEM_SIZE 4096 -`endif -`ifdef DMEM_SIZE_2p5_KB - `define DMEM_AWIDTH 11 - `define DMEM_SIZE 2560 -`endif -`ifdef DMEM_SIZE_2_KB - `define DMEM_AWIDTH 10 - `define DMEM_SIZE 2048 -`endif -`ifdef DMEM_SIZE_1_KB - `define DMEM_AWIDTH 9 - `define DMEM_SIZE 1024 -`endif -`ifdef DMEM_SIZE_512_B - `define DMEM_AWIDTH 8 - `define DMEM_SIZE 512 -`endif -`ifdef DMEM_SIZE_256_B - `define DMEM_AWIDTH 7 - `define DMEM_SIZE 256 -`endif -`ifdef DMEM_SIZE_128_B - `define DMEM_AWIDTH 6 - `define DMEM_SIZE 128 -`endif - -// Peripheral Memory Size -`ifdef PER_SIZE_32_KB - `define PER_AWIDTH 14 - `define PER_SIZE 32768 -`endif -`ifdef PER_SIZE_16_KB - `define PER_AWIDTH 13 - `define PER_SIZE 16384 -`endif -`ifdef PER_SIZE_8_KB - `define PER_AWIDTH 12 - `define PER_SIZE 8192 -`endif -`ifdef PER_SIZE_4_KB - `define PER_AWIDTH 11 - `define PER_SIZE 4096 -`endif -`ifdef PER_SIZE_2_KB - `define PER_AWIDTH 10 - `define PER_SIZE 2048 -`endif -`ifdef PER_SIZE_1_KB - `define PER_AWIDTH 9 - `define PER_SIZE 1024 -`endif -`ifdef PER_SIZE_512_B - `define PER_AWIDTH 8 - `define PER_SIZE 512 -`endif - -// Data Memory Base Adresses -`define DMEM_BASE `PER_SIZE - -// Program & Data Memory most significant address bit (for 16 bit words) -`define PMEM_MSB `PMEM_AWIDTH-1 -`define DMEM_MSB `DMEM_AWIDTH-1 -`define PER_MSB `PER_AWIDTH-1 - -// -// STATES, REGISTER FIELDS, ... -//====================================== - -// Instructions type -`define INST_SO 0 -`define INST_JMP 1 -`define INST_TO 2 - -// Single-operand arithmetic -`define RRC 0 -`define SWPB 1 -`define RRA 2 -`define SXT 3 -`define PUSH 4 -`define CALL 5 -`define RETI 6 -`define IRQ 7 - -// Conditional jump -`define JNE 0 -`define JEQ 1 -`define JNC 2 -`define JC 3 -`define JN 4 -`define JGE 5 -`define JL 6 -`define JMP 7 - -// Two-operand arithmetic -`define MOV 0 -`define ADD 1 -`define ADDC 2 -`define SUBC 3 -`define SUB 4 -`define CMP 5 -`define DADD 6 -`define BIT 7 -`define BIC 8 -`define BIS 9 -`define XOR 10 -`define AND 11 - -// Addressing modes -`define DIR 0 -`define IDX 1 -`define INDIR 2 -`define INDIR_I 3 -`define SYMB 4 -`define IMM 5 -`define ABS 6 -`define CONST 7 - -// Instruction state machine -`define I_IRQ_FETCH 3'h0 -`define I_IRQ_DONE 3'h1 -`define I_DEC 3'h2 -`define I_EXT1 3'h3 -`define I_EXT2 3'h4 -`define I_IDLE 3'h5 - -// Execution state machine -`define E_IRQ_0 4'h0 -`define E_IRQ_1 4'h1 -`define E_IRQ_2 4'h2 -`define E_IRQ_3 4'h3 -`define E_IRQ_4 4'h4 -`define E_SRC_AD 4'h5 -`define E_SRC_RD 4'h6 -`define E_SRC_WR 4'h7 -`define E_DST_AD 4'h8 -`define E_DST_RD 4'h9 -`define E_DST_WR 4'hA -`define E_EXEC 4'hB -`define E_JUMP 4'hC -`define E_IDLE 4'hD - -// ALU control signals -`define ALU_SRC_INV 0 -`define ALU_INC 1 -`define ALU_INC_C 2 -`define ALU_ADD 3 -`define ALU_AND 4 -`define ALU_OR 5 -`define ALU_XOR 6 -`define ALU_DADD 7 -`define ALU_STAT_7 8 -`define ALU_STAT_F 9 -`define ALU_SHIFT 10 -`define EXEC_NO_WR 11 - -// Debug interface -`define DBG_UART_WR 18 -`define DBG_UART_BW 17 -`define DBG_UART_ADDR 16:11 - -// Debug interface CPU_CTL register -`define HALT 0 -`define RUN 1 -`define ISTEP 2 -`define SW_BRK_EN 3 -`define FRZ_BRK_EN 4 -`define RST_BRK_EN 5 -`define CPU_RST 6 - -// Debug interface CPU_STAT register -`define HALT_RUN 0 -`define PUC_PND 1 -`define SWBRK_PND 3 -`define HWBRK0_PND 4 -`define HWBRK1_PND 5 - -// Debug interface BRKx_CTL register -`define BRK_MODE_RD 0 -`define BRK_MODE_WR 1 -`define BRK_MODE 1:0 -`define BRK_EN 2 -`define BRK_I_EN 3 -`define BRK_RANGE 4 - -// Basic clock module: BCSCTL1 Control Register -`define DIVAx 5:4 - -// Basic clock module: BCSCTL2 Control Register -`define SELS 3 -`define DIVSx 2:1 - - -// -// DEBUG INTERFACE EXTRA CONFIGURATION -//====================================== - -// Debug interface: CPU version -`define CPU_VERSION 3'h1 - -// Debug interface: Software breakpoint opcode -`define DBG_SWBRK_OP 16'h4343 - -// Debug UART interface auto data synchronization -// If the following define is commented out, then -// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly -// defined. -`define DBG_UART_AUTO_SYNC - -// Debug UART interface data rate -// In order to properly setup the UART debug interface, you -// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and -// the chosen BAUD rate from the UART interface. -// -//`define DBG_UART_BAUD 9600 -//`define DBG_UART_BAUD 19200 -//`define DBG_UART_BAUD 38400 -//`define DBG_UART_BAUD 57600 -//`define DBG_UART_BAUD 115200 -//`define DBG_UART_BAUD 230400 -//`define DBG_UART_BAUD 460800 -//`define DBG_UART_BAUD 576000 -//`define DBG_UART_BAUD 921600 -`define DBG_UART_BAUD 2000000 -`define DBG_DCO_FREQ 20000000 -`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) - -// Debug interface selection -// `define DBG_UART -> Enable UART (8N1) debug interface -// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED -// -`define DBG_UART -//`define DBG_JTAG - -// Enable/Disable the hardware breakpoint RANGE mode -`ifdef DBG_HWBRK_RANGE - `define HWBRK_RANGE 1'b1 -`else - `define HWBRK_RANGE 1'b0 -`endif - -// Counter width for the debug interface UART -`define DBG_UART_XFER_CNT_W 16 - -// Check configuration -`ifdef DBG_EN - `ifdef DBG_UART - `ifdef DBG_JTAG -CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED - `endif - `else - `ifdef DBG_JTAG -CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED - `else -CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED - `endif - `endif -`endif - -// -// MULTIPLIER CONFIGURATION -//====================================== - -// If uncommented, the following define selects -// the 16x16 multiplier (1 cycle) instead of the -// default 16x8 multplier (2 cycles) -//`define MPY_16x16 - \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v (nonexistent) @@ -1,633 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_undefines.v -// -// *Module Description: -// openMSP430 Verilog `undef file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 23 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ -//---------------------------------------------------------------------------- - -//---------------------------------------------------------------------------- -// BASIC SYSTEM CONFIGURATION -//---------------------------------------------------------------------------- - -// Program Memory sizes -`ifdef PMEM_SIZE_59_KB -`undef PMEM_SIZE_59_KB -`endif -`ifdef PMEM_SIZE_55_KB -`undef PMEM_SIZE_55_KB -`endif -`ifdef PMEM_SIZE_54_KB -`undef PMEM_SIZE_54_KB -`endif -`ifdef PMEM_SIZE_51_KB -`undef PMEM_SIZE_51_KB -`endif -`ifdef PMEM_SIZE_48_KB -`undef PMEM_SIZE_48_KB -`endif -`ifdef PMEM_SIZE_41_KB -`undef PMEM_SIZE_41_KB -`endif -`ifdef PMEM_SIZE_32_KB -`undef PMEM_SIZE_32_KB -`endif -`ifdef PMEM_SIZE_24_KB -`undef PMEM_SIZE_24_KB -`endif -`ifdef PMEM_SIZE_16_KB -`undef PMEM_SIZE_16_KB -`endif -`ifdef PMEM_SIZE_12_KB -`undef PMEM_SIZE_12_KB -`endif -`ifdef PMEM_SIZE_8_KB -`undef PMEM_SIZE_8_KB -`endif -`ifdef PMEM_SIZE_4_KB -`undef PMEM_SIZE_4_KB -`endif -`ifdef PMEM_SIZE_2_KB -`undef PMEM_SIZE_2_KB -`endif -`ifdef PMEM_SIZE_1_KB -`undef PMEM_SIZE_1_KB -`endif - -// Data Memory sizes -`ifdef DMEM_SIZE_32_KB -`undef DMEM_SIZE_32_KB -`endif -`ifdef DMEM_SIZE_24_KB -`undef DMEM_SIZE_24_KB -`endif -`ifdef DMEM_SIZE_16_KB -`undef DMEM_SIZE_16_KB -`endif -`ifdef DMEM_SIZE_10_KB -`undef DMEM_SIZE_10_KB -`endif -`ifdef DMEM_SIZE_8_KB -`undef DMEM_SIZE_8_KB -`endif -`ifdef DMEM_SIZE_5_KB -`undef DMEM_SIZE_5_KB -`endif -`ifdef DMEM_SIZE_4_KB -`undef DMEM_SIZE_4_KB -`endif -`ifdef DMEM_SIZE_2p5_KB -`undef DMEM_SIZE_2p5_KB -`endif -`ifdef DMEM_SIZE_2_KB -`undef DMEM_SIZE_2_KB -`endif -`ifdef DMEM_SIZE_1_KB -`undef DMEM_SIZE_1_KB -`endif -`ifdef DMEM_SIZE_512_B -`undef DMEM_SIZE_512_B -`endif -`ifdef DMEM_SIZE_256_B -`undef DMEM_SIZE_256_B -`endif -`ifdef DMEM_SIZE_128_B -`undef DMEM_SIZE_128_B -`endif - -// Include/Exclude Hardware Multiplier -`ifdef MULTIPLIER -`undef MULTIPLIER -`endif - -// Include Debug interface -`ifdef DBG_EN -`undef DBG_EN -`endif - - -//---------------------------------------------------------------------------- -// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS) -//---------------------------------------------------------------------------- - -// Peripheral Memory Space: -`ifdef PER_SIZE_32_KB -`undef PER_SIZE_32_KB -`endif -`ifdef PER_SIZE_16_KB -`undef PER_SIZE_16_KB -`endif -`ifdef PER_SIZE_8_KB -`undef PER_SIZE_8_KB -`endif -`ifdef PER_SIZE_4_KB -`undef PER_SIZE_4_KB -`endif -`ifdef PER_SIZE_2_KB -`undef PER_SIZE_2_KB -`endif -`ifdef PER_SIZE_1_KB -`undef PER_SIZE_1_KB -`endif -`ifdef PER_SIZE_512_B -`undef PER_SIZE_512_B -`endif - -// Let the CPU break after a PUC occurrence by default -`ifdef DBG_RST_BRK_EN -`undef DBG_RST_BRK_EN -`endif - -// Custom user version number -`ifdef USER_VERSION -`undef USER_VERSION -`endif - - -//---------------------------------------------------------------------------- -// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) -//---------------------------------------------------------------------------- - -// Number of hardware breakpoint units -`ifdef DBG_HWBRK_0 -`undef DBG_HWBRK_0 -`endif -`ifdef DBG_HWBRK_1 -`undef DBG_HWBRK_1 -`endif -`ifdef DBG_HWBRK_2 -`undef DBG_HWBRK_2 -`endif -`ifdef DBG_HWBRK_3 -`undef DBG_HWBRK_3 -`endif - -// Enable/Disable the hardware breakpoint RANGE mode -`ifdef DBG_HWBRK_RANGE -`undef DBG_HWBRK_RANGE -`endif - -// Input synchronizers -`ifdef SYNC_CPU_EN -`undef SYNC_CPU_EN -`endif -`ifdef SYNC_DBG_EN -`undef SYNC_DBG_EN -`endif -`ifdef SYNC_DBG_UART_RXD -`undef SYNC_DBG_UART_RXD -`endif -`ifdef SYNC_NMI -`undef SYNC_NMI -`endif - - -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// - -// Program Memory Size -`ifdef PMEM_AWIDTH -`undef PMEM_AWIDTH -`endif -`ifdef PMEM_SIZE -`undef PMEM_SIZE -`endif - -// Data Memory Size -`ifdef DMEM_AWIDTH -`undef DMEM_AWIDTH -`endif -`ifdef DMEM_SIZE -`undef DMEM_SIZE -`endif - -// Peripheral Memory Size -`ifdef PER_AWIDTH -`undef PER_AWIDTH -`endif -`ifdef PER_SIZE -`undef PER_SIZE -`endif - -// Data Memory Base Adresses -`ifdef DMEM_BASE -`undef DMEM_BASE -`endif - -// Program & Data Memory most significant address bit (for 16 bit words) -`ifdef PMEM_MSB -`undef PMEM_MSB -`endif -`ifdef DMEM_MSB -`undef DMEM_MSB -`endif -`ifdef PER_MSB -`undef PER_MSB -`endif - -// Instructions type -`ifdef INST_SO -`undef INST_SO -`endif -`ifdef INST_JMP -`undef INST_JMP -`endif -`ifdef INST_TO -`undef INST_TO -`endif - -// Single-operand arithmetic -`ifdef RRC -`undef RRC -`endif -`ifdef SWPB -`undef SWPB -`endif -`ifdef RRA -`undef RRA -`endif -`ifdef SXT -`undef SXT -`endif -`ifdef PUSH -`undef PUSH -`endif -`ifdef CALL -`undef CALL -`endif -`ifdef RETI -`undef RETI -`endif -`ifdef IRQ -`undef IRQ -`endif - -// Conditional jump -`ifdef JNE -`undef JNE -`endif -`ifdef JEQ -`undef JEQ -`endif -`ifdef JNC -`undef JNC -`endif -`ifdef JC -`undef JC -`endif -`ifdef JN -`undef JN -`endif -`ifdef JGE -`undef JGE -`endif -`ifdef JL -`undef JL -`endif -`ifdef JMP -`undef JMP -`endif - -// Two-operand arithmetic -`ifdef MOV -`undef MOV -`endif -`ifdef ADD -`undef ADD -`endif -`ifdef ADDC -`undef ADDC -`endif -`ifdef SUBC -`undef SUBC -`endif -`ifdef SUB -`undef SUB -`endif -`ifdef CMP -`undef CMP -`endif -`ifdef DADD -`undef DADD -`endif -`ifdef BIT -`undef BIT -`endif -`ifdef BIC -`undef BIC -`endif -`ifdef BIS -`undef BIS -`endif -`ifdef XOR -`undef XOR -`endif -`ifdef AND -`undef AND -`endif - -// Addressing modes -`ifdef DIR -`undef DIR -`endif -`ifdef IDX -`undef IDX -`endif -`ifdef INDIR -`undef INDIR -`endif -`ifdef INDIR_I -`undef INDIR_I -`endif -`ifdef SYMB -`undef SYMB -`endif -`ifdef IMM -`undef IMM -`endif -`ifdef ABS -`undef ABS -`endif -`ifdef CONST -`undef CONST -`endif - -// Instruction state machine -`ifdef I_IRQ_FETCH -`undef I_IRQ_FETCH -`endif -`ifdef I_IRQ_DONE -`undef I_IRQ_DONE -`endif -`ifdef I_DEC -`undef I_DEC -`endif -`ifdef I_EXT1 -`undef I_EXT1 -`endif -`ifdef I_EXT2 -`undef I_EXT2 -`endif -`ifdef I_IDLE -`undef I_IDLE -`endif - -// Execution state machine -`ifdef E_IRQ_0 -`undef E_IRQ_0 -`endif -`ifdef E_IRQ_1 -`undef E_IRQ_1 -`endif -`ifdef E_IRQ_2 -`undef E_IRQ_2 -`endif -`ifdef E_IRQ_3 -`undef E_IRQ_3 -`endif -`ifdef E_IRQ_4 -`undef E_IRQ_4 -`endif -`ifdef E_SRC_AD -`undef E_SRC_AD -`endif -`ifdef E_SRC_RD -`undef E_SRC_RD -`endif -`ifdef E_SRC_WR -`undef E_SRC_WR -`endif -`ifdef E_DST_AD -`undef E_DST_AD -`endif -`ifdef E_DST_RD -`undef E_DST_RD -`endif -`ifdef E_DST_WR -`undef E_DST_WR -`endif -`ifdef E_EXEC -`undef E_EXEC -`endif -`ifdef E_JUMP -`undef E_JUMP -`endif -`ifdef E_IDLE -`undef E_IDLE -`endif - -// ALU control signals -`ifdef ALU_SRC_INV -`undef ALU_SRC_INV -`endif -`ifdef ALU_INC -`undef ALU_INC -`endif -`ifdef ALU_INC_C -`undef ALU_INC_C -`endif -`ifdef ALU_ADD -`undef ALU_ADD -`endif -`ifdef ALU_AND -`undef ALU_AND -`endif -`ifdef ALU_OR -`undef ALU_OR -`endif -`ifdef ALU_XOR -`undef ALU_XOR -`endif -`ifdef ALU_DADD -`undef ALU_DADD -`endif -`ifdef ALU_STAT_7 -`undef ALU_STAT_7 -`endif -`ifdef ALU_STAT_F -`undef ALU_STAT_F -`endif -`ifdef ALU_SHIFT -`undef ALU_SHIFT -`endif -`ifdef EXEC_NO_WR -`undef EXEC_NO_WR -`endif - -// Debug interface -`ifdef DBG_UART_WR -`undef DBG_UART_WR -`endif -`ifdef DBG_UART_BW -`undef DBG_UART_BW -`endif -`ifdef DBG_UART_ADDR -`undef DBG_UART_ADDR -`endif - -// Debug interface CPU_CTL register -`ifdef HALT -`undef HALT -`endif -`ifdef RUN -`undef RUN -`endif -`ifdef ISTEP -`undef ISTEP -`endif -`ifdef SW_BRK_EN -`undef SW_BRK_EN -`endif -`ifdef FRZ_BRK_EN -`undef FRZ_BRK_EN -`endif -`ifdef RST_BRK_EN -`undef RST_BRK_EN -`endif -`ifdef CPU_RST -`undef CPU_RST -`endif - -// Debug interface CPU_STAT register -`ifdef HALT_RUN -`undef HALT_RUN -`endif -`ifdef PUC_PND -`undef PUC_PND -`endif -`ifdef SWBRK_PND -`undef SWBRK_PND -`endif -`ifdef HWBRK0_PND -`undef HWBRK0_PND -`endif -`ifdef HWBRK1_PND -`undef HWBRK1_PND -`endif - -// Debug interface BRKx_CTL register -`ifdef BRK_MODE_RD -`undef BRK_MODE_RD -`endif -`ifdef BRK_MODE_WR -`undef BRK_MODE_WR -`endif -`ifdef BRK_MODE -`undef BRK_MODE -`endif -`ifdef BRK_EN -`undef BRK_EN -`endif -`ifdef BRK_I_EN -`undef BRK_I_EN -`endif -`ifdef BRK_RANGE -`undef BRK_RANGE -`endif - -// Basic clock module: BCSCTL1 Control Register -`ifdef DIVAx -`undef DIVAx -`endif - -// Basic clock module: BCSCTL2 Control Register -`ifdef SELS -`undef SELS -`endif -`ifdef DIVSx -`undef DIVSx -`endif - - -// -// DEBUG INTERFACE EXTRA CONFIGURATION -//====================================== - -// Debug interface: CPU version -`ifdef CPU_VERSION -`undef CPU_VERSION -`endif - -// Debug interface: Software breakpoint opcode -`ifdef DBG_SWBRK_OP -`undef DBG_SWBRK_OP -`endif - -// Debug UART interface auto data synchronization -`ifdef DBG_UART_AUTO_SYNC -`undef DBG_UART_AUTO_SYNC -`endif - -// Debug UART interface data rate -`ifdef DBG_UART_BAUD -`undef DBG_UART_BAUD -`endif -`ifdef DBG_DCO_FREQ -`undef DBG_DCO_FREQ -`endif -`ifdef DBG_UART_CNT -`undef DBG_UART_CNT -`endif - -// Debug interface selection -`ifdef DBG_UART -`undef DBG_UART -`endif -`ifdef DBG_JTAG -`undef DBG_JTAG -`endif - -// Enable/Disable the hardware breakpoint RANGE mode -`ifdef HWBRK_RANGE -`undef HWBRK_RANGE -`endif - -// Counter width for the debug interface UART -`ifdef DBG_UART_XFER_CNT_W -`undef DBG_UART_XFER_CNT_W -`endif - -// -// MULTIPLIER CONFIGURATION -//====================================== - -`ifdef MPY_16x16 -`undef MPY_16x16 -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v (nonexistent) @@ -1,515 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430.v -// -// *Module Description: -// openMSP430 Top level file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module openMSP430 ( - -// OUTPUTs - aclk_en, // ACLK enable - dbg_freeze, // Freeze peripherals - dbg_uart_txd, // Debug interface: UART TXD - dmem_addr, // Data Memory address - dmem_cen, // Data Memory chip enable (low active) - dmem_din, // Data Memory data input - dmem_wen, // Data Memory write enable (low active) - irq_acc, // Interrupt request accepted (one-hot signal) - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_we, // Peripheral write enable (high active) - per_en, // Peripheral enable (high active) - pmem_addr, // Program Memory address - pmem_cen, // Program Memory chip enable (low active) - pmem_din, // Program Memory data input (optional) - pmem_wen, // Program Memory write enable (low active) (optional) - puc_rst, // Main system reset - smclk_en, // SMCLK enable - -// INPUTs - cpu_en, // Enable CPU code execution (asynchronous) - dbg_en, // Debug interface enable (asynchronous) - dbg_uart_rxd, // Debug interface: UART RXD (asynchronous) - dco_clk, // Fast oscillator (fast clock) - dmem_dout, // Data Memory data output - irq, // Maskable interrupts - lfxt_clk, // Low frequency oscillator (typ 32kHz) - nmi, // Non-maskable interrupt (asynchronous) - per_dout, // Peripheral data output - pmem_dout, // Program Memory data output - reset_n // Reset Pin (low active, asynchronous) -); - -// OUTPUTs -//========= -output aclk_en; // ACLK enable -output dbg_freeze; // Freeze peripherals -output dbg_uart_txd; // Debug interface: UART TXD -output [`DMEM_MSB:0] dmem_addr; // Data Memory address -output dmem_cen; // Data Memory chip enable (low active) -output [15:0] dmem_din; // Data Memory data input -output [1:0] dmem_wen; // Data Memory write enable (low active) -output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) -output mclk; // Main system clock -output [13:0] per_addr; // Peripheral address -output [15:0] per_din; // Peripheral data input -output [1:0] per_we; // Peripheral write enable (high active) -output per_en; // Peripheral enable (high active) -output [`PMEM_MSB:0] pmem_addr; // Program Memory address -output pmem_cen; // Program Memory chip enable (low active) -output [15:0] pmem_din; // Program Memory data input (optional) -output [1:0] pmem_wen; // Program Memory write enable (low active) (optional) -output puc_rst; // Main system reset -output smclk_en; // SMCLK enable - - -// INPUTs -//========= -input cpu_en; // Enable CPU code execution (asynchronous) -input dbg_en; // Debug interface enable (asynchronous) -input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous) -input dco_clk; // Fast oscillator (fast clock) -input [15:0] dmem_dout; // Data Memory data output -input [13:0] irq; // Maskable interrupts -input lfxt_clk; // Low frequency oscillator (typ 32kHz) -input nmi; // Non-maskable interrupt (asynchronous) -input [15:0] per_dout; // Peripheral data output -input [15:0] pmem_dout; // Program Memory data output -input reset_n; // Reset Pin (active low, asynchronous) - - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -wire [7:0] inst_ad; -wire [7:0] inst_as; -wire [11:0] inst_alu; -wire inst_bw; -wire inst_irq_rst; -wire inst_mov; -wire [15:0] inst_dest; -wire [15:0] inst_dext; -wire [15:0] inst_sext; -wire [7:0] inst_so; -wire [15:0] inst_src; -wire [2:0] inst_type; -wire [7:0] inst_jmp; -wire [3:0] e_state; -wire exec_done; -wire decode_noirq; -wire cpu_en_s; -wire cpuoff; -wire oscoff; -wire scg1; -wire por; -wire gie; - -wire [15:0] eu_mab; -wire [15:0] eu_mdb_in; -wire [15:0] eu_mdb_out; -wire [1:0] eu_mb_wr; -wire eu_mb_en; -wire [15:0] fe_mab; -wire [15:0] fe_mdb_in; -wire fe_mb_en; -wire fe_pmem_wait; - -wire pc_sw_wr; -wire [15:0] pc_sw; -wire [15:0] pc; -wire [15:0] pc_nxt; - -wire nmie; -wire nmi_acc; -wire nmi_evt; - -wire wdtie; -wire wdtifg_set; -wire wdtpw_error; -wire wdttmsel; -wire wdt_irq; -wire wdt_reset; - -wire dbg_clk; -wire dbg_rst; -wire dbg_en_s; -wire dbg_halt_st; -wire dbg_halt_cmd; -wire dbg_mem_en; -wire dbg_reg_wr; -wire dbg_cpu_reset; -wire [15:0] dbg_mem_addr; -wire [15:0] dbg_mem_dout; -wire [15:0] dbg_mem_din; -wire [15:0] dbg_reg_din; -wire [1:0] dbg_mem_wr; - -wire [15:0] per_dout_or; -wire [15:0] per_dout_sfr; -wire [15:0] per_dout_wdog; -wire [15:0] per_dout_mpy; -wire [15:0] per_dout_clk; - - -//============================================================================= -// 2) GLOBAL CLOCK & RESET MANAGEMENT -//============================================================================= - -omsp_clock_module clock_module_0 ( - -// OUTPUTs - .aclk_en (aclk_en), // ACLK enablex - .cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous) - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_en_s (dbg_en_s), // Debug interface enable (synchronous) - .dbg_rst (dbg_rst), // Debug unit reset - .mclk (mclk), // Main system clock - .per_dout (per_dout_clk), // Peripheral data output - .por (por), // Power-on reset - .puc_rst (puc_rst), // Main system reset - .smclk_en (smclk_en), // SMCLK enable - -// INPUTs - .cpu_en (cpu_en), // Enable CPU code execution (asynchronous) - .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface - .dbg_en (dbg_en), // Debug interface enable (asynchronous) - .dco_clk (dco_clk), // Fast oscillator (fast clock) - .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz) - .oscoff (oscoff), // Turns off LFXT1 clock input - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .reset_n (reset_n), // Reset Pin (low active, asynchronous) - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - .wdt_reset (wdt_reset) // Watchdog-timer reset -); - - -//============================================================================= -// 3) FRONTEND (<=> FETCH & DECODE) -//============================================================================= - -omsp_frontend frontend_0 ( - -// OUTPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .decode_noirq (decode_noirq), // Frontend decode instruction - .e_state (e_state), // Execution state - .exec_done (exec_done), // Execution completed - .inst_ad (inst_ad), // Decoded Inst: destination addressing mode - .inst_as (inst_as), // Decoded Inst: source addressing mode - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Decoded Inst: destination (one hot) - .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word - .inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_mov (inst_mov), // Decoded Inst: mov instruction - .inst_sext (inst_sext), // Decoded Inst: source extended instruction word - .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic - .inst_src (inst_src), // Decoded Inst: source (one hot) - .inst_type (inst_type), // Decoded Instruction type - .irq_acc (irq_acc), // Interrupt request accepted - .mab (fe_mab), // Frontend Memory address bus - .mb_en (fe_mb_en), // Frontend Memory bus enable - .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted - .pc (pc), // Program counter - .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) - -// INPUTs - .cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous) - .cpuoff (cpuoff), // Turns off the CPU - .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command - .dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access - .fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch - .gie (gie), // General interrupt enable - .irq (irq), // Maskable interrupts - .mclk (mclk), // Main system clock - .mdb_in (fe_mdb_in), // Frontend Memory data bus input - .nmi_evt (nmi_evt), // Non-maskable interrupt event - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .puc_rst (puc_rst), // Main system reset - .wdt_irq (wdt_irq) // Watchdog-timer interrupt -); - - -//============================================================================= -// 4) EXECUTION UNIT -//============================================================================= - -omsp_execution_unit execution_unit_0 ( - -// OUTPUTs - .cpuoff (cpuoff), // Turns off the CPU - .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input - .mab (eu_mab), // Memory address bus - .mb_en (eu_mb_en), // Memory bus enable - .mb_wr (eu_mb_wr), // Memory bus write transfer - .mdb_out (eu_mdb_out), // Memory data bus output - .oscoff (oscoff), // Turns off LFXT1 clock input - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write - .e_state (e_state), // Execution state - .exec_done (exec_done), // Execution completed - .gie (gie), // General interrupt enable - .inst_ad (inst_ad), // Decoded Inst: destination addressing mode - .inst_as (inst_as), // Decoded Inst: source addressing mode - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Decoded Inst: destination (one hot) - .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word - .inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_mov (inst_mov), // Decoded Inst: mov instruction - .inst_sext (inst_sext), // Decoded Inst: source extended instruction word - .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic - .inst_src (inst_src), // Decoded Inst: source (one hot) - .inst_type (inst_type), // Decoded Instruction type - .mclk (mclk), // Main system clock - .mdb_in (eu_mdb_in), // Memory data bus input - .pc (pc), // Program counter - .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) - .puc_rst (puc_rst) // Main system reset -); - - -//============================================================================= -// 5) MEMORY BACKBONE -//============================================================================= - -omsp_mem_backbone mem_backbone_0 ( - -// OUTPUTs - .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input - .dmem_addr (dmem_addr), // Data Memory address - .dmem_cen (dmem_cen), // Data Memory chip enable (low active) - .dmem_din (dmem_din), // Data Memory data input - .dmem_wen (dmem_wen), // Data Memory write enable (low active) - .eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input - .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input - .fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_we (per_we), // Peripheral write enable (high active) - .per_en (per_en), // Peripheral enable (high active) - .pmem_addr (pmem_addr), // Program Memory address - .pmem_cen (pmem_cen), // Program Memory chip enable (low active) - .pmem_din (pmem_din), // Program Memory data input (optional) - .pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional) - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_mem_en (dbg_mem_en), // Debug unit memory enable - .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write - .dmem_dout (dmem_dout), // Data Memory data output - .eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer - .eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output - .fe_mab (fe_mab[15:1]), // Frontend Memory address bus - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .per_dout (per_dout_or), // Peripheral data output - .pmem_dout (pmem_dout), // Program Memory data output - .puc_rst (puc_rst) // Main system reset -); - - -//============================================================================= -// 6) SPECIAL FUNCTION REGISTERS -//============================================================================= - -omsp_sfr sfr_0 ( - -// OUTPUTs - .nmie (nmie), // Non-maskable interrupt enable - .per_dout (per_dout_sfr), // Peripheral data output - .wdt_irq (wdt_irq), // Watchdog-timer interrupt - .wdt_reset (wdt_reset), // Watchdog-timer reset - .wdtie (wdtie), // Watchdog-timer interrupt enable - -// INPUTs - .mclk (mclk), // Main system clock - .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .por (por), // Power-on reset - .puc_rst (puc_rst), // Main system reset - .wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag - .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag - .wdtpw_error (wdtpw_error), // Watchdog-timer password error - .wdttmsel (wdttmsel) // Watchdog-timer mode select -); - - -//============================================================================= -// 7) WATCHDOG TIMER -//============================================================================= - -omsp_watchdog watchdog_0 ( - -// OUTPUTs - .nmi_evt (nmi_evt), // NMI Event - .per_dout (per_dout_wdog), // Peripheral data output - .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag - .wdtpw_error (wdtpw_error), // Watchdog-timer password error - .wdttmsel (wdttmsel), // Watchdog-timer mode select - -// INPUTs - .aclk_en (aclk_en), // ACLK enable - .dbg_freeze (dbg_freeze), // Freeze Watchdog counter - .mclk (mclk), // Main system clock - .nmi (nmi), // Non-maskable interrupt (asynchronous) - .nmie (nmie), // Non-maskable interrupt enable - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .puc_rst (puc_rst), // Main system reset - .smclk_en (smclk_en), // SMCLK enable - .wdtie (wdtie) // Watchdog-timer interrupt enable -); - - -//============================================================================= -// 8) HARDWARE MULTIPLIER -//============================================================================= -`ifdef MULTIPLIER -omsp_multiplier multiplier_0 ( - -// OUTPUTs - .per_dout (per_dout_mpy), // Peripheral data output - -// INPUTs - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .puc_rst (puc_rst) // Main system reset -); -`else -assign per_dout_mpy = 16'h0000; -`endif - -//============================================================================= -// 9) PERIPHERALS' OUTPUT BUS -//============================================================================= - -assign per_dout_or = per_dout | - per_dout_clk | - per_dout_sfr | - per_dout_wdog | - per_dout_mpy; - - -//============================================================================= -// 10) DEBUG INTERFACE -//============================================================================= - -`ifdef DBG_EN -omsp_dbg dbg_0 ( - -// OUTPUTs - .dbg_freeze (dbg_freeze), // Freeze peripherals - .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command - .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_mem_en (dbg_mem_en), // Debug unit memory enable - .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write - .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write - .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - -// INPUTs - .cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous) - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_en_s (dbg_en_s), // Debug interface enable (synchronous) - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input - .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input - .dbg_rst (dbg_rst), // Debug unit reset - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous) - .decode_noirq (decode_noirq), // Frontend decode instruction - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input - .pc (pc), // Program counter - .puc_rst (puc_rst) // Main system reset -); - -`else -assign dbg_freeze = ~cpu_en_s; -assign dbg_halt_cmd = 1'b0; -assign dbg_mem_addr = 16'h0000; -assign dbg_mem_dout = 16'h0000; -assign dbg_mem_en = 1'b0; -assign dbg_mem_wr = 2'b00; -assign dbg_reg_wr = 1'b0; -assign dbg_cpu_reset = 1'b0; -assign dbg_uart_txd = 1'b0; -`endif - - -endmodule // openMSP430 - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v (nonexistent) @@ -1,75 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_sync_cell.v -// -// *Module Description: -// Generic synchronizer for the openMSP430 -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 103 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ -//---------------------------------------------------------------------------- - -module omsp_sync_cell ( - -// OUTPUTs - data_out, // Synchronized data output - -// INPUTs - clk, // Receiving clock - data_in, // Asynchronous data input - rst // Receiving reset (active high) -); - -// OUTPUTs -//========= -output data_out; // Synchronized data output - -// INPUTs -//========= -input clk; // Receiving clock -input data_in; // Asynchronous data input -input rst; // Receiving reset (active high) - - -//============================================================================= -// 1) SYNCHRONIZER -//============================================================================= - -reg [1:0] data_sync; - -always @(posedge clk or posedge rst) - if (rst) data_sync <= 2'b00; - else data_sync <= {data_sync[0], data_in}; - -assign data_out = data_sync[1]; - - -endmodule // omsp_sync_cell -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v (nonexistent) @@ -1,820 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_frontend.v -// -// *Module Description: -// openMSP430 Instruction fetch and decode unit -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_frontend ( - -// OUTPUTs - dbg_halt_st, // Halt/Run status from CPU - decode_noirq, // Frontend decode instruction - e_state, // Execution state - exec_done, // Execution completed - inst_ad, // Decoded Inst: destination addressing mode - inst_as, // Decoded Inst: source addressing mode - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_dest, // Decoded Inst: destination (one hot) - inst_dext, // Decoded Inst: destination extended instruction word - inst_irq_rst, // Decoded Inst: Reset interrupt - inst_jmp, // Decoded Inst: Conditional jump - inst_mov, // Decoded Inst: mov instruction - inst_sext, // Decoded Inst: source extended instruction word - inst_so, // Decoded Inst: Single-operand arithmetic - inst_src, // Decoded Inst: source (one hot) - inst_type, // Decoded Instruction type - irq_acc, // Interrupt request accepted (one-hot signal) - mab, // Frontend Memory address bus - mb_en, // Frontend Memory bus enable - nmi_acc, // Non-Maskable interrupt request accepted - pc, // Program counter - pc_nxt, // Next PC value (for CALL & IRQ) - -// INPUTs - cpu_en_s, // Enable CPU code execution (synchronous) - cpuoff, // Turns off the CPU - dbg_halt_cmd, // Halt CPU command - dbg_reg_sel, // Debug selected register for rd/wr access - fe_pmem_wait, // Frontend wait for Instruction fetch - gie, // General interrupt enable - irq, // Maskable interrupts - mclk, // Main system clock - mdb_in, // Frontend Memory data bus input - nmi_evt, // Non-maskable interrupt event - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - puc_rst, // Main system reset - wdt_irq // Watchdog-timer interrupt -); - -// OUTPUTs -//========= -output dbg_halt_st; // Halt/Run status from CPU -output decode_noirq; // Frontend decode instruction -output [3:0] e_state; // Execution state -output exec_done; // Execution completed -output [7:0] inst_ad; // Decoded Inst: destination addressing mode -output [7:0] inst_as; // Decoded Inst: source addressing mode -output [11:0] inst_alu; // ALU control signals -output inst_bw; // Decoded Inst: byte width -output [15:0] inst_dest; // Decoded Inst: destination (one hot) -output [15:0] inst_dext; // Decoded Inst: destination extended instruction word -output inst_irq_rst; // Decoded Inst: Reset interrupt -output [7:0] inst_jmp; // Decoded Inst: Conditional jump -output inst_mov; // Decoded Inst: mov instruction -output [15:0] inst_sext; // Decoded Inst: source extended instruction word -output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic -output [15:0] inst_src; // Decoded Inst: source (one hot) -output [2:0] inst_type; // Decoded Instruction type -output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) -output [15:0] mab; // Frontend Memory address bus -output mb_en; // Frontend Memory bus enable -output nmi_acc; // Non-Maskable interrupt request accepted -output [15:0] pc; // Program counter -output [15:0] pc_nxt; // Next PC value (for CALL & IRQ) - -// INPUTs -//========= -input cpu_en_s; // Enable CPU code execution (synchronous) -input cpuoff; // Turns off the CPU -input dbg_halt_cmd; // Halt CPU command -input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access -input fe_pmem_wait; // Frontend wait for Instruction fetch -input gie; // General interrupt enable -input [13:0] irq; // Maskable interrupts -input mclk; // Main system clock -input [15:0] mdb_in; // Frontend Memory data bus input -input nmi_evt; // Non-maskable interrupt event -input [15:0] pc_sw; // Program counter software value -input pc_sw_wr; // Program counter software write -input puc_rst; // Main system reset -input wdt_irq; // Watchdog-timer interrupt - - -//============================================================================= -// 1) UTILITY FUNCTIONS -//============================================================================= - -// 16 bits one-hot decoder -function [15:0] one_hot16; - input [3:0] binary; - begin - one_hot16 = 16'h0000; - one_hot16[binary] = 1'b1; - end -endfunction - -// 8 bits one-hot decoder -function [7:0] one_hot8; - input [2:0] binary; - begin - one_hot8 = 8'h00; - one_hot8[binary] = 1'b1; - end -endfunction - - -//============================================================================= -// 2) Parameter definitions -//============================================================================= - -// -// 2.1) Instruction State machine definitons -//------------------------------------------- - -parameter I_IRQ_FETCH = `I_IRQ_FETCH; -parameter I_IRQ_DONE = `I_IRQ_DONE; -parameter I_DEC = `I_DEC; // New instruction ready for decode -parameter I_EXT1 = `I_EXT1; // 1st Extension word -parameter I_EXT2 = `I_EXT2; // 2nd Extension word -parameter I_IDLE = `I_IDLE; // CPU is in IDLE mode - -// -// 2.2) Execution State machine definitons -//------------------------------------------- - -parameter E_IRQ_0 = `E_IRQ_0; -parameter E_IRQ_1 = `E_IRQ_1; -parameter E_IRQ_2 = `E_IRQ_2; -parameter E_IRQ_3 = `E_IRQ_3; -parameter E_IRQ_4 = `E_IRQ_4; -parameter E_SRC_AD = `E_SRC_AD; -parameter E_SRC_RD = `E_SRC_RD; -parameter E_SRC_WR = `E_SRC_WR; -parameter E_DST_AD = `E_DST_AD; -parameter E_DST_RD = `E_DST_RD; -parameter E_DST_WR = `E_DST_WR; -parameter E_EXEC = `E_EXEC; -parameter E_JUMP = `E_JUMP; -parameter E_IDLE = `E_IDLE; - - -//============================================================================= -// 3) FRONTEND STATE MACHINE -//============================================================================= - -// The wire "conv" is used as state bits to calculate the next response -reg [2:0] i_state; -reg [2:0] i_state_nxt; - -reg [1:0] inst_sz; -wire [1:0] inst_sz_nxt; -wire irq_detect; -wire [2:0] inst_type_nxt; -wire is_const; -reg [15:0] sconst_nxt; -reg [3:0] e_state_nxt; - -// CPU on/off through the debug interface or cpu_en port -wire cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s; - -// States Transitions -always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or - irq_detect or cpuoff or cpu_halt_cmd or e_state) - case(i_state) - I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH : - (~cpuoff & ~cpu_halt_cmd) ? I_DEC : I_IDLE; - I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE; - I_IRQ_DONE : i_state_nxt = I_DEC; - I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH : - (cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE : - cpu_halt_cmd & (e_state==E_IDLE) ? I_IDLE : - pc_sw_wr ? I_DEC : - ~exec_done & ~(e_state==E_IDLE) ? I_DEC : // Wait in decode state - (inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed - I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH : - pc_sw_wr ? I_DEC : - (inst_sz!=2'b01) ? I_EXT2 : I_DEC; - I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC; - default : i_state_nxt = I_IRQ_FETCH; - endcase - -// State machine -always @(posedge mclk or posedge puc_rst) - if (puc_rst) i_state <= I_IRQ_FETCH; - else i_state <= i_state_nxt; - -// Utility signals -wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==E_IDLE))); -wire decode = decode_noirq | irq_detect; -wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==E_IDLE))) & ~(e_state_nxt==E_IDLE); - -// Debug interface cpu status -reg dbg_halt_st; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) dbg_halt_st <= 1'b0; - else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE); - - -//============================================================================= -// 4) INTERRUPT HANDLING -//============================================================================= - -// Detect nmi interrupt -reg inst_nmi; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_nmi <= 1'b0; - else if (nmi_evt) inst_nmi <= 1'b1; - else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0; - - -// Detect reset interrupt -reg inst_irq_rst; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_irq_rst <= 1'b1; - else if (exec_done) inst_irq_rst <= 1'b0; - -// Detect other interrupts -assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE)); - -// Select interrupt vector -reg [3:0] irq_num; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) irq_num <= 4'hf; - else if (irq_detect) irq_num <= inst_nmi ? 4'he : - irq[13] ? 4'hd : - irq[12] ? 4'hc : - irq[11] ? 4'hb : - (irq[10] | wdt_irq) ? 4'ha : - irq[9] ? 4'h9 : - irq[8] ? 4'h8 : - irq[7] ? 4'h7 : - irq[6] ? 4'h6 : - irq[5] ? 4'h5 : - irq[4] ? 4'h4 : - irq[3] ? 4'h3 : - irq[2] ? 4'h2 : - irq[1] ? 4'h1 : - irq[0] ? 4'h0 : 4'hf; - -wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0}; - -// Interrupt request accepted -wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}}; -wire [13:0] irq_acc = irq_acc_all[13:0]; -wire nmi_acc = irq_acc_all[14]; - - -//============================================================================= -// 5) FETCH INSTRUCTION -//============================================================================= - -// -// 5.1) PROGRAM COUNTER & MEMORY INTERFACE -//----------------------------------------- - -// Program counter -reg [15:0] pc; - -// Compute next PC value -wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0}; -wire [15:0] pc_nxt = pc_sw_wr ? pc_sw : - (i_state==I_IRQ_FETCH) ? irq_addr : - (i_state==I_IRQ_DONE) ? mdb_in : pc_incr; - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) pc <= 16'h0000; - else pc <= pc_nxt; - -// Check if ROM has been busy in order to retry ROM access -reg pmem_busy; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) pmem_busy <= 1'b0; - else pmem_busy <= fe_pmem_wait; - -// Memory interface -wire [15:0] mab = pc_nxt; -wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~cpu_halt_cmd); - - -// -// 5.2) INSTRUCTION REGISTER -//-------------------------------- - -// Instruction register -wire [15:0] ir = mdb_in; - -// Detect if source extension word is required -wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]); - -// Detect if destination extension word is required -wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]); - -// For the Symbolic addressing mode, add -2 to the extension word in order -// to make up for the PC address -wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) | - ((i_state==I_EXT2) & inst_ad[`SYMB]) | - ((i_state==I_EXT1) & ~inst_as[`SYMB] & - ~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000; - -wire [15:0] ext_nxt = ir + ext_incr; - -// Store source extension word -reg [15:0] inst_sext; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_sext <= 16'h0000; - else if (decode & is_const) inst_sext <= sconst_nxt; - else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0}; - else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt; - -// Source extension word is ready -wire inst_sext_rdy = (i_state==I_EXT1) & is_sext; - - -// Store destination extension word -reg [15:0] inst_dext; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_dext <= 16'h0000; - else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt; - else if (i_state==I_EXT2) inst_dext <= ext_nxt; - -// Destination extension word is ready -wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2)); - - -//============================================================================= -// 6) DECODE INSTRUCTION -//============================================================================= - -// -// 6.1) OPCODE: INSTRUCTION TYPE -//---------------------------------------- -// Instructions type is encoded in a one hot fashion as following: -// -// 3'b001: Single-operand arithmetic -// 3'b010: Conditional jump -// 3'b100: Two-operand arithmetic - -reg [2:0] inst_type; -assign inst_type_nxt = {(ir[15:14]!=2'b00), - (ir[15:13]==3'b001), - (ir[15:13]==3'b000)} & {3{~irq_detect}}; - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_type <= 3'b000; - else if (decode) inst_type <= inst_type_nxt; - -// -// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC -//---------------------------------------- -// Instructions are encoded in a one hot fashion as following: -// -// 8'b00000001: RRC -// 8'b00000010: SWPB -// 8'b00000100: RRA -// 8'b00001000: SXT -// 8'b00010000: PUSH -// 8'b00100000: CALL -// 8'b01000000: RETI -// 8'b10000000: IRQ - -reg [7:0] inst_so; -wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}}); - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_so <= 8'h00; - else if (decode) inst_so <= inst_so_nxt; - -// -// 6.3) OPCODE: CONDITIONAL JUMP -//-------------------------------- -// Instructions are encoded in a one hot fashion as following: -// -// 8'b00000001: JNE/JNZ -// 8'b00000010: JEQ/JZ -// 8'b00000100: JNC/JLO -// 8'b00001000: JC/JHS -// 8'b00010000: JN -// 8'b00100000: JGE -// 8'b01000000: JL -// 8'b10000000: JMP - -reg [2:0] inst_jmp_bin; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_jmp_bin <= 3'h0; - else if (decode) inst_jmp_bin <= ir[12:10]; - -wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}}; - - -// -// 6.4) OPCODE: TWO-OPERAND ARITHMETIC -//------------------------------------- -// Instructions are encoded in a one hot fashion as following: -// -// 12'b000000000001: MOV -// 12'b000000000010: ADD -// 12'b000000000100: ADDC -// 12'b000000001000: SUBC -// 12'b000000010000: SUB -// 12'b000000100000: CMP -// 12'b000001000000: DADD -// 12'b000010000000: BIT -// 12'b000100000000: BIC -// 12'b001000000000: BIS -// 12'b010000000000: XOR -// 12'b100000000000: AND - -wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}}; -wire [11:0] inst_to_nxt = inst_to_1hot[15:4]; - -reg inst_mov; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_mov <= 1'b0; - else if (decode) inst_mov <= inst_to_nxt[`MOV]; - - -// -// 6.5) SOURCE AND DESTINATION REGISTERS -//--------------------------------------- - -// Destination register -reg [3:0] inst_dest_bin; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_dest_bin <= 4'h0; - else if (decode) inst_dest_bin <= ir[3:0]; - -wire [15:0] inst_dest = dbg_halt_st ? one_hot16(dbg_reg_sel) : - inst_type[`INST_JMP] ? 16'h0001 : - inst_so[`IRQ] | - inst_so[`PUSH] | - inst_so[`CALL] ? 16'h0002 : - one_hot16(inst_dest_bin); - - -// Source register -reg [3:0] inst_src_bin; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_src_bin <= 4'h0; - else if (decode) inst_src_bin <= ir[11:8]; - -wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) : - inst_so[`RETI] ? 16'h0002 : - inst_so[`IRQ] ? 16'h0001 : - inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16'h0000; - - -// -// 6.6) SOURCE ADDRESSING MODES -//-------------------------------- -// Source addressing modes are encoded in a one hot fashion as following: -// -// 13'b0000000000001: Register direct. -// 13'b0000000000010: Register indexed. -// 13'b0000000000100: Register indirect. -// 13'b0000000001000: Register indirect autoincrement. -// 13'b0000000010000: Symbolic (operand is in memory at address PC+x). -// 13'b0000000100000: Immediate (operand is next word in the instruction stream). -// 13'b0000001000000: Absolute (operand is in memory at address x). -// 13'b0000010000000: Constant 4. -// 13'b0000100000000: Constant 8. -// 13'b0001000000000: Constant 0. -// 13'b0010000000000: Constant 1. -// 13'b0100000000000: Constant 2. -// 13'b1000000000000: Constant -1. - -reg [12:0] inst_as_nxt; - -wire [3:0] src_reg = inst_type_nxt[`INST_SO] ? ir[3:0] : ir[11:8]; - -always @(src_reg or ir or inst_type_nxt) - begin - if (inst_type_nxt[`INST_JMP]) - inst_as_nxt = 13'b0000000000001; - else if (src_reg==4'h3) // Addressing mode using R3 - case (ir[5:4]) - 2'b11 : inst_as_nxt = 13'b1000000000000; - 2'b10 : inst_as_nxt = 13'b0100000000000; - 2'b01 : inst_as_nxt = 13'b0010000000000; - default: inst_as_nxt = 13'b0001000000000; - endcase - else if (src_reg==4'h2) // Addressing mode using R2 - case (ir[5:4]) - 2'b11 : inst_as_nxt = 13'b0000100000000; - 2'b10 : inst_as_nxt = 13'b0000010000000; - 2'b01 : inst_as_nxt = 13'b0000001000000; - default: inst_as_nxt = 13'b0000000000001; - endcase - else if (src_reg==4'h0) // Addressing mode using R0 - case (ir[5:4]) - 2'b11 : inst_as_nxt = 13'b0000000100000; - 2'b10 : inst_as_nxt = 13'b0000000000100; - 2'b01 : inst_as_nxt = 13'b0000000010000; - default: inst_as_nxt = 13'b0000000000001; - endcase - else // General Addressing mode - case (ir[5:4]) - 2'b11 : inst_as_nxt = 13'b0000000001000; - 2'b10 : inst_as_nxt = 13'b0000000000100; - 2'b01 : inst_as_nxt = 13'b0000000000010; - default: inst_as_nxt = 13'b0000000000001; - endcase - end -assign is_const = |inst_as_nxt[12:7]; - -reg [7:0] inst_as; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_as <= 8'h00; - else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]}; - - -// 13'b0000010000000: Constant 4. -// 13'b0000100000000: Constant 8. -// 13'b0001000000000: Constant 0. -// 13'b0010000000000: Constant 1. -// 13'b0100000000000: Constant 2. -// 13'b1000000000000: Constant -1. -always @(inst_as_nxt) - begin - if (inst_as_nxt[7]) sconst_nxt = 16'h0004; - else if (inst_as_nxt[8]) sconst_nxt = 16'h0008; - else if (inst_as_nxt[9]) sconst_nxt = 16'h0000; - else if (inst_as_nxt[10]) sconst_nxt = 16'h0001; - else if (inst_as_nxt[11]) sconst_nxt = 16'h0002; - else if (inst_as_nxt[12]) sconst_nxt = 16'hffff; - else sconst_nxt = 16'h0000; - end - - -// -// 6.7) DESTINATION ADDRESSING MODES -//----------------------------------- -// Destination addressing modes are encoded in a one hot fashion as following: -// -// 8'b00000001: Register direct. -// 8'b00000010: Register indexed. -// 8'b00010000: Symbolic (operand is in memory at address PC+x). -// 8'b01000000: Absolute (operand is in memory at address x). - -reg [7:0] inst_ad_nxt; - -wire [3:0] dest_reg = ir[3:0]; - -always @(dest_reg or ir or inst_type_nxt) - begin - if (~inst_type_nxt[`INST_TO]) - inst_ad_nxt = 8'b00000000; - else if (dest_reg==4'h2) // Addressing mode using R2 - case (ir[7]) - 1'b1 : inst_ad_nxt = 8'b01000000; - default: inst_ad_nxt = 8'b00000001; - endcase - else if (dest_reg==4'h0) // Addressing mode using R0 - case (ir[7]) - 1'b1 : inst_ad_nxt = 8'b00010000; - default: inst_ad_nxt = 8'b00000001; - endcase - else // General Addressing mode - case (ir[7]) - 1'b1 : inst_ad_nxt = 8'b00000010; - default: inst_ad_nxt = 8'b00000001; - endcase - end - -reg [7:0] inst_ad; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_ad <= 8'h00; - else if (decode) inst_ad <= inst_ad_nxt; - - -// -// 6.8) REMAINING INSTRUCTION DECODING -//------------------------------------- - -// Operation size -reg inst_bw; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_bw <= 1'b0; - else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd; - -// Extended instruction size -assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} + - {1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])}; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_sz <= 2'b00; - else if (decode) inst_sz <= inst_sz_nxt; - - -//============================================================================= -// 7) EXECUTION-UNIT STATE MACHINE -//============================================================================= - -// State machine registers -reg [3:0] e_state; - - -// State machine control signals -//-------------------------------- - -wire src_acalc_pre = inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS]; -wire src_rd_pre = inst_as_nxt[`INDIR] | inst_as_nxt[`INDIR_I] | inst_as_nxt[`IMM] | inst_so_nxt[`RETI]; -wire dst_acalc_pre = inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]; -wire dst_acalc = inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]; -wire dst_rd_pre = inst_ad_nxt[`IDX] | inst_so_nxt[`PUSH] | inst_so_nxt[`CALL] | inst_so_nxt[`RETI]; -wire dst_rd = inst_ad[`IDX] | inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI]; - -wire inst_branch = (inst_ad_nxt[`DIR] & (ir[3:0]==4'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI]; - -reg exec_jmp; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) exec_jmp <= 1'b0; - else if (inst_branch & decode) exec_jmp <= 1'b1; - else if (e_state==E_JUMP) exec_jmp <= 1'b0; - -reg exec_dst_wr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) exec_dst_wr <= 1'b0; - else if (e_state==E_DST_RD) exec_dst_wr <= 1'b1; - else if (e_state==E_DST_WR) exec_dst_wr <= 1'b0; - -reg exec_src_wr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) exec_src_wr <= 1'b0; - else if (inst_type[`INST_SO] & (e_state==E_SRC_RD)) exec_src_wr <= 1'b1; - else if ((e_state==E_SRC_WR) || (e_state==E_DST_WR)) exec_src_wr <= 1'b0; - -reg exec_dext_rdy; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) exec_dext_rdy <= 1'b0; - else if (e_state==E_DST_RD) exec_dext_rdy <= 1'b0; - else if (inst_dext_rdy) exec_dext_rdy <= 1'b1; - -// Execution first state -wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? E_IRQ_0 : - cpu_halt_cmd | (i_state==I_IDLE) ? E_IDLE : - cpuoff ? E_IDLE : - src_acalc_pre ? E_SRC_AD : - src_rd_pre ? E_SRC_RD : - dst_acalc_pre ? E_DST_AD : - dst_rd_pre ? E_DST_RD : E_EXEC; - - -// State machine -//-------------------------------- - -// States Transitions -always @(e_state or dst_acalc or dst_rd or inst_sext_rdy or - inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr or - e_first_state or exec_src_wr) - case(e_state) - E_IDLE : e_state_nxt = e_first_state; - E_IRQ_0 : e_state_nxt = E_IRQ_1; - E_IRQ_1 : e_state_nxt = E_IRQ_2; - E_IRQ_2 : e_state_nxt = E_IRQ_3; - E_IRQ_3 : e_state_nxt = E_IRQ_4; - E_IRQ_4 : e_state_nxt = E_EXEC; - - E_SRC_AD : e_state_nxt = inst_sext_rdy ? E_SRC_RD : E_SRC_AD; - - E_SRC_RD : e_state_nxt = dst_acalc ? E_DST_AD : - dst_rd ? E_DST_RD : E_EXEC; - - E_DST_AD : e_state_nxt = (inst_dext_rdy | - exec_dext_rdy) ? E_DST_RD : E_DST_AD; - - E_DST_RD : e_state_nxt = E_EXEC; - - E_EXEC : e_state_nxt = exec_dst_wr ? E_DST_WR : - exec_jmp ? E_JUMP : - exec_src_wr ? E_SRC_WR : e_first_state; - - E_JUMP : e_state_nxt = e_first_state; - E_DST_WR : e_state_nxt = exec_jmp ? E_JUMP : e_first_state; - E_SRC_WR : e_state_nxt = e_first_state; - default : e_state_nxt = E_IRQ_0; - endcase - -// State machine -always @(posedge mclk or posedge puc_rst) - if (puc_rst) e_state <= E_IRQ_1; - else e_state <= e_state_nxt; - - -// Frontend State machine control signals -//---------------------------------------- - -wire exec_done = exec_jmp ? (e_state==E_JUMP) : - exec_dst_wr ? (e_state==E_DST_WR) : - exec_src_wr ? (e_state==E_SRC_WR) : (e_state==E_EXEC); - - -//============================================================================= -// 8) EXECUTION-UNIT STATE CONTROL -//============================================================================= - -// -// 8.1) ALU CONTROL SIGNALS -//------------------------------------- -// -// 12'b000000000001: Enable ALU source inverter -// 12'b000000000010: Enable Incrementer -// 12'b000000000100: Enable Incrementer on carry bit -// 12'b000000001000: Select Adder -// 12'b000000010000: Select AND -// 12'b000000100000: Select OR -// 12'b000001000000: Select XOR -// 12'b000010000000: Select DADD -// 12'b000100000000: Update N, Z & C (C=~Z) -// 12'b001000000000: Update all status bits -// 12'b010000000000: Update status bit for XOR instruction -// 12'b100000000000: Don't write to destination - -reg [11:0] inst_alu; - -wire alu_src_inv = inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] | - inst_to_nxt[`CMP] | inst_to_nxt[`BIC] ; - -wire alu_inc = inst_to_nxt[`SUB] | inst_to_nxt[`CMP]; - -wire alu_inc_c = inst_to_nxt[`ADDC] | inst_to_nxt[`DADD] | - inst_to_nxt[`SUBC]; - -wire alu_add = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] | - inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] | - inst_to_nxt[`CMP] | inst_type_nxt[`INST_JMP] | - inst_so_nxt[`RETI]; - - -wire alu_and = inst_to_nxt[`AND] | inst_to_nxt[`BIC] | - inst_to_nxt[`BIT]; - -wire alu_or = inst_to_nxt[`BIS]; - -wire alu_xor = inst_to_nxt[`XOR]; - -wire alu_dadd = inst_to_nxt[`DADD]; - -wire alu_stat_7 = inst_to_nxt[`BIT] | inst_to_nxt[`AND] | - inst_so_nxt[`SXT]; - -wire alu_stat_f = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] | - inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] | - inst_to_nxt[`CMP] | inst_to_nxt[`DADD] | - inst_to_nxt[`BIT] | inst_to_nxt[`XOR] | - inst_to_nxt[`AND] | - inst_so_nxt[`RRC] | inst_so_nxt[`RRA] | - inst_so_nxt[`SXT]; - -wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA]; - -wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT]; - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) inst_alu <= 12'h000; - else if (decode) inst_alu <= {exec_no_wr, - alu_shift, - alu_stat_f, - alu_stat_7, - alu_dadd, - alu_xor, - alu_or, - alu_and, - alu_add, - alu_inc_c, - alu_inc, - alu_src_inv}; - - -endmodule // omsp_frontend - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v (nonexistent) @@ -1,253 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_alu.v -// -// *Module Description: -// openMSP430 ALU -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_alu ( - -// OUTPUTs - alu_out, // ALU output value - alu_out_add, // ALU adder output value - alu_stat, // ALU Status {V,N,Z,C} - alu_stat_wr, // ALU Status write {V,N,Z,C} - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - exec_cycle, // Instruction execution cycle - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_jmp, // Decoded Inst: Conditional jump - inst_so, // Single-operand arithmetic - op_dst, // Destination operand - op_src, // Source operand - status // R2 Status {V,N,Z,C} -); - -// OUTPUTs -//========= -output [15:0] alu_out; // ALU output value -output [15:0] alu_out_add; // ALU adder output value -output [3:0] alu_stat; // ALU Status {V,N,Z,C} -output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input exec_cycle; // Instruction execution cycle -input [11:0] inst_alu; // ALU control signals -input inst_bw; // Decoded Inst: byte width -input [7:0] inst_jmp; // Decoded Inst: Conditional jump -input [7:0] inst_so; // Single-operand arithmetic -input [15:0] op_dst; // Destination operand -input [15:0] op_src; // Source operand -input [3:0] status; // R2 Status {V,N,Z,C} - - -//============================================================================= -// 1) FUNCTIONS -//============================================================================= - -function [4:0] bcd_add; - - input [3:0] X; - input [3:0] Y; - input C; - - reg [4:0] Z; - begin - Z = {1'b0,X}+{1'b0,Y}+{4'b0,C}; - if (Z<5'd10) bcd_add = Z; - else bcd_add = Z+5'd6; - end - -endfunction - - -//============================================================================= -// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE -//============================================================================= -// SINGLE-OPERAND ARITHMETIC: -//----------------------------------------------------------------------------- -// Mnemonic S-Reg, Operation Status bits -// D-Reg, V N Z C -// -// RRC dst C->MSB->...LSB->C * * * * -// RRA dst MSB->MSB->...LSB->C 0 * * * -// SWPB dst Swap bytes - - - - -// SXT dst Bit7->Bit8...Bit15 0 * * * -// PUSH src SP-2->SP, src->@SP - - - - -// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - - -// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * * -// -//----------------------------------------------------------------------------- -// TWO-OPERAND ARITHMETIC: -//----------------------------------------------------------------------------- -// Mnemonic S-Reg, Operation Status bits -// D-Reg, V N Z C -// -// MOV src,dst src -> dst - - - - -// ADD src,dst src + dst -> dst * * * * -// ADDC src,dst src + dst + C -> dst * * * * -// SUB src,dst dst + ~src + 1 -> dst * * * * -// SUBC src,dst dst + ~src + C -> dst * * * * -// CMP src,dst dst + ~src + 1 * * * * -// DADD src,dst src + dst + C -> dst (decimaly) * * * * -// BIT src,dst src & dst 0 * * * -// BIC src,dst ~src & dst -> dst - - - - -// BIS src,dst src | dst -> dst - - - - -// XOR src,dst src ^ dst -> dst * * * * -// AND src,dst src & dst -> dst 0 * * * -// -//----------------------------------------------------------------------------- -// * the status bit is affected -// - the status bit is not affected -// 0 the status bit is cleared -// 1 the status bit is set -//----------------------------------------------------------------------------- - -// Invert source for substract and compare instructions. -wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]); -wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src; - - -// Mask the bit 8 for the Byte instructions for correct flags generation -wire op_bit8_msk = ~exec_cycle | ~inst_bw; -wire [16:0] op_src_in = {1'b0, {op_src_inv[15:8] & {8{op_bit8_msk}}}, op_src_inv[7:0]}; -wire [16:0] op_dst_in = {1'b0, {op_dst[15:8] & {8{op_bit8_msk}}}, op_dst[7:0]}; - -// Clear the source operand (= jump offset) for conditional jumps -wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) | - (inst_jmp[`JGE] & (status[3]^status[2])) | - (inst_jmp[`JN] & ~status[2]) | - (inst_jmp[`JC] & ~status[0]) | - (inst_jmp[`JNC] & status[0]) | - (inst_jmp[`JEQ] & ~status[1]) | - (inst_jmp[`JNE] & status[1]); -wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}}; - -// Adder / AND / OR / XOR -wire [16:0] alu_add = op_src_in_jmp + op_dst_in; -wire [16:0] alu_and = op_src_in & op_dst_in; -wire [16:0] alu_or = op_src_in | op_dst_in; -wire [16:0] alu_xor = op_src_in ^ op_dst_in; - - -// Incrementer -wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) | - inst_alu[`ALU_INC]); -wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc}; - - - -// Decimal adder (DADD) -wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]); -wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]); -wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]); -wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]); -wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]}; - - -// Shifter for rotate instructions (RRC & RRA) -wire alu_shift_msb = inst_so[`RRC] ? status[0] : - inst_bw ? op_src[7] : op_src[15]; -wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8]; -wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]}; - - -// Swap bytes / Extend Sign -wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]}; -wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]}; - - -// Combine short paths toghether to simplify final ALU mux -wire alu_short_thro = ~(inst_alu[`ALU_AND] | - inst_alu[`ALU_OR] | - inst_alu[`ALU_XOR] | - inst_alu[`ALU_SHIFT] | - inst_so[`SWPB] | - inst_so[`SXT]); - -wire [16:0] alu_short = ({17{inst_alu[`ALU_AND]}} & alu_and) | - ({17{inst_alu[`ALU_OR]}} & alu_or) | - ({17{inst_alu[`ALU_XOR]}} & alu_xor) | - ({17{inst_alu[`ALU_SHIFT]}} & alu_shift) | - ({17{inst_so[`SWPB]}} & alu_swpb) | - ({17{inst_so[`SXT]}} & alu_sxt) | - ({17{alu_short_thro}} & op_src_in); - - -// ALU output mux -wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st | - inst_alu[`ALU_ADD]) ? alu_add_inc : - inst_alu[`ALU_DADD] ? alu_dadd : alu_short; - -assign alu_out = alu_out_nxt[15:0]; -assign alu_out_add = alu_add[15:0]; - - -//----------------------------------------------------------------------------- -// STATUS FLAG GENERATION -//----------------------------------------------------------------------------- - -wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) : - (op_src_in[15] & op_dst_in[15]); - -wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) | - ( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) : - ((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) | - ( op_src_in[15] & op_dst_in[15] & ~alu_out[15])); - -wire N = inst_bw ? alu_out[7] : alu_out[15]; -wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0); -wire C = inst_bw ? alu_out[8] : alu_out_nxt[16]; - -assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} : - inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} : - inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C}; - -assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000; - - -endmodule // omsp_alu - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v (nonexistent) @@ -1,350 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_register_file.v -// -// *Module Description: -// openMSP430 Register files -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_register_file ( - -// OUTPUTs - cpuoff, // Turns off the CPU - gie, // General interrupt enable - oscoff, // Turns off LFXT1 clock input - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - reg_dest, // Selected register destination content - reg_src, // Selected register source content - scg1, // System clock generator 1. Turns off the SMCLK - status, // R2 Status {V,N,Z,C} - -// INPUTs - alu_stat, // ALU Status {V,N,Z,C} - alu_stat_wr, // ALU Status write {V,N,Z,C} - inst_bw, // Decoded Inst: byte width - inst_dest, // Register destination selection - inst_src, // Register source selection - mclk, // Main system clock - pc, // Program counter - puc_rst, // Main system reset - reg_dest_val, // Selected register destination value - reg_dest_wr, // Write selected register destination - reg_pc_call, // Trigger PC update for a CALL instruction - reg_sp_val, // Stack Pointer next value - reg_sp_wr, // Stack Pointer write - reg_sr_wr, // Status register update for RETI instruction - reg_sr_clr, // Status register clear for interrupts - reg_incr // Increment source register -); - -// OUTPUTs -//========= -output cpuoff; // Turns off the CPU -output gie; // General interrupt enable -output oscoff; // Turns off LFXT1 clock input -output [15:0] pc_sw; // Program counter software value -output pc_sw_wr; // Program counter software write -output [15:0] reg_dest; // Selected register destination content -output [15:0] reg_src; // Selected register source content -output scg1; // System clock generator 1. Turns off the SMCLK -output [3:0] status; // R2 Status {V,N,Z,C} - -// INPUTs -//========= -input [3:0] alu_stat; // ALU Status {V,N,Z,C} -input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} -input inst_bw; // Decoded Inst: byte width -input [15:0] inst_dest; // Register destination selection -input [15:0] inst_src; // Register source selection -input mclk; // Main system clock -input [15:0] pc; // Program counter -input puc_rst; // Main system reset -input [15:0] reg_dest_val; // Selected register destination value -input reg_dest_wr; // Write selected register destination -input reg_pc_call; // Trigger PC update for a CALL instruction -input [15:0] reg_sp_val; // Stack Pointer next value -input reg_sp_wr; // Stack Pointer write -input reg_sr_wr; // Status register update for RETI instruction -input reg_sr_clr; // Status register clear for interrupts -input reg_incr; // Increment source register - - -//============================================================================= -// 1) AUTOINCREMENT UNIT -//============================================================================= - -wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002; -wire [15:0] reg_incr_val = reg_src+incr_op; - -wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val; - - -//============================================================================= -// 2) SPECIAL REGISTERS (R1/R2/R3) -//============================================================================= - -// Source input selection mask (for interrupt support) -//----------------------------------------------------- - -wire [15:0] inst_src_in = reg_sr_clr ? 16'h0004 : inst_src; - - -// R0: Program counter -//--------------------- - -wire [15:0] r0 = pc; - -wire [15:0] pc_sw = reg_dest_val_in; -wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call; - - -// R1: Stack pointer -//------------------- -reg [15:0] r1; -wire r1_wr = inst_dest[1] & reg_dest_wr; -wire r1_inc = inst_src_in[1] & reg_incr; - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r1 <= 16'h0000; - else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe; - else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe; - else if (r1_inc) r1 <= reg_incr_val & 16'hfffe; - - -// R2: Status register -//--------------------- -reg [15:0] r2; -wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr; - -wire r2_c = alu_stat_wr[0] ? alu_stat[0] : - r2_wr ? reg_dest_val_in[0] : r2[0]; // C - -wire r2_z = alu_stat_wr[1] ? alu_stat[1] : - r2_wr ? reg_dest_val_in[1] : r2[1]; // Z - -wire r2_n = alu_stat_wr[2] ? alu_stat[2] : - r2_wr ? reg_dest_val_in[2] : r2[2]; // N - -wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3]; - -wire r2_v = alu_stat_wr[3] ? alu_stat[3] : - r2_wr ? reg_dest_val_in[8] : r2[8]; // V - - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r2 <= 16'h0000; - else if (reg_sr_clr) r2 <= 16'h0000; - else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c}; - -assign status = {r2[8], r2[2:0]}; -assign gie = r2[3]; -assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr); -assign oscoff = r2[5]; -assign scg1 = r2[7]; - - -// R3: Constant generator -//------------------------ -reg [15:0] r3; -wire r3_wr = inst_dest[3] & reg_dest_wr; -wire r3_inc = inst_src_in[3] & reg_incr; - -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r3 <= 16'h0000; - else if (r3_wr) r3 <= reg_dest_val_in; - else if (r3_inc) r3 <= reg_incr_val; - - -//============================================================================= -// 4) GENERAL PURPOSE REGISTERS (R4...R15) -//============================================================================= - -// R4 -reg [15:0] r4; -wire r4_wr = inst_dest[4] & reg_dest_wr; -wire r4_inc = inst_src_in[4] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r4 <= 16'h0000; - else if (r4_wr) r4 <= reg_dest_val_in; - else if (r4_inc) r4 <= reg_incr_val; - -// R5 -reg [15:0] r5; -wire r5_wr = inst_dest[5] & reg_dest_wr; -wire r5_inc = inst_src_in[5] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r5 <= 16'h0000; - else if (r5_wr) r5 <= reg_dest_val_in; - else if (r5_inc) r5 <= reg_incr_val; - -// R6 -reg [15:0] r6; -wire r6_wr = inst_dest[6] & reg_dest_wr; -wire r6_inc = inst_src_in[6] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r6 <= 16'h0000; - else if (r6_wr) r6 <= reg_dest_val_in; - else if (r6_inc) r6 <= reg_incr_val; - -// R7 -reg [15:0] r7; -wire r7_wr = inst_dest[7] & reg_dest_wr; -wire r7_inc = inst_src_in[7] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r7 <= 16'h0000; - else if (r7_wr) r7 <= reg_dest_val_in; - else if (r7_inc) r7 <= reg_incr_val; - -// R8 -reg [15:0] r8; -wire r8_wr = inst_dest[8] & reg_dest_wr; -wire r8_inc = inst_src_in[8] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r8 <= 16'h0000; - else if (r8_wr) r8 <= reg_dest_val_in; - else if (r8_inc) r8 <= reg_incr_val; - -// R9 -reg [15:0] r9; -wire r9_wr = inst_dest[9] & reg_dest_wr; -wire r9_inc = inst_src_in[9] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r9 <= 16'h0000; - else if (r9_wr) r9 <= reg_dest_val_in; - else if (r9_inc) r9 <= reg_incr_val; - -// R10 -reg [15:0] r10; -wire r10_wr = inst_dest[10] & reg_dest_wr; -wire r10_inc = inst_src_in[10] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r10 <= 16'h0000; - else if (r10_wr) r10 <= reg_dest_val_in; - else if (r10_inc) r10 <= reg_incr_val; - -// R11 -reg [15:0] r11; -wire r11_wr = inst_dest[11] & reg_dest_wr; -wire r11_inc = inst_src_in[11] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r11 <= 16'h0000; - else if (r11_wr) r11 <= reg_dest_val_in; - else if (r11_inc) r11 <= reg_incr_val; - -// R12 -reg [15:0] r12; -wire r12_wr = inst_dest[12] & reg_dest_wr; -wire r12_inc = inst_src_in[12] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r12 <= 16'h0000; - else if (r12_wr) r12 <= reg_dest_val_in; - else if (r12_inc) r12 <= reg_incr_val; - -// R13 -reg [15:0] r13; -wire r13_wr = inst_dest[13] & reg_dest_wr; -wire r13_inc = inst_src_in[13] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r13 <= 16'h0000; - else if (r13_wr) r13 <= reg_dest_val_in; - else if (r13_inc) r13 <= reg_incr_val; - -// R14 -reg [15:0] r14; -wire r14_wr = inst_dest[14] & reg_dest_wr; -wire r14_inc = inst_src_in[14] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r14 <= 16'h0000; - else if (r14_wr) r14 <= reg_dest_val_in; - else if (r14_inc) r14 <= reg_incr_val; - -// R15 -reg [15:0] r15; -wire r15_wr = inst_dest[15] & reg_dest_wr; -wire r15_inc = inst_src_in[15] & reg_incr; -always @(posedge mclk or posedge puc_rst) - if (puc_rst) r15 <= 16'h0000; - else if (r15_wr) r15 <= reg_dest_val_in; - else if (r15_inc) r15 <= reg_incr_val; - - -//============================================================================= -// 5) READ MUX -//============================================================================= - -assign reg_src = (r0 & {16{inst_src_in[0]}}) | - (r1 & {16{inst_src_in[1]}}) | - (r2 & {16{inst_src_in[2]}}) | - (r3 & {16{inst_src_in[3]}}) | - (r4 & {16{inst_src_in[4]}}) | - (r5 & {16{inst_src_in[5]}}) | - (r6 & {16{inst_src_in[6]}}) | - (r7 & {16{inst_src_in[7]}}) | - (r8 & {16{inst_src_in[8]}}) | - (r9 & {16{inst_src_in[9]}}) | - (r10 & {16{inst_src_in[10]}}) | - (r11 & {16{inst_src_in[11]}}) | - (r12 & {16{inst_src_in[12]}}) | - (r13 & {16{inst_src_in[13]}}) | - (r14 & {16{inst_src_in[14]}}) | - (r15 & {16{inst_src_in[15]}}); - -assign reg_dest = (r0 & {16{inst_dest[0]}}) | - (r1 & {16{inst_dest[1]}}) | - (r2 & {16{inst_dest[2]}}) | - (r3 & {16{inst_dest[3]}}) | - (r4 & {16{inst_dest[4]}}) | - (r5 & {16{inst_dest[5]}}) | - (r6 & {16{inst_dest[6]}}) | - (r7 & {16{inst_dest[7]}}) | - (r8 & {16{inst_dest[8]}}) | - (r9 & {16{inst_dest[9]}}) | - (r10 & {16{inst_dest[10]}}) | - (r11 & {16{inst_dest[11]}}) | - (r12 & {16{inst_dest[12]}}) | - (r13 & {16{inst_dest[13]}}) | - (r14 & {16{inst_dest[14]}}) | - (r15 & {16{inst_dest[15]}}); - - -endmodule // omsp_register_file - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v (nonexistent) @@ -1,188 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of the authors nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -// THE POSSIBILITY OF SUCH DAMAGE -// -//---------------------------------------------------------------------------- -// -// *File Name: template_periph_16b.v -// -// *Module Description: -// 16 bit peripheral template. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- - -module template_periph_16b ( - -// OUTPUTs - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0190; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 3; - -// Register addresses offset -parameter [DEC_WD-1:0] CNTRL1 = 'h0, - CNTRL2 = 'h2, - CNTRL3 = 'h4, - CNTRL4 = 'h6; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1), - CNTRL2_D = (BASE_REG << CNTRL2), - CNTRL3_D = (BASE_REG << CNTRL3), - CNTRL4_D = (BASE_REG << CNTRL4); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) | - (CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}) | - (CNTRL3_D & {DEC_SZ{(reg_addr == CNTRL3 )}}) | - (CNTRL4_D & {DEC_SZ{(reg_addr == CNTRL4 )}}); - -// Read/Write probes -wire reg_write = |per_we & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// CNTRL1 Register -//----------------- -reg [15:0] cntrl1; - -wire cntrl1_wr = reg_wr[CNTRL1]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl1 <= 16'h0000; - else if (cntrl1_wr) cntrl1 <= per_din; - - -// CNTRL2 Register -//----------------- -reg [15:0] cntrl2; - -wire cntrl2_wr = reg_wr[CNTRL2]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl2 <= 16'h0000; - else if (cntrl2_wr) cntrl2 <= per_din; - - -// CNTRL3 Register -//----------------- -reg [15:0] cntrl3; - -wire cntrl3_wr = reg_wr[CNTRL3]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl3 <= 16'h0000; - else if (cntrl3_wr) cntrl3 <= per_din; - - -// CNTRL4 Register -//----------------- -reg [15:0] cntrl4; - -wire cntrl4_wr = reg_wr[CNTRL4]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl4 <= 16'h0000; - else if (cntrl4_wr) cntrl4 <= per_din; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}}; -wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}}; -wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}}; -wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}}; - -wire [15:0] per_dout = cntrl1_rd | - cntrl2_rd | - cntrl3_rd | - cntrl4_rd; - - -endmodule // template_periph_16b

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v (nonexistent) @@ -1,196 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2009 Authors -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of the authors nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -// THE POSSIBILITY OF SUCH DAMAGE -// -//---------------------------------------------------------------------------- -// -// *File Name: template_periph_8b.v -// -// *Module Description: -// 8 bit peripheral template. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- - -module template_periph_8b ( - -// OUTPUTs - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0090; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 2; - -// Register addresses offset -parameter [DEC_WD-1:0] CNTRL1 = 'h0, - CNTRL2 = 'h1, - CNTRL3 = 'h2, - CNTRL4 = 'h3; - - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1), - CNTRL2_D = (BASE_REG << CNTRL2), - CNTRL3_D = (BASE_REG << CNTRL3), - CNTRL4_D = (BASE_REG << CNTRL4); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) | - (CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) | - (CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) | - (CNTRL4_D & {DEC_SZ{(reg_addr==(CNTRL4 >>1))}}); - -// Read/Write probes -wire reg_lo_write = per_we[0] & reg_sel; -wire reg_hi_write = per_we[1] & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; -wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// CNTRL1 Register -//----------------- -reg [7:0] cntrl1; - -wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1]; -wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl1 <= 8'h00; - else if (cntrl1_wr) cntrl1 <= cntrl1_nxt; - - -// CNTRL2 Register -//----------------- -reg [7:0] cntrl2; - -wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2]; -wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl2 <= 8'h00; - else if (cntrl2_wr) cntrl2 <= cntrl2_nxt; - - -// CNTRL3 Register -//----------------- -reg [7:0] cntrl3; - -wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3]; -wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl3 <= 8'h00; - else if (cntrl3_wr) cntrl3 <= cntrl3_nxt; - - -// CNTRL4 Register -//----------------- -reg [7:0] cntrl4; - -wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4]; -wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cntrl4 <= 8'h00; - else if (cntrl4_wr) cntrl4 <= cntrl4_nxt; - - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}}); -wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}}); -wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}}); -wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[CNTRL4]}})} << (8 & {4{CNTRL4[0]}}); - -wire [15:0] per_dout = cntrl1_rd | - cntrl2_rd | - cntrl3_rd | - cntrl4_rd; - - -endmodule // template_periph_8b

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v (nonexistent) @@ -1,809 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_gpio.v -// -// *Module Description: -// Digital I/O interface -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- - -module omsp_gpio ( - -// OUTPUTs - irq_port1, // Port 1 interrupt - irq_port2, // Port 2 interrupt - p1_dout, // Port 1 data output - p1_dout_en, // Port 1 data output enable - p1_sel, // Port 1 function select - p2_dout, // Port 2 data output - p2_dout_en, // Port 2 data output enable - p2_sel, // Port 2 function select - p3_dout, // Port 3 data output - p3_dout_en, // Port 3 data output enable - p3_sel, // Port 3 function select - p4_dout, // Port 4 data output - p4_dout_en, // Port 4 data output enable - p4_sel, // Port 4 function select - p5_dout, // Port 5 data output - p5_dout_en, // Port 5 data output enable - p5_sel, // Port 5 function select - p6_dout, // Port 6 data output - p6_dout_en, // Port 6 data output enable - p6_sel, // Port 6 function select - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - p1_din, // Port 1 data input - p2_din, // Port 2 data input - p3_din, // Port 3 data input - p4_din, // Port 4 data input - p5_din, // Port 5 data input - p6_din, // Port 6 data input - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst // Main system reset -); - -// PARAMETERs -//============ -parameter P1_EN = 1'b1; // Enable Port 1 -parameter P2_EN = 1'b1; // Enable Port 2 -parameter P3_EN = 1'b0; // Enable Port 3 -parameter P4_EN = 1'b0; // Enable Port 4 -parameter P5_EN = 1'b0; // Enable Port 5 -parameter P6_EN = 1'b0; // Enable Port 6 - - -// OUTPUTs -//========= -output irq_port1; // Port 1 interrupt -output irq_port2; // Port 2 interrupt -output [7:0] p1_dout; // Port 1 data output -output [7:0] p1_dout_en; // Port 1 data output enable -output [7:0] p1_sel; // Port 1 function select -output [7:0] p2_dout; // Port 2 data output -output [7:0] p2_dout_en; // Port 2 data output enable -output [7:0] p2_sel; // Port 2 function select -output [7:0] p3_dout; // Port 3 data output -output [7:0] p3_dout_en; // Port 3 data output enable -output [7:0] p3_sel; // Port 3 function select -output [7:0] p4_dout; // Port 4 data output -output [7:0] p4_dout_en; // Port 4 data output enable -output [7:0] p4_sel; // Port 4 function select -output [7:0] p5_dout; // Port 5 data output -output [7:0] p5_dout_en; // Port 5 data output enable -output [7:0] p5_sel; // Port 5 function select -output [7:0] p6_dout; // Port 6 data output -output [7:0] p6_dout_en; // Port 6 data output enable -output [7:0] p6_sel; // Port 6 function select -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [7:0] p1_din; // Port 1 data input -input [7:0] p2_din; // Port 2 data input -input [7:0] p3_din; // Port 3 data input -input [7:0] p4_din; // Port 4 data input -input [7:0] p5_din; // Port 5 data input -input [7:0] p6_din; // Port 6 data input -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Masks -parameter P1_EN_MSK = {8{P1_EN[0]}}; -parameter P2_EN_MSK = {8{P2_EN[0]}}; -parameter P3_EN_MSK = {8{P3_EN[0]}}; -parameter P4_EN_MSK = {8{P4_EN[0]}}; -parameter P5_EN_MSK = {8{P5_EN[0]}}; -parameter P6_EN_MSK = {8{P6_EN[0]}}; - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0000; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 6; - -// Register addresses offset -parameter [DEC_WD-1:0] P1IN = 'h20, // Port 1 - P1OUT = 'h21, - P1DIR = 'h22, - P1IFG = 'h23, - P1IES = 'h24, - P1IE = 'h25, - P1SEL = 'h26, - P2IN = 'h28, // Port 2 - P2OUT = 'h29, - P2DIR = 'h2A, - P2IFG = 'h2B, - P2IES = 'h2C, - P2IE = 'h2D, - P2SEL = 'h2E, - P3IN = 'h18, // Port 3 - P3OUT = 'h19, - P3DIR = 'h1A, - P3SEL = 'h1B, - P4IN = 'h1C, // Port 4 - P4OUT = 'h1D, - P4DIR = 'h1E, - P4SEL = 'h1F, - P5IN = 'h30, // Port 5 - P5OUT = 'h31, - P5DIR = 'h32, - P5SEL = 'h33, - P6IN = 'h34, // Port 6 - P6OUT = 'h35, - P6DIR = 'h36, - P6SEL = 'h37; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] P1IN_D = (BASE_REG << P1IN), // Port 1 - P1OUT_D = (BASE_REG << P1OUT), - P1DIR_D = (BASE_REG << P1DIR), - P1IFG_D = (BASE_REG << P1IFG), - P1IES_D = (BASE_REG << P1IES), - P1IE_D = (BASE_REG << P1IE), - P1SEL_D = (BASE_REG << P1SEL), - P2IN_D = (BASE_REG << P2IN), // Port 2 - P2OUT_D = (BASE_REG << P2OUT), - P2DIR_D = (BASE_REG << P2DIR), - P2IFG_D = (BASE_REG << P2IFG), - P2IES_D = (BASE_REG << P2IES), - P2IE_D = (BASE_REG << P2IE), - P2SEL_D = (BASE_REG << P2SEL), - P3IN_D = (BASE_REG << P3IN), // Port 3 - P3OUT_D = (BASE_REG << P3OUT), - P3DIR_D = (BASE_REG << P3DIR), - P3SEL_D = (BASE_REG << P3SEL), - P4IN_D = (BASE_REG << P4IN), // Port 4 - P4OUT_D = (BASE_REG << P4OUT), - P4DIR_D = (BASE_REG << P4DIR), - P4SEL_D = (BASE_REG << P4SEL), - P5IN_D = (BASE_REG << P5IN), // Port 5 - P5OUT_D = (BASE_REG << P5OUT), - P5DIR_D = (BASE_REG << P5DIR), - P5SEL_D = (BASE_REG << P5SEL), - P6IN_D = (BASE_REG << P6IN), // Port 6 - P6OUT_D = (BASE_REG << P6OUT), - P6DIR_D = (BASE_REG << P6DIR), - P6SEL_D = (BASE_REG << P6SEL); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (P1IN_D & {DEC_SZ{(reg_addr==(P1IN >>1)) & P1_EN[0]}}) | - (P1OUT_D & {DEC_SZ{(reg_addr==(P1OUT >>1)) & P1_EN[0]}}) | - (P1DIR_D & {DEC_SZ{(reg_addr==(P1DIR >>1)) & P1_EN[0]}}) | - (P1IFG_D & {DEC_SZ{(reg_addr==(P1IFG >>1)) & P1_EN[0]}}) | - (P1IES_D & {DEC_SZ{(reg_addr==(P1IES >>1)) & P1_EN[0]}}) | - (P1IE_D & {DEC_SZ{(reg_addr==(P1IE >>1)) & P1_EN[0]}}) | - (P1SEL_D & {DEC_SZ{(reg_addr==(P1SEL >>1)) & P1_EN[0]}}) | - (P2IN_D & {DEC_SZ{(reg_addr==(P2IN >>1)) & P2_EN[0]}}) | - (P2OUT_D & {DEC_SZ{(reg_addr==(P2OUT >>1)) & P2_EN[0]}}) | - (P2DIR_D & {DEC_SZ{(reg_addr==(P2DIR >>1)) & P2_EN[0]}}) | - (P2IFG_D & {DEC_SZ{(reg_addr==(P2IFG >>1)) & P2_EN[0]}}) | - (P2IES_D & {DEC_SZ{(reg_addr==(P2IES >>1)) & P2_EN[0]}}) | - (P2IE_D & {DEC_SZ{(reg_addr==(P2IE >>1)) & P2_EN[0]}}) | - (P2SEL_D & {DEC_SZ{(reg_addr==(P2SEL >>1)) & P2_EN[0]}}) | - (P3IN_D & {DEC_SZ{(reg_addr==(P3IN >>1)) & P3_EN[0]}}) | - (P3OUT_D & {DEC_SZ{(reg_addr==(P3OUT >>1)) & P3_EN[0]}}) | - (P3DIR_D & {DEC_SZ{(reg_addr==(P3DIR >>1)) & P3_EN[0]}}) | - (P3SEL_D & {DEC_SZ{(reg_addr==(P3SEL >>1)) & P3_EN[0]}}) | - (P4IN_D & {DEC_SZ{(reg_addr==(P4IN >>1)) & P4_EN[0]}}) | - (P4OUT_D & {DEC_SZ{(reg_addr==(P4OUT >>1)) & P4_EN[0]}}) | - (P4DIR_D & {DEC_SZ{(reg_addr==(P4DIR >>1)) & P4_EN[0]}}) | - (P4SEL_D & {DEC_SZ{(reg_addr==(P4SEL >>1)) & P4_EN[0]}}) | - (P5IN_D & {DEC_SZ{(reg_addr==(P5IN >>1)) & P5_EN[0]}}) | - (P5OUT_D & {DEC_SZ{(reg_addr==(P5OUT >>1)) & P5_EN[0]}}) | - (P5DIR_D & {DEC_SZ{(reg_addr==(P5DIR >>1)) & P5_EN[0]}}) | - (P5SEL_D & {DEC_SZ{(reg_addr==(P5SEL >>1)) & P5_EN[0]}}) | - (P6IN_D & {DEC_SZ{(reg_addr==(P6IN >>1)) & P6_EN[0]}}) | - (P6OUT_D & {DEC_SZ{(reg_addr==(P6OUT >>1)) & P6_EN[0]}}) | - (P6DIR_D & {DEC_SZ{(reg_addr==(P6DIR >>1)) & P6_EN[0]}}) | - (P6SEL_D & {DEC_SZ{(reg_addr==(P6SEL >>1)) & P6_EN[0]}}); - -// Read/Write probes -wire reg_lo_write = per_we[0] & reg_sel; -wire reg_hi_write = per_we[1] & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; -wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// P1IN Register -//--------------- -wire [7:0] p1in; - -omsp_sync_cell sync_cell_p1in_0 (.data_out(p1in[0]), .clk(mclk), .data_in(p1_din[0] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_1 (.data_out(p1in[1]), .clk(mclk), .data_in(p1_din[1] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_2 (.data_out(p1in[2]), .clk(mclk), .data_in(p1_din[2] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_3 (.data_out(p1in[3]), .clk(mclk), .data_in(p1_din[3] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_4 (.data_out(p1in[4]), .clk(mclk), .data_in(p1_din[4] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_5 (.data_out(p1in[5]), .clk(mclk), .data_in(p1_din[5] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_6 (.data_out(p1in[6]), .clk(mclk), .data_in(p1_din[6] & P1_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p1in_7 (.data_out(p1in[7]), .clk(mclk), .data_in(p1_din[7] & P1_EN[0]), .rst(puc_rst)); - - -// P1OUT Register -//---------------- -reg [7:0] p1out; - -wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT] : reg_lo_wr[P1OUT]; -wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1out <= 8'h00; - else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK; - -assign p1_dout = p1out; - - -// P1DIR Register -//---------------- -reg [7:0] p1dir; - -wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR] : reg_lo_wr[P1DIR]; -wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1dir <= 8'h00; - else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK; - -assign p1_dout_en = p1dir; - - -// P1IFG Register -//---------------- -reg [7:0] p1ifg; - -wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG] : reg_lo_wr[P1IFG]; -wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0]; -wire [7:0] p1ifg_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1ifg <= 8'h00; - else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK; - else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK; - -// P1IES Register -//---------------- -reg [7:0] p1ies; - -wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES] : reg_lo_wr[P1IES]; -wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1ies <= 8'h00; - else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK; - - -// P1IE Register -//---------------- -reg [7:0] p1ie; - -wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE] : reg_lo_wr[P1IE]; -wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1ie <= 8'h00; - else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK; - - -// P1SEL Register -//---------------- -reg [7:0] p1sel; - -wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL] : reg_lo_wr[P1SEL]; -wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1sel <= 8'h00; - else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK; - -assign p1_sel = p1sel; - - -// P2IN Register -//--------------- -wire [7:0] p2in; - -omsp_sync_cell sync_cell_p2in_0 (.data_out(p2in[0]), .clk(mclk), .data_in(p2_din[0] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_1 (.data_out(p2in[1]), .clk(mclk), .data_in(p2_din[1] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_2 (.data_out(p2in[2]), .clk(mclk), .data_in(p2_din[2] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_3 (.data_out(p2in[3]), .clk(mclk), .data_in(p2_din[3] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_4 (.data_out(p2in[4]), .clk(mclk), .data_in(p2_din[4] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_5 (.data_out(p2in[5]), .clk(mclk), .data_in(p2_din[5] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_6 (.data_out(p2in[6]), .clk(mclk), .data_in(p2_din[6] & P2_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p2in_7 (.data_out(p2in[7]), .clk(mclk), .data_in(p2_din[7] & P2_EN[0]), .rst(puc_rst)); - - -// P2OUT Register -//---------------- -reg [7:0] p2out; - -wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT] : reg_lo_wr[P2OUT]; -wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2out <= 8'h00; - else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK; - -assign p2_dout = p2out; - - -// P2DIR Register -//---------------- -reg [7:0] p2dir; - -wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR] : reg_lo_wr[P2DIR]; -wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2dir <= 8'h00; - else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK; - -assign p2_dout_en = p2dir; - - -// P2IFG Register -//---------------- -reg [7:0] p2ifg; - -wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG] : reg_lo_wr[P2IFG]; -wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0]; -wire [7:0] p2ifg_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2ifg <= 8'h00; - else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK; - else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK; - - -// P2IES Register -//---------------- -reg [7:0] p2ies; - -wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES] : reg_lo_wr[P2IES]; -wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2ies <= 8'h00; - else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK; - - -// P2IE Register -//---------------- -reg [7:0] p2ie; - -wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE] : reg_lo_wr[P2IE]; -wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2ie <= 8'h00; - else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK; - - -// P2SEL Register -//---------------- -reg [7:0] p2sel; - -wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL] : reg_lo_wr[P2SEL]; -wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2sel <= 8'h00; - else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK; - -assign p2_sel = p2sel; - - -// P3IN Register -//--------------- -wire [7:0] p3in; - -omsp_sync_cell sync_cell_p3in_0 (.data_out(p3in[0]), .clk(mclk), .data_in(p3_din[0] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_1 (.data_out(p3in[1]), .clk(mclk), .data_in(p3_din[1] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_2 (.data_out(p3in[2]), .clk(mclk), .data_in(p3_din[2] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_3 (.data_out(p3in[3]), .clk(mclk), .data_in(p3_din[3] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_4 (.data_out(p3in[4]), .clk(mclk), .data_in(p3_din[4] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_5 (.data_out(p3in[5]), .clk(mclk), .data_in(p3_din[5] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_6 (.data_out(p3in[6]), .clk(mclk), .data_in(p3_din[6] & P3_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p3in_7 (.data_out(p3in[7]), .clk(mclk), .data_in(p3_din[7] & P3_EN[0]), .rst(puc_rst)); - - -// P3OUT Register -//---------------- -reg [7:0] p3out; - -wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT] : reg_lo_wr[P3OUT]; -wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p3out <= 8'h00; - else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK; - -assign p3_dout = p3out; - - -// P3DIR Register -//---------------- -reg [7:0] p3dir; - -wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR] : reg_lo_wr[P3DIR]; -wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p3dir <= 8'h00; - else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK; - -assign p3_dout_en = p3dir; - - -// P3SEL Register -//---------------- -reg [7:0] p3sel; - -wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL] : reg_lo_wr[P3SEL]; -wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p3sel <= 8'h00; - else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK; - -assign p3_sel = p3sel; - - -// P4IN Register -//--------------- -wire [7:0] p4in; - -omsp_sync_cell sync_cell_p4in_0 (.data_out(p4in[0]), .clk(mclk), .data_in(p4_din[0] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_1 (.data_out(p4in[1]), .clk(mclk), .data_in(p4_din[1] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_2 (.data_out(p4in[2]), .clk(mclk), .data_in(p4_din[2] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_3 (.data_out(p4in[3]), .clk(mclk), .data_in(p4_din[3] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_4 (.data_out(p4in[4]), .clk(mclk), .data_in(p4_din[4] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_5 (.data_out(p4in[5]), .clk(mclk), .data_in(p4_din[5] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_6 (.data_out(p4in[6]), .clk(mclk), .data_in(p4_din[6] & P4_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p4in_7 (.data_out(p4in[7]), .clk(mclk), .data_in(p4_din[7] & P4_EN[0]), .rst(puc_rst)); - - -// P4OUT Register -//---------------- -reg [7:0] p4out; - -wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT] : reg_lo_wr[P4OUT]; -wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p4out <= 8'h00; - else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK; - -assign p4_dout = p4out; - - -// P4DIR Register -//---------------- -reg [7:0] p4dir; - -wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR] : reg_lo_wr[P4DIR]; -wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p4dir <= 8'h00; - else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK; - -assign p4_dout_en = p4dir; - - -// P4SEL Register -//---------------- -reg [7:0] p4sel; - -wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL] : reg_lo_wr[P4SEL]; -wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p4sel <= 8'h00; - else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK; - -assign p4_sel = p4sel; - - -// P5IN Register -//--------------- -wire [7:0] p5in; - -omsp_sync_cell sync_cell_p5in_0 (.data_out(p5in[0]), .clk(mclk), .data_in(p5_din[0] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_1 (.data_out(p5in[1]), .clk(mclk), .data_in(p5_din[1] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_2 (.data_out(p5in[2]), .clk(mclk), .data_in(p5_din[2] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_3 (.data_out(p5in[3]), .clk(mclk), .data_in(p5_din[3] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_4 (.data_out(p5in[4]), .clk(mclk), .data_in(p5_din[4] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_5 (.data_out(p5in[5]), .clk(mclk), .data_in(p5_din[5] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_6 (.data_out(p5in[6]), .clk(mclk), .data_in(p5_din[6] & P5_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p5in_7 (.data_out(p5in[7]), .clk(mclk), .data_in(p5_din[7] & P5_EN[0]), .rst(puc_rst)); - - -// P5OUT Register -//---------------- -reg [7:0] p5out; - -wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT] : reg_lo_wr[P5OUT]; -wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p5out <= 8'h00; - else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK; - -assign p5_dout = p5out; - - -// P5DIR Register -//---------------- -reg [7:0] p5dir; - -wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR] : reg_lo_wr[P5DIR]; -wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p5dir <= 8'h00; - else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK; - -assign p5_dout_en = p5dir; - - -// P5SEL Register -//---------------- -reg [7:0] p5sel; - -wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL] : reg_lo_wr[P5SEL]; -wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p5sel <= 8'h00; - else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK; - -assign p5_sel = p5sel; - - -// P6IN Register -//--------------- -wire [7:0] p6in; - -omsp_sync_cell sync_cell_p6in_0 (.data_out(p6in[0]), .clk(mclk), .data_in(p6_din[0] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_1 (.data_out(p6in[1]), .clk(mclk), .data_in(p6_din[1] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_2 (.data_out(p6in[2]), .clk(mclk), .data_in(p6_din[2] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_3 (.data_out(p6in[3]), .clk(mclk), .data_in(p6_din[3] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_4 (.data_out(p6in[4]), .clk(mclk), .data_in(p6_din[4] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_5 (.data_out(p6in[5]), .clk(mclk), .data_in(p6_din[5] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_6 (.data_out(p6in[6]), .clk(mclk), .data_in(p6_din[6] & P6_EN[0]), .rst(puc_rst)); -omsp_sync_cell sync_cell_p6in_7 (.data_out(p6in[7]), .clk(mclk), .data_in(p6_din[7] & P6_EN[0]), .rst(puc_rst)); - - -// P6OUT Register -//---------------- -reg [7:0] p6out; - -wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT] : reg_lo_wr[P6OUT]; -wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p6out <= 8'h00; - else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK; - -assign p6_dout = p6out; - - -// P6DIR Register -//---------------- -reg [7:0] p6dir; - -wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR] : reg_lo_wr[P6DIR]; -wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p6dir <= 8'h00; - else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK; - -assign p6_dout_en = p6dir; - - -// P6SEL Register -//---------------- -reg [7:0] p6sel; - -wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL] : reg_lo_wr[P6SEL]; -wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p6sel <= 8'h00; - else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK; - -assign p6_sel = p6sel; - - - -//============================================================================ -// 4) INTERRUPT GENERATION -//============================================================================ - -// Port 1 interrupt -//------------------ - -// Delay input -reg [7:0] p1in_dly; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p1in_dly <= 8'h00; - else p1in_dly <= p1in & P1_EN_MSK; - -// Edge detection -wire [7:0] p1in_re = p1in & ~p1in_dly; -wire [7:0] p1in_fe = ~p1in & p1in_dly; - -// Set interrupt flag -assign p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7], - p1ies[6] ? p1in_fe[6] : p1in_re[6], - p1ies[5] ? p1in_fe[5] : p1in_re[5], - p1ies[4] ? p1in_fe[4] : p1in_re[4], - p1ies[3] ? p1in_fe[3] : p1in_re[3], - p1ies[2] ? p1in_fe[2] : p1in_re[2], - p1ies[1] ? p1in_fe[1] : p1in_re[1], - p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK; - -// Generate CPU interrupt -assign irq_port1 = |(p1ie & p1ifg) & P1_EN[0]; - - -// Port 1 interrupt -//------------------ - -// Delay input -reg [7:0] p2in_dly; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) p2in_dly <= 8'h00; - else p2in_dly <= p2in & P2_EN_MSK; - -// Edge detection -wire [7:0] p2in_re = p2in & ~p2in_dly; -wire [7:0] p2in_fe = ~p2in & p2in_dly; - -// Set interrupt flag -assign p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7], - p2ies[6] ? p2in_fe[6] : p2in_re[6], - p2ies[5] ? p2in_fe[5] : p2in_re[5], - p2ies[4] ? p2in_fe[4] : p2in_re[4], - p2ies[3] ? p2in_fe[3] : p2in_re[3], - p2ies[2] ? p2in_fe[2] : p2in_re[2], - p2ies[1] ? p2in_fe[1] : p2in_re[1], - p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK; - -// Generate CPU interrupt -assign irq_port2 = |(p2ie & p2ifg) & P2_EN[0]; - - -//============================================================================ -// 5) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] p1in_rd = {8'h00, (p1in & {8{reg_rd[P1IN]}})} << (8 & {4{P1IN[0]}}); -wire [15:0] p1out_rd = {8'h00, (p1out & {8{reg_rd[P1OUT]}})} << (8 & {4{P1OUT[0]}}); -wire [15:0] p1dir_rd = {8'h00, (p1dir & {8{reg_rd[P1DIR]}})} << (8 & {4{P1DIR[0]}}); -wire [15:0] p1ifg_rd = {8'h00, (p1ifg & {8{reg_rd[P1IFG]}})} << (8 & {4{P1IFG[0]}}); -wire [15:0] p1ies_rd = {8'h00, (p1ies & {8{reg_rd[P1IES]}})} << (8 & {4{P1IES[0]}}); -wire [15:0] p1ie_rd = {8'h00, (p1ie & {8{reg_rd[P1IE]}})} << (8 & {4{P1IE[0]}}); -wire [15:0] p1sel_rd = {8'h00, (p1sel & {8{reg_rd[P1SEL]}})} << (8 & {4{P1SEL[0]}}); -wire [15:0] p2in_rd = {8'h00, (p2in & {8{reg_rd[P2IN]}})} << (8 & {4{P2IN[0]}}); -wire [15:0] p2out_rd = {8'h00, (p2out & {8{reg_rd[P2OUT]}})} << (8 & {4{P2OUT[0]}}); -wire [15:0] p2dir_rd = {8'h00, (p2dir & {8{reg_rd[P2DIR]}})} << (8 & {4{P2DIR[0]}}); -wire [15:0] p2ifg_rd = {8'h00, (p2ifg & {8{reg_rd[P2IFG]}})} << (8 & {4{P2IFG[0]}}); -wire [15:0] p2ies_rd = {8'h00, (p2ies & {8{reg_rd[P2IES]}})} << (8 & {4{P2IES[0]}}); -wire [15:0] p2ie_rd = {8'h00, (p2ie & {8{reg_rd[P2IE]}})} << (8 & {4{P2IE[0]}}); -wire [15:0] p2sel_rd = {8'h00, (p2sel & {8{reg_rd[P2SEL]}})} << (8 & {4{P2SEL[0]}}); -wire [15:0] p3in_rd = {8'h00, (p3in & {8{reg_rd[P3IN]}})} << (8 & {4{P3IN[0]}}); -wire [15:0] p3out_rd = {8'h00, (p3out & {8{reg_rd[P3OUT]}})} << (8 & {4{P3OUT[0]}}); -wire [15:0] p3dir_rd = {8'h00, (p3dir & {8{reg_rd[P3DIR]}})} << (8 & {4{P3DIR[0]}}); -wire [15:0] p3sel_rd = {8'h00, (p3sel & {8{reg_rd[P3SEL]}})} << (8 & {4{P3SEL[0]}}); -wire [15:0] p4in_rd = {8'h00, (p4in & {8{reg_rd[P4IN]}})} << (8 & {4{P4IN[0]}}); -wire [15:0] p4out_rd = {8'h00, (p4out & {8{reg_rd[P4OUT]}})} << (8 & {4{P4OUT[0]}}); -wire [15:0] p4dir_rd = {8'h00, (p4dir & {8{reg_rd[P4DIR]}})} << (8 & {4{P4DIR[0]}}); -wire [15:0] p4sel_rd = {8'h00, (p4sel & {8{reg_rd[P4SEL]}})} << (8 & {4{P4SEL[0]}}); -wire [15:0] p5in_rd = {8'h00, (p5in & {8{reg_rd[P5IN]}})} << (8 & {4{P5IN[0]}}); -wire [15:0] p5out_rd = {8'h00, (p5out & {8{reg_rd[P5OUT]}})} << (8 & {4{P5OUT[0]}}); -wire [15:0] p5dir_rd = {8'h00, (p5dir & {8{reg_rd[P5DIR]}})} << (8 & {4{P5DIR[0]}}); -wire [15:0] p5sel_rd = {8'h00, (p5sel & {8{reg_rd[P5SEL]}})} << (8 & {4{P5SEL[0]}}); -wire [15:0] p6in_rd = {8'h00, (p6in & {8{reg_rd[P6IN]}})} << (8 & {4{P6IN[0]}}); -wire [15:0] p6out_rd = {8'h00, (p6out & {8{reg_rd[P6OUT]}})} << (8 & {4{P6OUT[0]}}); -wire [15:0] p6dir_rd = {8'h00, (p6dir & {8{reg_rd[P6DIR]}})} << (8 & {4{P6DIR[0]}}); -wire [15:0] p6sel_rd = {8'h00, (p6sel & {8{reg_rd[P6SEL]}})} << (8 & {4{P6SEL[0]}}); - -wire [15:0] per_dout = p1in_rd | - p1out_rd | - p1dir_rd | - p1ifg_rd | - p1ies_rd | - p1ie_rd | - p1sel_rd | - p2in_rd | - p2out_rd | - p2dir_rd | - p2ifg_rd | - p2ies_rd | - p2ie_rd | - p2sel_rd | - p3in_rd | - p3out_rd | - p3dir_rd | - p3sel_rd | - p4in_rd | - p4out_rd | - p4dir_rd | - p4sel_rd | - p5in_rd | - p5out_rd | - p5dir_rd | - p5sel_rd | - p6in_rd | - p6out_rd | - p6dir_rd | - p6sel_rd; - -endmodule // omsp_gpio

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v (nonexistent) @@ -1,79 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_timerA_defines.v -// -// *Module Description: -// omsp_timerA Configuration file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 103 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ -//---------------------------------------------------------------------------- -//`define OMSP_TA_NO_INCLUDE -`ifdef OMSP_TA_NO_INCLUDE -`else -`include "omsp_timerA_undefines.v" -`endif - -//---------------------------------------------------------------------------- -// TIMER A CONFIGURATION -//---------------------------------------------------------------------------- - - - -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// - -// Timer A: TACTL Control Register -`define TASSELx 9:8 -`define TAIDx 7:6 -`define TAMCx 5:4 -`define TACLR 2 -`define TAIE 1 -`define TAIFG 0 - -// Timer A: TACCTLx Capture/Compare Control Register -`define TACMx 15:14 -`define TACCISx 13:12 -`define TASCS 11 -`define TASCCI 10 -`define TACAP 8 -`define TAOUTMODx 7:5 -`define TACCIE 4 -`define TACCI 3 -`define TAOUT 2 -`define TACOV 1 -`define TACCIFG 0

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v (nonexistent) @@ -1,754 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_timerA.v -// -// *Module Description: -// Timer A top-level -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_TA_NO_INCLUDE -`else -`include "omsp_timerA_defines.v" -`endif - -module omsp_timerA ( - -// OUTPUTs - irq_ta0, // Timer A interrupt: TACCR0 - irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2 - per_dout, // Peripheral data output - ta_out0, // Timer A output 0 - ta_out0_en, // Timer A output 0 enable - ta_out1, // Timer A output 1 - ta_out1_en, // Timer A output 1 enable - ta_out2, // Timer A output 2 - ta_out2_en, // Timer A output 2 enable - -// INPUTs - aclk_en, // ACLK enable (from CPU) - dbg_freeze, // Freeze Timer A counter - inclk, // INCLK external timer clock (SLOW) - irq_ta0_acc, // Interrupt request TACCR0 accepted - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst, // Main system reset - smclk_en, // SMCLK enable (from CPU) - ta_cci0a, // Timer A capture 0 input A - ta_cci0b, // Timer A capture 0 input B - ta_cci1a, // Timer A capture 1 input A - ta_cci1b, // Timer A capture 1 input B - ta_cci2a, // Timer A capture 2 input A - ta_cci2b, // Timer A capture 2 input B - taclk // TACLK external timer clock (SLOW) -); - -// OUTPUTs -//========= -output irq_ta0; // Timer A interrupt: TACCR0 -output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2 -output [15:0] per_dout; // Peripheral data output -output ta_out0; // Timer A output 0 -output ta_out0_en; // Timer A output 0 enable -output ta_out1; // Timer A output 1 -output ta_out1_en; // Timer A output 1 enable -output ta_out2; // Timer A output 2 -output ta_out2_en; // Timer A output 2 enable - -// INPUTs -//========= -input aclk_en; // ACLK enable (from CPU) -input dbg_freeze; // Freeze Timer A counter -input inclk; // INCLK external timer clock (SLOW) -input irq_ta0_acc; // Interrupt request TACCR0 accepted -input mclk; // Main system clock -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset -input smclk_en; // SMCLK enable (from CPU) -input ta_cci0a; // Timer A capture 0 input A -input ta_cci0b; // Timer A capture 0 input B -input ta_cci1a; // Timer A capture 1 input A -input ta_cci1b; // Timer A capture 1 input B -input ta_cci2a; // Timer A capture 2 input A -input ta_cci2b; // Timer A capture 2 input B -input taclk; // TACLK external timer clock (SLOW) - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0100; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 7; - -// Register addresses offset -parameter [DEC_WD-1:0] TACTL = 'h60, - TAR = 'h70, - TACCTL0 = 'h62, - TACCR0 = 'h72, - TACCTL1 = 'h64, - TACCR1 = 'h74, - TACCTL2 = 'h66, - TACCR2 = 'h76, - TAIV = 'h2E; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL), - TAR_D = (BASE_REG << TAR), - TACCTL0_D = (BASE_REG << TACCTL0), - TACCR0_D = (BASE_REG << TACCR0), - TACCTL1_D = (BASE_REG << TACCTL1), - TACCR1_D = (BASE_REG << TACCR1), - TACCTL2_D = (BASE_REG << TACCTL2), - TACCR2_D = (BASE_REG << TACCR2), - TAIV_D = (BASE_REG << TAIV); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) | - (TAR_D & {DEC_SZ{(reg_addr == TAR )}}) | - (TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) | - (TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) | - (TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) | - (TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) | - (TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) | - (TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) | - (TAIV_D & {DEC_SZ{(reg_addr == TAIV )}}); - -// Read/Write probes -wire reg_write = |per_we & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// TACTL Register -//----------------- -reg [9:0] tactl; - -wire tactl_wr = reg_wr[TACTL]; -wire taclr = tactl_wr & per_din[`TACLR]; -wire taifg_set; -wire taifg_clr; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tactl <= 10'h000; - else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; - else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; - - -// TAR Register -//----------------- -reg [15:0] tar; - -wire tar_wr = reg_wr[TAR]; - -wire tar_clk; -wire tar_clr; -wire tar_inc; -wire tar_dec; -wire [15:0] tar_add = tar_inc ? 16'h0001 : - tar_dec ? 16'hffff : 16'h0000; -wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add); - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tar <= 16'h0000; - else if (tar_wr) tar <= per_din; - else if (taclr) tar <= 16'h0000; - else if (tar_clk & ~dbg_freeze) tar <= tar_nxt; - - -// TACCTL0 Register -//------------------ -reg [15:0] tacctl0; - -wire tacctl0_wr = reg_wr[TACCTL0]; -wire ccifg0_set; -wire cov0_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tacctl0 <= 16'h0000; - else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; - else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; - -wire cci0; -reg scci0; -wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0}; - - -// TACCR0 Register -//------------------ -reg [15:0] taccr0; - -wire taccr0_wr = reg_wr[TACCR0]; -wire cci0_cap; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) taccr0 <= 16'h0000; - else if (taccr0_wr) taccr0 <= per_din; - else if (cci0_cap) taccr0 <= tar; - - -// TACCTL1 Register -//------------------ -reg [15:0] tacctl1; - -wire tacctl1_wr = reg_wr[TACCTL1]; -wire ccifg1_set; -wire ccifg1_clr; -wire cov1_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tacctl1 <= 16'h0000; - else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; - else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; - -wire cci1; -reg scci1; -wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0}; - - -// TACCR1 Register -//------------------ -reg [15:0] taccr1; - -wire taccr1_wr = reg_wr[TACCR1]; -wire cci1_cap; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) taccr1 <= 16'h0000; - else if (taccr1_wr) taccr1 <= per_din; - else if (cci1_cap) taccr1 <= tar; - - -// TACCTL2 Register -//------------------ -reg [15:0] tacctl2; - -wire tacctl2_wr = reg_wr[TACCTL2]; -wire ccifg2_set; -wire ccifg2_clr; -wire cov2_set; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tacctl2 <= 16'h0000; - else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; - else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; - -wire cci2; -reg scci2; -wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0}; - - -// TACCR2 Register -//------------------ -reg [15:0] taccr2; - -wire taccr2_wr = reg_wr[TACCR2]; -wire cci2_cap; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) taccr2 <= 16'h0000; - else if (taccr2_wr) taccr2 <= per_din; - else if (cci2_cap) taccr2 <= tar; - - -// TAIV Register -//------------------ - -wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 : - (tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 : - (tactl[`TAIFG] & tactl[`TAIE]) ? 4'hA : - 4'h0; - -assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2); -assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4); -assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA); - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] tactl_rd = {6'h00, tactl} & {16{reg_rd[TACTL]}}; -wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}}; -wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}}; -wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}}; -wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}}; -wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}}; -wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}}; -wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}}; -wire [15:0] taiv_rd = {12'h000, taiv} & {16{reg_rd[TAIV]}}; - -wire [15:0] per_dout = tactl_rd | - tar_rd | - tacctl0_rd | - taccr0_rd | - tacctl1_rd | - taccr1_rd | - tacctl2_rd | - taccr2_rd | - taiv_rd; - - -//============================================================================ -// 5) Timer A counter control -//============================================================================ - -// Clock input synchronization (TACLK & INCLK) -//----------------------------------------------------------- -wire taclk_s; -wire inclk_s; - -omsp_sync_cell sync_cell_taclk ( - .data_out (taclk_s), - .clk (mclk), - .data_in (taclk), - .rst (puc_rst) -); - -omsp_sync_cell sync_cell_inclk ( - .data_out (inclk_s), - .clk (mclk), - .data_in (inclk), - .rst (puc_rst) -); - - -// Clock edge detection (TACLK & INCLK) -//----------------------------------------------------------- - -reg taclk_dly; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) taclk_dly <= 1'b0; - else taclk_dly <= taclk_s; - -wire taclk_en = taclk_s & ~taclk_dly; - - -reg inclk_dly; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) inclk_dly <= 1'b0; - else inclk_dly <= inclk_s; - -wire inclk_en = inclk_s & ~inclk_dly; - - -// Timer clock input mux -//----------------------------------------------------------- - -wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en : - (tactl[`TASSELx]==2'b01) ? aclk_en : - (tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en; - - -// Generate update pluse for the counter (<=> divided clock) -//----------------------------------------------------------- -reg [2:0] clk_div; - -assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 : - (tactl[`TAIDx]==2'b01) ? clk_div[0] : - (tactl[`TAIDx]==2'b10) ? &clk_div[1:0] : - &clk_div[2:0]); - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) clk_div <= 3'h0; - else if (tar_clk | taclr) clk_div <= 3'h0; - else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1; - - -// Time counter control signals -//----------------------------------------------------------- - -assign tar_clr = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0)) | - ((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000)); - -assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) | - ((tactl[`TAMCx]==2'b11) & ~tar_dec); - -reg tar_dir; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) tar_dir <= 1'b0; - else if (taclr) tar_dir <= 1'b0; - else if (tactl[`TAMCx]==2'b11) - begin - if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0; - else if (tar>=taccr0) tar_dir <= 1'b1; - end - else tar_dir <= 1'b0; - -assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0)); - - -//============================================================================ -// 6) Timer A comparator -//============================================================================ - -wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0); -wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1); -wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2); - - -//============================================================================ -// 7) Timer A capture logic -//============================================================================ - -// Input selection -//------------------ -assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a : - (tacctl0[`TACCISx]==2'b01) ? ta_cci0b : - (tacctl0[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a : - (tacctl1[`TACCISx]==2'b01) ? ta_cci1b : - (tacctl1[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a : - (tacctl2[`TACCISx]==2'b01) ? ta_cci2b : - (tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -// CCIx synchronization -wire cci0_s; -wire cci1_s; -wire cci2_s; - -omsp_sync_cell sync_cell_cci0 ( - .data_out (cci0_s), - .clk (mclk), - .data_in (cci0), - .rst (puc_rst) -); -omsp_sync_cell sync_cell_cci1 ( - .data_out (cci1_s), - .clk (mclk), - .data_in (cci1), - .rst (puc_rst) -); -omsp_sync_cell sync_cell_cci2 ( - .data_out (cci2_s), - .clk (mclk), - .data_in (cci2), - .rst (puc_rst) -); - -// Register CCIx for edge detection -reg cci0_dly; -reg cci1_dly; -reg cci2_dly; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) - begin - cci0_dly <= 1'b0; - cci1_dly <= 1'b0; - cci2_dly <= 1'b0; - end - else - begin - cci0_dly <= cci0_s; - cci1_dly <= cci1_s; - cci2_dly <= cci2_s; - end - - -// Generate SCCIx -//------------------ - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) scci0 <= 1'b0; - else if (tar_clk & equ0) scci0 <= cci0_s; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) scci1 <= 1'b0; - else if (tar_clk & equ1) scci1 <= cci1_s; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) scci2 <= 1'b0; - else if (tar_clk & equ2) scci2 <= cci2_s; - - -// Capture mode -//------------------ -wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 : - (tacctl0[`TACMx]==2'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge - (tacctl0[`TACMx]==2'b10) ? (~cci0_s & cci0_dly) : // Falling edge - ( cci0_s ^ cci0_dly); // Both edges - -wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 : - (tacctl1[`TACMx]==2'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge - (tacctl1[`TACMx]==2'b10) ? (~cci1_s & cci1_dly) : // Falling edge - ( cci1_s ^ cci1_dly); // Both edges - -wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 : - (tacctl2[`TACMx]==2'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge - (tacctl2[`TACMx]==2'b10) ? (~cci2_s & cci2_dly) : // Falling edge - ( cci2_s ^ cci2_dly); // Both edges - -// Event Synchronization -//----------------------- - -reg cci0_evt_s; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci0_evt_s <= 1'b0; - else if (tar_clk) cci0_evt_s <= 1'b0; - else if (cci0_evt) cci0_evt_s <= 1'b1; - -reg cci1_evt_s; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci1_evt_s <= 1'b0; - else if (tar_clk) cci1_evt_s <= 1'b0; - else if (cci1_evt) cci1_evt_s <= 1'b1; - -reg cci2_evt_s; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci2_evt_s <= 1'b0; - else if (tar_clk) cci2_evt_s <= 1'b0; - else if (cci2_evt) cci2_evt_s <= 1'b1; - -reg cci0_sync; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci0_sync <= 1'b0; - else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s); - -reg cci1_sync; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci1_sync <= 1'b0; - else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s); - -reg cci2_sync; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cci2_sync <= 1'b0; - else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s); - - -// Generate final capture command -//----------------------------------- - -assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt; -assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt; -assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt; - - -// Generate capture overflow flag -//----------------------------------- - -reg cap0_taken; -wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cap0_taken <= 1'b0; - else if (cci0_cap) cap0_taken <= 1'b1; - else if (cap0_taken_clr) cap0_taken <= 1'b0; - -reg cap1_taken; -wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cap1_taken <= 1'b0; - else if (cci1_cap) cap1_taken <= 1'b1; - else if (cap1_taken_clr) cap1_taken <= 1'b0; - -reg cap2_taken; -wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cap2_taken <= 1'b0; - else if (cci2_cap) cap2_taken <= 1'b1; - else if (cap2_taken_clr) cap2_taken <= 1'b0; - - -assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0]; -assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1]; -assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2]; - - -//============================================================================ -// 8) Timer A output unit -//============================================================================ - -// Output unit 0 -//------------------- -reg ta_out0; - -wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output -wire ta_out0_mode1 = equ0 ? 1'b1 : ta_out0; // Set -wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset - equ0 ? 1'b0 : ta_out0; -wire ta_out0_mode3 = equ0 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out0; -wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle -wire ta_out0_mode5 = equ0 ? 1'b0 : ta_out0; // Reset -wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set - equ0 ? 1'b1 : ta_out0; -wire ta_out0_mode7 = equ0 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out0; - -wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 : - (tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 : - (tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 : - (tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 : - (tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 : - (tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 : - (tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 : - ta_out0_mode7; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) ta_out0 <= 1'b0; - else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0; - else if (tar_clk) ta_out0 <= ta_out0_nxt; - -assign ta_out0_en = ~tacctl0[`TACAP]; - - -// Output unit 1 -//------------------- -reg ta_out1; - -wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output -wire ta_out1_mode1 = equ1 ? 1'b1 : ta_out1; // Set -wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset - equ0 ? 1'b0 : ta_out1; -wire ta_out1_mode3 = equ1 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out1; -wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle -wire ta_out1_mode5 = equ1 ? 1'b0 : ta_out1; // Reset -wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set - equ0 ? 1'b1 : ta_out1; -wire ta_out1_mode7 = equ1 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out1; - -wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 : - (tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 : - (tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 : - (tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 : - (tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 : - (tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 : - (tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 : - ta_out1_mode7; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) ta_out1 <= 1'b0; - else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0; - else if (tar_clk) ta_out1 <= ta_out1_nxt; - -assign ta_out1_en = ~tacctl1[`TACAP]; - - -// Output unit 2 -//------------------- -reg ta_out2; - -wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output -wire ta_out2_mode1 = equ2 ? 1'b1 : ta_out2; // Set -wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset - equ0 ? 1'b0 : ta_out2; -wire ta_out2_mode3 = equ2 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out2; -wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle -wire ta_out2_mode5 = equ2 ? 1'b0 : ta_out2; // Reset -wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set - equ0 ? 1'b1 : ta_out2; -wire ta_out2_mode7 = equ2 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out2; - -wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 : - (tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 : - (tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 : - (tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 : - (tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 : - (tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 : - (tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 : - ta_out2_mode7; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) ta_out2 <= 1'b0; - else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0; - else if (tar_clk) ta_out2 <= ta_out2_nxt; - -assign ta_out2_en = ~tacctl2[`TACAP]; - - -//============================================================================ -// 9) Timer A interrupt generation -//============================================================================ - - -assign taifg_set = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0)) | - ((tactl[`TAMCx]==2'b10) & (tar==16'hffff)) | - ((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec)); - -assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ0)); -assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ1)); -assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ2)); - - -wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]); - -wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) | - (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) | - (tacctl2[`TACCIFG] & tacctl2[`TACCIE]); - - -endmodule // omsp_timerA - -`ifdef OMSP_TA_NO_INCLUDE -`else -`include "omsp_timerA_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v (nonexistent) @@ -1,108 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_timerA_undefines.v -// -// *Module Description: -// omsp_timerA Verilog `undef file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 23 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ -//---------------------------------------------------------------------------- - -//---------------------------------------------------------------------------- -// SYSTEM CONFIGURATION -//---------------------------------------------------------------------------- - - - -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// - -// Timer A: TACTL Control Register -`ifdef TASSELx -`undef TASSELx -`endif -`ifdef TAIDx -`undef TAIDx -`endif -`ifdef TAMCx -`undef TAMCx -`endif -`ifdef TACLR -`undef TACLR -`endif -`ifdef TAIE -`undef TAIE -`endif -`ifdef TAIFG -`undef TAIFG -`endif - -// Timer A: TACCTLx Capture/Compare Control Register -`ifdef TACMx -`undef TACMx -`endif -`ifdef TACCISx -`undef TACCISx -`endif -`ifdef TASCS -`undef TASCS -`endif -`ifdef TASCCI -`undef TASCCI -`endif -`ifdef TACAP -`undef TACAP -`endif -`ifdef TAOUTMODx -`undef TAOUTMODx -`endif -`ifdef TACCIE -`undef TACCIE -`endif -`ifdef TACCI -`undef TACCI -`endif -`ifdef TAOUT -`undef TAOUT -`endif -`ifdef TACOV -`undef TACOV -`endif -`ifdef TACCIFG -`undef TACCIFG -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v (nonexistent) @@ -1,356 +0,0 @@ - -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_multiplier.v -// -// *Module Description: -// 16x16 Hardware multiplier. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 23 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_multiplier ( - -// OUTPUTs - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input puc_rst; // Main system reset - - -//============================================================================= -// 1) PARAMETER/REGISTERS & WIRE DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0130; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 4; - -// Register addresses offset -parameter [DEC_WD-1:0] OP1_MPY = 'h0, - OP1_MPYS = 'h2, - OP1_MAC = 'h4, - OP1_MACS = 'h6, - OP2 = 'h8, - RESLO = 'hA, - RESHI = 'hC, - SUMEXT = 'hE; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY), - OP1_MPYS_D = (BASE_REG << OP1_MPYS), - OP1_MAC_D = (BASE_REG << OP1_MAC), - OP1_MACS_D = (BASE_REG << OP1_MACS), - OP2_D = (BASE_REG << OP2), - RESLO_D = (BASE_REG << RESLO), - RESHI_D = (BASE_REG << RESHI), - SUMEXT_D = (BASE_REG << SUMEXT); - - -// Wire pre-declarations -wire result_wr; -wire result_clr; -wire early_read; - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (OP1_MPY_D & {DEC_SZ{(reg_addr == OP1_MPY )}}) | - (OP1_MPYS_D & {DEC_SZ{(reg_addr == OP1_MPYS )}}) | - (OP1_MAC_D & {DEC_SZ{(reg_addr == OP1_MAC )}}) | - (OP1_MACS_D & {DEC_SZ{(reg_addr == OP1_MACS )}}) | - (OP2_D & {DEC_SZ{(reg_addr == OP2 )}}) | - (RESLO_D & {DEC_SZ{(reg_addr == RESLO )}}) | - (RESHI_D & {DEC_SZ{(reg_addr == RESHI )}}) | - (SUMEXT_D & {DEC_SZ{(reg_addr == SUMEXT )}}); - -// Read/Write probes -wire reg_write = |per_we & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// OP1 Register -//----------------- -reg [15:0] op1; - -wire op1_wr = reg_wr[OP1_MPY] | - reg_wr[OP1_MPYS] | - reg_wr[OP1_MAC] | - reg_wr[OP1_MACS]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) op1 <= 16'h0000; - else if (op1_wr) op1 <= per_din; - -wire [15:0] op1_rd = op1; - - -// OP2 Register -//----------------- -reg [15:0] op2; - -wire op2_wr = reg_wr[OP2]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) op2 <= 16'h0000; - else if (op2_wr) op2 <= per_din; - -wire [15:0] op2_rd = op2; - - -// RESLO Register -//----------------- -reg [15:0] reslo; - -wire [15:0] reslo_nxt; -wire reslo_wr = reg_wr[RESLO]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) reslo <= 16'h0000; - else if (reslo_wr) reslo <= per_din; - else if (result_clr) reslo <= 16'h0000; - else if (result_wr) reslo <= reslo_nxt; - -wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo; - - -// RESHI Register -//----------------- -reg [15:0] reshi; - -wire [15:0] reshi_nxt; -wire reshi_wr = reg_wr[RESHI]; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) reshi <= 16'h0000; - else if (reshi_wr) reshi <= per_din; - else if (result_clr) reshi <= 16'h0000; - else if (result_wr) reshi <= reshi_nxt; - -wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi; - - -// SUMEXT Register -//----------------- -reg [1:0] sumext_s; - -wire [1:0] sumext_s_nxt; - -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) sumext_s <= 2'b00; - else if (op2_wr) sumext_s <= 2'b00; - else if (result_wr) sumext_s <= sumext_s_nxt; - -wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt}; -wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s}; -wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] | - reg_rd[OP1_MPYS] | - reg_rd[OP1_MAC] | - reg_rd[OP1_MACS]}}; -wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}}; -wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}}; -wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}}; -wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}}; - -wire [15:0] per_dout = op1_mux | - op2_mux | - reslo_mux | - reshi_mux | - sumext_mux; - - -//============================================================================ -// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC -//============================================================================ - -// Multiplier configuration -//-------------------------- - -// Detect signed mode -reg sign_sel; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) sign_sel <= 1'b0; - else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS]; - - -// Detect accumulate mode -reg acc_sel; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) acc_sel <= 1'b0; - else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS]; - - -// Detect whenever the RESHI and RESLO registers should be cleared -assign result_clr = op2_wr & ~acc_sel; - -// Combine RESHI & RESLO -wire [31:0] result = {reshi, reslo}; - - -// 16x16 Multiplier (result computed in 1 clock cycle) -//----------------------------------------------------- -`ifdef MPY_16x16 - -// Detect start of a multiplication -reg cycle; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cycle <= 1'b0; - else cycle <= op2_wr; - -assign result_wr = cycle; - -// Expand the operands to support signed & unsigned operations -wire signed [16:0] op1_xp = {sign_sel & op1[15], op1}; -wire signed [16:0] op2_xp = {sign_sel & op2[15], op2}; - - -// 17x17 signed multiplication -wire signed [33:0] product = op1_xp * op2_xp; - -// Accumulate -wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]}; - - -// Next register values -assign reslo_nxt = result_nxt[15:0]; -assign reshi_nxt = result_nxt[31:16]; -assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} : - {1'b0, result_nxt[32]}; - - -// Since the MAC is completed within 1 clock cycle, -// an early read can't happen. -assign early_read = 1'b0; - - -// 16x8 Multiplier (result computed in 2 clock cycles) -//----------------------------------------------------- -`else - -// Detect start of a multiplication -reg [1:0] cycle; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) cycle <= 2'b00; - else cycle <= {cycle[0], op2_wr}; - -assign result_wr = |cycle; - - -// Expand the operands to support signed & unsigned operations -wire signed [16:0] op1_xp = {sign_sel & op1[15], op1}; -wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]}; -wire signed [8:0] op2_lo_xp = { 1'b0, op2[7:0]}; -wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp; - - -// 17x9 signed multiplication -wire signed [25:0] product = op1_xp * op2_xp; - -wire [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} : - {{8{sign_sel & product[23]}}, product[23:0]}; - -// Accumulate -wire [32:0] result_nxt = {1'b0, result} + {1'b0, product_xp[31:0]}; - - -// Next register values -assign reslo_nxt = result_nxt[15:0]; -assign reshi_nxt = result_nxt[31:16]; -assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} : - {1'b0, result_nxt[32] | sumext_s[0]}; - -// Since the MAC is completed within 2 clock cycle, -// an early read can happen during the second cycle. -assign early_read = cycle[1]; - -`endif - - -endmodule // omsp_multiplier - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v (nonexistent) @@ -1,290 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_dbg_uart.v -// -// *Module Description: -// Debug UART communication interface (8N1, Half-duplex) -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_dbg_uart ( - -// OUTPUTs - dbg_addr, // Debug register address - dbg_din, // Debug register data input - dbg_rd, // Debug register data read - dbg_uart_txd, // Debug interface: UART TXD - dbg_wr, // Debug register data write - -// INPUTs - dbg_clk, // Debug unit clock - dbg_dout, // Debug register data output - dbg_rd_rdy, // Debug register data is ready for read - dbg_rst, // Debug unit reset - dbg_uart_rxd, // Debug interface: UART RXD - mem_burst, // Burst on going - mem_burst_end, // End TX/RX burst - mem_burst_rd, // Start TX burst - mem_burst_wr, // Start RX burst - mem_bw // Burst byte width -); - -// OUTPUTs -//========= -output [5:0] dbg_addr; // Debug register address -output [15:0] dbg_din; // Debug register data input -output dbg_rd; // Debug register data read -output dbg_uart_txd; // Debug interface: UART TXD -output dbg_wr; // Debug register data write - -// INPUTs -//========= -input dbg_clk; // Debug unit clock -input [15:0] dbg_dout; // Debug register data output -input dbg_rd_rdy; // Debug register data is ready for read -input dbg_rst; // Debug unit reset -input dbg_uart_rxd; // Debug interface: UART RXD -input mem_burst; // Burst on going -input mem_burst_end; // End TX/RX burst -input mem_burst_rd; // Start TX burst -input mem_burst_wr; // Start RX burst -input mem_bw; // Burst byte width - - -//============================================================================= -// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING -//============================================================================= - -// Synchronize RXD input -//-------------------------------- -`ifdef SYNC_DBG_UART_RXD - - wire uart_rxd_n; - - omsp_sync_cell sync_cell_uart_rxd ( - .data_out (uart_rxd_n), - .clk (dbg_clk), - .data_in (~dbg_uart_rxd), - .rst (dbg_rst) - ); - wire uart_rxd = ~uart_rxd_n; -`else - wire uart_rxd = dbg_uart_rxd; -`endif - -// RXD input buffer -//-------------------------------- -reg [1:0] rxd_buf; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) rxd_buf <= 2'h3; - else rxd_buf <= {rxd_buf[0], uart_rxd}; - -// Majority decision -//------------------------ -reg rxd_maj; - -wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd} + - {1'b0, rxd_buf[0]} + - {1'b0, rxd_buf[1]}; -wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10); - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) rxd_maj <= 1'b0; - else rxd_maj <= rxd_maj_nxt; - -wire rxd_s = rxd_maj; -wire rxd_fe = rxd_maj & ~rxd_maj_nxt; -wire rxd_re = ~rxd_maj & rxd_maj_nxt; - - -//============================================================================= -// 2) UART STATE MACHINE -//============================================================================= - -// Receive state -//------------------------ -reg [2:0] uart_state; -reg [2:0] uart_state_nxt; - -wire sync_done; -wire xfer_done; -reg [19:0] xfer_buf; - -// State machine definition -parameter RX_SYNC = 3'h0; -parameter RX_CMD = 3'h1; -parameter RX_DATA1 = 3'h2; -parameter RX_DATA2 = 3'h3; -parameter TX_DATA1 = 3'h4; -parameter TX_DATA2 = 3'h5; - -// State transition -always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw) - case (uart_state) - RX_SYNC : uart_state_nxt = RX_CMD; - RX_CMD : uart_state_nxt = mem_burst_wr ? - (mem_bw ? RX_DATA2 : RX_DATA1) : - mem_burst_rd ? - (mem_bw ? TX_DATA2 : TX_DATA1) : - (xfer_buf[`DBG_UART_WR] ? - (xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) : - (xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1)); - RX_DATA1 : uart_state_nxt = RX_DATA2; - RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? - (mem_bw ? RX_DATA2 : RX_DATA1) : - RX_CMD; - TX_DATA1 : uart_state_nxt = TX_DATA2; - TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? - (mem_bw ? TX_DATA2 : TX_DATA1) : - RX_CMD; - default : uart_state_nxt = RX_CMD; - endcase - -// State machine -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) uart_state <= RX_SYNC; - else if (xfer_done | sync_done | - mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt; - -// Utility signals -wire cmd_valid = (uart_state==RX_CMD) & xfer_done; -wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2); - - -//============================================================================= -// 3) UART SYNCHRONIZATION -//============================================================================= -// After DBG_RST, the host needs to fist send a synchronization character (0x80) -// If this feature doesn't work properly, it is possible to disable it by -// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file. - -reg sync_busy; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) sync_busy <= 1'b0; - else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1; - else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0; - -assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy; - -`ifdef DBG_UART_AUTO_SYNC - -reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000}; - else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1}; - -wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3]; -`else -wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT; -`endif - - -//============================================================================= -// 4) UART RECEIVE / TRANSMIT -//============================================================================= - -// Transfer counter -//------------------------ -reg [3:0] xfer_bit; -reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt; - -wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1)); -wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC)); -wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}}); -assign xfer_done = (xfer_bit==4'hb); - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) xfer_bit <= 4'h0; - else if (txd_start | rxd_start) xfer_bit <= 4'h1; - else if (xfer_done) xfer_bit <= 4'h0; - else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}}; - else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]}; - else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max; - else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}}; - - -// Receive/Transmit buffer -//------------------------- -wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]}; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) xfer_buf <= 20'h00000; - else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0}; - else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt; - - -// Generate TXD output -//------------------------ -reg dbg_uart_txd; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) dbg_uart_txd <= 1'b1; - else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0]; - - -//============================================================================= -// 5) INTERFACE TO DEBUG REGISTERS -//============================================================================= - -reg [5:0] dbg_addr; - always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) dbg_addr <= 6'h00; - else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR]; - -reg dbg_bw; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) dbg_bw <= 1'b0; - else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW]; - -wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw; - -wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} : - {xfer_buf[18:11], xfer_buf[8:1]}; -wire dbg_wr = (xfer_done & (uart_state==RX_DATA2)); -wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) : - (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd; - - - -endmodule // omsp_dbg_uart - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v (nonexistent) @@ -1,277 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_dbg_hwbrk.v -// -// *Module Description: -// Hardware Breakpoint / Watchpoint module -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 109 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_dbg_hwbrk ( - -// OUTPUTs - brk_halt, // Hardware breakpoint command - brk_pnd, // Hardware break/watch-point pending - brk_dout, // Hardware break/watch-point register data input - -// INPUTs - brk_reg_rd, // Hardware break/watch-point register read select - brk_reg_wr, // Hardware break/watch-point register write select - dbg_clk, // Debug unit clock - dbg_din, // Debug register data input - dbg_rst, // Debug unit reset - eu_mab, // Execution-Unit Memory address bus - eu_mb_en, // Execution-Unit Memory bus enable - eu_mb_wr, // Execution-Unit Memory bus write transfer - eu_mdb_in, // Memory data bus input - eu_mdb_out, // Memory data bus output - exec_done, // Execution completed - fe_mb_en, // Frontend Memory bus enable - pc // Program counter -); - -// OUTPUTs -//========= -output brk_halt; // Hardware breakpoint command -output brk_pnd; // Hardware break/watch-point pending -output [15:0] brk_dout; // Hardware break/watch-point register data input - -// INPUTs -//========= -input [3:0] brk_reg_rd; // Hardware break/watch-point register read select -input [3:0] brk_reg_wr; // Hardware break/watch-point register write select -input dbg_clk; // Debug unit clock -input [15:0] dbg_din; // Debug register data input -input dbg_rst; // Debug unit reset -input [15:0] eu_mab; // Execution-Unit Memory address bus -input eu_mb_en; // Execution-Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer -input [15:0] eu_mdb_in; // Memory data bus input -input [15:0] eu_mdb_out; // Memory data bus output -input exec_done; // Execution completed -input fe_mb_en; // Frontend Memory bus enable -input [15:0] pc; // Program counter - - -//============================================================================= -// 1) WIRE & PARAMETER DECLARATION -//============================================================================= - -wire range_wr_set; -wire range_rd_set; -wire addr1_wr_set; -wire addr1_rd_set; -wire addr0_wr_set; -wire addr0_rd_set; - - -parameter BRK_CTL = 0, - BRK_STAT = 1, - BRK_ADDR0 = 2, - BRK_ADDR1 = 3; - - -//============================================================================= -// 2) CONFIGURATION REGISTERS -//============================================================================= - -// BRK_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE -// -// ACCESS_MODE: - 00 : Disabled -// - 01 : Detect read access -// - 10 : Detect write access -// - 11 : Detect read/write access -// NOTE: '10' & '11' modes are not supported on the instruction flow -// -// BREAK_EN: - 0 : Watchmode enable -// - 1 : Break enable -// -// INST_EN: - 0 : Checks are done on the execution unit (data flow) -// - 1 : Checks are done on the frontend (instruction flow) -// -// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1 -// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range -// -//----------------------------------------------------------------------------- -reg [4:0] brk_ctl; - -wire brk_ctl_wr = brk_reg_wr[BRK_CTL]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) brk_ctl <= 5'h00; - else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]}; - -wire [7:0] brk_ctl_full = {3'b000, brk_ctl}; - - -// BRK_STAT Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD -//----------------------------------------------------------------------------- -reg [5:0] brk_stat; - -wire brk_stat_wr = brk_reg_wr[BRK_STAT]; -wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE, - range_rd_set & `HWBRK_RANGE, - addr1_wr_set, addr1_rd_set, - addr0_wr_set, addr0_rd_set}; -wire [5:0] brk_stat_clr = ~dbg_din[5:0]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) brk_stat <= 6'h00; - else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set); - else brk_stat <= (brk_stat | brk_stat_set); - -wire [7:0] brk_stat_full = {2'b00, brk_stat}; -wire brk_pnd = |brk_stat; - - -// BRK_ADDR0 Register -//----------------------------------------------------------------------------- -reg [15:0] brk_addr0; - -wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) brk_addr0 <= 16'h0000; - else if (brk_addr0_wr) brk_addr0 <= dbg_din; - - -// BRK_ADDR1/DATA0 Register -//----------------------------------------------------------------------------- -reg [15:0] brk_addr1; - -wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) brk_addr1 <= 16'h0000; - else if (brk_addr1_wr) brk_addr1 <= dbg_din; - - -//============================================================================ -// 3) DATA OUTPUT GENERATION -//============================================================================ - -wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}}; -wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}}; -wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}}; -wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}}; - -wire [15:0] brk_dout = brk_ctl_rd | - brk_stat_rd | - brk_addr0_rd | - brk_addr1_rd; - - -//============================================================================ -// 4) BREAKPOINT / WATCHPOINT GENERATION -//============================================================================ - -// Comparators -//--------------------------- -// Note: here the comparison logic is instanciated several times in order -// to improve the timings, at the cost of a bit more area. - -wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE]; -wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE]; -wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & - brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; - -reg fe_mb_en_buf; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) fe_mb_en_buf <= 1'b0; - else fe_mb_en_buf <= fe_mb_en; - -wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; -wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; -wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & - brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; - - -// Detect accesses -//--------------------------- - -// Detect Instruction read access -wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN]; -wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN]; -wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN]; - -// Detect Execution-Unit write access -wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; -wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; -wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; - -// Detect DATA read access -// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read -// before being written back. In that case, the read flag should not be set. -// In general, We should here make sure no write access occures during the -// same instruction cycle before setting the read flag. -reg [2:0] d_rd_trig; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) d_rd_trig <= 3'h0; - else if (exec_done) d_rd_trig <= 3'h0; - else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, - equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, - equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr}; - -wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr; -wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr; -wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr; - - -// Set flags -assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd); -assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr; -assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd); -assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr; -assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd); -assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr; - - -// Break CPU -assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set; - - -endmodule // omsp_dbg_hwbrk - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v (nonexistent) @@ -1,220 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_sfr.v -// -// *Module Description: -// Processor Special function register -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_sfr ( - -// OUTPUTs - nmie, // Non-maskable interrupt enable - per_dout, // Peripheral data output - wdt_irq, // Watchdog-timer interrupt - wdt_reset, // Watchdog-timer reset - wdtie, // Watchdog-timer interrupt enable - -// INPUTs - mclk, // Main system clock - nmi_acc, // Non-Maskable interrupt request accepted - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_we, // Peripheral write enable (high active) - por, // Power-on reset - puc_rst, // Main system reset - wdtifg_clr, // Clear Watchdog-timer interrupt flag - wdtifg_set, // Set Watchdog-timer interrupt flag - wdtpw_error, // Watchdog-timer password error - wdttmsel // Watchdog-timer mode select -); - -// OUTPUTs -//========= -output nmie; // Non-maskable interrupt enable -output [15:0] per_dout; // Peripheral data output -output wdt_irq; // Watchdog-timer interrupt -output wdt_reset; // Watchdog-timer reset -output wdtie; // Watchdog-timer interrupt enable - -// INPUTs -//========= -input mclk; // Main system clock -input nmi_acc; // Non-Maskable interrupt request accepted -input [13:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_we; // Peripheral write enable (high active) -input por; // Power-on reset -input puc_rst; // Main system reset -input wdtifg_clr; // Clear Watchdog-timer interrupt flag -input wdtifg_set; // Set Watchdog-timer interrupt flag -input wdtpw_error; // Watchdog-timer password error -input wdttmsel; // Watchdog-timer mode select - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register base address (must be aligned to decoder bit width) -parameter [14:0] BASE_ADDR = 15'h0000; - -// Decoder bit width (defines how many bits are considered for address decoding) -parameter DEC_WD = 2; - -// Register addresses offset -parameter [DEC_WD-1:0] IE1 = 'h0, - IFG1 = 'h2; - -// Register one-hot decoder utilities -parameter DEC_SZ = 2**DEC_WD; -parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; - -// Register one-hot decoder -parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1), - IFG1_D = (BASE_REG << IFG1); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Local register selection -wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); - -// Register local address -wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]}; - -// Register address decode -wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) | - (IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}); - -// Read/Write probes -wire reg_lo_write = per_we[0] & reg_sel; -wire reg_hi_write = per_we[1] & reg_sel; -wire reg_read = ~|per_we & reg_sel; - -// Read/Write vectors -wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}}; -wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}}; -wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// IE1 Register -//-------------- -wire [7:0] ie1; -wire ie1_wr = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1]; -wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0]; - -reg nmie; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) nmie <= 1'b0; - else if (nmi_acc) nmie <= 1'b0; - else if (ie1_wr) nmie <= ie1_nxt[4]; - -reg wdtie; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) wdtie <= 1'b0; - else if (ie1_wr) wdtie <= ie1_nxt[0]; - -assign ie1 = {3'b000, nmie, 3'b000, wdtie}; - - -// IFG1 Register -//--------------- -wire [7:0] ifg1; -wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1]; -wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0]; - -reg nmiifg; -always @ (posedge mclk or posedge puc_rst) - if (puc_rst) nmiifg <= 1'b0; - else if (nmi_acc) nmiifg <= 1'b1; - else if (ifg1_wr) nmiifg <= ifg1_nxt[4]; - -reg wdtifg; -always @ (posedge mclk or posedge por) - if (por) wdtifg <= 1'b0; - else if (wdtifg_set) wdtifg <= 1'b1; - else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0; - else if (ifg1_wr) wdtifg <= ifg1_nxt[0]; - -assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg}; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}}); -wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}}); - -wire [15:0] per_dout = ie1_rd | - ifg1_rd; - - -//============================================================================= -// 5) WATCHDOG INTERRUPT & RESET -//============================================================================= - -// Watchdog interrupt generation -//--------------------------------- -wire wdt_irq = wdttmsel & wdtifg & wdtie; - - -// Watchdog reset generation -//----------------------------- -reg wdt_reset; - -always @ (posedge mclk or posedge por) - if (por) wdt_reset <= 1'b0; - else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel); - - -endmodule // omsp_sfr - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v (nonexistent) @@ -1,841 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: omsp_dbg.v -// -// *Module Description: -// Debug interface -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev: 111 $ -// $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ -//---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif - -module omsp_dbg ( - -// OUTPUTs - dbg_freeze, // Freeze peripherals - dbg_halt_cmd, // Halt CPU command - dbg_mem_addr, // Debug address for rd/wr access - dbg_mem_dout, // Debug unit data output - dbg_mem_en, // Debug unit memory enable - dbg_mem_wr, // Debug unit memory write - dbg_reg_wr, // Debug unit CPU register write - dbg_cpu_reset, // Reset CPU from debug interface - dbg_uart_txd, // Debug interface: UART TXD - -// INPUTs - cpu_en_s, // Enable CPU code execution (synchronous) - dbg_clk, // Debug unit clock - dbg_en_s, // Debug interface enable (synchronous) - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_din, // Debug unit Memory data input - dbg_reg_din, // Debug unit CPU register data input - dbg_rst, // Debug unit reset - dbg_uart_rxd, // Debug interface: UART RXD (asynchronous) - decode_noirq, // Frontend decode instruction - eu_mab, // Execution-Unit Memory address bus - eu_mb_en, // Execution-Unit Memory bus enable - eu_mb_wr, // Execution-Unit Memory bus write transfer - eu_mdb_in, // Memory data bus input - eu_mdb_out, // Memory data bus output - exec_done, // Execution completed - fe_mb_en, // Frontend Memory bus enable - fe_mdb_in, // Frontend Memory data bus input - pc, // Program counter - puc_rst // Main system reset -); - -// OUTPUTs -//========= -output dbg_freeze; // Freeze peripherals -output dbg_halt_cmd; // Halt CPU command -output [15:0] dbg_mem_addr; // Debug address for rd/wr access -output [15:0] dbg_mem_dout; // Debug unit data output -output dbg_mem_en; // Debug unit memory enable -output [1:0] dbg_mem_wr; // Debug unit memory write -output dbg_reg_wr; // Debug unit CPU register write -output dbg_cpu_reset; // Reset CPU from debug interface -output dbg_uart_txd; // Debug interface: UART TXD - -// INPUTs -//========= -input cpu_en_s; // Enable CPU code execution (synchronous) -input dbg_clk; // Debug unit clock -input dbg_en_s; // Debug interface enable (synchronous) -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_din; // Debug unit Memory data input -input [15:0] dbg_reg_din; // Debug unit CPU register data input -input dbg_rst; // Debug unit reset -input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous) -input decode_noirq; // Frontend decode instruction -input [15:0] eu_mab; // Execution-Unit Memory address bus -input eu_mb_en; // Execution-Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer -input [15:0] eu_mdb_in; // Memory data bus input -input [15:0] eu_mdb_out; // Memory data bus output -input exec_done; // Execution completed -input fe_mb_en; // Frontend Memory bus enable -input [15:0] fe_mdb_in; // Frontend Memory data bus input -input [15:0] pc; // Program counter -input puc_rst; // Main system reset - - -//============================================================================= -// 1) WIRE & PARAMETER DECLARATION -//============================================================================= - -// Diverse wires and registers -wire [5:0] dbg_addr; -wire [15:0] dbg_din; -wire dbg_wr; -reg mem_burst; -wire dbg_reg_rd; -wire dbg_mem_rd; -reg dbg_mem_rd_dly; -wire dbg_swbrk; -wire dbg_rd; -reg dbg_rd_rdy; -wire mem_burst_rd; -wire mem_burst_wr; -wire brk0_halt; -wire brk0_pnd; -wire [15:0] brk0_dout; -wire brk1_halt; -wire brk1_pnd; -wire [15:0] brk1_dout; -wire brk2_halt; -wire brk2_pnd; -wire [15:0] brk2_dout; -wire brk3_halt; -wire brk3_pnd; -wire [15:0] brk3_dout; - -// Register addresses -parameter CPU_ID_LO = 6'h00; -parameter CPU_ID_HI = 6'h01; -parameter CPU_CTL = 6'h02; -parameter CPU_STAT = 6'h03; -parameter MEM_CTL = 6'h04; -parameter MEM_ADDR = 6'h05; -parameter MEM_DATA = 6'h06; -parameter MEM_CNT = 6'h07; -`ifdef DBG_HWBRK_0 -parameter BRK0_CTL = 6'h08; -parameter BRK0_STAT = 6'h09; -parameter BRK0_ADDR0 = 6'h0A; -parameter BRK0_ADDR1 = 6'h0B; -`endif -`ifdef DBG_HWBRK_1 -parameter BRK1_CTL = 6'h0C; -parameter BRK1_STAT = 6'h0D; -parameter BRK1_ADDR0 = 6'h0E; -parameter BRK1_ADDR1 = 6'h0F; -`endif -`ifdef DBG_HWBRK_2 -parameter BRK2_CTL = 6'h10; -parameter BRK2_STAT = 6'h11; -parameter BRK2_ADDR0 = 6'h12; -parameter BRK2_ADDR1 = 6'h13; -`endif -`ifdef DBG_HWBRK_3 -parameter BRK3_CTL = 6'h14; -parameter BRK3_STAT = 6'h15; -parameter BRK3_ADDR0 = 6'h16; -parameter BRK3_ADDR1 = 6'h17; -`endif - -// Register one-hot decoder -parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO); -parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI); -parameter CPU_CTL_D = (64'h1 << CPU_CTL); -parameter CPU_STAT_D = (64'h1 << CPU_STAT); -parameter MEM_CTL_D = (64'h1 << MEM_CTL); -parameter MEM_ADDR_D = (64'h1 << MEM_ADDR); -parameter MEM_DATA_D = (64'h1 << MEM_DATA); -parameter MEM_CNT_D = (64'h1 << MEM_CNT); -`ifdef DBG_HWBRK_0 -parameter BRK0_CTL_D = (64'h1 << BRK0_CTL); -parameter BRK0_STAT_D = (64'h1 << BRK0_STAT); -parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0); -parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1); -`endif -`ifdef DBG_HWBRK_1 -parameter BRK1_CTL_D = (64'h1 << BRK1_CTL); -parameter BRK1_STAT_D = (64'h1 << BRK1_STAT); -parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0); -parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1); -`endif -`ifdef DBG_HWBRK_2 -parameter BRK2_CTL_D = (64'h1 << BRK2_CTL); -parameter BRK2_STAT_D = (64'h1 << BRK2_STAT); -parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0); -parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1); -`endif -`ifdef DBG_HWBRK_3 -parameter BRK3_CTL_D = (64'h1 << BRK3_CTL); -parameter BRK3_STAT_D = (64'h1 << BRK3_STAT); -parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0); -parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1); -`endif - -// PUC is localy used as a data. -reg [1:0] puc_sync; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) puc_sync <= 2'b11; - else puc_sync <= {puc_sync[0] , puc_rst}; -wire puc_s = puc_sync[1]; - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Select Data register during a burst -wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr; - -// Register address decode -reg [63:0] reg_dec; -always @(dbg_addr_in) - case (dbg_addr_in) - CPU_ID_LO : reg_dec = CPU_ID_LO_D; - CPU_ID_HI : reg_dec = CPU_ID_HI_D; - CPU_CTL : reg_dec = CPU_CTL_D; - CPU_STAT : reg_dec = CPU_STAT_D; - MEM_CTL : reg_dec = MEM_CTL_D; - MEM_ADDR : reg_dec = MEM_ADDR_D; - MEM_DATA : reg_dec = MEM_DATA_D; - MEM_CNT : reg_dec = MEM_CNT_D; -`ifdef DBG_HWBRK_0 - BRK0_CTL : reg_dec = BRK0_CTL_D; - BRK0_STAT : reg_dec = BRK0_STAT_D; - BRK0_ADDR0: reg_dec = BRK0_ADDR0_D; - BRK0_ADDR1: reg_dec = BRK0_ADDR1_D; -`endif -`ifdef DBG_HWBRK_1 - BRK1_CTL : reg_dec = BRK1_CTL_D; - BRK1_STAT : reg_dec = BRK1_STAT_D; - BRK1_ADDR0: reg_dec = BRK1_ADDR0_D; - BRK1_ADDR1: reg_dec = BRK1_ADDR1_D; -`endif -`ifdef DBG_HWBRK_2 - BRK2_CTL : reg_dec = BRK2_CTL_D; - BRK2_STAT : reg_dec = BRK2_STAT_D; - BRK2_ADDR0: reg_dec = BRK2_ADDR0_D; - BRK2_ADDR1: reg_dec = BRK2_ADDR1_D; -`endif -`ifdef DBG_HWBRK_3 - BRK3_CTL : reg_dec = BRK3_CTL_D; - BRK3_STAT : reg_dec = BRK3_STAT_D; - BRK3_ADDR0: reg_dec = BRK3_ADDR0_D; - BRK3_ADDR1: reg_dec = BRK3_ADDR1_D; -`endif - default: reg_dec = {64{1'b0}}; - endcase - -// Read/Write probes -wire reg_write = dbg_wr; -wire reg_read = 1'b1; - -// Read/Write vectors -wire [63:0] reg_wr = reg_dec & {64{reg_write}}; -wire [63:0] reg_rd = reg_dec & {64{reg_read}}; - - -//============================================================================= -// 3) REGISTER: CORE INTERFACE -//============================================================================= - -// CPU_ID Register -//----------------- -// ------------------------------------------------------------------- -// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 | -// |----------------------------+-----------------+------+-------------| -// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION | -// -------------------------------------------------------------------- -// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 | -// |----------------------------+-------------------------------+------| -// | PMEM_SIZE | DMEM_SIZE | MPY | -// ------------------------------------------------------------------- - -wire [2:0] cpu_version = `CPU_VERSION; -`ifdef ASIC -wire cpu_asic = 1'b1; -`else -wire cpu_asic = 1'b0; -`endif -wire [4:0] user_version = `USER_VERSION; -wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size -`ifdef MULTIPLIER -wire mpy_info = 1'b1; -`else -wire mpy_info = 1'b0; -`endif -wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size -wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size - -wire [31:0] cpu_id = {pmem_size, - dmem_size, - mpy_info, - per_space, - user_version, - cpu_asic, - cpu_version}; - - -// CPU_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT -//----------------------------------------------------------------------------- -reg [6:3] cpu_ctl; - -wire cpu_ctl_wr = reg_wr[CPU_CTL]; - -always @ (posedge dbg_clk or posedge dbg_rst) -`ifdef DBG_RST_BRK_EN - if (dbg_rst) cpu_ctl <= 4'h4; -`else - if (dbg_rst) cpu_ctl <= 4'h0; -`endif - else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3]; - -wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000}; - -wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st; -wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st; -wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st; - - -// CPU_STAT Register -//------------------------------------------------------------------------------------ -// 7 6 5 4 3 2 1 0 -// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN -//------------------------------------------------------------------------------------ -reg [3:2] cpu_stat; - -wire cpu_stat_wr = reg_wr[CPU_STAT]; -wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s}; -wire [3:2] cpu_stat_clr = ~dbg_din[3:2]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) cpu_stat <= 2'b00; - else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set); - else cpu_stat <= (cpu_stat | cpu_stat_set); - -wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd, - cpu_stat, 1'b0, dbg_halt_st}; - - -//============================================================================= -// 4) REGISTER: MEMORY INTERFACE -//============================================================================= - -// MEM_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved B/W MEM/REG RD/WR START -// -// START : - 0 : Do nothing. -// - 1 : Initiate memory transfer. -// -// RD/WR : - 0 : Read access. -// - 1 : Write access. -// -// MEM/REG: - 0 : Memory access. -// - 1 : CPU Register access. -// -// B/W : - 0 : 16 bit access. -// - 1 : 8 bit access (not valid for CPU Registers). -// -//----------------------------------------------------------------------------- -reg [3:1] mem_ctl; - -wire mem_ctl_wr = reg_wr[MEM_CTL]; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_ctl <= 3'h0; - else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1]; - -wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0}; - -reg mem_start; -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_start <= 1'b0; - else mem_start <= mem_ctl_wr & dbg_din[0]; - -wire mem_bw = mem_ctl[3]; - -// MEM_DATA Register -//------------------ -reg [15:0] mem_data; -reg [15:0] mem_addr; -wire mem_access; - -wire mem_data_wr = reg_wr[MEM_DATA]; - -wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din : - mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} : - {8'h00, dbg_mem_din[7:0]}; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_data <= 16'h0000; - else if (mem_data_wr) mem_data <= dbg_din; - else if (dbg_reg_rd) mem_data <= dbg_reg_din; - else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw; - - -// MEM_ADDR Register -//------------------ -reg [15:0] mem_cnt; - -wire mem_addr_wr = reg_wr[MEM_ADDR]; -wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2])); -wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2])); - -wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 : - (dbg_mem_acc & ~mem_bw) ? 16'h0002 : - (dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_addr <= 16'h0000; - else if (mem_addr_wr) mem_addr <= dbg_din; - else mem_addr <= mem_addr + mem_addr_inc; - -// MEM_CNT Register -//------------------ - -wire mem_cnt_wr = reg_wr[MEM_CNT]; - -wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 : - (dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000; - -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_cnt <= 16'h0000; - else if (mem_cnt_wr) mem_cnt <= dbg_din; - else mem_cnt <= mem_cnt + mem_cnt_dec; - - -//============================================================================= -// 5) BREAKPOINTS / WATCHPOINTS -//============================================================================= - -`ifdef DBG_HWBRK_0 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1], - reg_rd[BRK0_ADDR0], - reg_rd[BRK0_STAT], - reg_rd[BRK0_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1], - reg_wr[BRK0_ADDR0], - reg_wr[BRK0_STAT], - reg_wr[BRK0_CTL]}; - -omsp_dbg_hwbrk dbg_hwbr_0 ( - -// OUTPUTs - .brk_halt (brk0_halt), // Hardware breakpoint command - .brk_pnd (brk0_pnd), // Hardware break/watch-point pending - .brk_dout (brk0_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_din (dbg_din), // Debug register data input - .dbg_rst (dbg_rst), // Debug unit reset - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .pc (pc) // Program counter -); - -`else -assign brk0_halt = 1'b0; -assign brk0_pnd = 1'b0; -assign brk0_dout = 16'h0000; -`endif - -`ifdef DBG_HWBRK_1 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1], - reg_rd[BRK1_ADDR0], - reg_rd[BRK1_STAT], - reg_rd[BRK1_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1], - reg_wr[BRK1_ADDR0], - reg_wr[BRK1_STAT], - reg_wr[BRK1_CTL]}; - -omsp_dbg_hwbrk dbg_hwbr_1 ( - -// OUTPUTs - .brk_halt (brk1_halt), // Hardware breakpoint command - .brk_pnd (brk1_pnd), // Hardware break/watch-point pending - .brk_dout (brk1_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_din (dbg_din), // Debug register data input - .dbg_rst (dbg_rst), // Debug unit reset - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .pc (pc) // Program counter -); - -`else -assign brk1_halt = 1'b0; -assign brk1_pnd = 1'b0; -assign brk1_dout = 16'h0000; -`endif - - `ifdef DBG_HWBRK_2 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1], - reg_rd[BRK2_ADDR0], - reg_rd[BRK2_STAT], - reg_rd[BRK2_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1], - reg_wr[BRK2_ADDR0], - reg_wr[BRK2_STAT], - reg_wr[BRK2_CTL]}; - -omsp_dbg_hwbrk dbg_hwbr_2 ( - -// OUTPUTs - .brk_halt (brk2_halt), // Hardware breakpoint command - .brk_pnd (brk2_pnd), // Hardware break/watch-point pending - .brk_dout (brk2_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_din (dbg_din), // Debug register data input - .dbg_rst (dbg_rst), // Debug unit reset - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .pc (pc) // Program counter -); - -`else -assign brk2_halt = 1'b0; -assign brk2_pnd = 1'b0; -assign brk2_dout = 16'h0000; -`endif - -`ifdef DBG_HWBRK_3 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1], - reg_rd[BRK3_ADDR0], - reg_rd[BRK3_STAT], - reg_rd[BRK3_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1], - reg_wr[BRK3_ADDR0], - reg_wr[BRK3_STAT], - reg_wr[BRK3_CTL]}; - -omsp_dbg_hwbrk dbg_hwbr_3 ( - -// OUTPUTs - .brk_halt (brk3_halt), // Hardware breakpoint command - .brk_pnd (brk3_pnd), // Hardware break/watch-point pending - .brk_dout (brk3_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_din (dbg_din), // Debug register data input - .dbg_rst (dbg_rst), // Debug unit reset - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .pc (pc) // Program counter -); - -`else -assign brk3_halt = 1'b0; -assign brk3_pnd = 1'b0; -assign brk3_dout = 16'h0000; -`endif - - -//============================================================================ -// 6) DATA OUTPUT GENERATION -//============================================================================ - -wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}}; -wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}}; -wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}}; -wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}}; -wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}}; -wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}}; -wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}}; -wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}}; - -wire [15:0] dbg_dout = cpu_id_lo_rd | - cpu_id_hi_rd | - cpu_ctl_rd | - cpu_stat_rd | - mem_ctl_rd | - mem_data_rd | - mem_addr_rd | - mem_cnt_rd | - brk0_dout | - brk1_dout | - brk2_dout | - brk3_dout; - -// Tell UART/JTAG interface that the data is ready to be read -always @ (posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) dbg_rd_rdy <= 1'b0; - else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly); - else dbg_rd_rdy <= dbg_rd; - - -//============================================================================ -// 7) CPU CONTROL -//============================================================================ - -// Reset CPU -//-------------------------- -wire dbg_cpu_reset = cpu_ctl[`CPU_RST]; - - -// Break after reset -//-------------------------- -wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_s; - - -// Freeze peripherals -//-------------------------- -wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s); - - -// Software break -//-------------------------- -assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN]; - - -// Single step -//-------------------------- -reg [1:0] inc_step; -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) inc_step <= 2'b00; - else if (istep) inc_step <= 2'b11; - else inc_step <= {inc_step[0], 1'b0}; - - -// Run / Halt -//-------------------------- -reg halt_flag; - -wire mem_halt_cpu; -wire mem_run_cpu; - -wire halt_flag_clr = run_cpu | mem_run_cpu; -wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu | - brk0_halt | brk1_halt | brk2_halt | brk3_halt; - -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) halt_flag <= 1'b0; - else if (halt_flag_clr) halt_flag <= 1'b0; - else if (halt_flag_set) halt_flag <= 1'b1; - -wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1]; - - -//============================================================================ -// 8) MEMORY CONTROL -//============================================================================ - -// Control Memory bursts -//------------------------------ - -wire mem_burst_start = (mem_start & |mem_cnt); -wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt); - -// Detect when burst is on going -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_burst <= 1'b0; - else if (mem_burst_start) mem_burst <= 1'b1; - else if (mem_burst_end) mem_burst <= 1'b0; - -// Control signals for UART/JTAG interface -assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]); -assign mem_burst_wr = (mem_burst_start & mem_ctl[1]); - -// Trigger CPU Register or memory access during a burst -reg mem_startb; -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_startb <= 1'b0; - else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd; - -// Combine single and burst memory start of sequence -wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb); - - -// Memory access state machine -//------------------------------ -reg [1:0] mem_state; -reg [1:0] mem_state_nxt; - -// State machine definition -parameter M_IDLE = 2'h0; -parameter M_SET_BRK = 2'h1; -parameter M_ACCESS_BRK = 2'h2; -parameter M_ACCESS = 2'h3; - -// State transition -always @(mem_state or mem_seq_start or dbg_halt_st) - case (mem_state) - M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE : - dbg_halt_st ? M_ACCESS : M_SET_BRK; - M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK; - M_ACCESS_BRK : mem_state_nxt = M_IDLE; - M_ACCESS : mem_state_nxt = M_IDLE; - default : mem_state_nxt = M_IDLE; - endcase - -// State machine -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) mem_state <= M_IDLE; - else mem_state <= mem_state_nxt; - -// Utility signals -assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK); -assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE); -assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK); - - -// Interface to CPU Registers and Memory bacbkone -//------------------------------------------------ -assign dbg_mem_addr = mem_addr; -assign dbg_mem_dout = ~mem_bw ? mem_data : - mem_addr[0] ? {mem_data[7:0], 8'h00} : - {8'h00, mem_data[7:0]}; - -assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2]; -assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2]; - -assign dbg_mem_en = mem_access & ~mem_ctl[2]; -assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1]; - -wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 : - mem_addr[0] ? 2'b10 : 2'b01; -assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk; - - -// It takes one additional cycle to read from Memory as from registers -always @(posedge dbg_clk or posedge dbg_rst) - if (dbg_rst) dbg_mem_rd_dly <= 1'b0; - else dbg_mem_rd_dly <= dbg_mem_rd; - - -//============================================================================= -// 9) UART COMMUNICATION -//============================================================================= -`ifdef DBG_UART -omsp_dbg_uart dbg_uart_0 ( - -// OUTPUTs - .dbg_addr (dbg_addr), // Debug register address - .dbg_din (dbg_din), // Debug register data input - .dbg_rd (dbg_rd), // Debug register data read - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - .dbg_wr (dbg_wr), // Debug register data write - -// INPUTs - .dbg_clk (dbg_clk), // Debug unit clock - .dbg_dout (dbg_dout), // Debug register data output - .dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read - .dbg_rst (dbg_rst), // Debug unit reset - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD - .mem_burst (mem_burst), // Burst on going - .mem_burst_end(mem_burst_end), // End TX/RX burst - .mem_burst_rd (mem_burst_rd), // Start TX burst - .mem_burst_wr (mem_burst_wr), // Start RX burst - .mem_bw (mem_bw) // Burst byte width -); - -`else -assign dbg_addr = 6'h00; -assign dbg_din = 16'h0000; -assign dbg_rd = 1'b0; -assign dbg_uart_txd = 1'b0; -assign dbg_wr = 1'b0; -`endif - - -//============================================================================= -// 10) JTAG COMMUNICATION -//============================================================================= -`ifdef DBG_JTAG -JTAG INTERFACE IS NOT SUPPORTED YET -`else -`endif - -endmodule // dbg - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v (nonexistent) @@ -1,563 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2011 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_fpga.v -// -// *Module Description: -// openMSP430 FPGA Top-level for the Avnet LX9 Microboard -// -// *Author(s): -// - Ricardo Ribalda, ricardo.ribalda@gmail.com -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -`include "openmsp430/openMSP430_defines.v" - -module openMSP430_fpga ( - // Clock Sources - CLK_66MHz, - // Clock output - MCLK, - //Swich buttons - SW3, - SW2, - SW1, - SW0, - // Push Button Switches - BTN0, - // J5 PMOD_P4 and ground - DBG_OFF, - // LEDs - LED3, - LED2, - LED1, - LED0, - // RS-232 Port - UART_RXD, - UART_TXD -); - -// Clock Sources -input CLK_66MHz; - -output MCLK; - -// Slide Switches -input SW3; -input SW2; -input SW1; -input SW0; - -// Push Button Switches -input BTN0; - -// J5 PMOD_P4 and ground -input DBG_OFF; - -// LEDs -output LED3; -output LED2; -output LED1; -output LED0; - -// RS-232 Port -input UART_RXD; -output UART_TXD; - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -// openMSP430 output buses -wire [13:0] per_addr; -wire [15:0] per_din; -wire [1:0] per_we; -wire [`DMEM_MSB:0] dmem_addr; -wire [15:0] dmem_din; -wire [1:0] dmem_wen; -wire [1:0] dmem_wen_n; -wire [`PMEM_MSB:0] pmem_addr; -wire [15:0] pmem_din; -wire [1:0] pmem_wen; -wire [1:0] pmem_wen_n; -wire [13:0] irq_acc; - -// openMSP430 input buses -wire [13:0] irq_bus; -wire [15:0] per_dout; -wire [15:0] dmem_dout; -wire [15:0] pmem_dout; - -// GPIO -wire [7:0] p1_din; -wire [7:0] p1_dout; -wire [7:0] p1_dout_en; -wire [7:0] p1_sel; -wire [7:0] p2_din; -wire [7:0] p2_dout; -wire [7:0] p2_dout_en; -wire [7:0] p2_sel; -wire [7:0] p3_dout; -wire [7:0] p3_dout_en; -wire [7:0] p4_din; -wire [15:0] per_dout_dio; - -// Timer A -wire [15:0] per_dout_tA; - -// Others -wire reset_pin; - -//============================================================================= -// 2) CLOCK GENERATION -//============================================================================= - -// Input buffers -//------------------------ -IBUFG ibuf_clk_main (.O(clk_66M_in), .I(CLK_66MHz)); - - -// Digital Clock Manager -//------------------------ -DCM_SP #( - .CLKFX_MULTIPLY(3), - .CLKFX_DIVIDE(10), - .CLKIN_PERIOD(15.000), - )dcm_inst( -// OUTPUTs - .CLKFX (dcm_clk), - .CLK0 (CLK0_BUF), - .LOCKED (dcm_locked), -// INPUTs - .CLKFB (CLKFB_IN), - .CLKIN (clk_66M_in), - .PSEN (1'b0), - .RST (reset_pin) -); - -BUFG CLK0_BUFG_INST ( - .I(CLK0_BUF), - .O(CLKFB_IN) -); - -//synthesis translate_off -defparam dcm_inst.CLKFX_MULTIPLY = 3; -defparam dcm_inst.CLKFX_DIVIDE = 10; -defparam dcm_int.CLKIN_PERIOD = 15.000; -//synthesis translate_on - -// Clock buffers -//------------------------ -BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk)); - -//============================================================================= -// 3) RESET GENERATION & FPGA STARTUP -//============================================================================= - -// Reset input buffer -IBUF ibuf_reset_n (.O(reset_pin), .I(BTN0)); -wire reset_pin_n = ~reset_pin; - -// Release the reset only, if the DCM is locked -assign reset_n = reset_pin_n & dcm_locked; - -//============================================================================= -// 4) OPENMSP430 -//============================================================================= - -openMSP430 openMSP430_0 ( - -// OUTPUTs - .aclk_en (aclk_en), // ACLK enable - .dbg_freeze (dbg_freeze), // Freeze peripherals - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - .dmem_addr (dmem_addr), // Data Memory address - .dmem_cen (dmem_cen), // Data Memory chip enable (low active) - .dmem_din (dmem_din), // Data Memory data input - .dmem_wen (dmem_wen), // Data Memory write enable (low active) - .irq_acc (irq_acc), // Interrupt request accepted (one-hot signal) - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_we (per_we), // Peripheral write enable (high active) - .per_en (per_en), // Peripheral enable (high active) - .pmem_addr (pmem_addr), // Program Memory address - .pmem_cen (pmem_cen), // Program Memory chip enable (low active) - .pmem_din (pmem_din), // Program Memory data input (optional) - .pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional) - .puc_rst (puc_rst), // Main system reset - .smclk_en (smclk_en), // SMCLK enable - -// INPUTs - .cpu_en (1'b1), // Enable CPU code execution (asynchronous) - .dbg_en (1'b1), // Debug interface enable (asynchronous) - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD - .dco_clk (clk_sys), // Fast oscillator (fast clock) - .dmem_dout (dmem_dout), // Data Memory data output - .irq (irq_bus), // Maskable interrupts - .lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz) - .nmi (nmi), // Non-maskable interrupt (asynchronous) - .per_dout (per_dout), // Peripheral data output - .pmem_dout (pmem_dout), // Program Memory data output - .reset_n (reset_n) // Reset Pin (low active) -); - - -//============================================================================= -// 5) OPENMSP430 PERIPHERALS -//============================================================================= - -// -// Digital I/O -//------------------------------- - -omsp_gpio #(.P1_EN(1), - .P2_EN(1), - .P3_EN(1), - .P4_EN(1), - .P5_EN(0), - .P6_EN(0)) gpio_0 ( - -// OUTPUTs - .irq_port1 (irq_port1), // Port 1 interrupt - .irq_port2 (irq_port2), // Port 2 interrupt - .p1_dout (p1_dout), // Port 1 data output - .p1_dout_en (p1_dout_en), // Port 1 data output enable - .p1_sel (p1_sel), // Port 1 function select - .p2_dout (p2_dout), // Port 2 data output - .p2_dout_en (p2_dout_en), // Port 2 data output enable - .p2_sel (p2_sel), // Port 2 function select - .p3_dout (p3_dout), // Port 3 data output - .p3_dout_en (p3_dout_en), // Port 3 data output enable - .p3_sel (), // Port 3 function select - .p4_dout (), // Port 4 data output - .p4_dout_en (), // Port 4 data output enable - .p4_sel (), // Port 4 function select - .p5_dout (), // Port 5 data output - .p5_dout_en (), // Port 5 data output enable - .p5_sel (), // Port 5 function select - .p6_dout (), // Port 6 data output - .p6_dout_en (), // Port 6 data output enable - .p6_sel (), // Port 6 function select - .per_dout (per_dout_dio), // Peripheral data output - -// INPUTs - .mclk (mclk), // Main system clock - .p1_din (p1_din), // Port 1 data input - .p2_din (p2_din), // Port 2 data input - .p3_din (8'h00), // Port 3 data input - .p4_din (p4_din), // Port 4 data input - .p5_din (8'h00), // Port 5 data input - .p6_din (8'h00), // Port 6 data input - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .puc_rst (puc_rst) // Main system reset -); - -// -// Timer A -//---------------------------------------------- - -omsp_timerA timerA_0 ( - -// OUTPUTs - .irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0 - .irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2 - .per_dout (per_dout_tA), // Peripheral data output - .ta_out0 (ta_out0), // Timer A output 0 - .ta_out0_en (ta_out0_en), // Timer A output 0 enable - .ta_out1 (ta_out1), // Timer A output 1 - .ta_out1_en (ta_out1_en), // Timer A output 1 enable - .ta_out2 (ta_out2), // Timer A output 2 - .ta_out2_en (ta_out2_en), // Timer A output 2 enable - -// INPUTs - .aclk_en (aclk_en), // ACLK enable (from CPU) - .dbg_freeze (dbg_freeze), // Freeze Timer A counter - .inclk (inclk), // INCLK external timer clock (SLOW) - .irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_we (per_we), // Peripheral write enable (high active) - .puc_rst (puc_rst), // Main system reset - .smclk_en (smclk_en), // SMCLK enable (from CPU) - .ta_cci0a (ta_cci0a), // Timer A capture 0 input A - .ta_cci0b (ta_cci0b), // Timer A capture 0 input B - .ta_cci1a (ta_cci1a), // Timer A capture 1 input A - .ta_cci1b (1'b0), // Timer A capture 1 input B - .ta_cci2a (ta_cci2a), // Timer A capture 2 input A - .ta_cci2b (1'b0), // Timer A capture 2 input B - .taclk (taclk) // TACLK external timer clock (SLOW) -); - -// -// Combine peripheral data buses -//------------------------------- - -assign per_dout = per_dout_dio | - per_dout_tA; -// -// Assign interrupts -//------------------------------- - -assign nmi = 1'b0; -assign irq_bus = {1'b0, // Vector 13 (0xFFFA) - 1'b0, // Vector 12 (0xFFF8) - 1'b0, // Vector 11 (0xFFF6) - 1'b0, // Vector 10 (0xFFF4) - Watchdog - - irq_ta0, // Vector 9 (0xFFF2) - irq_ta1, // Vector 8 (0xFFF0) - 1'b0, // Vector 7 (0xFFEE) - 1'b0, // Vector 6 (0xFFEC) - 1'b0, // Vector 5 (0xFFEA) - 1'b0, // Vector 4 (0xFFE8) - irq_port2, // Vector 3 (0xFFE6) - irq_port1, // Vector 2 (0xFFE4) - 1'b0, // Vector 1 (0xFFE2) - 1'b0}; // Vector 0 (0xFFE0) - -// -// GPIO Function selection -//-------------------------- - -// P1.0/TACLK I/O pin / Timer_A, clock signal TACLK input -// P1.1/TA0 I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output -// P1.2/TA1 I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output -// P1.3/TA2 I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output -// P1.4/SMCLK I/O pin / SMCLK signal output -// P1.5/TA0 I/O pin / Timer_A, compare: Out0 output -// P1.6/TA1 I/O pin / Timer_A, compare: Out1 output -// P1.7/TA2 I/O pin / Timer_A, compare: Out2 output -wire [7:0] p1_io_mux_b_unconnected; -wire [7:0] p1_io_dout; -wire [7:0] p1_io_dout_en; -wire [7:0] p1_io_din; - -io_mux #8 io_mux_p1 ( - .a_din (p1_din), - .a_dout (p1_dout), - .a_dout_en (p1_dout_en), - - .b_din ({p1_io_mux_b_unconnected[7], - p1_io_mux_b_unconnected[6], - p1_io_mux_b_unconnected[5], - p1_io_mux_b_unconnected[4], - ta_cci2a, - ta_cci1a, - ta_cci0a, - taclk - }), - .b_dout ({ta_out2, - ta_out1, - ta_out0, - (smclk_en & mclk), - ta_out2, - ta_out1, - ta_out0, - 1'b0 - }), - .b_dout_en ({ta_out2_en, - ta_out1_en, - ta_out0_en, - 1'b1, - ta_out2_en, - ta_out1_en, - ta_out0_en, - 1'b0 - }), - - .io_din (p1_io_din), - .io_dout (p1_io_dout), - .io_dout_en (p1_io_dout_en), - - .sel (p1_sel) -); - - - -// P2.0/ACLK I/O pin / ACLK output -// P2.1/INCLK I/O pin / Timer_A, clock signal at INCLK -// P2.2/TA0 I/O pin / Timer_A, capture: CCI0B input -// P2.3/TA1 I/O pin / Timer_A, compare: Out1 output -// P2.4/TA2 I/O pin / Timer_A, compare: Out2 output -wire [7:0] p2_io_mux_b_unconnected; -wire [7:0] p2_io_dout; -wire [7:0] p2_io_dout_en; -wire [7:0] p2_io_din; - -io_mux #8 io_mux_p2 ( - .a_din (p2_din), - .a_dout (p2_dout), - .a_dout_en (p2_dout_en), - - .b_din ({p2_io_mux_b_unconnected[7], - p2_io_mux_b_unconnected[6], - p2_io_mux_b_unconnected[5], - p2_io_mux_b_unconnected[4], - p2_io_mux_b_unconnected[3], - ta_cci0b, - inclk, - p2_io_mux_b_unconnected[0] - }), - .b_dout ({1'b0, - 1'b0, - 1'b0, - ta_out2, - ta_out1, - 1'b0, - 1'b0, - (aclk_en & mclk) - }), - .b_dout_en ({1'b0, - 1'b0, - 1'b0, - ta_out2_en, - ta_out1_en, - 1'b0, - 1'b0, - 1'b1 - }), - - .io_din (p2_io_din), - .io_dout (p2_io_dout), - .io_dout_en (p2_io_dout_en), - - .sel (p2_sel) -); - - -//============================================================================= -// 6) PROGRAM AND DATA MEMORIES -//============================================================================= - -assign dmem_cen_n = ~ dmem_cen; -assign pmem_cen_n = ~ pmem_cen; -assign dmem_wen_n = ~ dmem_wen; -assign pmem_wen_n = ~ pmem_wen; - - -// Data Memory -ram_8x512 ram_8x512_hi ( - .addra (dmem_addr), - .clka (clk_sys), - .dina (dmem_din[15:8]), - .douta (dmem_dout[15:8]), - .ena (dmem_cen_n), - .wea (dmem_wen_n[1]) -); -ram_8x512 ram_8x512_lo ( - .addra (dmem_addr), - .clka (clk_sys), - .dina (dmem_din[7:0]), - .douta (dmem_dout[7:0]), - .ena (dmem_cen_n), - .wea (dmem_wen_n[0]) -); - - -// Program Memory -rom_8x2k rom_8x2k_hi ( - .addra (pmem_addr), - .clka (clk_sys), - .dina (pmem_din[15:8]), - .douta (pmem_dout[15:8]), - .ena (pmem_cen_n), - .wea (pmem_wen_n[1]) -); - -rom_8x2k rom_8x2k_lo ( - .addra (pmem_addr), - .clka (clk_sys), - .dina (pmem_din[7:0]), - .douta (pmem_dout[7:0]), - .ena (pmem_cen_n), - .wea (pmem_wen_n[0]) -); - -assign chipscope_debug[15:0] =pmem_din; -assign chipscope_debug[31:16] =pmem_dout; -assign chipscope_debug[42:32] =pmem_addr; -assign chipscope_debug[44:43] =pmem_wen_n; -assign chipscope_debug[45] =pmem_cen_n; -assign chipscope_debug[46] =reset_n; -assign chipscope_debug[47] =reset_pin; -assign chipscope_debug[48] =dcm_locked; -assign chipscope_debug[49] =DBG_OFF; -assign chipscope_debug[63:50] = 15'h000000; - - -//============================================================================= -// 7) I/O CELLS -//============================================================================= - - -// Slide Switches (Port 1 inputs) -//-------------------------------- -IBUF SW3_PIN (.O(p4_din[3]), .I(SW3)); -IBUF SW2_PIN (.O(p4_din[2]), .I(SW2)); -IBUF SW1_PIN (.O(p4_din[1]), .I(SW1)); -IBUF SW0_PIN (.O(p4_din[0]), .I(SW0)); - -// LEDs (Port 1 outputs) -//----------------------- -OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3)); -OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2)); -OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1)); -OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0)); - -// RS-232 Port -//---------------------- -// P1.1 (TX) and P2.2 (RX) -assign p1_io_din = 8'h00; -assign p2_io_din[1:0] = 2'h00; -assign p2_io_din[7:3] = 5'h00; - -wire uart_txd_out = DBG_OFF ? p1_io_dout[1] : dbg_uart_txd; -wire uart_rxd_in; -assign p2_io_din[2] = DBG_OFF ? uart_rxd_in :1'b1; -assign dbg_uart_rxd = DBG_OFF ? 1'b1 :uart_rxd_in ; - - -IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD)); -OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD)); - -//DEBUG -wire [64:0] chipscope_debug; -wire [35:0] chipscope_control; -chipscope_ila chipscope_ila( - .CONTROL (chipscope_control), - .CLK (clk_sys), - .TRIG0 (chipscope_debug)); - -chipscope_icon chipscope_icon( - .CONTROL0 (chipscope_control) ); - -assign MCLK = clk_sys; - -endmodule // openMSP430_fpga

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco (nonexistent) @@ -1,137 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 13.2 -# Date: Wed Jul 20 22:49:39 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_ila:1.04.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET check_bramcount=false -CSET component_name=chipscope_ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=0 -CSET data_same_as_trigger=true -CSET disable_save_keep=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET example_design=false -CSET exclude_from_data_storage_1=false -CSET exclude_from_data_storage_10=false -CSET exclude_from_data_storage_11=false -CSET exclude_from_data_storage_12=false -CSET exclude_from_data_storage_13=false -CSET exclude_from_data_storage_14=false -CSET exclude_from_data_storage_15=false -CSET exclude_from_data_storage_16=false -CSET exclude_from_data_storage_2=false -CSET exclude_from_data_storage_3=false -CSET exclude_from_data_storage_4=false -CSET exclude_from_data_storage_5=false -CSET exclude_from_data_storage_6=false -CSET exclude_from_data_storage_7=false -CSET exclude_from_data_storage_8=false -CSET exclude_from_data_storage_9=false -CSET match_type_1=basic_with_edges -CSET match_type_10=basic_with_edges -CSET match_type_11=basic_with_edges -CSET match_type_12=basic_with_edges -CSET match_type_13=basic_with_edges -CSET match_type_14=basic_with_edges -CSET match_type_15=basic_with_edges -CSET match_type_16=basic_with_edges -CSET match_type_2=basic_with_edges -CSET match_type_3=basic_with_edges -CSET match_type_4=basic_with_edges -CSET match_type_5=basic_with_edges -CSET match_type_6=basic_with_edges -CSET match_type_7=basic_with_edges -CSET match_type_8=basic_with_edges -CSET match_type_9=basic_with_edges -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=64 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: 6ed9c9be

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc (nonexistent) @@ -1,80 +0,0 @@ -#ChipScope Core Generator Project File Version 3.0 -#Thu Jul 21 00:51:04 CEST 2011 -SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -SignalExport.bus<0000>.name=TRIG0 -SignalExport.bus<0000>.offset=0.0 -SignalExport.bus<0000>.precision=0 -SignalExport.bus<0000>.radix=Bin -SignalExport.bus<0000>.scaleFactor=1.0 -SignalExport.clockChannel=CLK -SignalExport.dataEqualsTrigger=true -SignalExport.triggerChannel<0000><0000>=TRIG0[0] -SignalExport.triggerChannel<0000><0001>=TRIG0[1] -SignalExport.triggerChannel<0000><0002>=TRIG0[2] -SignalExport.triggerChannel<0000><0003>=TRIG0[3] -SignalExport.triggerChannel<0000><0004>=TRIG0[4] -SignalExport.triggerChannel<0000><0005>=TRIG0[5] -SignalExport.triggerChannel<0000><0006>=TRIG0[6] -SignalExport.triggerChannel<0000><0007>=TRIG0[7] -SignalExport.triggerChannel<0000><0008>=TRIG0[8] -SignalExport.triggerChannel<0000><0009>=TRIG0[9] -SignalExport.triggerChannel<0000><0010>=TRIG0[10] -SignalExport.triggerChannel<0000><0011>=TRIG0[11] -SignalExport.triggerChannel<0000><0012>=TRIG0[12] -SignalExport.triggerChannel<0000><0013>=TRIG0[13] -SignalExport.triggerChannel<0000><0014>=TRIG0[14] -SignalExport.triggerChannel<0000><0015>=TRIG0[15] -SignalExport.triggerChannel<0000><0016>=TRIG0[16] -SignalExport.triggerChannel<0000><0017>=TRIG0[17] -SignalExport.triggerChannel<0000><0018>=TRIG0[18] -SignalExport.triggerChannel<0000><0019>=TRIG0[19] -SignalExport.triggerChannel<0000><0020>=TRIG0[20] -SignalExport.triggerChannel<0000><0021>=TRIG0[21] -SignalExport.triggerChannel<0000><0022>=TRIG0[22] -SignalExport.triggerChannel<0000><0023>=TRIG0[23] -SignalExport.triggerChannel<0000><0024>=TRIG0[24] -SignalExport.triggerChannel<0000><0025>=TRIG0[25] -SignalExport.triggerChannel<0000><0026>=TRIG0[26] -SignalExport.triggerChannel<0000><0027>=TRIG0[27] -SignalExport.triggerChannel<0000><0028>=TRIG0[28] -SignalExport.triggerChannel<0000><0029>=TRIG0[29] -SignalExport.triggerChannel<0000><0030>=TRIG0[30] -SignalExport.triggerChannel<0000><0031>=TRIG0[31] -SignalExport.triggerChannel<0000><0032>=TRIG0[32] -SignalExport.triggerChannel<0000><0033>=TRIG0[33] -SignalExport.triggerChannel<0000><0034>=TRIG0[34] -SignalExport.triggerChannel<0000><0035>=TRIG0[35] -SignalExport.triggerChannel<0000><0036>=TRIG0[36] -SignalExport.triggerChannel<0000><0037>=TRIG0[37] -SignalExport.triggerChannel<0000><0038>=TRIG0[38] -SignalExport.triggerChannel<0000><0039>=TRIG0[39] -SignalExport.triggerChannel<0000><0040>=TRIG0[40] -SignalExport.triggerChannel<0000><0041>=TRIG0[41] -SignalExport.triggerChannel<0000><0042>=TRIG0[42] -SignalExport.triggerChannel<0000><0043>=TRIG0[43] -SignalExport.triggerChannel<0000><0044>=TRIG0[44] -SignalExport.triggerChannel<0000><0045>=TRIG0[45] -SignalExport.triggerChannel<0000><0046>=TRIG0[46] -SignalExport.triggerChannel<0000><0047>=TRIG0[47] -SignalExport.triggerChannel<0000><0048>=TRIG0[48] -SignalExport.triggerChannel<0000><0049>=TRIG0[49] -SignalExport.triggerChannel<0000><0050>=TRIG0[50] -SignalExport.triggerChannel<0000><0051>=TRIG0[51] -SignalExport.triggerChannel<0000><0052>=TRIG0[52] -SignalExport.triggerChannel<0000><0053>=TRIG0[53] -SignalExport.triggerChannel<0000><0054>=TRIG0[54] -SignalExport.triggerChannel<0000><0055>=TRIG0[55] -SignalExport.triggerChannel<0000><0056>=TRIG0[56] -SignalExport.triggerChannel<0000><0057>=TRIG0[57] -SignalExport.triggerChannel<0000><0058>=TRIG0[58] -SignalExport.triggerChannel<0000><0059>=TRIG0[59] -SignalExport.triggerChannel<0000><0060>=TRIG0[60] -SignalExport.triggerChannel<0000><0061>=TRIG0[61] -SignalExport.triggerChannel<0000><0062>=TRIG0[62] -SignalExport.triggerChannel<0000><0063>=TRIG0[63] -SignalExport.triggerPort<0000>.name=TRIG0 -SignalExport.triggerPortCount=1 -SignalExport.triggerPortIsData<0000>=true -SignalExport.triggerPortWidth<0000>=64 -SignalExport.type=ila -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v (nonexistent) @@ -1,179 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2011 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// You must compile the wrapper file ram_8x512.v when simulating -// the core, ram_8x512. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -`timescale 1ns/1ps - -module ram_8x512( - clka, - ena, - wea, - addra, - dina, - douta -); - -input clka; -input ena; -input [0 : 0] wea; -input [8 : 0] addra; -input [7 : 0] dina; -output [7 : 0] douta; - -// synthesis translate_off - - BLK_MEM_GEN_V6_2 #( - .C_ADDRA_WIDTH(9), - .C_ADDRB_WIDTH(9), - .C_ALGORITHM(1), - .C_AXI_ID_WIDTH(4), - .C_AXI_SLAVE_TYPE(0), - .C_AXI_TYPE(1), - .C_BYTE_SIZE(9), - .C_COMMON_CLK(0), - .C_DEFAULT_DATA("0"), - .C_DISABLE_WARN_BHV_COLL(0), - .C_DISABLE_WARN_BHV_RANGE(0), - .C_FAMILY("spartan6"), - .C_HAS_AXI_ID(0), - .C_HAS_ENA(1), - .C_HAS_ENB(0), - .C_HAS_INJECTERR(0), - .C_HAS_MEM_OUTPUT_REGS_A(0), - .C_HAS_MEM_OUTPUT_REGS_B(0), - .C_HAS_MUX_OUTPUT_REGS_A(0), - .C_HAS_MUX_OUTPUT_REGS_B(0), - .C_HAS_REGCEA(0), - .C_HAS_REGCEB(0), - .C_HAS_RSTA(0), - .C_HAS_RSTB(0), - .C_HAS_SOFTECC_INPUT_REGS_A(0), - .C_HAS_SOFTECC_OUTPUT_REGS_B(0), - .C_INIT_FILE_NAME("no_coe_file_loaded"), - .C_INITA_VAL("0"), - .C_INITB_VAL("0"), - .C_INTERFACE_TYPE(0), - .C_LOAD_INIT_FILE(0), - .C_MEM_TYPE(0), - .C_MUX_PIPELINE_STAGES(0), - .C_PRIM_TYPE(1), - .C_READ_DEPTH_A(512), - .C_READ_DEPTH_B(512), - .C_READ_WIDTH_A(8), - .C_READ_WIDTH_B(8), - .C_RST_PRIORITY_A("CE"), - .C_RST_PRIORITY_B("CE"), - .C_RST_TYPE("SYNC"), - .C_RSTRAM_A(0), - .C_RSTRAM_B(0), - .C_SIM_COLLISION_CHECK("ALL"), - .C_USE_BYTE_WEA(0), - .C_USE_BYTE_WEB(0), - .C_USE_DEFAULT_DATA(0), - .C_USE_ECC(0), - .C_USE_SOFTECC(0), - .C_WEA_WIDTH(1), - .C_WEB_WIDTH(1), - .C_WRITE_DEPTH_A(512), - .C_WRITE_DEPTH_B(512), - .C_WRITE_MODE_A("WRITE_FIRST"), - .C_WRITE_MODE_B("WRITE_FIRST"), - .C_WRITE_WIDTH_A(8), - .C_WRITE_WIDTH_B(8), - .C_XDEVICEFAMILY("spartan6") - ) - inst ( - .CLKA(clka), - .ENA(ena), - .WEA(wea), - .ADDRA(addra), - .DINA(dina), - .DOUTA(douta), - .RSTA(), - .REGCEA(), - .CLKB(), - .RSTB(), - .ENB(), - .REGCEB(), - .WEB(), - .ADDRB(), - .DINB(), - .DOUTB(), - .INJECTSBITERR(), - .INJECTDBITERR(), - .SBITERR(), - .DBITERR(), - .RDADDRECC(), - .S_ACLK(), - .S_ARESETN(), - .S_AXI_AWID(), - .S_AXI_AWADDR(), - .S_AXI_AWLEN(), - .S_AXI_AWSIZE(), - .S_AXI_AWBURST(), - .S_AXI_AWVALID(), - .S_AXI_AWREADY(), - .S_AXI_WDATA(), - .S_AXI_WSTRB(), - .S_AXI_WLAST(), - .S_AXI_WVALID(), - .S_AXI_WREADY(), - .S_AXI_BID(), - .S_AXI_BRESP(), - .S_AXI_BVALID(), - .S_AXI_BREADY(), - .S_AXI_ARID(), - .S_AXI_ARADDR(), - .S_AXI_ARLEN(), - .S_AXI_ARSIZE(), - .S_AXI_ARBURST(), - .S_AXI_ARVALID(), - .S_AXI_ARREADY(), - .S_AXI_RID(), - .S_AXI_RDATA(), - .S_AXI_RRESP(), - .S_AXI_RLAST(), - .S_AXI_RVALID(), - .S_AXI_RREADY(), - .S_AXI_INJECTSBITERR(), - .S_AXI_INJECTDBITERR(), - .S_AXI_SBITERR(), - .S_AXI_DBITERR(), - .S_AXI_RDADDRECC() - ); - -// synthesis translate_on - -endmodule

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo (nonexistent) @@ -1,30 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2011 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 13.2 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_ila.veo -// /___/ /\ Timestamp : Thu Jul 21 00:50:57 CEST 2011 -// \ \ / \ -// \___\/\___\ -// -// Design Name: ISE Instantiation template -/////////////////////////////////////////////////////////////////////////////// - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -chipscope_ila YourInstanceName ( - .CONTROL(CONTROL), // INOUT BUS [35:0] - .CLK(CLK), // IN - .TRIG0(TRIG0) // IN BUS [63:0] -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise (nonexistent) @@ -1,398 +0,0 @@ - - - -

- - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy (nonexistent) @@ -1,17 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 chipscope_ila -RECTANGLE Normal 32 32 288 704 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName control[35:0] -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 112 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Wide 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName trig0[63:0] -PINATTR Polarity IN -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt (nonexistent) @@ -1,51 +0,0 @@ -The following files were generated for 'chipscope_ila' in directory -/home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/ - -XCO file generator: - Generate an XCO file for compatibility with legacy flows. - - * chipscope_ila.xco - -Creates an implementation netlist: - Creates an implementation netlist for the IP. - - * chipscope_ila.cdc - * chipscope_ila.ngc - * chipscope_ila.v - * chipscope_ila.veo - -Creates an HDL instantiation template: - Creates an HDL instantiation template for the IP. - - * chipscope_ila.veo - -IP Symbol Generator: - Generate an IP symbol based on the current project options'. - - * chipscope_ila.asy - -Generate ISE metadata: - Create a metadata file for use when including this core in ISE designs - - * chipscope_ila_xmdf.tcl - -Generate ISE subproject: - Create an ISE subproject for use when including this core in ISE designs - - * chipscope_ila.gise - * chipscope_ila.xise - -Deliver Readme: - Text file indicating the files generated and how they are used. - - * chipscope_ila_readme.txt - -Generate FLIST file: - Text file listing all of the output files produced when a customized core was - generated in the CORE Generator. - - * chipscope_ila_flist.txt - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise (nonexistent) @@ -1,32 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl (nonexistent) @@ -1,71 +0,0 @@ -# The package naming convention is _xmdf -package provide chipscope_ila_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::chipscope_ila_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::chipscope_ila_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila -} -# ::chipscope_ila_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v (nonexistent) @@ -1,31 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2011 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 13.2 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_ila.v -// /___/ /\ Timestamp : Thu Jul 21 00:50:57 CEST 2011 -// \ \ / \ -// \___\/\___\ -// -// Design Name: Verilog Synthesis Wrapper -/////////////////////////////////////////////////////////////////////////////// -// This wrapper is used to integrate with Project Navigator and PlanAhead - -`timescale 1ns/1ps - -module chipscope_ila( - CONTROL, - CLK, - TRIG0); - - -inout [35 : 0] CONTROL; -input CLK; -input [63 : 0] TRIG0; - -endmodule

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl (nonexistent) @@ -1,119 +0,0 @@ -# The package naming convention is _xmdf -package provide rom_8x2k_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::rom_8x2k_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::rom_8x2k_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name rom_8x2k -} -# ::rom_8x2k_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::rom_8x2k_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type text -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/example_design/bmg_wrapper.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/example_design/rom_8x2k_top.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/example_design/rom_8x2k_top.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/example_design/rom_8x2k_top.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/planAhead_rdn.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/planAhead_rdn.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/planAhead_rdn.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_ste/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom_8x2k -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise (nonexistent) @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc (nonexistent) @@ -1,417 +0,0 @@ - - - xilinx.com - project - coregen - 1.0 - - - chipscope_icon - - - chipscope_icon - USER1 - false - false - false - 1 - false - true - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx9 - spartan6 - csg324 - -2 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - - - - chipscope_ila - - - chipscope_ila - 8 - 8 - 8 - 8 - basic_with_edges - basic_with_edges - basic_with_edges - false - 8 - basic_with_edges - basic_with_edges - 8 - basic_with_edges - 8 - true - 8 - basic_with_edges - 8 - 8 - 8 - basic_with_edges - basic_with_edges - basic_with_edges - basic_with_edges - 1 - basic_with_edges - 1 - basic_with_edges - 1 - basic_with_edges - 1 - basic_with_edges - 1 - basic_with_edges - 1 - 1 - 1 - false - false - Rising - Disabled - Disabled - Disabled - true - Disabled - Disabled - Disabled - Disabled - 0 - false - true - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1024 - 1 - 1 - Disabled - Disabled - Disabled - Disabled - Disabled - false - Disabled - false - false - Disabled - false - false - Disabled - false - false - Disabled - false - false - false - false - false - false - false - false - false - 64 - 8 - 8 - 8 - 8 - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx9 - spartan6 - csg324 - -2 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - - - - ram_8x512 - - - ram_8x512 - Native - AXI4_Full - Memory_Slave - false - 4 - Single_Port_RAM - No_ECC - false - false - false - Single_Bit_Error_Injection - false - 9 - Minimum_Area - 8kx2 - false - 8 - 512 - 8 - WRITE_FIRST - Use_ENA_Pin - 8 - 8 - WRITE_FIRST - Always_Enabled - false - false - false - false - false - false - false - false - 0 - false - no_coe_file_loaded - false - 0 - false - false - CE - 0 - false - false - CE - 0 - SYNC - false - 100 - 50 - 100 - 50 - 100 - 100 - ALL - false - false - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx9 - spartan6 - csg324 - -2 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2011-03-11T08:24:14.000Z - - - - - - rom_8x2k - - - rom_8x2k - Native - AXI4_Full - Memory_Slave - false - 4 - Single_Port_RAM - No_ECC - false - false - false - Single_Bit_Error_Injection - false - 9 - Minimum_Area - 8kx2 - false - 16 - 2048 - 16 - WRITE_FIRST - Use_ENA_Pin - 16 - 16 - WRITE_FIRST - Always_Enabled - false - false - false - false - false - false - false - false - 0 - false - no_coe_file_loaded - false - 0 - false - false - CE - 0 - false - false - CE - 0 - SYNC - false - 100 - 50 - 0 - 0 - 100 - 0 - ALL - false - false - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx9 - spartan6 - csg324 - -2 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - 2011-03-11T08:24:14.000Z - - - - - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc6slx9 - spartan6 - csg324 - -2 - - - BusFormatAngleBracketNotRipped - Verilog - true - Other - false - false - false - Ngc - false - - - Behavioral - Verilog - false - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$0`444<,[o}e~g`n;"2*732(-80!<74012345678=:0<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;=95>1;KMTPR=imnym1??:1<20>732@D[YY4NDEPB845=87;?7<:5IORVP?GCL[H7=>4?>01853586=2;=6B[[PTV9`jssi5;>6=0>0:39MKVR\3}nm1>50?31?64=AGZ^X7JFA=12>586:2996D@_UU8GMG:493:5=>5<2;MVPUSS2MEJ0>?50?30?64=G\^[YY4KOC>05?69981?6D@_UU8GMUG;;3:5=<5;:HLSQQ11197>LHW]]0\IL2<:1<24>2=AGZ^X7YJB=194;753=0DYY^ZT;FLTD:4294:>6:5OTVSQQ1d:4ph}?d{n998 <7;@FGVD:7601JHI\N<02==>GCL[K7=<06;@FGVD:6:7h0MIJ]A=30>58>3HNO^L2>3?:8EABUI5;546OKDSC?6;>GCL[K7:364AEFQE91902KOH_O38?:8EABUI53546OKDS@?4;?89B@ATE48;556OKDS@?578e3HNO^O2>3;2==>GCL[H7=>07;@FGVG:6611JHI\M<3<;?DBCZK68255NDEPA818?3HNO^O2:>99B@ATE4?437LJKRC>4:==FLMXI0507;@FGVG:>6:1J@A64BTQ\MK@H:2IN=?5LHDAH[IODMGYNSYW_E59@HN613JF@=5>9;BNH62623JF@>U64CMI1\4>7=2IGG4>;;BNHE0=DDBK:;6MCK@3G62=DDBK:H994CMIB5A>33JF@N85LLJ@21>EKCJ;>7NBDD078GIMC^j1H@FJY_EKUMAC23JF@JU64CMIE\4>712IDA@G[TDF20>EHZLULICK]AUKLJZOINF=0O_KNTDF`?AGSIV]BHYFPAb9GEQGX_@N_DRL9;EKB85803MCJ0<>17:FJE9766>1OEL2>2?58@LG;9:4<7IGN<06=3>BNI5;>2:5KI@>22;19?2NBM1?6>79GMD:66>1OEL2=0?58@LG;:84<7IGN<30=3>BNI5882:5KI@>10;1808;EKB8709?2NBM1<8>69GMD:507=0HDO328<5?AOF4;4<7IGN<22==>BNI59:6=08;EKB8679>2NBM1=16:FJE929>2NBM1;16:FJE909>2NBM1916:FJE9>9>2NBM1716:FJF969?2NBN1??>69GMG:697=0HDL313<4?AOE4895;6JFB=37:2=CAK6:9394DH@?53803MCI0<917:FJF97?6>1OEO2>9?48@LD;97=0HDL321<4?AOE4;;5;6JFB=01:2=CAK69?394DH@?61803MCI0?;17:FJF9416>1OEO2=7?58@LD;:14<7IGM<3;=2>BNJ585;6JFB=13:<=CAK68=7>17:FJF9566?1OEO2<>79GMG:36?1OEO2:>79GMG:16?1OEO28>79GMG:?6?1OEO26>69GMUG;87=0HD^N<0<4?AOWI58556JFP@>0>5803MC[M1=17:FJTG:76>1OE]L31?58@LVE4;427IG_B=194;109;EMB85803MEJ0<>17:FLE9766>1OCL2>2?58@JG;9:4<7IAN<06=3>BHI5;>2:5KO@>22;19?2NDM1?6>79GKD:66>1OCL2=0?58@JG;:84<7IAN<30=3>BHI5882:5KO@>10;1808;EMB8709?2NDM1<8>69GKD:507=0HBO328<5?AIF4;4<7IAN<22==>BHI59:6=08;EMB8679>2NDM1=16:FLE929>2NDM1;16:FLE909>2NDM1916:FLE9>9>2NDM1717:FLEZTBO?1OCO2?>69GKG:687=0HBL310<4?AIE4885;6J@B=30:2=CGK6:8394DN@?50803MEI0<817:FLF9706>1OCO2>8?58@JD;904=7IAM<0<4?AIE4;:5;6J@B=02:2=CGK69>394DN@?66803MEI0?:17:FLF9426>1OCO2=6?58@JD;:>4<7IAM<3:=3>BHJ5822;5KOC>1:2=CGK68<374DN@?74<76>1OCO2<1?48@JD;;7<0HBL34?48@JD;=7<0HBL36?48@JD;?7<0HBL38?48@JD;17=0HBLPRDE4?AIWI5:5;6J@P@>2:2=CGYK7>374DNRB86<76>1OC]O33?58@JVE494<7IA_B=3=3>BHXK69245KOQ@?7?69?2ND\O2<>29FJD5OIA]ZT<=64IOKWTZ6602CEEY^P03:8MKOSXV:846GAIUR\41>:8:KMMQVX8?20ECG[P^243>OIA]U;<:5FNHV\441M7:KMMQY7K>1BBDZP0E58MKOSW9O<7D@FT^2E3>OIA]U:<:5FNHV\541469JJLRX9<=0ECG[_044?LHN\V;<;6GAIU]2<2=NF@^T=494IOKW[4G03@DBXR?M7:KMMQY6K>1BBDZP1E58MKOSW8O<7D@FT^3E3>OIA]U9<:5FNHV\641494IOKW[7G03@DBXR1BBDZP2E58MKOSW;O<7D@FT^0E3>OIA]U8<:5FNHV\741<8;HLJPZ54?2CEEYQ<469JJLRX;<=0ECG[_244?LHN\V9<;6GAIU]0<2=NF@^T?494IOKW[6G03@DBXR=M7:KMMQY4K>1BBDZP3E58MKOSW:O<7D@FT^1E2>OIA]UJ:6GAIU]A=>OIA]UMEAK9;MMB@@B13EEHGHJ8;MMDMFGKk2Gjfb|YesqjkkeH6?2DNXZA]K59MKKC?3F$==ujPL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ6:RP@JHBi2XJAO?9BVGQ2>TBOJOJ:6\JGBGA0>TT\H>0^^ZM7:PPPQ_WMl1Y_YQ_RHMQMQ_XIl1Y_YQ_RHMQMQ_XJ8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI<=4SHO\GJJKAZCDBRMGEBIb?VOJWMO]ENK9;RMVVFC?3ZZJ^YOA669PVSGKWH=0__XNL^@5?VRF\\Y?7^WAC59W]UC0=2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX4X(uid$y#~8Pnnkmmq(uid%X\#]FMQNF[UTNE82%~lc85:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,vdkkgfzP=P }al,q+v0Xffceey }al-PT+UNEYFNS]\FM0:-vdkd3\YN^RXFSH@OA<=QAL]TXT^J6:UFE969>2]NM1?16:UFE94902]NM1=50?48S@G;;7<0[HL30?48S@D;97<0[HL32?:8S@D;;3:5:6YJB=1=f>QUA]OTJD\\Tb9TVLRBWDEOIROl;VPJP@YJGMOTNgcl{k7<3l4aefqe97729427ljkr`>24;>gcl{k78364aefqe93902koho36?:8eabui5=546okdsc?<;>99gmkg;98437igaa=31:==cagk7=>07;ekme9736h1oeco31483:==cagk7=808;ekme979?2nbbl2=>69gmkg;;7=0hd`n<5<4?aoii5?5;6jfn`>5:2=cagk7;394dhlb8=803mcem1718:flqqg;8730hb{{a=33:<=cg|~j027;?c9gkprf48?1<374dnwwe972611ocxzn<0<;?air|h69255kotvb868?3me~xl2;>99gkprf4<437iazt`>5:==cg|~j0:07;emvpd:?611ocxzn<8<0?`hf02dloo{fle:8vjkX0q8`8ih4rno\<}4l$kf`S`kb_fgm[s0X:%qhSljkr`]tmaro58;'oRokds`\slbs`4;: nQnlfmqmqnj58&hSlvf_hf\slbs`4>'oRowi^qoescX|pzn1="l_`zj[qwm4;'oRlvtd]pmc:1%iTobcboo]`hn;7$jUoikozlu]geqg:8%iThd}nbmg\sdtiWkb}Snacl<2/gZbn{hhgiRynro]alsYuigmn1="l_dnbfjtf|`eeSig}=.jli`)uajkyhb!gabijjb)kp0'fen|`/nrfjhuw<::$j}in/ykomk~Xdq3Tnbo}d.msakktx=9;#zc/wgqmii`'jeyijka/uos+Ze`'%iTjlcflx?ptdtsig<'oRfns^c{mZoc59&hSeo|_dlb94*dWakxSh`m=1.`[mgtW`dainzjrs?3(fYoizUfi`Q`uurvpZtbozUj1="l_icp[hcjWf|xzPrdep[g;7$jUcm~Qbuy]lqqvr|Vxnk~Qn=1.`[mgtWdsSb{{ptv\v`atWk7; nQgar]qabebi4:'oRfns^pfcfce59&hSeo|_sqwe86+kVbjR||tc?3(fYoizUxckzjcb]jjussW{olRo20-a\lduX{flinmPotvsqqYumnyTn0>#c^kmmqYaaeoTblcj=om\gjcXn`fnSaanddf/gZoia}kTzlb20-a\mkosjV|j`0>#c^kmp`taijoTxt~j=1.`[iiflVceeyQiimg>4)eXelgTxt~j=1.`[hsWyc{iagae^qwebct59&hS}|fm^vzt`;6$jUyiljPddrwlZg::9>3 nQ}e`f\``vs`Vh6>=:7,b]qadbX`ndRo217.`[wcflV}bhyfPb<35(fYu{}U{~da}iu{\e8EB$jUyyQrhmqmqXj4IN nQ}su]w}uc:[PDH nQ}supbiZg:8%iT~~z}al]a95*dWzcfSnaclhqjkkYd`li`1LBC,b]vw`Yeq}oT{ho20-a\qvcXjp~nSzkm=1.`[pubWmommxb{_ecwe86+kVxiRklc<2/gZstmVydjyklc<2/gZqbiV}bhyf21-a\s`dX`nd0?#c^uqmqcXllzdRo2216;(fYpz`~nSikti]a97630%iT{g{e^ol``Yf5^XBXHQIISQW(fYpz`~nS`ake^`>SWOSMVLB^^Z#c^uqmqcX`ndRo217.`[rtn|lU|eizg_c?22)eXpmo}enkialko}8uwi{~jb;s>c:pliZ>:b&i`fQbel]dakYq>V8'wp64wdc?4?69>2}nm1>1}ABs64572:9m88ua16095>h6?:0=7)?80;35g>{T428277bc0908?k:l;R30f?7e93:1=>h:3:f2f7<7280:w^:l:057>4242899hi6?:21e0<=q\8??6=4>:081b~U3k3;<87?;3;306ab?8398j974$07f>45c3_;<=74=r9:l1<6s+156951=e9k81<7851c68 1d=9k90(<;>:09'506=9>?0e:18'510=9>=0b<:::098m4>7290/=9851658j4222;10e<9i:18'510=9>=0b<:::298m41b290/=9851658j4222=10e<9k:18'510=9>=0b<:::498m41d290/=9851658j4222?10e<9m:18'510=9>=0b<:::698m41f290/=9851658j4222110e<96:18'510=9>=0b<:::898m411290/=9851658j4222h10e<7::18'510=90>0b<:::198m4?4290/=9851868j4222810e<7=:18'510=90>0b<:::398m4?6290/=9851868j4222:10e<7?:18'510=90>0b<:::598m4>a290/=9851868j4222<10e<7j:18'510=90>0b<:::798m4?c290/=9851868j4222>10e<7l:18'510=90>0b<:::998m4?e290/=9851868j4222010e<7n:18'510=90>0b<:::`98m4?>290/=9851868j4222k10e<77:18'510=90>0b<:::b98m4?0290/=9851868j4222m10e<79:18'510=90>0b<:::d98m4>b290/=9851868j4222o10e<6k:188m4d72900c:18'510=9h?0b<:::598k4g7290/=9851`78j4222<10c10c5<7s-;>m7ki;I35`>N6=m1dih4?::a50d=83hh6=4?{%36e?7302B::i5G14f8^62=kr?1:7k5138e>45=990h6o4k:039e?{i"bk3oo7)h?:29'b4<43-l96>5+f280?!`32:1/j84<;%d5>6=#n>087)h7:29'b<<43-lj6>5+fc80?!`d2:1/ji4<;%df>6=#no087)??0;18 4662:1/==<53:&246<43-;;87=4$026>6=#99<1?6*>0680?!770390(<>6:29'55g=;2.:5+11g97>"68o087)?>0;18 4762:1/=<<53:&256<43-;:87=4$036>6=#98<1?6*>1680?!760390(5+10g97>"69o087)?=0;18 4462:1/=?<53:&266<43-;987=4$006>6=#9;<1?6*>2680?!750390(<<6:29'57g=;2.:>o4<;%31g?5<,88o6>5+13g97>"6:o087)?<0;18 4562:1/=><53:&276<43-;887=4$016>6=#9:<1?6*>3680?!740380(<=6:39'56g=9=80(<:k:07:?!73m39>7)?;f;16?!72:3987)?:3;361>"6=?097)?:7;08 40f28<27)?9b;35=>o6<00;66g=64:4n066>5=478:0>h6<<0:76g62;29 42120>0b<:::398m<7=83.:8;464:l200<432c::>4?:%372?71:2d:884?;:k224<72-;?:7?92:l200<632c::=4?:%372?71:2d:884=;:k21c<72-;?:7?92:l200<432ei87>5$065>g5>6=54oc094?"64482?>ie83:1(<:9:c18j4222;10clh50;&203=6o=4n066>1=478a7>h6<<0>76anc;29 4212k90b<:::798kdd=83.:8;4m3:l200<032ejm7>5$065>g5>6554o`;94?"6448:?>if03:1(<:9:c18j4222h10cl950;&203=6o=4n066>f=1<7*>478a7>h6<<0o76an3;29 4212k90b<:::d98kd4=83.:8;4m3:l2005$065>g5>6<>4;nc3>5<#9=<1n>5a157954=478a7>h6<<0:>65`9d83>!73>3h87c?;5;30?>i>l3:1(<:9:c18j42228>07b7l:18'510=j:1e=9;51498kgd=83.:8;4m3:l200<6>21dnl4?:%372?d43g;?97?8;:ma=?6=,8>=6o=4n066>4><3fh36=4+1549f6=i9=?1=454oc594?"64482e>=hj?0;6)?;6;`0?k73=3;i76am5;29 4212k90b<:::0a8?jd6290/=985b29m513=9m10cl850;&203e:9l=g<72-;?:7l<;o371?7a32c:m7>5$065>4?>6=54i0:94?"64482?>o6?3:1(<:9:0;8j4222;10e<850;&203<612d:884<;:k17?6=,8>=6<74n066>1=4782=>h6<<0>76g=1;29 4212830b<:::798m76=83.:8;4>9:l200<032c:j7>5$065>4?>6554i0g94?"6448:?>o6l3:1(<:9:0;8j4222h10e=6<74n066>f=4782=>h6<<0o76g=9;29 4212;20b<:::198m71=83.:8;4=8:l200<632c9:7>5$065>7>>6?54i3794?"64480?>o4:3:1(<:9:3:8j4222=10e>?50;&203<502d:884:;:k04?6=,8>=6?64n066>3=4781<>h6<<0<76g=e;29 4212;20b<:::998m7b=83.:8;4=8:l200<>32c9o7>5$065>7>>6l54i3`94?"6448a?>o5i3:1(<:9:3:8j4222j10e?:50;&203<502d:884k;:k;=?6=,8>=6564n066>5=478;<>h6<<0:76g75;29 4212120b<:::398m=2=83.:8;478:l200<432c3?7>5$065>=>>6954i9094?"64486?>o?93:1(<:9:9:8j4222?10e5>50;&203=6564n066>==o1<7*>478;<>h6<<0276g8d;29 4212120b<:::`98m2e=83.:8;478:l2005$065>=>>6n54i6;94?"6448g?>o003:1(<:9:9:8j4222l10e:950;&203=6564n066>46<3`=>6=4+1549<==i9=?1=<54i6694?"644826>=n?:0;6)?;6;:;?k73=3;876g82;29 4212120b<:::068?l16290/=985899m513=9<10e4>50;&2036:9j5$065>=>>6<64;h:g>5<#9=<1455a15795<=478;<>h6<<0:m65f8c83>!73>3237c?;5;3a?>o?i3:1(<:9:9:8j42228i07d69:18'510=011e=9;51e98m2d=83.:8;478:l200<6m21b;=4?:%372?>?3g;?97?i;:mf7?6=,8>=6h<4n066>5=478f6>h6<<0:76aj0;29 4212l80b<:::398ka`=83.:8;4j2:l200<432c2m7>5$065>>6=54i8:94?"64482?>o>?3:1(<:9:8;8j4222;10e4850;&203<>12d:884<;:mf=6h94n066>5=478f3>h6<<0:76aj5;29 4212l=0b<:::398k`2=83.:8;4j7:l200<432eo:7>5$065>a3>6=54oe694?"64482?>ic:3:1(<:9:e78j4222;10ci?50;&203=6i;4n066>1=478g1>h6<<0>76ale;29 4212m?0b<:::798kfb=83.:8;4k5:l200<032eho7>5$065>a3>6554ob`94?"6448:?>idi3:1(<:9:e78j4222h10cn750;&203=6i;4n066>f=478g1>h6<<0o76al5;29 4212m?0b<:::d98kf2=83.:8;4k5:l2005$065>a3>6<>4;na1>5<#9=<1h85a157954=478g1>h6<<0:>65`c183>!73>3n>7c?;5;30?>ien3:1(<:9:e78j42228>07blj:18'510=l<1e=9;51498kab=83.:8;4k5:l200<6>21dhn4?:%372?b23g;?97?8;:mgf?6=,8>=6i;4n066>4><3fnj6=4+1549`0=i9=?1=454oe;94?"64482e>=hl10;6)?;6;f6?k73=3;i76ak7;29 4212m?0b<:::0a8?jb4290/=985d49m513=9m10cn650;&203e:9lfa<72-;?:7j:;o371?7a32c::54?:%372?71?2d:884?;:k223<72-;?:7?97:l200<632c::84?:%372?71?2d:884=;:k221<72-;?:7?97:l200<432c=47>5$065>31>6=54i7494?"64482?>o1<3:1(<:9:758j4222;10e;=50;&203<1?2d:884<;:k56?6=,8>=6;94n066>1=47853>h6<<0>76g90;29 4212?=0b<:::798m0`=83.:8;497:l200<032c>i7>5$065>31>6554i4f94?"6448:?>o2k3:1(<:9:758j4222h10e8l50;&203<1?2d:884m;:k6=?6=,8>=6;94n066>f=47853>h6<<0o76g:7;29 4212?=0b<:::d98m00=83.:8;497:l20097>5$065>31>6<>4;h77>5<#9=<1::5a157954=47853>h6<<0:>65f5383>!73>3<<7c?;5;30?>o293:1(<:9:758j42228>07d;?:18'510=>>1e=9;51498m3`=83.:8;497:l200<6>21b:h4?:%372?003g;?97?8;:k5`?6=,8>=6;94n066>4><3`4482e>=n>h0;6)?;6;44?k73=3;i76g99;29 4212?=0b<:::0a8?l02290/=985669m513=9m10e8o50;&203<1?2d:884>e:9j0c<72-;?:788;o371?7a32wi=8m50;``>5<7s-;>m7?;8:J22a=O9:5cz792?c=9;0m6<=5118`>g5=#mk0nh6*jc;gg?!`72:1/j<4<;%d1>6=#n:087)h;:29'b0<43-l=6>5+f680?!`?2:1/j44<;%db>6=#nk087)hl:29'ba<43-ln6>5+fg80?!778390(<>>:29'554=;2.:<>4<;%330?5<,8:>6>5+11497>"68>087)??8;18 46>2:1/==o53:&24g<43-;;o7=4$02g>6=#99o1?6*>0g80?!768390(:29'544=;2.:=>4<;%320?5<,8;>6>5+10497>"69>087)?>8;18 47>2:1/=6=#98o1?6*>1g80?!758390(<<>:29'574=;2.:>>4<;%310?5<,88>6>5+13497>"6:>087)?=8;18 44>2:1/=?o53:&26g<43-;9o7=4$00g>6=#9;o1?6*>2g80?!748390(<=>:29'564=;2.:?>4<;%300?5<,89>6>5+12497>"6;>087)?<8;08 45>2;1/=>o51508 42c28?27)?;e;16?!73n39>7)?:2;10?!72;3;>96*>5781?!72?380(<8n:04:?!71j3;=56g>4883>>o4l3:17dkn:188m42d2900e9<50;9j51g=831b=9l50;9ja<<722c297>5$065><2>6=54i8194?"64482?>o>:3:1(<:9:868j4222;10e4?50;&203<><2d:884<;:k226<72-;?:7?92:l200<732c::<4?:%372?71:2d:884>;:k225<72-;?:7?92:l200<532c:9k4?:%372?71:2d:884<;:ma0?6=,8>=6o=4n066>5=478a7>h6<<0:76am0;29 4212k90b<:::398kd`=83.:8;4m3:l200<432eji7>5$065>g5>6954o`f94?"64486?>ifk3:1(<:9:c18j4222?10cll50;&203=6o=4n066>==478a7>h6<<0276an8;29 4212k90b<:::`98kd1=83.:8;4m3:l2005$065>g5>6n54o`694?"6448g?>if;3:1(<:9:c18j4222l10cl<50;&203=6o=4n066>46<3fk;6=4+1549f6=i9=?1=<54o8d94?"644826>=h1l0;6)?;6;`0?k73=3;876a6d;29 4212k90b<:::068?j?d290/=985b29m513=9<10col50;&2036:9lfd<72-;?:7l<;o371?7032ei57>5$065>g5>6<64;n`;>5<#9=<1n>5a15795<=478a7>h6<<0:m65`b783>!73>3h87c?;5;3a?>ie=3:1(<:9:c18j42228i07bl>:18'510=j:1e=9;51e98kd0=83.:8;4m3:l200<6m21d5o4?:%372?d43g;?97?i;:k2e?6=,8>=6<74n066>5=4782=>h6<<0:76g>7;29 4212830b<:::398m40=83.:8;4>9:l200<432c9?7>5$065>4?>6954i3094?"64486?>o593:1(<:9:0;8j4222?10e?>50;&203<612d:8848;:k2b?6=,8>=6<74n066>==4782=>h6<<0276g>d;29 4212830b<:::`98m4e=83.:8;4>9:l2005$065>4?>6n54i0794?"6448g?>o513:1(<:9:3:8j4222910e?950;&203<502d:884>;:k12?6=,8>=6?64n066>7=4781<>h6<<0876g<2;29 4212;20b<:::598m67=83.:8;4=8:l200<232c8<7>5$065>7>>6;54i3d94?"64484?>o5m3:1(<:9:3:8j4222110e?j50;&203<502d:8846;:k1g?6=,8>=6?64n066>d=4781<>h6<<0i76g=a;29 4212;20b<:::b98m72=83.:8;4=8:l2005$065>=>>6=54i9594?"64482?>o?=3:1(<:9:9:8j4222;10e5:50;&203=6564n066>1=478;<>h6<<0>76g71;29 4212120b<:::798m=6=83.:8;478:l200<032c5$065>=>>6554i6g94?"6448:?>o0l3:1(<:9:9:8j4222h10e:m50;&203=6564n066>f=31<7*>478;<>h6<<0o76g88;29 4212120b<:::d98m21=83.:8;478:l2005$065>=>>6<>4;h56>5<#9=<1455a157954=>1<7*>478;<>h6<<0:>65f7283>!73>3237c?;5;30?>o0:3:1(<:9:9:8j42228>07d9>:18'510=011e=9;51498m<6=83.:8;478:l200<6>21b4k4?:%372?>?3g;?97?8;:k;a?6=,8>=6564n066>4><3`2o6=4+1549<==i9=?1=454i9a94?"64482e>=n0k0;6)?;6;:;?k73=3;i76g7a;29 4212120b<:::0a8?l>1290/=985899m513=9m10e:l50;&203e:9j35<72-;?:767;o371?7a32en?7>5$065>`4>6=54od394?"66`>4482?>ib83:1(<:9:d08j4222;10cih50;&203=6474n066>5=478:=>h6<<0:76g67;29 4212030b<:::398m<0=83.:8;469:l200<432en47>5$065>`1>6=54od494?"64482?>ib=3:1(<:9:d58j4222;10ch:50;&203=6i;4n066>5=1<7*>478g1>h6<<0:76ak2;29 4212m?0b<:::398ka7=83.:8;4k5:l200<432eo<7>5$065>a3>6954obd94?"64486?>idm3:1(<:9:e78j4222?10cnj50;&203=6i;4n066>==478g1>h6<<0276ala;29 4212m?0b<:::`98kf?=83.:8;4k5:l2005$065>a3>6n54ob494?"6448g?>id=3:1(<:9:e78j4222l10cn:50;&203=6i;4n066>46<3fi96=4+1549`0=i9=?1=<54ob394?"644826>=hk90;6)?;6;f6?k73=3;876amf;29 4212m?0b<:::068?jdb290/=985d49m513=9<10cij50;&2036:9l`f<72-;?:7j:;o371?7032eon7>5$065>a3>6<64;nfb>5<#9=<1h85a15795<=478g1>h6<<0:m65`d983>!73>3n>7c?;5;3a?>ic?3:1(<:9:e78j42228i07bj<:18'510=l<1e=9;51e98kf>=83.:8;4k5:l200<6m21dni4?:%372?b23g;?97?i;:k22=<72-;?:7?97:l200<732c::;4?:%372?71?2d:884>;:k220<72-;?:7?97:l200<532c::94?:%372?71?2d:884<;:k5=6;94n066>5=47853>h6<<0:76g94;29 4212?=0b<:::398m35=83.:8;497:l200<432c=>7>5$065>31>6954i7394?"64486?>o183:1(<:9:758j4222?10e8h50;&203<1?2d:8848;:k6a?6=,8>=6;94n066>==47853>h6<<0276g:c;29 4212?=0b<:::`98m0d=83.:8;497:l20057>5$065>31>6n54i4:94?"6448g?>o2?3:1(<:9:758j4222l10e8850;&203<1?2d:884i;:k61?6=,8>=6;94n066>46<3`??6=4+154922=i9=?1=<54i4194?"644826>=n=;0;6)?;6;44?k73=3;876g:1;29 4212?=0b<:::068?l37290/=985669m513=9<10e;h50;&203<1?2d:884>6:9j2`<72-;?:788;o371?7032c=h7>5$065>31>6<64;h4`>5<#9=<1::5a15795<=47853>h6<<0:m65f6`83>!73>3<<7c?;5;3a?>o113:1(<:9:758j42228i07d8::18'510=>>1e=9;51e98m0g=83.:8;497:l200<6m21b8k4?:%372?003g;?97?i;:p516=83h70?:b;0:?872j38<70?:b;05?872j38>70?:b;11?872j39:70?:b;13?872j38m70?:b;0f?872j38o70?:b;0`?872j38i70?:b;0b?872j38?70?:b;4;?872j3<=70?:b;47?872j3<870?:b;41?872j3<:70?:b;43?872j3?m70?:b;7f?872j3?o70?:b;7`?872j3?i70?:b;7:?872j3?370?:b;74?872j3?=70?:b;76?872j3??70?:b;70?872j3?970?:b;72?872j3?;70?:b;4e?872j370?:b;57?872j3=870?:b;51?872j3=:70?:b;;3?872j32m70?:b;:f?872j32o70?:b;:`?872j32i70?:b;:b?872j32=70?:b;5a?872j3=;70?:b;;6?872j33870?:b;;1?872j33j70?:b;;;?872j33<70?:b;;5?872j3;=463>5c8223=:940334;>n7:=;<36f?cf34;>n7?;9:?21g<6h70?:c;3`?872k3;i70?:c;36?872k38270?:c;04?872k38=70?:c;06?872k39970?:c;12?872k39;70?:c;0e?872k38n70?:c;0g?872k38h70?:c;0a?872k38j70?:c;07?872k3<370?:c;45?872k370?:c;77?872k3?870?:c;71?872k3?:70?:c;73?872k370?:c;57?872k3=870?:c;51?872k3=:70?:c;;3?872k32m70?:c;:f?872k32o70?:c;:`?872k32i70?:c;:b?872k32=70?:c;5a?872k3=;70?:c;;6?872k33870?:c;;1?872k33:70?:c;;b?872k33370?:c;;4?872k33=70?:c;35<>;6=j0::;5214a9533<58?h6<8;;<36g?2534;>o7kn;<36g?73127:9n4>4`9>50e=9=h01<;l:06`?xu61o0;6?uQ18d8943e20h0q~?n7;296~X6i>16=8l5a79~w4g?2909wS?n8:?21g34;>n7l:;|q2ed<72;qU=lo4=07a>g052z\2eg=:95<5sW;jo63>5c8a<>{t9hn1<7ad83>7}Y9ho01<;m:ed8yv7fn3:1>vP>ag9>50e=1k1v;<36g?d63ty:m?4?:3y]5d4<58?h6o;4}r3b7?6=:rT:m>5214a9f3=z{8k?6=4={_3b0>;6=j0i;6s|1`494?4|V8k=70?:c;`;?xu6j90;6>uQ1c28943e2l301<;l:d;8yv7?l3:1?vP>8e9>50d=;m16=8m53e9~w4>b2909wS?7e:?21g<3n2wx=4850;0xZ4?134;>n7;n;|q2=2<72;qU=494=07a>3352z\2===:95<5sW;2563>5c85e>{t90k1<79c83>7}Y90h01<;m:7a8yv7>k3:1>vP>9b9>50d=>m1v<7k:181[7>l27:9o461:p5;6=j0=56s|18094?4|V83970?:c;4b?xu61:0;6?uQ1818943d2?h0q~?65;296~X61<16=8m56b9~w4112908wS?86:?21g<6l27:9n4>d:p52?=839pR<96;<36f?7b34;>o7?j;|q23d<72:qU=:o4=07a>4`<58?h6=5rs05`>5<4sW;5c815>;6=j09=6s|16f94?5|V8=o70?:b;01?872k3897p}>7d83>6}Y9>o01<;m:318943d2;90q~?8f;297~X6?o16=8l5179>50e=9?1v<6?:180[7?827:9o4>7:?21f<6?2wx=5?50;1xZ4>634;>n7?7;<36g?7?3ty:;54?:2y]52><58?i64g59z\2f3=:940634;>n7?90:?21g<6=o16=8m51718943d28<:70?:c;354>;6=j0:9k5r}o3a1?6=9rB:9i5rn0`5>5<6sA;>h6sa1c594?7|@8?o7p`>b983>4}O951zJ21a=zf8hn6=4>{I36`>{i9kl1<7?tH07g?xh6k90;65e9~j4e5290:wE?:d:m5f5=83;pD<;k;|l2g1<728qC=8j4}o3`1?6=9rB:9i5rn0a5>5<6sA;>h6sa1b594?7|@8?o7p`>c983>4}O951zJ21a=zf8in6=4>{I36`>{i9jl1<7?tH07g?xh6l90;65e9~j4b5290:wE?:d:m5a5=83;pD<;k;|l2`1<728qC=8j4}o3g1?6=9rB:9i5rn0f5>5<6sA;>h6sa1e594?7|@8?o7p`>d983>4}O951zJ21a=zf8nn6=4>{I36`>{i9ml1<7?tH07g?xh6m90;65e9~j4c5290:wE?:d:m5`5=83;pD<;k;|~yEFDs;;864?maba26xFGJr:vLM^t}AB \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp (nonexistent) @@ -1,162 +0,0 @@ -Encore.Project.ProjectDir = /home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/tmp/_cg -Encore.Project.ElaborationDir = /home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/tmp/_cg -Encore.Project.TmpDir = /home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/tmp/_cg -Encore.Project.Path = /home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/tmp/_cg -Encore.Project.FlowVendor = Other -Encore.Project.VhdlSim = false -Encore.Project.VerilogSim = true -Encore.Project.XDevice = xc6slx9 -Encore.Project.XDeviceFamily = spartan6 -Encore.Project.XSpeedGrade = -2 -Encore.Project.XPackage = csg324 - -c_xco_list = Component_Name=chipscope_ila;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=1024;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=46;Match_Units_1=4;Counter_Width_1=2;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false -c_xdevicefamily = spartan6 -c_core_type = 2 -c_mfg_id = 1 -c_major_version = 13 -c_minor_version = 2 -c_build_revision = 0 -c_core_major_ver = 1 -c_core_minor_ver = 4 -c_core_minor_alpha_ver = 97 -c_ram_type = 1 -c_srl16_type = 2 -c_use_inv_clk = 0 -c_use_rpm = 1 -c_use_trig_out = 0 -c_use_atc_clkin = 0 -c_use_data = 0 -c_use_trig0 = 1 -c_use_trig1 = 0 -c_use_trig2 = 0 -c_use_trig3 = 0 -c_use_trig4 = 0 -c_use_trig5 = 0 -c_use_trig6 = 0 -c_use_trig7 = 0 -c_use_trig8 = 0 -c_use_trig9 = 0 -c_use_trig10 = 0 -c_use_trig11 = 0 -c_use_trig12 = 0 -c_use_trig13 = 0 -c_use_trig14 = 0 -c_use_trig15 = 0 -c_use_trigdata0 = 1 -c_use_trigdata1 = 0 -c_use_trigdata2 = 0 -c_use_trigdata3 = 0 -c_use_trigdata4 = 0 -c_use_trigdata5 = 0 -c_use_trigdata6 = 0 -c_use_trigdata7 = 0 -c_use_trigdata8 = 0 -c_use_trigdata9 = 0 -c_use_trigdata10 = 0 -c_use_trigdata11 = 0 -c_use_trigdata12 = 0 -c_use_trigdata13 = 0 -c_use_trigdata14 = 0 -c_use_trigdata15 = 0 -c_data_width = 1 -c_data_depth = 1024 -c_use_gap = 0 -c_timestamp_type = 0 -c_timestamp_width = 32 -c_timestamp_depth = 512 -c_use_storage_qual = 1 -c_tseq_type = 0 -c_num_tseq_cnt = 0 -c_tseq_cnt1_width = 1 -c_tseq_cnt0_width = 1 -c_num_tseq_states = 1 -c_use_tc_mcnt = 0 -c_tc_mcnt_width = 1 -c_ext_cap_rate_mode = 0 -c_ext_cap_pin_mode = 0 -c_num_ext_cap_pins = 8 -c_ext_cap_use_reg = 1 -c_num_match_units = 4 -c_trig0_width = 46 -c_trig1_width = 1 -c_trig2_width = 1 -c_trig3_width = 1 -c_trig4_width = 1 -c_trig5_width = 1 -c_trig6_width = 1 -c_trig7_width = 1 -c_trig8_width = 1 -c_trig9_width = 1 -c_trig10_width = 1 -c_trig11_width = 1 -c_trig12_width = 1 -c_trig13_width = 1 -c_trig14_width = 1 -c_trig15_width = 1 -c_m0_tpid = 0 -c_m1_tpid = 0 -c_m2_tpid = 0 -c_m3_tpid = 0 -c_m4_tpid = 4 -c_m5_tpid = 5 -c_m6_tpid = 6 -c_m7_tpid = 7 -c_m8_tpid = 8 -c_m9_tpid = 9 -c_m10_tpid = 10 -c_m11_tpid = 11 -c_m12_tpid = 12 -c_m13_tpid = 13 -c_m14_tpid = 14 -c_m15_tpid = 15 -c_m0_type = 1 -c_m1_type = 1 -c_m2_type = 1 -c_m3_type = 1 -c_m4_type = 0 -c_m5_type = 0 -c_m6_type = 0 -c_m7_type = 0 -c_m8_type = 0 -c_m9_type = 0 -c_m10_type = 0 -c_m11_type = 0 -c_m12_type = 0 -c_m13_type = 0 -c_m14_type = 0 -c_m15_type = 0 -c_use_mcnt0 = 1 -c_use_mcnt1 = 1 -c_use_mcnt2 = 1 -c_use_mcnt3 = 1 -c_use_mcnt4 = 0 -c_use_mcnt5 = 0 -c_use_mcnt6 = 0 -c_use_mcnt7 = 0 -c_use_mcnt8 = 0 -c_use_mcnt9 = 0 -c_use_mcnt10 = 0 -c_use_mcnt11 = 0 -c_use_mcnt12 = 0 -c_use_mcnt13 = 0 -c_use_mcnt14 = 0 -c_use_mcnt15 = 0 -c_mcnt0_width = 2 -c_mcnt1_width = 2 -c_mcnt2_width = 2 -c_mcnt3_width = 2 -c_mcnt4_width = 1 -c_mcnt5_width = 1 -c_mcnt6_width = 1 -c_mcnt7_width = 1 -c_mcnt8_width = 1 -c_mcnt9_width = 1 -c_mcnt10_width = 1 -c_mcnt11_width = 1 -c_mcnt12_width = 1 -c_mcnt13_width = 1 -c_mcnt14_width = 1 -c_mcnt15_width = 1 -c_example_design = true -ComponentName = chipscope_ila

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt (nonexistent) @@ -1,50 +0,0 @@ -The following files were generated for 'chipscope_icon' in directory -/home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_lx9_board/openmsp430/rtl/verilog/coregen/ - -XCO file generator: - Generate an XCO file for compatibility with legacy flows. - - * chipscope_icon.xco - -Creates an implementation netlist: - Creates an implementation netlist for the IP. - - * chipscope_icon.ngc - * chipscope_icon.v - * chipscope_icon.veo - -Creates an HDL instantiation template: - Creates an HDL instantiation template for the IP. - - * chipscope_icon.veo - -IP Symbol Generator: - Generate an IP symbol based on the current project options'. - - * chipscope_icon.asy - -Generate ISE metadata: - Create a metadata file for use when including this core in ISE designs - - * chipscope_icon_xmdf.tcl - -Generate ISE subproject: - Create an ISE subproject for use when including this core in ISE designs - - * chipscope_icon.gise - * chipscope_icon.xise - -Deliver Readme: - Text file indicating the files generated and how they are used. - - * chipscope_icon_readme.txt - -Generate FLIST file: - Text file listing all of the output files produced when a customized core was - generated in the CORE Generator. - - * chipscope_icon_flist.txt - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl (nonexistent) @@ -1,67 +0,0 @@ -# The package naming convention is _xmdf -package provide chipscope_icon_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::chipscope_icon_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::chipscope_icon_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon -} -# ::chipscope_icon_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_ds512.pdf =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_ds512.pdf (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_ds512.pdf (nonexistent)

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_ds512.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt (nonexistent) @@ -1,203 +0,0 @@ - Core name: Xilinx LogiCORE Block Memory Generator - Version: 6.2 - Release Date: June 22, 2011 - - -================================================================================ - -This document contains the following sections: - -1. Introduction -2. New Features -3. Supported Devices -4. Resolved Issues -5. Known Issues -6. Technical Support -7. Core Release History -8. Legal Disclaimer - -================================================================================ - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm - - -2. NEW FEATURES - - - ISE 13.2 software support - - Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support - -3. SUPPORTED DEVICES - -The following device families are supported by the core for this release. - -Zynq-7000* - -Virtex-7 -Virtex-7 XT (7vx485t) -Virtex-7 -2L - -Kintex-7 -Kintex-7 -2L - -Artix-7* - -Virtex-6 XC CXT/LXT/SXT/HXT -Virtex-6 XQ LXT/SXT -Virtex-6 -1L XQ LXT/SXT - -Spartan-6 XC LX/LXT -Spartan-6 XA -Spartan-6 XQ LX/LXT -Spartan-6 -1L XQ LX - -Virtex-5 XC LX/LXT/SXT/TXT/FXT -Virtex-5 XQ LX/ LXT/SXT/FXT - -Virtex-4 XC LX/SX/FX -Virtex-4 XQ LX/SX/FX -Virtex-4 XQR LX/SX/FX - -Spartan-3 XC -Spartan-3 XA -Spartan-3A XC 3A / 3A DSP / 3AN DSP -Spartan-3A XA 3A / 3A DSP -Spartan-3E XC -Spartan-3E XA - -*To access these devices in the ISE Design Suite, contact your Xilinx FAE. - -4. RESOLVED ISSUES - -The following issues are resolved in Block Memory Generator v6.2: - - 1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices) - Version Fixed: v6.2 - - CR 587481 - - AR 39718 - -5. KNOWN ISSUES - -The following are known issues for v6.2 of this core at time of release: - - 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) - Work around: The user must review the possible scenarios that causes the collission and revise - their design to avoid those situations. - - CR588505 - - Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with - Write Mode = Read First in conjunction with asynchronous clocking - - 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. - - 3. Core does not generate for large memories. Depending on the - machine the ISE CORE Generator software runs on, the maximum size of the memory that - can be generated will vary. For example, a Dual Pentium-4 server - with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes - - CR 415768 - - AR 24034 - -The most recent information, including known issues, workarounds, and resolutions for -this version is provided in the IP Release Notes User Guide located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -6. TECHNICAL SUPPORT - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; -03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support -09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support -07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support -04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support -03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue -12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power - Device support; Automotive Spartan 3A - DSP device support -09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 -06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 -04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 -09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 -03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 -10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 -07/2007 Xilinx, Inc. 2.5 Revised to v2.5 -04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 -02/2007 Xilinx, Inc. 2.4 Revised to v2.4 -11/2006 Xilinx, Inc. 2.3 Revised to v2.3 -09/2006 Xilinx, Inc. 2.2 Revised to v2.2 -06/2006 Xilinx, Inc. 2.1 Revised to v2.1 -01/2006 Xilinx, Inc. 1.1 Initial release -================================================================================ - -8. Legal Disclaimer - - (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt (nonexistent) @@ -1,23 +0,0 @@ -# Output products list for -blk_mem_gen_ds512.pdf -blk_mem_gen_v6_2_readme.txt -rom_8x2k.asy -rom_8x2k.gise -rom_8x2k.ngc -rom_8x2k.v -rom_8x2k.veo -rom_8x2k.xco -rom_8x2k.xise -rom_8x2k_flist.txt -rom_8x2k_ste/example_design/bmg_wrapper.vhd -rom_8x2k_ste/example_design/rom_8x2k_top.ucf -rom_8x2k_ste/example_design/rom_8x2k_top.vhd -rom_8x2k_ste/example_design/rom_8x2k_top.xdc -rom_8x2k_ste/implement/implement.sh -rom_8x2k_ste/implement/planAhead_rdn.bat -rom_8x2k_ste/implement/planAhead_rdn.sh -rom_8x2k_ste/implement/planAhead_rdn.tcl -rom_8x2k_ste/implement/xst.prj -rom_8x2k_ste/implement/xst.scr -rom_8x2k_xmdf.tcl -summary.log

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp (nonexistent) @@ -1,22 +0,0 @@ -# Date: Wed Jul 20 14:13:06 2011 - -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -SET workingdirectory = ./tmp/ - -# CRC: 362d8c1f

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$0f15=6:2.Yi{g|inl9$4(5=<*/>6#>1:27?5679=1;<=<;;12301=7892?7=>>0593476339:?<95?0927?5778=1;==?;;10341=7<9:?7=6?00920>7789>0=;??1:07?76788=0?;4FNNWW>FII\[EG<1=::1<2?12<<9:;86;>01f82vj1jyl??:"209;0>>789;;75>?1923456799:;EKC;=;96MCK3Z;?FJL:Q;3<85LLJ;31>EKCH;<7NBDA0F13>EKCH;O8:5LLJC2@=3EKCM;>7NBDDWa8GIMC^VNBZDJJ5:AOOC^?3JF@JU?7029@HW?27;eEHF]XD@=2>5?a8GJHSZFF;0<81c:ALJQTHD96:;3m4CNLWVJJ74825o6M@NUPLH5:617h0OB@[RNN3848d3JEEX_AC0=03:f=DGG^YCA>320<`?FII\[EG<1<=>b9@KKRUGE:7>>0l;BMMPWIK858?2n5LOOVQKI6;:<4h7NAATSMO49416j1HCCZ]OM2?628d3JEEX_AC0=0;:f=DGG^YCA>32800;cEHF]XD@=2<>c9@KKRUGE:783l4CNLWVJJ74<4i7NAATSMO4909j2IDBY\@L1>4:g=DGG^YCA>38?`8GJHSZFF;040>4:ALV@Y@MGOYMYG@N^KMBJ1;E68@766:2NB86J]CJa8@WELWEEHMAQFc:FQGNYKGJKGSB=4FEA7?CBDM:1MHH=4FEP7?CBUM8h0J_AB #F\GIM%(]E+.GQLLJ #PLA6j2LYC@.-J^AOO'&SG)(OSNBD"!VJC7g/pR0b?CTHE)(^SNBD"!VL$'SXKEA),<;?01,3456789:;,}]7;GPLIZHDN81L?6IAD09J6>O7:2C:>6G=2:K06>O3:2C>56GAIUQWEQC43@D]m6D[AF]@LDOI12@_MJQ[ERV6?OYDDB80@D<4LN48HJGCMM<0@BMDEE58HJANKHF?7A[[159OQQ433E__895CUU44?HS_KPUG96CZXG76?HS_N?i0Ald`rWgqwliik2Gbbb|Yesqjkk4I?3F$==ujPL09S0>VFZ]8m7]K]INF#&OYDDB(+?=>?0/234567(yY+DDIG 42-456789*.m6^FN^@VWLB_j2ZBBRLZSOCNA<=WCVBGYY@B6:RP@JHB92[:7_;4RDQFP2=U]G^N_Y?4S29PAI3<[ACMX3]YTHRZ@_K:8PVYMWJF@56Z\_K]WKZB>3]YTYRZ@_K;8PVYRW]ETY95[YQG0`>S7'\UBOB@ I^[FWZDTKHD%YRL\/H]P2+OTQG$BSX]J_RMEPGUDIGUN]= Z_CQ6`>S7'\UBOB@ I^[FWZDTKHD%YRL\/H]VW@YTGO^I_NOA_DS3*LYR[LUS_YQ[CJ]TKWMFZF_EHRK^1/W\MFIIWKYHMCQMUGE12>S7'\UBOB@ I^[FWZDTKHD%YRL\/hFQGNYKGJKG>o5Z0.W\MFII'\UHAI!H_UCQC@R\99W%ER@J0/W\PDT@M]8i7X> U^K@KK)RWJGO#JQ[ASEFP^76U'CTBH>!U^VBVBCS:k1^<"[PIBMM+PYDEM%LSYO]GDVX57[)AVDN<#[PT@PDAQ4e3\:$YRGLOO-V[FKC'NU_M_IJTZ30Y+OXFL:%YRZNRFGW6g=R8&_TENAA/T]@IA)@W]KYKHZT15_-MZHB8'_TXL\HEU0a?P6(]VCHCC!Z_BOG+BYSI[MNXV?:]/K\AT6)]V^J^JK[2`9V4*SXAJEE#XQLME-D[QGUOL^P:P F_OG3*PYSI[MNX?o4U1-V[LEHF&_TO@J G^VBVBCSS>W%ER@J0/W\PDT@M]8j7X> U^K@KK)RWJGO#JQ[ASEFP^>Z&@UEI= Z_UCQC@R5i2_;#XQFCNL,QZEJL&MTXL\HEUY:Y+OXFL:%YRZNRFGW6f=R8&_TENAA/T]@IA)RWJEFAL@K_RGO+L2)N@Q;Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;;Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;:Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;9Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;8Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;?Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;>Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDGDGJBIQ\EM-J0+@NS;W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHEDKEHR]JL.K7*CO\;T$^SA[[2b9V4*SXAJEE#XQLME-V[FIJEHDOS^KC/H6-BL]3U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^3Z&\UGYYn5Z0.W\MFII'\UHAI!Z_BMNIDHCWZOG#D:!FHY;Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ;^*PYK]]8h7X> U^K@KK)RWJGO#XQLOSG\MAYTME%B8#HF[1_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT11_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT10_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT13_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT12_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT15_-QZJR\;n0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT14_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@RD]J@ZUBD&C?"KGT1\,V[ISS:j1^<"[PIBMM+PYDEM%^SNA]E^KG[VCK'@>%JDU=]/W\HPR5k2_;#XQFCNL,QZEJL&_TOB\J_HF\W@J(A=$MEV=R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC_KPIE]PAI)N<'LBW9S!U^NVP7e<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP9P Z_MWW6f=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q=Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR=V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS1W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\1T$^SA[[169V4*SXAJEE#XQLME-V[VCKWg;i7X> U^K@KK)RWJGO#XQ[ASEFPZEB9?1^<"[PIBMM+PYDEM%b_HBPn0`8Q5)RW@IDB"[PCLF,mQGUOL^7==0>b:W3+PYNKFD$YRMBD.kWEWAB\5;:2 U^K@KK)RWJGO#dZNRFGW8<86i2_;#XQFCNL,QZEJL&c_M_IJT^AF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ;Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8:V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8;V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8;V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS88V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS88V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS89V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS89V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8>V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8>V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8?V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8?V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS8W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\9T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]5U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^4Z&\UGOHn5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY7Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ6^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[4_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT5\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU9]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV8R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW:S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP;P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ3Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR2V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS0W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\1T$^SAMJ1d9V4*SXAJEE#XQLTSN\KPR(]VIFHJ\_00g8Q5)RW@IDB"[PCUPO[JSS'\UHAII]P002?P6(]VCHCC!Z_BVQHZIR\&_THLZN_WCOMA4?3\:$YRGLOO-V[FRUDVE^X"gLOLOBJAY@ZYUXIA2?>3:8Q5)RW@IDB"[PCUPO[JSS'`IDA@OAD^EQTZUBD5;5>=5Z0.W\MFII'\UHX_BPOTV,mAGSIV\J@DJ=1:W3+PYNKFD$YR][AU-E[VRF\R:V"XQ\T@V15>S7'\UBOB@ U^QWEQ)AWZ^JXV?R.T]PPDR592_;#XQFCNL,QZUSI]%MS^ZNTZ0^*PYT\H^9=6[?/T]JGJH(]VY_MY!I_RVBP^5Z&\UXXLZ>a:W3+PYNKFD$YR][AU-V[FKCO[Z;=i5Z0.W\MFII'\UXXLZ U^FBPDYQIECO=l5Z0.W\MFII'\UXXLZ U^QWEQEJL8i0Y=!Z_HALJ*SX[]K_#XQ\T@V@IAYi:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5;5><5Z0.W\MFII'\UXXLZ U^QWEQYDF]%HE1<1209V4*SXAJEE#XQ\T@V,QZUSI]UHBY!LI=1=64=R8&_TENAA/T]PPDR(]VY_MYQLNU-@M929:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5?5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%O0=0=0:W3+PYNKFD$YR][AU-V[VRF\VIEX"J31?03?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/E>1:76<]9%^SDM@N.W\WQGS'\UXXLZPCOV,@959:91^<"[PIBMM+PYT\H^$YR][AU]@JQ)C4=49<6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&N793R.T]E@WC5>2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\8T$^SA[[299V4*SXAJEE#XQ\T@V,QZUSI]UHBY!H[1_-QZ^HZJS9o6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP=P HnI,V[HS_KP8<7X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ:Q#[PFEPF63=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_4[)]VF^X?64U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV?R.T][KWE^:j1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S;W%KcF!U^OV\F_5?2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\:T$^SKJ]E348Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ0^*PYK]]837X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ9Q#[PXNP@]7e<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^5Z&NdC"XQBUYAZ62=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_6[)]VLO^H<9;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU<]/W\HPR502_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\;T$^SUA]CX0`?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY7Y+Ai@'_TAXVLY358Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ6^*PYAL[O9:6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP8P Z_MWW6==R8&_TENAA/T]PPDR(]VY_MYQLNU-D_1[)]VRD^NW=7:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT5\,V[CBUM;<0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR?V"XQCUU0;?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY6Y+SXPFXHU?>4U1-V[LEHF&_T_YO[/T]PPDRXKG^$_1>1219V4*SXAJEE#XQ\T@V,QZUSI]UHBY!\<0<14>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.Q?6;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+V:46;:0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR([5>5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%X080>c:W3+PYNKFD$YR][AU-V[VRF\VBBKE?m;T2,QZODGG%^S^ZNT.W\WQGSWEE\=;5Z0.W\MFII'\UXXLZ U^VGK4d<]9%^SDM@N.W\WQGS'\U_HBQaeyv2a>S7'\UBOB@ U^QWEQ)nKDNTK_^?_RGO5f=R8&_TENAA/T]PPDR(aMK_MRXNLHF2=>S7'\UBOB@ U^QWEQ)n[]K_0=0>9:W3+PYNKFD$YR][AU-jWQGS484:56[?/T]JGJH(]VY_MY!fSUCW878612_;#XQFCNL,QZUSI]%b_YO[<2<2g>S7'\UBOB@ U^QWEQ)n[]K_O@JPCD3f?P6(]VCHCC!Z_RVBP*oT\H^HAIQLE^l2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<1<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<0<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<3<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<2<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<5<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<4<2f>S7'\UBOB@ U^QWEQ)n[]K_SEGHH0c8Q5)RW@IDB"[PSUCW+lUSI]UGCZ?n;T2,QZODGG%^S^ZNT.kW@JYimq~9n6[?/T]JGJH(]VYRBN!H_R[MGZQHZMQ;Q#GPND2-QZ@CZ;h0Y=!Z_HALJ*SX[PDH#JQ\YOA\SJTCS8W%ER@J0/W\BAT5j2_;#XQFCNL,QZU^FJ%LS^WAC^ULVA]5U'CTBH>!U^DGV7d<]9%^SDM@N.W\W\HD'NUXUCMPWNPG_6[)AVDN<#[PFEP1f>S7'\UBOB@ U^QZJF)@WZSEORY@REY7Y+OXFL:%YRHKR3`8Q5)RW@IDB"[PSXL@+BYTQGIT[B\K[4_-MZHB8'_TJI\=b:W3+PYNKFD$YR]VNB-D[V_IKV]D^IU9]/K\AT6)]VLO^ U^K@KK)RWZSEO"g\YOA\SJTC4<4:i6[?/T]JGJH(]VYRBN!fSXL@[RIUL5<5=>5Z0.W\MFII'\U_HDQ}ef13?P6(]VCHCC!Z_UFL[HS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M2545<]9%^SDM@N.W\PAIXzlm:96[?/T]JGJH(]VcOMYOPCLF23>S7'\UBOB@ U^kGEQGXKDNTb<<4U1-V[LEHF&_Te^KC_o3:?P6(]VCHCC!fCNONEKBXO[Z7<3?6;T2,QZODGG%bOBCBAOF\CWV;97;27X> U^K@KK)nKFGFMCJPSDN?4;7f3\:$YRGLOO-jGJKJIGNT_HB311<2e>S7'\UBOB@ iBMNIDHCWZOG0 U^K@KK)nKFGFMCJPSDN?5186i2_;#XQFCNL,mFIJEHDOS^KC<07=5<=R8&_TENAA/hALIHGILVYN@1?1189V4*SXAJEE#dM@MLCM@ZUBD585=45Z0.W\MFII'`IDA@OAD^QFH959901^<"[PIBMM+lEHEDKEHR]JL=6=5<=R8&_TENAA/hALIHGILVYN@1;1189V4*SXAJEE#dM@MLCM@ZUBD5<5=45Z0.W\MFII'`IDA@OAD^QFH919901^<"[PIBMM+lEHEDKEHR]JL=:=5<=R8&_TENAA/hALIHGILVYN@171149V4*SXAJEE#dM@RD]J@9699<1^<"[PIBMM+lEHZLUBH1?1149V4*SXAJEE#dM@RD]J@9499<1^<"[PIBMM+lEHZLUBH1=1189V4*SXAJEE#dM@RD]J@ZUBD5:5=l5Z0.W\MFII'`ID^HQFD^QFH9726890Y=!Z_HALJ*oCI]KTO@J>5:W3+PYNKFD$eIO[A^AN@Zha3\:$YRGLOO-j@WELm2_;#XQFCNL,mVCK991^<"[PIBMM+lUBDVdm7X> U^K@KK)n[PDHi6[?/T]JGJH(a]NBi6[?/T]JGJH(a]ND=;5Z0.W\MFII'`^OCRXJC=36:45<]9%^SDM@N.kW@JYimq~o7X> iRJJBQYH]]o0Y=!fUQFBP@YH]]<0Y]JNTDa8QVCUW_CXEOBJ6:W\FP@@=2_TOAE<;WA@=>PNM^U_U]K>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG:;YMQG\0YXWQFEARQP10]\[P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS89V"XQCCD1`?ZYXPEDFSRQ>2^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\9=W%YRBLE2a8[ZY_DGGTSR?<_^]V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]6=T$^SAMJ3c9\[Z^KFDUTS<:P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^7Z&\UGOH=m;^]\\IHJWVU:9RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX6X(RWEIN?o5P_^ZOJHYXW8XWV_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV;R.T]OG@5e3VUTTA@B_^]2=ZYX]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP:P Z_MAF7g=XWVRGB@QP_0]\[P6(]VCHCC!Z_BOG+PYDGDGJBIQ\EM-J0+@NS88V"XQCUU1a?ZYXPEDFSRQ=0^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\?T$^SAMJ3c9\[Z^KFDUTS??P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^>Z&\UGOH=m;^]\\IHJWVU9>RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX=X(RWEIN>i5P_^ZOJHYXW;9TSR[?/T]JGJH(]VI_^AQ@UU-V[FKCO[Z;?=5P_^ZOJHYXW;>TSR[?/T]JGJH(]VI_^AQ@UU-V[AGSIV\J@DJ=a:]\[]JIEVUT>8QP_T2,QZODGG%^S^WAC.W\CJRX[PDH?o5P_^ZOJHYXW;UTSX> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[02^*PYK]]9j7RQPXMLN[ZY4WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU7]/W\HPR4i2UTSUBAM^]\0ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP:P Z_MWW7d=XWVRGB@QP_4]\[P6(]VCHCC!Z_BOG+PYDGDGJBIQ\EM-J0+@NS=W%YRBZT2c8[ZY_DGGTSR8P_^W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^4Z&\UGYY=n;^]\\IHJWVU]/W\HFCc3hyrbnQkebmgaw?bdjtm2_xiR]`fu`pgdh:nhfxi!mPxegumfcaidcgu0}asvbj3*dWjeyiRzvpd?2(fYjiceyS{k}shmm945+kVgbbb|Pvdppmjh::%iTnxgcd^pfrlungg7; nQlosg\idlhzV|n~0?#c^alv`YjageyS{k}=4.`[fiumVgbbb|PamrkeZpbz43< nQbff]j`87+kVxiRlzfs?3(fYr{lUxe`3?,b]vw`Ytgo~inoa=1.`[ugu|Vcoobjj_sgdmvrbz4:'oR{|e^hwebYe}om6=!mPnto\gjhszffT|b|{s<3/gZstmVidby|`l1?2(fYr{lUhccz}om3>4)eX}zoTob`{rnn195*dW|ynSnaatsmo786+kVxiRm`nuplh1;7$jU~hQloovqki3:8%iTy~kPcnlwvjj159&hSx}j_bmmpwik?4:'oR{|e^aljqthd17; nQzsd]`kkruge36#c^wpaZehf}xd`2<2/gZstmVidby|`l01>4)eX}zoTob`{rnn2086+kVxiRkwt^`pgdh:8%iTy~kPuowpaaYe{jke1="l_tqf[}usW}i`Sza}k`plqkb:9%iTiuobpmg\``unog7mma}j,b]vw`tX{jkeSnfnio?2(x7e3jbb|~m`pd]jgjhX\@GN_]KL_OAE77=d``zxob~j_haljZp6W9?Tm!.Wimkm|%EHZL*Lick}aumq$45):>1hcx`{es48gvYj}q20o~Qbuy35e>odggUinoaf:k`kkYe{jkeSo{ig0a8mfiiWkyhmcQmuge\PLKB[YOHSU][f:k`kkYdemUoinake89jgjhXkfxnh6gloo]`pwjXg|~i7dm`n^qweqst12chccQ|yoa;?kadj|cghpNOp536?EF9j;1J7:51zQ6b?7f;33:6<==de:3>653j51e395?74:mn3<7=<4cd8W6>=9m;1=7?<2ef;4?54:182>4}T=o0:m>461;306ab?83988o84vUc1>5<62804;*77>5<#1?0>96`65;38?.34290/5;4:5:l:1?4<3"?96=4+97861>h>=3907&;>:18'=3<2=2d297:4;*73>5<#1?0>96`65;78?.2b290/5;4:5:l:1?0<3">o6=4+97861>h>=3=07&:l:18'=3<2=2d29764;*6a>5<#1?0>96`65;;8?.2f290/5;4:5:l:1?g<3">26=4+97861>h>=3h07&:7:18'=3<2=2d297m4;*64>5<#1?0>96`65;f8?.21290/5;4:5:l:1?c<3">>6=4+97861>h>=3l07&:<:18'=3<2=2d297??;:)76?6=,0<1985a94825>=,<80;6)79:478j<3=9;10'9>50;&:2?323g3>6<=4;*1e>5<#1?0>96`65;37?>-4m3:1(485549m=0<6=21 ?i4?:%;5>03>3?>7c7::058?.5e290/5;4:5:l:1?7?32!8m7>5$84910=i1<0:565$5e83>!?124d<3"?i6=4+97861>h>=3;h76%:a;29 <0==<1e584>d:9(1<<72-3=68;4n8795`=<#<21<7*66;76?k?228l07&:i:18'=3<2=2d297<>;:)70?6=,0<1985a94816>=,;00;6)79:478j<3=::10n<7k:182>5<7s-h:6<78;I3:f>N61=1d5?4?::a5t$c3934=O90h0D<7;;n53>5<h0j3;0b:m50:m:b?6=3fk>6=44o8a94?=hi=0;66a>9283>>i>j3:17b7j:188md0=831d>?4?::mbe?6=3f<86=44}c`0>5<52;09wE?64:&a5?7di2c=87>5;n46>5<6=4=:183!d628l0D<7m;I3:0>o0:3:17b7?:188yg7dj3:1<7>50zJ2=1=#j80j56Bn9;3x db=1=1vq~8;:181[0334;2979=;|q51?6=:rT=963>948:4>{zj8k0D<7m;I3:0>o0:3:17b7?:188yg71m3:1>7>50z&a5?1f3A;2n6F>959j37<722e2<7>5;|`22g<72=0;6=u+b085<>N61k1C=4:4$6;97>o593:17d<<:188m36=831d544?::a53?=83>1<7>t$c392==O90h0D<7;;%5:>6=n:80;66g=3;29?l072900c4750;9~f40d290?6=4?{%`2>30<@83i7E?64:&4=?5>o183:17b76:188ygba29096=4?{%`2>2g<@83i7E?64:k46?6=3f3;6=44}cg3>5<4290;w)l>:968L4?e3A;286*89;34?!?028h=7d9<:188m22=831d5=4?::afg<72<0;6=u+b0853>N61k1C=4:4$6;97>o593:17d<<:188m61=831b:=4?::m:=?6=3thio7>55;294~"e93<<7E?6b:J2=1=#?0087d<>:188m75=831b?:4?::k54?6=3f326=44}c`g>5<2290;w)l>:758L4?e3A;286*89;18m77=831b>>4?::k03?6=3`<;6=44o8;94?=zjko1<7;50;2x g7=>>1C=4l4H0;7?!1>2:1b><4?::k17?6=3`9<6=44i7294?=h100;66smb483>0<729q/n<497:J2=g=O90>0(:753:k15?6=3`886=44i2594?=n>90;66a69;29?xde>3:197>50z&a5?003A;2n6F>959'3<<43`8:6=44i3194?=n;>0;66g90;29?j?>2900qol8:186>5<7s-h:6;94H0;a?M7><2.<57=4i3394?=n::0;66g<7;29?l072900c4750;9~fg>=83?1<7>t$c3922=O90h0D<7;;%5:>6=n:80;66g=3;29?l502900e;>50;9l=<<722win44?:483>5}#j80=;6F>9c9K5<2<,>31?6g=1;29?l442900e>950;9j25<722e257>5;|`ae?6==3:1j2B:595+7880?l462900e?=50;9j72<722c=<7>5;n;:>5<6=4::183!d621?0D<7m;I3:0>"013;h7)78:0c6?l142900e::50;9j30<722c<:7>5;n;3>5<"013;37)78:0c6?l142900e::50;9j30<722c<:7>5;n;3>5<"013;>7)78:0`3?l142900e::50;9j30<722c<:7>5;n;3>5<"013;97)78:0`3?l142900e::50;9j30<722c<:7>5;n;3>5<"013;;7)78:0`4?l142900e::50;9j30<722c<:7>5;n;3>5<"013l0(4951c58m25=831b;94?::k41?6=3`==6=44o8294?=zjjo1<7;50;2x g7=0<1C=4l4H0;7?!1>2l1/5:4>b99j36<722c<87>5;h56>5<<1<75`9183>>{ekm0;684?:1y'f450z&a5?>23A;2n6F>959'3<5<>1<75f7483>>o0>3:17b7?:188ygee290>6=4?{%`2>=3<@83i7E?64:&4=?g<,0=1=o74i6194?=n?=0;66g85;29?l112900c4>50;9~ffg=83?1<7>t$c39<0=O90h0D<7;;%5:><=#1>0:nl5f7283>>o0<3:17d9::188m20=831d5=4?::ag<<72<0;6=u+b08;1>N61k1C=4:4$6;9<>">?3;im6g83;29?l132900e:;50;9j33<722e2<7>5;|``j2B:595+7884?!?028hi7d9<:188m22=831b;84?::k42?6=3f3;6=44}ca4>5<2290;w)l>:978L4?e3A;286*89;48 <1=9kh0e:=50;9j31<722c<97>5;h55>5<5;h56>5<<1<75`9183>>{ejo0;684?:1y'f45;h57>5<?1<75f7783>>i>83:17plk5;291?6=8r.i=76:;I3:f>N61=1/;44>c:k47?6=3`=?6=44i6794?=n??0;66a60;29?xdc<3:197>50z&a5?>23A;2n6F>959'3<<602c5;h57>5<?1<75f7783>>i>83:17plk3;291?6=8r.i=76:;I3:f>N61=1/;44>5:k47?6=3`=?6=44i6794?=n??0;66a60;29?xdc:3:197>50z&a5?>23A;2n6F>959'3<<6:2c5;h57>5<?1<75f7783>>i>83:17plk1;291?6=8r.i=76:;I3:f>N61=1/;44>0:k47?6=3`=?6=44i6794?=n??0;66a60;29?xdc83:197>50z&a5?>23A;2n6F>959'3<5<7s-h:65;4H0;a?M7><2.<57k4i6194?=n?=0;66g85;29?l112900c4>50;9~fab=83?1<7>t$c39<0=O90h0D<7;;%5:>f=n?:0;66g84;29?l122900e:850;9l=5<722wihn4?:483>5}#j80396F>9c9K5<2<,>31n6g83;29?l132900e:;50;9j33<722e2<7>5;|`gf?6==3:1j2B:595+788b?l142900e::50;9j30<722c<:7>5;n;3>5<"01330e:=50;9j31<722c<97>5;h55>5<5;h56>5<<1<75`9183>>{el10;684?:1y'f45;h57>5<?1<75f7783>>i>83:17plk7;291?6=8r.i=76:;I3:f>N61=1/;449;h50>5<>1<75f7483>>o0>3:17b7?:188ygb1290>6=4?{%`2>=3<@83i7E?64:&4=?3 91<75f7583>>o0=3:17d99:188k<6=831vnnh50;794?6|,k;1485G18`8L4?33-=2695f7283>>o0<3:17d9::188m20=831d5=4?::aa2<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:nn5f7283>>o0<3:17d9::188m20=831d5=4?::aa=<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:nn5f7283>>o0<3:17d9::188m20=831d5=4?::ab0<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:ml5f7283>>o0<3:17d9::188m20=831d5=4?::ab3<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:ml5f7283>>o0<3:17d9::188m20=831d5=4?::ab2<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mo5f7283>>o0<3:17d9::188m20=831d5=4?::ab=<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mo5f7283>>o0<3:17d9::188m20=831d5=4?::ab<<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mn5f7283>>o0<3:17d9::188m20=831d5=4?::abd<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mn5f7283>>o0<3:17d9::188m20=831d5=4?::abg<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mi5f7283>>o0<3:17d9::188m20=831d5=4?::abf<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mi5f7283>>o0<3:17d9::188m20=831d5=4?::aba<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mh5f7283>>o0<3:17d9::188m20=831d5=4?::ab`<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mh5f7283>>o0<3:17d9::188m20=831d5=4?::abc<72<0;6=u+b08;1>N61k1C=4:4$6;95f=#1>0:mk5f7283>>o0<3:17d9::188m20=831d5=4?::a556=83?1<7>t$c39<0=O90h0D<7;;%5:>4e<,0=1=lh4i6194?=n?=0;66g85;29?l112900c4>50;9~f466290>6=4?{%`2>=3<@83i7E?64:&4=?7d3-3<6;h50>5<>1<75f7483>>o0>3:17b7?:188yg77:3:197>50z&a5?>23A;2n6F>959'3<<6k2.2;7?m1:k47?6=3`=?6=44i6794?=n??0;66a60;29?xd68:0;684?:1y'f4b39j36<722c<87>5;h56>5<<1<75`9183>>{e99>1<7;50;2x g7=0<1C=4l4H0;7?!1>28i0(4951c08m25=831b;94?::k41?6=3`==6=44o8294?=zj8:>6=4::183!d621?0D<7m;I3:0>"013;h7)78:0`0?l142900e::50;9j30<722c<:7>5;n;3>5<55;294~"e932>7E?6b:J2=1=#?00:o6*67;3a7>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thn57>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3a`>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thnm7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3a`>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thnn7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3aa>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thno7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3aa>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thnh7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b2>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thni7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b2>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thnj7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b3>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thm<7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b3>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thm=7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b<>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thm>7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b<>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thm?7>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b=>o0;3:17d9;:188m23=831b;;4?::m:4?6=3thm87>55;294~"e932>7E?6b:J2=1=#?00:o6*67;3b=>o0;3:17d9;:188m23=831b;;4?::m:4?6=3th:<54?:283>5}#j80386F>9c9K5<2<,>31=95+9682f1=n?:0;66g84;29?j?72900qo??7;297?6=8r.i=76;;I3:f>N61=1/;44>1:&:3?7e<2c5;h57>5<5<4290;w)l>:968L4?e3A;286*89;3a?!?028h>7d9<:188m22=831d5=4?::a516=83>1<7>t$c39<<=O90h0D<7;;h50>5<>1<75f9e83>>i>83:17pl>3d83>1<729q/n<478:J2=g=O90>0e:=50;9j31<722c2h7>5;n;3>5<54;294~"e93237E?6b:J2=1=n?:0;66g84;29?l?c2900c4>50;9~f46c290>6=4?{%`2>=3<@83i7E?64:&4=?b 91<75f7583>>o0=3:17d99:188k<6=831vn<>j:186>5<7s-h:65;4H0;a?M7><2.<578>;h50>5<>1<75f7483>>o0>3:17b7?:188yg77n3:197>50z&a5?>23A;2n6F>959'3<<612c5;h57>5<?1<75f7783>>i>83:17pl>1183>0<729q/n<475:J2=g=O90>0(:75129j36<722c<87>5;h56>5<<1<75`9183>>{e98>1<7<50;2x g7=?h1C=4l4H0;7?l152900c4>50;9~f47629086=4?{%`2>=2<@83i7E?64:&4=?763`=86=44i6694?=h190;66sm10194?3=83:p(o?5849K50D<7m;I3:0>"013;i7)78:0`6?l142900e::50;9l=5<722wi=>h50;694?6|,k;1:55G18`8L4?33-=26>5f2083>>o5;3:17d8?:188k5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c314?6=<3:1j2B:595f2483>>o1:3:17d7k:188k2`=831vn<<8:180>5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c310?6=<3:1j2B:595f2483>>o1:3:17d7k:188k2`=831vn<5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c31j2B:595f2483>>o1:3:17d7k:188k2`=831vn<5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c31g?6=<3:1j2B:595f2483>>o1:3:17d7k:188k2`=831vn<=<:180>5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c304?6=<3:1j2B:595f2483>>o1:3:17d7k:188k2`=831vn<=9:180>5<7s-h:6<7n;I3:f>N61=1b>84?::k4a?6=3f3;6=44}c316?6=:3:1j2B:595+78820>o0;3:17b7?:188yg75>3:1>7>50z&a5?>43A;2n6F>959'3<<6<2c5;n;3>5<52;294~"e93287E?6b:J2=1=#?00:86g83;29?j?72900qo?=e;296?6=8r.i=76<;I3:f>N61=1/;44>4:k47?6=3f3;6=44}c306?6=:3:1j2B:595+78820>o0;3:17b7?:188yg74=3:1>7>50z&a5?>43A;2n6F>959'3<<6<2c5;n;3>5<55;294~"e93:188m75=831b:=4?::k:e?6=3f326=44}c311?6==3:1j2B:595+7880?l462900e?=50;9j25<722c2m7>5;n;:>5<55;294~"e93:188m75=831b:=4?::k:e?6=3f326=44}c31`?6==3:1j2B:595+7880?l462900e?=50;9j25<722c2m7>5;n;:>5<55;294~"e93:188m75=831b:=4?::k:e?6=3f326=44}c300?6==3:1j2B:595+7880?l462900e?=50;9j25<722c2m7>5;n;:>5<n7>55;294~"e932>7E?6b:J2=1=#?00n7d9<:188m22=831b;84?::k42?6=3f3;6=44}c36=?6=;3:1j2B:595+7882f>">?3;i:6g83;29?l132900c4>50;9~f43c29096=4?{%`2>2g<@83i7E?64:k46?6=3f3;6=44}c36e?6==3:1j2B:595+788e?l142900e::50;9j30<722c<:7>5;n;3>5<o7>55;294~"e93:188m75=831b:=4?::k:e?6=3f326=44}c366?6=<3:1j2B:595+7880?l462900e;>50;9j=d<722e257>5;|`216<72=0;6=u+b085=>N61k1C=4:4$6;97>o593:17d8?:188m1<7>t$c392<=O90h0D<7;;%5:>6=n:80;66g90;29?l?f2900c4750;9~f432290?6=4?{%`2>3?<@83i7E?64:&4=?5>o>i3:17b76:188yg72>3:187>50z&a5?0>3A;2n6F>959'3<<43`8:6=44i7294?=n1h0;66a69;29?xd6=>0;694?:1y'f4<112B:5o5G1868 2?=;2c9=7>5;h43>5<>{e9<21<7:50;2x g7=>01C=4l4H0;7?!1>2:1b><4?::k54?6=3`3j6=44o8;94?=zj8"013;o7d9<:188m22=831b;84?::k42?6=3`=<6=44i6:94?=h190;66sm1b694?6=83:p(o?5a89Ke2=Ki00?w)oi:7f8 g6=>l1/mh49c:&bg?0e3twx9:4?:3y]12=:9?k1;:5rs4494?4|V<<01k=5919~w02=838pR8:4=g39=5=z{<91<74=d;9=5=z{=o1<7008:4>{tbc<>82wx8l4?:3y]0d=:nm02<6s|4883>7}Y<016jo460:p0=<72;qU8552f88:4>{t<>0;6?uQ469>b2<>82wx8;4?:3y]03=:n<02<6s|4483>7}Y<<16i:460:p06<72;qU8>52f58:4>{t<;0;6?uQ439>b7<>82wx8<4?:3y]04=:n902<6s|4183>7}Y<916ih460:p7c<72;qU?k52eb8:4>{t;l0;6?uQ3d9>ad<>82wx?i4?:3y]7a=:99<15=5rs2a94?4|V:i01<>;:828yv5e2909wS=m;<336??73ty8m7>52z\0e>;68902<6s|5e83>7}Y=m16jh460:p1f<72;qU9n52fb8:4>{t=k0;6?uQ5c9>bd<>82wx9l4?:3y]1d=:n102<6s|5883>7}Y=016j;460:p1=<72;qU9552e98:4>{t<=0;68uQ459>53?=1016nl490:?21=<1827:9l486:p5=?=83;owS=6;<`0>33<58<26??4=04a>77<5kk1><52b8815>;e038:70l8:3389g0=:816n84=1:?aa?4634ho6??4=ca964=:jk09=63>3g815>;6;=09=63>30815>;6:m09=63>28815>;6:<09=63>20815>;6=109=63>56815>;6=?09=63>54815>;6==09=63>52815>;6=;09=63>5b815>{t0j0;6iu218f9=7=:9?31>>5217`966=:9:l1>>52126966=:9:;1>>5213f966=:9;31>>52137966=:9;;1>>52132960=:9;91>85214a925=z{=l1<79t=0;`>26:3:1>v3>6b815>;e:3;2?6s|18394?2|5l:1;95211;931=:9881;952b38:b>{tj=0;6?u2b2850>;e:3<87p}>8983>7}:9?i1:=5217f9=5=z{82i6=4={<35g?5034;=i77?;|q2544=?:16=8m5989~w4>b2909w0?9b;;:?8d52h<0q~?7f;296~;6;o02563>6`84<>{t9>;1<7:t=cd9=5=:m10<863j7;57?876;3=?7p}>7983>6}:k?02<63i6;57?8`22>>0q~?89;297~;d?33;70h7:6689c1=?=1v<9n:1808e?20:01ko5759>b<<0<2wx=:l50;1x9f?=1916jn484:?ef?133ty:;n4?:2y>gd<>827mi79;;2253z?`f??734;;<79;;2253z?`g??734;;>79;;<335?133ty:;k4?:2y>ga<>827:<9484:?246<0<2wx=5>50;1x9fc=1916==85759>553=?=1v<9=:1808e720:01ho5759>a<<0<2wx=:=50;1x9f7=1916in484:?ff?133ty:;94?:2y>g7<>827ni79;;2253z?`7??734l;6::4=dd931=z{8==6=4<{<6<5o81;952f0840>{t9>=1<7=t=b79=5=:n=0<863i3;57?xu60<0;6??t=bd9=5=:n=0<963i3;56?8`52>?01k?5749>b5<0=27nj79:;23<5ln1;852eb841>;bj3=>70kn:6789`?=?<16==85749>553=?<16==:5749>555=?<16==<5749>557=?<16==>5749>bc<0=27mi79:;23<5oi1;852fc841>;ai3=>70h6:6789c>=?<16j:485:?e2?1234l>6:;4=d:930=:m>0<96s|19494?4|5m?15=52101930=z{82:6=4>3z?a3??>34h=6;>4=bd936=:l?0901i75729>`d<0;27on79<;25<5mn1;>52dd847>;c83=870j>:6189a4=?:16h>483:?g0?1434n>6:=4=04b>207>512y>f=<>127i;78?;22<5m<1;952d6840>;c03=?70j6:6689ag=?=16ho484:?gg?1334no6::4=eg931=:l90<863k1;57?8b52>>01i=5759>`1<0<27o979;;<35e?123ty:4>4?:01x9g?=1016n5490:?`b?1234n=6:;4=e5930=:l10<963k9;56?8bf2>?01il5749>`f<0=27oh79:;23<5m:1;852d0841>;c:3=>70j<:6789a2=?<16h8485:?22d<0<2wx=5:50;308df20301o75619>gc<0>27o:799;20<5m21;;52d8842>;ci3==70jm:6489ae=??16hi486:?ga?1134n;6:84=e3933=:l;0<:63k3;55?8b32><01i;5779>53g=?:1v<8i:1878de20301<>8:618946?2>901:618yv7083:19v3mc;;:?8de2?:01<>8:668946?2>>01:668yv7??3:18v3>6b8:=>;6>m0<>63j0;50?872l3=97p}>9183>7}:9?h1:=5217c9=5=z{82j6=4<{<35a?1534h964k4=ed937=z{82o6=4={<35=?0734h96l;4}rg2>594=c;972=:j108;63m7;14?8d12:=01o;5369>f`<4?27ih7=8;<``>61<5kh1?:52dg8:4>{tm?0;6ou2b`817>;e138870l7:3189g1=::16n;4=3:?a1?4434hn6?=4=cf966=:jj09?63mb;00?8c720:0q~k;:1826~;el33270ll:7289g`=?:16o;483:?`3?1434i36:=4=b;936=:kh0901nj5729>g`<0;27h<79<;25<5j81;>52c2847>;d<3=870m::618yvc2290:>v3me;;:?8dc2?:01oh5759>g3<0<27h;79;;22<5j31;952c`840>;dj3=?70ml:6689fb=?=16oh484:?`4?1334i:6::4=b0931=:k:0<863l4;57?8e22>>0q~k=:1826~;e=33270lj:7289g`=?<16o;485:?`3?1234i36:;4=b;930=:kh0<963lb;56?8ed2>?01nj5749>g`<0=27h<79:;23<5j81;852c2841>;d<3=>70m::678yvc4290:>v3m6;;:?8d22?:01oh5779>g3<0>27h;799;20<5j31;;52c`842>;dj3==70ml:6489fb=??16oh486:?`4?1134i:6:84=b0933=:k:0<:63l4;55?8e22><0q~??b;2954}:99215=52f2842>;a93==70ki:6489`b=??16io486:?f=?1134;;9799;<337?1134;;=799;20<5on1;;52fc842>;a13==70h8:6489c3=??16i:486:p55g=83;:w0??7;;3?8`32><01k<5779>b5<0>27ni799;20<5lk1;;52114933=:99>1;;52110933=:99:1;;52fd842>;ak3==70hn:6489c>=??16j;486:?f20:01k:5729>b6<0;27m>79<;25<5o:1;>52eg847>;bm3=870kk:6189`e=?:16io483:?fe?1434o26:=4=025>25<58:>6:=4=027>25<58:86:=4=021>25<58::6:=4=023>25<5ol1;>52fd847>;al3=870hl:6189cd=?:16jl483:?e=?1434l36:=4=g5936=:n?0901h95729~w4362909w0?5183>7}:9:o15=52152936=z{8>m6=4={<30`??734;?<79;;|q206<72;q6==j5919>56c=?:1v<:;:181877m33;70?5rs065>5<5s4;:<77?;<30`?133ty:854?:6y>542=1916=>:59`9>567=1h16=?j59`9>57?=1h16=?;59`9>577=1h1v<:>:181876;3==70?>1;;3?xu6<>0;6?u21019=5=:98>1;?5rs061>5<5s4;:>77?;<327?143ty:8h4?:2y>516=1m16=>:5989>563=?:1v<:k:187874l33o70?5rs06a>5<1s4;:<79:;<33b?1234;;i79:;<33`?1234;95776;<31e?143ty:8l4?:7y>546=?=16==h5759>55c=?=16==j5759>573=1016=?85729~w42>290=w0?>0;50?877n3=870??e;50?877l3=870?=1;;:?875:3=87p}>1`83>7}:9;;1:=521319=5=z{8;>6=4<{<310?4234;9;7<:;<314?1a3ty:=o4?:3y>573=>916=?95919~w4712908w0?=8;06?875j38>70?=4;5e?xu69j0;6?u213;925=:9;h15=5rs034>5<4s4;9o7<:;<31b?4234;9479i;|q25a<72;q6=?j5619>57`=191v70?<3;06?875k3=m7p}>1d83>7}:9:;1:=521219=5=z{8;26=4={<302?4234;8<79i;|q25c<72;q6=>:5619>560=191v<=8:180875:33;70?=0;;g?875;3=n7p}>3983>6}:9;<15=521369=a=:9;=1;h5rs01:>5<4s4;9m77?;<3157e=1m16=?h57d9~w45e2908w0?<2;;3?874833o70?<3;5f?xu6;j0;6?u21279=5=:9:<1;h5rs042>5<5s4;>579<;<36f??73ty:9k4?:3y>50e=::16=875919~w43b2902w0?:8;;b?872?33j70?:6;;b?872=33j70?:4;;b?872;33j70?:2;;b?872k33j70?:d;;3?xu6>;0;6?u21409=<=:95rs040>5<4s4;>?776;<366?0734;>n79;;|q221<72:q6=8:5989>505=>916=8l5749~w4022908w0?:5;;:?872<3<;70?:b;55?xu6>?0;6>u21449=<=:934;>:78?;<36e?133ty::=4?:3y>50g=1916=875759~w40?2908w0?:8;;:?872?3<;70?:a;56?x{i;8=1<7?tH0;7?xh4910;6959~j67f290:wE?64:m74d=83;pD<7;;|l05f<728qC=4:4}o12`?6=9rB:595rn23f>5<6sA;286sa30d94?7|@83?7p`<2183>4}O90>0qc==1;295~N61=1vb><=:182M7><2we??=50;3xL4?33td8>94?:0yK5<251zJ2=1=zf:8=6=4>{I3:0>{i;;=1<7?tH0;7?xh4:10;6959~j64f290:wE?64:m77d=83;pD<7;;|l06f<728qC=4:4}o11`?6=9rB:595rn20f>5<6sA;286sa33d94?7|@83?7p`<3183>4}O90>0qc=<1;295~N61=1vb>==:182M7><2we?>=50;3xL4?33td8?94?:0yK5<251zJ2=1=zf:9=6=4>{I3:0>{i;:=1<7?tH0;7?xh4;10;6vF7f:J;a>N61=1Qmo4>{6f9yxh4;h0;6959~j65d290:wE6i;I:f?M7><2Pjn7?t1849y_0a28qjn7srn21g>5<6sA2m7E6j;I3:0>\f03;p<7srn21f>5<5sA;286sa32d94?7|@83?7p`<4183>4}O90>0qc=;1;295~N61=1vb>:=:182M7><2we?9=50;3xL4?33td8894?:0yK5<251zJ2=1=zf:>=6=4>{I3:0>{i;==1<7?tH0;7?xh4<10;6959~j62f290:wE?64:m71d=83;pD<7;;|l00f<728qC=4:4}o17`?6=9rB:595rn26f>5<6sA;286sa35d94?7|@83?7p`<5183>4}O90>0qc=:1;295~N61=1vb>;=:182M7><2we?8=50;3xL4?33td8994?:0yK5<297>51zJ2=1=zf:?=6=4>{I3:0>{i;<=1<7?tH0;7?xh4=10;6959~j63f290:wE?64:m70d=83;pD<7;;|l01f<728qC=4:4}o16`?6=9rB:595rn27f>5<6sA;286sa34d94?7|@83?7p`<6183>4}O90>0qc=91;295~N61=1vb>8=:182M7><2we?;=50;3xL4?33td8:94?:0yK5<251zJ2=1=zf:<=6=4>{I3:0>{i;?=1<7?tH0;7?xh4>10;6959~j60f290:wE?64:m73d=83;pD<7;;|l02f<728qC=4:4}o15`?6=9rB:595rn24f>5<6sA;286sa37d94?7|@83?7p`<7183>4}O90>0qc=81;295~N61=1vb>9=:182M7><2we?:=50;3xL4?33td8;94?:0yK5<251zJ2=1=zf:==6=4>{I3:0>{i;>=1<7?tH0;7?xh4?10;6959~j61f290:wE?64:m72d=83;pD<7;;|l03f<728qC=4:4}o14`?6=9rB:595rn25f>5<6sA;286sa36d94?7|@83?7p`<8183>4}O90>0qc=71;295~N61=1vb>6=:182M7><2we?5=50;3xL4?33td8494?:0yK5<251zJ2=1=zf:2=6=4>{I3:0>{i;1=1<7?tH0;7?xh4010;6959~j6>f290:wE?64:m7=d=83;pD<7;;|l05<6sA;286sa39d94?7|@83?7p`<9183>4}O90>0qc=61;295~N61=1vb>7=:182M7><2we?4=50;3xL4?33td8594?:0yK5<251zJ2=1=zutwKLNu;148g7`27>?wKLOu?}ABSxFG \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$01344<,[o}e~g`n;"2*732(-80!<;40123416<89:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012345679h1:?7GAPTV9EABUI^XJHI\31383:4g<9:0BB][[:@FGVGTCIMNY0<<50?37?40=AGZ^X7JFAEK?50<768>0=;4FNQWW>AOEL@6:97>114922?IR\Y__6IANDN>21?699<1::7AZTQWW>AIELF6:97>11192>LHW]]0|il2?:1<20>4=AGZ^X7JFP@FJT97=87;?7?4FNQWW>AOWJMC[0<4?>0186?OIX\^1[HOXEM>2>586;281EC^ZT;UFFRCR480;2<;42;MVPUSS2ME[MIA_<083:43<:3E^X][[:EMSFAIW480;2i59smz:gva4:='9=<57:HLSQQ1129;>JSSX\^1hb{{a=594;75300BB][[:`fgvd:?294n7LJKR@UQEABU494m7LJKR@UQEABU48:5j6OKDSCTVDBCZ5;:2g9B@ATF_[KOH_2>2?g8EABUI^XJHI\31?g8EABUI^XJHI\32?g8EABUI^XJHI\33?g8EABUI^XJHI\34?g8EABUI^XJHI\35?g8EABUI^XJHI\36?g8EABUI^XJHI\37?g8EABUI^XJHI\38?g8EABUI^XJHI\39?g8EABUJ[NJHI\30?d8EABUJ[NJHI\31126?69n2KOH_L]D@FGV9756l1JHI\MRECG@W:66l1JHI\MRECG@W:56l1JHI\MRECG@W:46l1JHI\MRECG@W:36l1JHI\MRECG@W:26l1JHI\MRECG@W:16l1JHI\MRECG@W:06l1JHI\MRECG@W:?6l1JHI\MRECG@W:>6:1J@A64BTQ\MK@H:2IN=?5LHDAH[IODMGYNSYW_E59@HN613JF@=5>9;BNH62623JF@>U64CMI1\4>7=2IGG4>:;BNHE4181;8GJKJA]^NH<:4CNPF[BCIM[K_EB@PIODL3>EUMH^NHn5KAUC\SLBS@VKh7IO[A^UJ@QNXJ11OELJF<1<:?AOFL@6:<374DHCGM976601OELJF<00==>BNIMC7=>06;EKB@L:6<7h0HDOKI=36>58>3MCJHD2>5?:8@LGCA5;546JFAEK?6;>BNIMC7:364DHCGM91902NBMIG38?:8@LGCA53546JFBEK?4;?89GMGBN48;556JFBEK?578>3MCIHD2>3?;8@LDCA5;?2o5KICFJ843=8730HDLKI=36:==CAKNB0<07;EKA@L:5611OEOJF<2<;?AOEL@6?255KICFJ808?3MCIHD29>99GMGBN4>437IGMDH>;:==CAKNB040n;EKSEAOW494h7IG_AEKS84<76h1OE]OKIQ>2:d=CAYHOE]2?>b9GMUDCAY6:6=0n;EKSFAOW48437IANDN>3:<=CGHND0<>19:FLEAI;98427IANDN>26;?89GKDBH48>5n6J@AEM?50<7601OCLJ@<07=<>BHIME7=364DNCGK94902NDMIA33?:8@JGCG5>546J@AEM?1;>BHIME75394DNC\V@A?3MEIHB2?>89GKGBH48:556J@BEM?548>3MEIHB2>2?;8@JDCG5;8245KOCFL8429j2NDNIA31483:<=CGKND0<;18:FLFAI;9720HBLKO=0=<>BHJME7?364DN@GK92902NDNIA35?:8@JDCG5<546J@BEM?3;>3:f=CGYHOC]2>:17KOCSD38C6=@FM20ECG[P^23<>OIA]ZT<<64IOKWTZ6502CEEY^P0258MKOSW9:<7D@FT^223>OIA]U;>:5FNHV\461=0ECG[_1:4?LHN\V:2;6GAIU]3E2=NF@^TK7:KMMQY7M>1BBDZP0G58MKOSW8:<7D@FT^323>OIA]U:>:5FNHV\561669JJLRX9>=0ECG[_0:4?LHN\V;2;6GAIU]2E2=NF@^T=O94IOKW[4E03@DBXR?K7:KMMQY6M>1BBDZP1G48MKOSWH<0ECG[_C;8MKOSWOCGI;5CO@FF@3=KGJANH:5COFK@EIeKnffx]i}foo08J415\IL]@KIJN[@EESNFJCJ48WJSUKL=0__XNL^C4?VTQIEUI:6][AUWP0>U^FJ90XI^;;U[SA22<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&xjaaa`pZ2^*wgj&{%x:R``iokw*wgj'ZZ%_DC_LD]SVLK>&{kfo6[\ES]UMVOEDL30ZDKX_U[SA<=PMH]N@1>1b:UFERCK480;245XE@UFH97912]NNZKZ<119:UFFRCR484i7Z\FTD]EMWUSk2]YEYKPMNFF[De<_[C_IRC@DD]A5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^T\ECI;6V\T^EM@g=_WJEYIRGAFN48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n29[wq53:==flmxj0<07;`fgvd:5611jhi|n<2<;?dbczh6?255ndepb808?3hno~l29>99b`atf4>4j7ljkr`>;>58?3hno~l27>0:8fimXelgTkh`PgdlfvleXkz~y=;5mlj]nahY`mgU{~dcPwhfwl4ddkcVgnaRaztqww[gjhkb>0oaen7:fjjd:76>1oeco31?58`lhf4;4<7igaa=1=3>bnfh6?2:5kioc?1;199gkprf4:437iazt`>7:==cg|~j0807;emvpd:16h1ocxzn<683:==cg|~j0:0<;dlb<>h`kkb`i74r`o\<}36:=n=7ob_9z657*edbUfi`Qheo]u2Z4+sjUjhi|n_vkgpm;>$jUjhi|m_vkgpm;>$jUj`ja}iujn94*dWhrbSdjPwhfwl82+kVkseR}cawg\p|vb59&hSlvf_u{sa87+kVhrxhQ|i{g>=)eXkfgfccQllj?3(fYcmok~`yQkauc>4)eXl`yjnakPw`pm[gnqWjeg`0>#c^fjwddkmV}j~cQmhw]qekab59&hShbnbnpbpliiWmcy1"f`md-qmfgulf%cmnefnf-o|<+jajxd#b~jnlqs066(nymj#ugcioz\h}?Xjfkyh"aeoopt157'{~g#{k}immd+fiumnoe#yc/^ad+)eXnhgb`t3|p`pwek0+kVbjRowi^kg95*dWakxSh`n=0.`[mgtWldi1="l_icp[lhmmj~n~3?,b]kevYjmdUdyy~zt^pfcvYf59&hSeo|_lgn[jssx|~T~hi|_c?3(fYoizUfyuQ`uurvpZtbozUj1="l_icp[hsWf|xzPrdep[g;7$jUcm~Q}efafe86+kVbjR|jgbga95*dWakxS}{a<2/gZnf{Vxxxo3?,b]kevYtgo~nonQfnqww[wc`{Vk6144+kVxnmiQkeqvk[g;29;&hSknd^uj`qnXi42'oR|jae]tmaroWk73 nQ}su]svliua}sTm0MJ,b]qwqYwz`eyeywPb#c^wpaZcdk4:'oR{|e^qlbqcdk4:'oRyja^uj`qn:9%iT{hlPwhfwl87+kV}yeykPddrwlZg:=88'oRy}iug\``vs`Vh69<<#c^uqmqcXefnnSl3XRHVF[COU[]&hSz|ftd]nkacXj4]YEYKPFHPPP)eX{ciRyfduj\e8>+kV}yeykPwhfwlZd:0%iTtikyibgeehokq4y{mznn72`>tfeV2s9<<#bmi\i`kXoldTz;Q=,z;?rcf490;2;5xe`>3:xFGxm80LMv>2c8E>1<6sZ>j6<>>:e79564cl1:1?>k64zleb?7{T<10:<<4k5;306ab?8398i4o4Sbf957g=83;8>ij70;10a<`<[=21=?o50;306ab?8398il>4d00a>5<628qX8l4>008g1?74:mn3<7=dzQ7e?7793n>6<==de:3>65b111/ik4lf:Tea?4|}m:1=6{k1;28y!b128;0n<4;31>45=u-lh644c3->26<4=#m:0:=n9921<7*k8;33f>hc?3907d??7;29 a>=99h0bi954:9j550=83.o47??b:lg3?3<3`;;97>5$e:955d4;h32`?6=,m21==n98i1<7*k8;32a>hc?3807d?>b;29 a>=98o0bi953:9j54g=83.o47?>e:lg3?2<3`;:57>5$e:954c4;n312?6=,m21=?94ne595>=h9;?1<7*k8;313>hc?3807b?=4;29 a>=9;=0bi953:9l575=83.o47?=7:lg3?2<3f;9>7>5$e:95715}#mj0j96Fia:Jfa>if<3:17pljd;292`<729q/in4ka:Jee>Nbm2P8>7mt4;79b?772j0i6i4j:984>3<>2td?n7?=;o6`>44"fk390(lj53:&ba?5<,hl1?6*m0;18 g7=;2.i>7=4$c197>"e<390(o;53:&a2?5<,k=1?6*m8;18 g?=;2.im7=4$c`97>"ek390(oj53:&aa?5<,kl1?6*l0;18 f7=;2.h>7=4$b197>"d<390(n;53:&`2?5<,j=1?6*l8;18 f?=;2.hm7<4$b`96>"dk3n?7)jm:d`8 `6=mh1/i<4<3:&f6?543-o>6>?4$d596>"b0380(k95f79'b=2coj7>5;hc3>5<>o4n3:17d:>:188mab=831bhh4?::ke6?6=,m21j<5ad683?>oa83:1(i65f09m`2<632e5$e:93g=il>0;76a8a;29 a>=?k1eh:4>;:m4=?6=,m21;o5ad681?>i003:1(i657c9m`2<432e<;7>5$e:93g=il>0?76a86;29 a>=?k1eh:4:;:m;1?6=,m21;o5ad685?>i?<3:1(i657c9m`2<032e3?7>5$e:93g=il>0376a72;29 a>=?k1eh:46;:m;5?6=,m21;o5ad68b?>i?83:1(i657c9m`25$e:93g=il>0h76a8e;29 a>=?k1eh:4k;:m4`?6=,m21;o5ad68f?>i0=3:1(i657c9m`25$e:9=d=il>0;76a69;29 a>=1h1eh:4>;:m:a?6=,m215i5ad683?>i>k3:1(i659e9m`2<632cm97>5$e:9b1=il>0;76gi3;29 a>=n=1eh:4>;:k2=?6=,m21=55ad683?>o6?3:1(i65199m`2<632c::7>5$e:95==il>0976g=2;29 a>=911eh:4<;:k15?6=,m21=55ad687?>o583:1(i65199m`2<232c:j7>5$e:95==il>0=76g>e;29 a>=911eh:48;:k2`?6=,m21=55ad68;?>o6k3:1(i65199m`2<>32c:n7>5$e:95==il>0j76g>a;29 a>=911eh:4m;:k21?6=,m21=55ad68`?>o0<3:1(i65729m`2<732c<>7>5$e:936=il>0:76g95;29 a>=>=1eh:4?;:k57?6=,m21:95ad682?>o1:3:1(i65659m`2<532c==7>5$e:921=il>0876g90;29 a>=>=1eh:4;;:k6b?6=,m21:95ad686?>o1m3:1(i65659m`2<132c=h7>5$e:921=il>0<76g9c;29 a>=>=1eh:47;:k5f?6=,m21:95ad68:?>o1i3:1(i65659m`25$e:921=il>0i76g98;29 a>=>=1eh:4l;:k53?6=,m21:95ad68g?>o1>3:1(i65659m`2i7>5$e:921=il>0m76g:4;29 a>==:1eh:4?;:k66?6=,m219>5ad682?>o293:1(i65529m`2<532c><7>5$e:916=il>0876g;f;29 a>==:1eh:4;;:k7a?6=,m219>5ad686?>o2l3:1(i65529m`2<132c>o7>5$e:916=il>0<76g:b;29 a>==:1eh:47;:k6e?6=,m219>5ad68:?>o213:1(i65529m`247>5$e:916=il>0i76g:7;29 a>==:1eh:4l;:k62?6=,m219>5ad68g?>o2=3:1(i65529m`25$e:916=il>0m76g=7;29 a>=:?1eh:4?;:k11?6=,m21>;5ad682?>o5<3:1(i65279m`2<532c8<7>5$e:963=il>0876g=f;29 a>=:?1eh:4;;:k1a?6=,m21>;5ad686?>o5l3:1(i65279m`2<132c9o7>5$e:963=il>0<76g=b;29 a>=:?1eh:47;:k1e?6=,m21>;5ad68:?>o513:1(i65279m`25$e:963=il>0i76g=3;29 a>=:?1eh:4l;:m;a?6=,m214i5ad683?>i?k3:1(i658e9m`2<632e3n7>5$e:90976a7a;29 a>=0m1eh:4<;:m;=?6=,m214i5ad687?>i?03:1(i658e9m`2<232e2;7>5$e:90=76a66;29 a>=0m1eh:48;:m:1?6=,m214i5ad68;?>i><3:1(i658e9m`2<>32e2?7>5$e:90j76a62;29 a>=0m1eh:4m;:m:5?6=,m214i5ad68`?>i>83:1(i658e9m`25$e:90n76a77;29 a>=0m1eh:4i;:k45?6=,m21;=5ad683?>o1n3:1(i65719m`2<632wxh?4?:24x9cd=i=16ii4>c:?f`?7e34oo601hj5319>aa<5n27nh77b<5ln1>n52ee81f>;bl38j70kk:3;89`b=:116ii4=3:?f`?3334oo68<4=df914=:mm0><63jd;7a?8cc2aa<2027nh78:;35<5ln1:?52ee855>;bl3<;70kk:4d89`b=>l16ii49d:?f`?0d34oo6;l4=df92d=:mm0=563jd;4;?8cc2?=01hj5679>aa<2m27nh79>;3`<5ln1;952ee846>;bl3l>70kk:g189`b=<816ii4n0:?f`?bd34oo6ij4=df9``=:mm0oj6s|13294?4|V88;70kk:678yv7593:1>vP>209>aa<0l2wx=?<50;0xZ44534oo6:k4}r317?6=:rT:>>52ee84b>{t9;>1<70q~?=5;296~X6:<16ii475:p570=838pR<<9;2052z\26==:mm0<;6s|13;94?4|V88270kk:8d8yv76>3:1>vP>179>aa<4n2wx=<950;0xZ47034oo69j4}r32{t9831<7a;296~X69h16ii4:7:p54d=838pR0e52z\25f=:mm0>h6s|10f94?4|V8;o70kk:5g8yv76n3:1>vP>1g9>aa<3n2wx===50;0xZ46434oo6{t99?1<78;7752z\24==:mm09>6s|11;94?4|V8:270kk:048yv77i3:1>vP>0`9>aa<6?2wx==m50;0xZ46d34oo6<74}r31b?6=;rT:>k52ee8e6>;bl3l;7psa9983>4}Oml1vb4750;3xL`c{Igf?xh>j3:1=vFje:m=f<728qCih5rn8f94?7|@lo0qc7j:182Mcb3td2j7>51zJfa>{ii90;65<6sAon7p`n3;295~Nbm2wem94?:0yKa`=zfh?1<7?tHdg8ykg1290:wEkj;|lb3?6=9rBni6saa983>4}Oml1vbl750;3xL`c{Igf?xhfj3:1=vFje:mef<728qCih5rn`f94?7|@lo0qcoj:182Mcb3tdjj7>51zJfa>{ij90;65<6sAon7p`m3;295~Nbm2wen94?:0yKa`=zutwKLNuk2;:1`257n1wKLOu?}ABSxFG \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise (nonexistent) @@ -1,398 +0,0 @@ - - - -

- - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo (nonexistent) @@ -1,68 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2011 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 * -* * -* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * -* Block Memory and Single Port Block Memory LogiCOREs, but is not a * -* direct drop-in replacement. It should be used in all new Xilinx * -* designs. The core supports RAM and ROM functions over a wide range of * -* widths and depths. Use this core to generate block memories with * -* symmetric or asymmetric read and write port widths, as well as cores * -* which can perform simultaneous write operations to separate * -* locations, and simultaneous read operations from the same location. * -* For more information on differences in interface and feature support * -* between this core and the Dual Port Block Memory and Single Port * -* Block Memory LogiCOREs, please consult the data sheet. * -*******************************************************************************/ - -// Interfaces: -// AXI_SLAVE_S_AXI -// AXILite_SLAVE_S_AXI - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -rom_8x2k your_instance_name ( - .clka(clka), // input clka - .ena(ena), // input ena - .wea(wea), // input [0 : 0] wea - .addra(addra), // input [10 : 0] addra - .dina(dina), // input [15 : 0] dina - .douta(douta) // output [15 : 0] douta -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file rom_8x2k.v when simulating -// the core, rom_8x2k. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco (nonexistent) @@ -1,105 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 13.2 -# Date: Wed Jul 20 21:27:41 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 -# END Select -# BEGIN Parameters -CSET additional_inputs_for_power_estimation=false -CSET algorithm=Minimum_Area -CSET assume_synchronous_clk=false -CSET axi_id_width=4 -CSET axi_slave_type=Memory_Slave -CSET axi_type=AXI4_Full -CSET byte_size=9 -CSET coe_file=no_coe_file_loaded -CSET collision_warnings=ALL -CSET component_name=rom_8x2k -CSET disable_collision_warnings=false -CSET disable_out_of_range_warnings=false -CSET ecc=false -CSET ecctype=No_ECC -CSET enable_a=Use_ENA_Pin -CSET enable_b=Always_Enabled -CSET error_injection_type=Single_Bit_Error_Injection -CSET fill_remaining_memory_locations=false -CSET interface_type=Native -CSET load_init_file=false -CSET memory_type=Single_Port_RAM -CSET operating_mode_a=WRITE_FIRST -CSET operating_mode_b=WRITE_FIRST -CSET output_reset_value_a=0 -CSET output_reset_value_b=0 -CSET pipeline_stages=0 -CSET port_a_clock=100 -CSET port_a_enable_rate=100 -CSET port_a_write_rate=50 -CSET port_b_clock=0 -CSET port_b_enable_rate=0 -CSET port_b_write_rate=0 -CSET primitive=8kx2 -CSET read_width_a=16 -CSET read_width_b=16 -CSET register_porta_input_of_softecc=false -CSET register_porta_output_of_memory_core=false -CSET register_porta_output_of_memory_primitives=false -CSET register_portb_output_of_memory_core=false -CSET register_portb_output_of_memory_primitives=false -CSET register_portb_output_of_softecc=false -CSET remaining_memory_locations=0 -CSET reset_memory_latch_a=false -CSET reset_memory_latch_b=false -CSET reset_priority_a=CE -CSET reset_priority_b=CE -CSET reset_type=SYNC -CSET softecc=false -CSET use_axi_id=false -CSET use_byte_write_enable=false -CSET use_error_injection_pins=false -CSET use_regcea_pin=false -CSET use_regceb_pin=false -CSET use_rsta_pin=false -CSET use_rstb_pin=false -CSET write_depth_a=2048 -CSET write_width_a=16 -CSET write_width_b=16 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2011-03-11T08:24:14.000Z -# END Extra information -GENERATE -# CRC: 4f6097fd

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log (nonexistent) @@ -1,10 +0,0 @@ -Welcome to Xilinx CORE Generator. -Help system initialized. -CoreGen has not been configured with any user repositories. -CoreGen has been configured with the following Xilinx repositories: - - '/opt/xilinx/13.2/ISE_DS/ISE/coregen/' [using existing xil_index.xml] -The IP Catalog has been reloaded. -Opening project file -/home/ricardo/hacking/lx9-micro/openmsp430/fpga/xilinx_avnet_lx9microbard/ise/rt -l/verilog/coregen/coregen.cgp. -Closed project file.

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy (nonexistent) @@ -1,29 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 rom_8x2k -RECTANGLE Normal 32 32 544 1376 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName addra[10:0] -PINATTR Polarity IN -LINE Wide 0 112 32 112 -PIN 0 112 LEFT 36 -PINATTR PinName dina[15:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName ena -PINATTR Polarity IN -LINE Wide 0 208 32 208 -PIN 0 208 LEFT 36 -PINATTR PinName wea[0:0] -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName clka -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName douta[15:0] -PINATTR Polarity OUT -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt (nonexistent) @@ -1,11 +0,0 @@ -# Output products list for -chipscope_icon.asy -chipscope_icon.gise -chipscope_icon.ngc -chipscope_icon.v -chipscope_icon.veo -chipscope_icon.xco -chipscope_icon.xise -chipscope_icon_flist.txt -chipscope_icon_readme.txt -chipscope_icon_xmdf.tcl

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt (nonexistent) @@ -1,25 +0,0 @@ -# Output products list for -_dbg/xil_257.in -_dbg/xil_257.out -blk_mem_gen_ds512.pdf -blk_mem_gen_v6_2_readme.txt -ram_8x512.asy -ram_8x512.gise -ram_8x512.ngc -ram_8x512.v -ram_8x512.veo -ram_8x512.xco -ram_8x512.xise -ram_8x512_flist.txt -ram_8x512_ste/example_design/bmg_wrapper.vhd -ram_8x512_ste/example_design/ram_8x512_top.ucf -ram_8x512_ste/example_design/ram_8x512_top.vhd -ram_8x512_ste/example_design/ram_8x512_top.xdc -ram_8x512_ste/implement/implement.sh -ram_8x512_ste/implement/planAhead_rdn.bat -ram_8x512_ste/implement/planAhead_rdn.sh -ram_8x512_ste/implement/planAhead_rdn.tcl -ram_8x512_ste/implement/xst.prj -ram_8x512_ste/implement/xst.scr -ram_8x512_xmdf.tcl -summary.log

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$8a344<,[o}e~g`n;"2*732(-80!?0893456789:;8=5?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>>0:23456789:;<=>?0033?56789:;==??013351=789>?7=>?1022446788;;7=<7A54@A45>J<=OJ<>4026444228;>=<=:;4:20B52<8=:;86>I2338542<990BB][[:FCM@ZO;13:586?>0G37?42=AGZ^X7OKDSC?56<768>0=94FNQWW>DBCZK6:?7>1169217?50?31?64=AGZ^X7JFB=12>586;2996B[[PTV9@JG;;80;2<=4338LQQVR\3NDN1=>:1<22>512@DDYY4LOOVQKI:4=3:5=6:;;533447<<3CE\XZ5DHRB86<768;087GAPTV9@LVE4:0;2<>44;KMTPR=_LK7?7>11197>LHW]]0\IO2<:1<26>2=G\^[YY4KOQC?7?699;1?6B[[PTV9@JVE4:0;2<>45476103298;:=115950?OIX\^1X_GH0=40>58c3?ygt4m|g207)72;908<5478=1J0=0;;@>2:1=F4;4?7L2<>79B81<76=1J0907;@C;4=6?88:0MLO=A@:3<5G5092;==5NA@C3E54FIHK;M=>7;@FGVD:7601JHI\N<02==>GCL[K7=<06;@FGVD:6:7h0MIJ]A=30>58>3HNO^L2>3?:8EABUI5;546OKDSC?6;>GCL[K7:364AEFQE91902KOH_O38?:8EABUI53546OKDS@?4;?89B@ATE48;556OKDS@?578e3HNO^O2>3;2==>GCL[H7=>07;@FGVG:6611JHI\M<3<;?DBCZK68255NDEPA818?3HNO^O2:>99B@ATE4?437LJKRC>4:==FLMXI0507;@FGVG:>681I46LZS^KMBJ77NBDB078GIMD9<1H@FJ>5:AOOAPd3JF@H[QKIWKGA0=DDBLS46MCKGZ2<535LLS;8GJKJA]^NHl5LOOVQKI:76k1HCCZ]OM>24;dEHF]XD@1?8>c9@KKRUGE6:43l4CNLWVJJ;904j7NAATSMO848e3JEEX_AC<32=f>EHF]XD@1<>>c9@KKRUGE69>3l4CNLWVJJ;::4i7NAATSMO8729j2IDBY\@L=06:g=DGG^YCA2=6?`8GJHSZFF7>:0m;BMMPWIK4;25n6M@NUPLH94>6h1HCCZ]OM>1:g=DGG^YCA2<0?`8GJHSZFF7?<0m;BMMPWIK4:85n6M@NUPLH9546k1HCCZ]OM>00;b=<9;E0\GIMd3MK_MRYFDUJ\Ef=CI]KT[DJ[H^@1?AO13MCJ0=08;EKB8469?2NBM1?>>69GMD:6:7=0HDO312<4?AOF48>5;6JFA=36:2=CAH6::394DHC?52803MCJ0<617:FJE97>6?1OEL2>>69GMD:587=0HDO320<4?AOF4;85;6JFA=00:2=CAH698394DHC?60803MCJ0?817:FJE9406>1OEL2=8?58@LG;:04=7IGN<3<4?AOF4::556JFA=12>5803MCJ0>?16:FJE959>2NBM1:16:FJE939>2NBM1816:FJE919>2NBM1616:FJE9?9>2NBN1>17:FJF9776>1OEO2>1?58@LD;9;4<7IGM<01=3>BNJ5;?2:5KIC>21;169GMG:617<0HDL31?58@LD;:94<7IGM<33=3>BNJ5892:5KIC>17;1908;EKA8739?2NBN1<9>69GMG:5?7=0HDL329<4?AOE4;35:6JFB=0=3>BNJ59;245KIC>05?69?2NBN1=>>79GMG:46?1OEO2;>79GMG:26?1OEO29>79GMG:06?1OEO27>79GMG:>6>1OE]O30?58@LVF484<7IG_A=0==>BNXH686=08;EKSE959?2NB\O2?>69GMUD;97=0HD^M<3<:?AOWJ591<394DHRA86813MEJ0=08;EMB8469?2NDM1?>>69GKD:6:7=0HBO312<4?AIF48>5;6J@A=36:2=CGH6::394DNC?52803MEJ0<617:FLE97>6?1OCL2>>69GKD:587=0HBO320<4?AIF4;85;6J@A=00:2=CGH698394DNC?60803MEJ0?817:FLE9406>1OCL2=8?58@JG;:04=7IAN<3<4?AIF4::556J@A=12>5803MEJ0>?16:FLE959>2NDM1:16:FLE939>2NDM1816:FLE919>2NDM1616:FLE9?9?2NDMR\JG79GKG:76>1OCO2>0?58@JD;984<7IAM<00=3>BHJ5;82:5KOC>20;169GKG:607=0HBL318<5?AIE484<7IAM<32=3>BHJ58:2:5KOC>16;1>08;EMA8729?2NDN1<:>69GKG:5>7=0HBL326<4?AIE4;25;6J@B=0::3=CGK692:5KOC>04;?69GKG:497<0HBL33?48@JD;<7<0HBL35?48@JD;>7<0HBL37?48@JD;07<0HBL39?58@JDXZLM<7IA_A=2=3>BHXH6:2:5KOQC?6;?4?>69GKUG;;7=0HB^M<1<4?AIWJ5;5;6J@PC>1:<=CGYH7?7>17:FLTG:46<1OSNBD1:G1?@253LL87H@N3:GMFg=BFVXXX_OB_@`8AKYU[]XJARL;;G23746IF12@GFEFIHK?7K8>049EEIUB:2LO==5ID67A=67BK?>J4?><;GF@0>@CKL90JIK<;GFS7>@CZ=1MH_K<;GFP0>@AN9>0JKHJ119EBC@A9O;MJKHI1G224>@ANOLMJK6N89:;<=773OLMJKHIFG1EBC3AN8:0JKHIFGDEBC@AIH2;==5IFGDEBC@ANOLMJKK>8:DQKH&%L;UH@F,/TN"EBV&SAN;37K\@M!DEW%RH(+N9SNBD"!VJC==AZFGTBNH>;F;8CDHCWJCTE45HAOF\M969j2MJBIQF<023:g=@IGNTE1??1?`8CDHCW@6:0724;d112518e3NKEHRG3107=f>AFFMUB0c9DEKBXA5;:;3l4G@LG[L:6914i7JOAD^K?54?9i2MJBIQF<03=f>AFFMUB0<c9DEKBXA5;9=3l4G@LG[L:6:;4i7JOAD^K?5759j2MJBIQF<007:g=@IGNTE1?=5?`8CDHCW@6:>;0m;FCM@ZO;9;=5n6INNE]J844?6k1LMCJPI=31=;g2?`8CDHCW@6:?=0m;FCM@ZO;9:;5n6INNE]J84556k1LMCJPI=307;d35;1b:EBJAYN489=2o5HAOF\M974?7h0KL@K_H>27=8e3NKEHRG312;=e>AFFMUB0<=1b:EBJAYN48>;2o5HAOF\M97397h0KL@K_H>2078e3NKEHRG3151=f>AFFMUB0<:;>c9DEKBXA5;?93l4G@LG[L:62148f3NKEHRG3144j7JOAD^K?5=8f3NKEHRG318<:?BGILVC7=3o4G@LG[L:587k0KL@K_H>15;g11;g1=;?`9DEKBXA59;2l5HAOF\M9566h1LMCJPI=11:d=@IGNTE1=<>`9DEKBXA59?2l5HAOF\M9526h1LMCJPI=15:d=@IGNTE1=8>`9DEKBXA5932l5HAOF\M95>601LMCJPI=1=e>AFFMUB09>1a:EBJAYN4=;5m6INNE]J8149i2MJBIQF<51=e>AFFMUB09:1a:EBJAYN4=?5m6INNE]J8109i2MJBIQF<55=e>AFFMUB0961a:EBJAYN4=3556INNE]J818f3NKEHRG35154;g3o4G@LG[L:1;7k0KL@K_H>50;g5<;g`9DEKBXA5=82l5HAOF\M9136h1LMCJPI=56:d=@IGNTE199>`9DEKBXA5=<2l5HAOF\M91?6h1LMCJPI=5::<=@IGNTE191a:EBJAYN41:5m6INNE]J8=79i2MJBIQF<90=e>AFFMUB05=1a:EBJAYN41>5m6INNE]J8=39i2MJBIQF<94=e>AFFMUB0591a:EBJAYN4125m6INNE]J8=?912MJBIQF<9=;H31?L453@997D:=;H7;?LHN\YU;<55FNHVS[57?3@DBX]Q?299JJLRWW9937D@FTQ]30==NF@^[S=;7;HLJPUY7>11BBDZ__15:?LHN\Z^JXH94IOKW[5603@DBXR>>7:KMMQY7:>1BBDZP0258MKOSW9><7D@FT^263>OIA]U;::5FNHV\421?2CEEYQ?A69JJLRX8K=0ECG[_1A4?LHN\V:O;6GAIU]3A2=NF@^T7:KMMQY6:>1BBDZP1258MKOSW8><7D@FT^363>OIA]U:::5FNHV\521?2CEEYQ>A69JJLRX9K=0ECG[_0A4?LHN\V;O;6GAIU]2A2=NF@^T=K94IOKW[7603@DBXR<>7:KMMQY5:>1BBDZP2258MKOSW;><7D@FT^063>OIA]U9::5FNHV\621?2CEEYQ=A69JJLRX:K=0ECG[_3A4?LHN\V8O;6GAIU]1A2=NF@^T>K94IOKW[6603@DBXR=>7:KMMQY4:>1BBDZP3258MKOSW:><7D@FT^163>OIA]U8::5FNHV\72168;HLJPZ5>?2CEEYQQ#[PG@LG[VTKWZFBOHJCK;1GE?5CO79OKDBBL?1GCNEJD69OKBODIE>0@XZ>4:NVP72KRPJST@85BUYD41>KRPO2h7@oeosTfvvohfj1Feca}Vdppmjh53G:97C?<;O1;7>H41:1E8<=4N504?KCS_FX@:6@@CMKS3>HHELXLI95AOOG2?J>5_RD48TVBHFL;0]>5^1418U6763[k0^LCM17@TAW0UUDJ;=I:5\RMA06@g<[[FTMRG30?`8WWJXIVC7==0m;RPO[DYN48;5n6]]L^C\M9756k1X^AQN_H>27;d<[[FTMRG3152<;g<[[FTMRG31?c8WWJXIVC7>3o4SSN\EZO;;7k0__BPA^K?0;g<[[FTMRG35?c8WWJXIVC7:3o4SSN\EZO;?7k0__BPA^K?<;g<[[FTMRG39?:8WWJXKLUB56]]L^AOOZO03ZXGSIQF7:QQHZWXG>1X^[OC_@58WWPFDVH=7^ZNTTQ7?V_IK11_I_CFN@N;?QOJMZZNO>5[NL58PKKXFL^37Y\FG1>3:<=SZ@M;0<>19:VQMB6;98427Y\FG1>26;?<\[CL<1?<>89WVLA748>556Z]IF2?508>3]XBK=2>6?;8PWO@85;<245[RHE384>912^YEJ>318<;?QTNO96:245[RHE3876912^YEJ>320<:?QTNO969>374TSKD4944601_^DI?<36==>RUAN:7>806;UPJC5:5>730X_GH0=04:<=SZ@M;0?619:VQMB6;:0437Y\FG1>1:<=SZ@M;0>>19:VQMB6;;8427Y\FG1>06;?<\[CL<1=<>89WVLA74:>556Z]IF2?708>3]XBK=2<6?;8PWO@859<245[RHE386>912^YEJ>338<;?QTNO968245[RHE3816912^YEJ>340<:?QTNO96?>374TSKD4924601_^DI?<56==>RUAN:78806;UPJC5:3>730X_GH0=64:<=SZ@M;09619:VQMB6;<0437Y\FG1>7:<=SZ@M;08>19:VQMB6;=8427Y\FG1>66;?<\[CL<1;<>89WVLA74<>556Z]IF2?108>3]XBK=2:6?;8PWO@85?<245[RHE380>912^YEJ>358<;?QTNO96>245[RHE3836912^YEJ>360<:?QTNO96=>3l4TSKD490429427Y\FG1>57;><\[CL<1818:VQMB6;?720X_GH0=:=<>RUAN:753:4TSWFf>RTWM8TXBQ[2c9WWZL5W]ETH?l4TR]I7ZRHWM8i7Y]PJ5]WKZB5<2^R\H=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP

WNOEW=S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV??]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T10_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T13_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ31Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ30Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX56[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX51[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^73U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^72U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9 I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T1\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[0_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T21_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ03Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ02Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX64[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX67[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^45U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^44U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\::W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:=W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8>Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>8S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>;S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<9]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<8]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T26_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T29_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0;Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0:Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX6<[)AVYY@YQAE^2-BC5b3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX6X(NWZXGXR@J_1,GH\?4k2_;#DQAO^F-QZOKI&CTH\ Z_ESR+AJ^W0$O@TQ6_FGM_7[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX75[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^57U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^56U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;8W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;;W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR99Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR98Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?>S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?9S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=;]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=:]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T34_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T37_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ15Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ14Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX72[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7=[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5?U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5>U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;0W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS:W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<9W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>:Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T45_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ67Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ66Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX00[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX03[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^21U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^20U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<>W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<1W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>3Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>2Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP84S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8P F_RPOPZHBW9$O@T7WNOEW9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9=S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;?]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T50_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T53_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ71Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ70Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX16[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX11[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^33U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^32U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\= I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T5\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[4_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T61_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ43Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ42Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX24[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX27[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^05U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^04U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>:W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS?W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS>W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\0T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS1W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\1T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS0W%ER]]LU]MAZ6)NO897X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0=0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=33:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9849?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?=>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5685;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;?2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~314<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9716;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=:0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=3;:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9049>6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>14;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;;5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=2?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8759::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6983<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<37=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:5>7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0?91229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>1<;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;35>?5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7585;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx59:2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~333<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9546;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?90=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=16:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;?49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1=8>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7=85;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5922?<4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~33?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8169::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6?=3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<50=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:3;7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{09:1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>71;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=<5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2;7?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos81>9::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6?53<=;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<5<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9376;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz79<0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=71:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;=:49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;;>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1085;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5?=2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~356<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt93?6;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7940=2:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=7=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:187887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0;?1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>56;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4?95>?5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}29>308Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?3;453\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4149>6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|171629V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQ\IOEOAZTH_'_T^IQLOM]B@AT(AV]BHYFP7/w\pf123\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[VOIOEOT^BY!U^PG[FIKWHNO^"GPWHFWLZ1)}V~hS=!VER]OQQ0)]VF^X;8:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGV*OX_@N_DR9!u^v`[43?3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[VOIOEOT^BY!U^PG[FIKWHNO^"||t4g8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPSHLDH@YUG^$^S_JPCNN\EABU'}iTzhm30?7f?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_RKMCICXZF]%YR\K_BMO[DBCZ&~hS{kl<0<54>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^QJJBJBW[E\"XQ]D^ALHZGCL[%~Sn`{/BK?5;073\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[VOIOEOT^BY!U^PG[FIKWHNO^"{Pcov,GL:56?:0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OX[@DL@HQ]OV,V[WBXKFFTMIJ]/t]`jq)DA595:=5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP,qZei|&IB09090:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ER]FNFNF[WIP&\UYHRM@L^CG@W)rWjd#NG35?43?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_RKMCICXZF]%YR\K_BMO[DBCZ&Tocz CH>5:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\WLH@DLUYCZ Z_SF\GJJXIMNY#xQlnu-G8582n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZUNFNFNS_AX.T]Q@ZEHDVKOH_!z_blw+A:66j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVYBBJBJ_SMT*PYULVID@ROKDS-v[fhs'M6828h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CT_D@HLD]QKR(RW[NTOBBPAEFQ+pYdf}%O090:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ER]FNFNF[WIP&\UYHRM@L^CG@W)rWjd#I2:>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPSHLDH@YUG^$^S_JPCNN\EABU'|Uhby!K<7<5f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^QJJBJBW[E\"XQ]D^ALHZGCL[%~Sn`{/FY3Y+Ai@'_TAXVLY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPSHLDH@YUG^$^S_JPCNN\EABU'|Uhby!H[1_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWZCEKAKPRNU-QZTCWJEGSLJKR.w\gkr(OR:V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_RKMCICXZF]%YR\K_BMO[DBCZ&Tocz GZ2^*PY_G[IR:o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP,qZei|&MP=P HnI,V[HS_KP<=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWZCEKAKPRNU-QZTCWJEGSLJKR.w\gkr(OR;V"XQIDSG51>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^QJJBJBW[E\"XQ]D^ALHZGCL[%~Sn`{/FY2Y+SXD\^=;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVYBBJBJ_SMT*PYULVID@ROKDS-v[fhs'NQ:Q#[PXNP@]3d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\WLH@DLUYCZ Z_SF\GJJXIMNY#xQlnu-D_7[)OgB%YRCZXB[52>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^QJJBJBW[E\"XQ]D^ALHZGCL[%~Sn`{/FY1Y+SXNMXN:85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP,qZei|&MP>P Z_MWW22=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]PMKAKMVXD[#[PRE]@KIYFLMX$yRmat.EX6X(RWQEYOT8m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGV*sXkg~$KV=R.FlK*PYJ]QIR:;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP,qZei|&MP?P Z_GFQA33<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\WLH@DLUYCZ Z_SF\GJJXIMNY#xQlnu-D_6[)]VF^X;94U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CT_D@HLD]QKR(RW[NTOBBPAEFQ+pYdf}%LW>S!U^ZLVF_1j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZUNFNFNS_AX.T]Q@ZEHDVKOH_!z_blw+B]3U'MeD#[PMTZ@]30<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\WLH@DLUYCZ Z_SF\GJJXIMNY#xQlnu-D_1[)]VLO^H8:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGV*sXkg~$KV:R.T]OQQ003\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[VOIOEOT^BY!U^PG[FIKWHNO^"{Pcov,C^2Z&\USC_MV6c9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQ\IOEOAZTH_'_T^IQLOM]B@AT(}Viex"IT5\,DjM(RWD_SOT89;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGV*sXkg~$KV;R.T]E@WC1=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZUNFNFNS_AX.T]Q@ZEHDVKOH_!z_blw+B]2U'_T@XZ97:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ER]FNFNF[WIP&\UYHRM@L^CG@W)rWjd#JU:]/W\\JTDQ?<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OX[@DL@HQ]OV,V[WBXKFFTMIJ]/t]`jq)@S?W%YRHKRD46?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_RKMCICXZF]%YR\K_BMO[DBCZ&Tocz GZ4^*PYK]]<<7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWZCEKAKPRNU-QZTCWJEGSLJKR.w\gkr(OR I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWZCEKAKPRNU-QZTCWJEGSLJKR.w\gkr([5959k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP,qZei|&Y783;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGV*sXkg~$_1;15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQ\IOEOAZTH_'_T^IQLOM]B@AT(}Viex"]36?7b?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_RKMCICXZF]%YR\K_BMO[DBCZ&T~~z9c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ER]FNFNF[WIP&\UYHRM@L^CG@WYCDP%LS_KH_CKW_5[)]VLO^H8l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS^GAGMG\VJQ)]VXOSNAC_@FGVZBKQ&MT^HIPBHVX5X(RWONYI;m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CT_D@HLD]QKR(RW[NTOBBPAEFQ[AJ^'NUYIJQMIUY1Y+SXNMXN:n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UXECICE^PLS+SXZMUHCAQNDEP\@I_(OVXNKRLFTZ1^*PYAL[O=o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVYBBJBJ_SMT*PYULVID@ROKDS]GH\)@W[OLSOG[[5_-QZ@CZL I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWZCEKAKPRNU-QZTCWJEGSLJKR^FO]*AXZLMTNDZT5\,V[CBUM?i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OX[@DL@HQ]OV,V[WBXKFFTMIJ]_ENZ+BYUMNUIEYU9]/W\BATB1j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYUID%BS^8!U^AP[GTFEVIJ_NOKE^Q5+LYCMY^CSAZJQ^35O+SX[KXJAR> I^@2f>2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTFE&CT_; Z_BQ\FWGJWJKXOLJJ_R4,MZBBX]BT@YK^_04H*PYTJ[KFS=!F_C3;OBR7&NUYM@L>8Z2^*pYuidh:4"[PR@OA5=Ynfzgmyk?a79V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]AL-J[V0)]VIXSO\NM^ABWFGCMVY=#DQKEQVK[IRBYV;=G#[PSCPBIZ6(AVH:4FI[0/E\VDKE91Q;Q#{Pr`oa5=)RW[KFN<6Pioqvhdrb;0i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZHG$ER]9.T]@WZDUIDUHM^MNDD]P2*OXLLZ_DRB[EP]22N(RWZHYM@Q?/H]A5=M@\9$LS_OBB0:X5X(rW{kfn<6 U^PBIG7?i?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYUID%BS^8!U^AP[GTFEVIJ_NOKE^Q5+LYCMY^CSAZJQ^35O+SX[KXJAR> I^@2Xagy~`lzj1`48Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PR@O,MZU1&\UH_RL]AL]@EVEFLLUX:"GPDDRWLZJSMXU::F Z_R@QEHY7'@UI=5EHT1,D[WGJJ82P=P z_scnf4>(]VXJAO?7_hlpqigsm;3h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[KF#DQ\6/W\GVYEZHGTOL]LAEG\W3)NWMO[XEQCTDS\53M)]VYI^LCP0.K\F4>LO]:%KR\NMC3;_7[)}Vxjao?7/T]QEHD60h<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZHG$ER]9.T]@WZDUIDUHM^MNDD]P2*OXLLZ_DRB[EP]22N(RWZHYM@Q?/H]A5=M@\9$LS_OBB0:X6X(rW{kfn<6 U^PBIG7?W`dxyao{e0c5?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SCN+LYT>'_TO^QMR@O\GDUDIMOT_;!F_EGSPMYK\L[T=;E!U^QAVDKX8&CTN<6DGU2-CZTFEK;3W?S!u^pbig7?'\UYM@L>8^kmwpjf|l82o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXJA"GPS7,V[FUXJ[KFSNO\C@FF[V0(AVNN\YFPLUGR[40L&\UXN_OB_1-J[G7?CN^;"JQ]AL@2<^5Z&|Uym`l>8.W\VDKE91k=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[KF#DQ\6/W\GVYEZHGTOL]LAEG\W3)NWMO[XEQCTDS\53M)]VYI^LCP0.K\F4>LO]:%KR\NMC3;_6[)}Vxjao?7/T]QEHD60Vcexbntd2b2>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PBI*OX[?$^SN]PBSCN[FGTKHNNS^8 I^FFTQNXD]OZS<8D.T]PFWGJW9%BSO?7KFV3*BYUIDH:4V=R.t]qehd60&_T^LCM19]jjvski}o89n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O0&\UFYU?=8.Onq}YHW8:>h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L1)]VG^T<<7/Lov|ZIX99;>o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L1)]VG^T<<7/Lov|ZIX9;?h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M2(RWD_S=?6 Mlw{[JY6;5!Bmtz\KZ7495!Bmtz\KZ74:5!Bmtz\KZ74;5!Bmtz\KZ73=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[426=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[425=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[424=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[423=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[422=j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[432l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5072l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5042l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5052k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\533b3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]1[c12j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\70e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F7/W\IP^6:1%FaxvPO^121g=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G8.T]NQ]750&GfyuQ@_57`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\GJJXE\R$E: Z_LW[57>(EdsSBQ;14`8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B;#[PMTZ26=)Je|rTCR6:b:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_BMO[HS_'@=%YRCZX00;+HkrpVET58m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQLOM]NQ])N?'_TAXV>29-Nip~XGV3:9n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O0&\UFYU?=8.Onq}YHW08?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN484?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4;4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4:4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4=4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4<4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4?4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4>4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN414?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN404?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;87>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+A:66=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,@9496:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ D=4=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!K<6<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J38?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#I26>4:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV>R.FlK*PYJ]QIR9>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S9W%YRHKRD71?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU?]/W\HPR2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX4X(RWQEYOT;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ:Q#IaH/W\IP^DQ<90Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^7Z&\UMH_K:2:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP=P Z_MWW11=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[0_-QZ^HZJS>46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\:T$LbE Z_LW[G\343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY1Y+SXNMXN9?5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S;W%YRBZT468Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KVS7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT3\,V[CBUM<80Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^5Z&\UGYY;;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ8Q#[PXNP@]0><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ6^*BhO&\UFYUMV529V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW9S!U^DGV@353\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY7Y+SXD\^>86[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT5\,V[ISS==1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_0[)]VRD^NW:8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP:P HnI,V[HS_KP?87X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]1U'_TJI\J539V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW;S!U^NVP02<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ4^*PY_G[IR955Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S>W%KcF!U^OV\F_2;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX3X(RWONYI8<4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR=V"XQCUU77?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU8]/W\\JTDQ<20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^>Z&NdC"XQBUYAZ16=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[9_-QZ@CZL?97X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]?U'_T@XZ:4:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP4P Z_YMQG\343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY:Y+SXNMXN9?5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S0W%YRBZT468Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV7R.T][KWE^1:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ S=1=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!\<5<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"]35?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#^29>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$_1914b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X050;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&Y753:7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRm`l^cg`w:76=20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWjegSljkr=3=0==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\gjjXimny0?0;8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQlom]b`at;;7>37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVid`Rokds>7:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[fikWhno~1;1499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPcnn\eabu4?4?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUhcaQndep\`i;87>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVid`Rokds]gh|:66=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWjegSljkr^fo}9496:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[fikWhno~Rjcy=4=01=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf494?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo311<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;984?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo313<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;9:4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo315<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;9<4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo317<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;9>4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo319<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;904?86[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo31?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:587>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2=1?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:5:7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2=3?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:5<7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2=5?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:5>7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2=7?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:507>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2=9?67?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:56=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1=?>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9566=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1==>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9546=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1=;>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9526=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1=9>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9506=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1=7>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe95>6=>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1=1449V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8169<<1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j09?1449V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8149<<1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j09=1449V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8129<<1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j09;1449V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8109<<1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j0991449V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb81>9<<1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j0971459V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8183=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k79=0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?1483=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k79?0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?1683=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7990;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?1083=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k79;0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?1283=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7950;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?1<83<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k793::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>54;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6==3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>56;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6=?3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>50;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6=93::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>52;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6=;3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>5<;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6=53:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>5:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5=;29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=52:12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5=5895Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<9<70>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;17>37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVxd{Rokds>3:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[wipWhno~1?1499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPrnu\eabu4;4?46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUyczQndep?7;2?3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZthVkoh2;>5:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_smt[dbcz5?5855Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPaefq838302_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYug~Ujhi|37?6;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^plsZgcl{632964U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSax_`fgv9?9<:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXzf}Tic?9;T2,MZHHWM$^SDBN/T]GKPR5j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$O@^PRDQFP63<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CTECZLAQ]E*PYDIY]N<>;4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\MKRDIYUM"XQLAQUF50e<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKMEEI"GPYDQOQQ0)AVSN_R\_M/K\]@UXG[OL"B[[_SGD14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYDLFDN#DQVERNVP3(NWPOXS_^B.T]NQ]@0=:1^<"GPNN]G*PYNDH%^SJS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZECGGO$ERWJSMWW2+UUDV[7=3;;;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BOSV@UB\&CTUH]CUU4-MZ_B[VX[A#[PMTZE300<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKDZYI^K[/H]ZAVJR\?$BSTK\_SRN*PYTZE99SL;9;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BOSV@UB\&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZD3i2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VIF\_K\EU-J[\CTD\^="^\C_P120g=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYDEYXN_HZ I^[FWISS>'YY@R_30?6a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FKWZLYNX"GPYDQOQQ0)[[FT]1?15`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$BSTK\_NPFC+IR\VXNK8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#GPYDQ\VUK)]VG^TK9PAC71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU7'@URI^BZT7,J[\CTW[ZF"XQBUYD4[FB3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)AVSN_R\_M/W\IP^A0<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'CTUH]PRQO-QZUUD:8TM8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#GPYDQ\VUK)]VYY@> I^[FWISS>'YY@RCZX6>3:1?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+UUDVG^T:2>>548Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV6(AVSN_A[[6/QQHZKRP1>37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]?/H]ZAVJR\?$X^AQ^30>3:1><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+UUDV[8=1?1499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.RPO[T564;4?:6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%__BPQ=2=03=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*VTKWX6:2984U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#]]L^S?6;213\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY;#DQVERNVP3(TZEUZ0>0:a:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'CTUH]POSGD*JSSW[OL9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="DQVER]QTH(RWD_SJ:QNB408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV7(AVSN_A[[6/K\]@UXZYG%YRCZXG5\GA2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(NWPOXS_^B.T]NQ]@?=81^<"GPNN]G*PYNDH%^SJ.T]MW4)NWPOX@XZ9.H]ZAVYUXD$^S^\C33]@14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*LY^MZUY\@ Z_RPO77YC<01^<"GPNN]G*PYNDH%^SJ.T]MW4)NWPOX@XZ9.RPO[HS_0=20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^? I^[FWISS>'YY@R_<1=2=0==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*VTKWX9:0<0;8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!SSN\U67;:7>=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$X^AQ^<1<72>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-WWJXY5;58;5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="^\C_P>1:10<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ;$ERWJSMWW2+UUDV[7?3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_RAF+LY^MZF^X; Z_RPOG40B<11^<"GPNN]G*PYNDH%^SJS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZUDZZ^$ERWJSMWW2+OXQLYT^]C!U^OV\C12;2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VYH^^Z I^[FWISS>'CTUH]PRQO-QZUUD:8TM8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PSBPPP*OXQLYGYY8!I^[FWZTWE'_T__B<2^@73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZUDZZ^$ERWJSMWW2+UUDV[8=964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PSBPPP*OXQLYGYY8!SSN\U969<11^<"GPNN]G*PYNDH%^SJS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZQDM&CTUH]CUU4-QZUUDJ;=I974U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PWIANTFC(AVSN_A[[6/W\WWJ4:=30Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_T[AMBPBG,MZ_B[E__:#[PSSN067?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&YHBYQLE3c8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*UDF]UHA]1:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(KHZTMIJ]_og{p959<91^<"GPNN]G*PYNDH%^SJ528Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,GDVXIMNYSckwt=5=05=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)DIYUJHI\Pndzw8=8382_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&IJ\ROKDS]ma}r;17>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V>R.T]PAI2f3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR;;Q#[PSDN7e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.G]PAI]69T$^S^KC4`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGVj7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V?;]/W\W@J3i2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][1_-QZEFXVKOH_;:;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_5[)]VIJ\ROKDS]NQ]353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW=S!U^k@EUYFLMX>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ3^*PYDIYUJHI\:5:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^7Z&\UHM]QNDEP\IP^2:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V?R.T]jGDVXIMNY9<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY1Y+SXKHZTMIJ]549V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]5U'_TOL^PAEFQ[HS_=;1^<"GPNN]G*PYNDH%^SJ;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_1[)]VIJ\ROKDS76?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS=W%YRMNP^CG@WYJ]Q?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][5_-QZoDIYUJHI\:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^3Z&\UHM]QNDEP61>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR?V"XQLAQ]B@ATXE\R>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ7^*PYnKHZTMIJ]509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]1U'_TOL^PAEFQ10=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q=Q#[PC@R\EABUWD_S9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY5Y+SXaJK[SLJKR438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\?T$^SNO__@FGV03<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP;P Z_BCS[DBCZVG^T8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX3X(RW`IJ\ROKDS72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS1W%YRMNP^CG@W323\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW5S!U^ABTZGCL[UFYU;=;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_=[)]VcHM]QNDEP65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR3V"XQLAQ]B@AT2=2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V7R.T]@EUYFLMXTAXV:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^?Z&\UbOL^PAEFQ17=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,GL:66<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'JC7>3;=;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"MF<2<66>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-@M929=;1^<"GPNN]G*PYNDH%^SJ.T]PGKR(K@6>28<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#NG36?71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.AJ8282:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)DA5259?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$OD26>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>3:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:66<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'M6928?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#I2<>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>7:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:26<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'M6=28?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#I28>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>;:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:>6 I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP=P HnI,V[HS_KP?37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP=P Z_GFQA01<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]6U'_T@XZ:9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[0_-QZ^HZJS>h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW?S!GoJ-QZKRPJS>46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW?S!U^DGV@303\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\:T$^SA[[589V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ0^*PY_G[IR9i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV=R.FlK*PYJ]QIR955Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV=R.T]E@WC2?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S:W%YRBZT4;8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY0Y+SXPFXHU8j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU;]/EmL+SXE\RHU864U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU;]/W\BATB=>1^<"GPNN]G*PYNDH%^SJ.T]PGKR(OR>V"XQCUU7:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX0X(RWQEYOT;k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT5\,DjM(RWD_SOT;7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT5\,V[CBUM<=0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ>Q#[PLTV6=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_0[)]VRD^NW:d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[7_-CkN)]VG^TNW:8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[7_-QZ@CZL?<7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP:P Z_MWW1<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^0Z&\USC_MV5e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ5^*BhO&\UFYUMV599V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ5^*PYAL[O>;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW:S!U^NVP0?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]0U'_TTB\LY4f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY;Y+Ai@'_TAXVLY4:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY;Y+SXNMXN9:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV6R.T]OQQ3>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\0T$^SUA]CX7;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX=X(RWONYI894U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU6]/W\HPR212_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S0W%YRV@RB[65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P858292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T484>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%X0?0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!\<2<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P818292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T4<4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%X0;0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!\<6<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P8=8292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T404?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/BK?5;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$OD2=>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)DA595855Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.AJ818302_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#NG35?6;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(K@6=2964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-@M919<11^<"GPNN]G*PYNDH%^SJS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'JC753:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@969<>1^<"GPNN]G*PYNDH%^SJ.T]TGKR(L5858:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?7;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H1:1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*B;=7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ D=4=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&N7;3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@9>9<>1^<"GPNN]G*PYNDH%^SJ.T]TGKR(OR:V"J`G.T]NQ]E^?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY2Y+Ai@'_TAXVLY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S8W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR;V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR;V"XQWOSAZ16=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP>P HnI,V[HS_KP>n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ0^*PYAL[O?h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY1Y+SXD\^?j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY1Y+SXPFXHU8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_6[)OgB%YRCZXB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ8Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP?P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP?P Z_YMQG\343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV:R.FlK*PYJ]QIR8h5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX0X(RWONYI9j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_1[)]VF^X9h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_1[)]VRD^NW:3:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]2U'MeD#[PMTZ@]1c<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW8S!U^DGV@2c3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV;R.T]OQQ2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV;R.T][KWE^=:1^<"GPNN]G*PYNDH%^SJW%KcF!U^OV\F_3m2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU8]/W\BATB I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ:^*BhO&\UFYUMV4d9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\0T$^SKJ]E5f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S1W%YRBZT5d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S1W%YRV@RB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ2Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP5P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP5P Z_YMQG\203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_1>1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;97><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ S=0=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y7?3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W929<>1^<"GPNN]G*PYNDH%^SJ.T]TGKR([5<58:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.Q?3;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_161469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;179=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#XQMRJ202>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*SXJ[A:485Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!Z_RAMPZEJX&CTO^QHAOF-QZETWNKEHR]]L.K\W3(RWJYTKL@K_RPO[V0(AV_XIR\_M^LF4+SXOHDOS^\C_RGW<3=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)RW^IEXRFLMQ-J[FUXOHDO"XQLS^EBJAYTZE%BS^8!U^AP[BGILVYY@R]9/H]VW@YUXDUEI= Z_FCM@ZUUDVYNX584U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ U^U@JQYKKDZ$ERM\_FCM@+SXKZULMCJPSSN,MZU1&\UH_RINNE]PVIYT>&CTY^KPRQO\J@6)]VMJBIQ\RM]PAQ5e3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a=2=7g=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyo31?1a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``Wmkm1<13c9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-`bbYci}k7?3=m;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsi5>58=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7==0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in2>1?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=31:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8459<91^<"GPNN]G*PYNDH%^SJ2d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~jS{kl<0<0b>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*eaoVnjxlQyeb>1:6`<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8684n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&imkRjnt`]uaf:36:l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb[scd4<48j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpdYqmj6=2>h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ cge\`drfWoh0:02d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~jS{kl<8<0g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oDIYUJHI\30?1`?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lEFXVKOH_2>>2a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mFGWWHNO^1<13b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jGDVXIMNY0>02>m4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iBCS[DBCZ5<5?n5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fC@R\EABU4>48o6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"gLAQ]B@AT;079h7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#dMNP^CG@W:>6:20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$e^MAT=2=7==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)n[JD_0<0<8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.kPGKR;:7937X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#d]LNU>0:6><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(aZIEX1:1399V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jWFHS4<4846[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"g\COV?2;5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`YHBY28>2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mVEI\525?55Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fSBLW8<85m2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YR]LNU]@IUYV:11^<"GPNN]G*PYNDH%^SJS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]V^YEJ>=9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZRUAN;9j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^U@JQYOKDZT]?h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\SFHSWEIF\R_=9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,SFHSWJO9n6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B WBLW[MEJX;o0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"YLNU]KGHVXKL8o7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!XCOV\LFKWWX8i7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!XCOV\HFKW:l1^<"GPNN]G*PYNDH%^SJ6;i0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"gLAQ]TVZCI:m1^<"GPNN]G*PYNDH%^SJR]^.T]@EUESZEUBS^\CT^LF[4(RWJG[^H]JT^OPAQ5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZEUBS^\CT^LF[4(RWGY;S@]JT2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQHZOX[[F_SCKP1/W\JV7XEZO_?l5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C_H]PVIRXFLU:"XQ\CSQW[HUB\;>0Y=!F_OM\@+SXAEK$YR\\T.E\VVR\8T$^S_][259V4*OXFFUO"XQFL@-V[WUS'NUY_YU>]/W\VVR5<2_;#DQAO^F-QZOKI&_T^^Z G^PPP^4Z&\UY_Y<;;T2,MZHHWM$^SDBN/T]QWQ)@W[Y_W>S!U^PPP72<]9%BSCAPD/W\MIG(]VXXX"IPRRVX0X(RW[Y_>95Z0.K\JJYC&\UB@L!Z_SQW+BYU[]Q>Q#[PRRV10>S7'@UECRJ!U^KOE*SXZZ^$KR\\TZ4^*PYU[]8?7X> I^LL[A(RW@FJ#XQ]SU-D[WUSS>W%YR\\T328Q5)NWGETH#[PIMC,QZTT\&BJ@YQumqf5<=R8&CTBBQK.T]JHD)RW[Y_#]A]219V4*OXFFUO"XQFL@-V[WUS'YXNS_K\EU214>S7'@UECRJ!U^KOE*SXZZ^$\_KPRDQFP44?3\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TOAKNR358Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+PYCG\^946[?/H]MKZB)]VCGM"[PRRV,QZGUEVRMI_!Z_EMVP54?3\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_THB[[1268Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+PY@MGUOIAOV[0_-QZ@C;=1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRIJN^FFHD_\:T$^SKJ<4:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[BCIWMOGMTU<]/W\BA533\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TKH@PDDNB]^2Z&\UMH?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]QBATB:11^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRZIDSG1g>S7'@UECRJ!U^KOE*SXZZ^$YRO]M^ZEAW)cagUgmymgee06?P6(AVDDSI Z_HNB+PYU[]%^SL\B_YDFV*oDD[837X> I^LL[A(RW@FJ#XQ]SU-V[DTJWQLN^"gKIO>3:7><]9%BSCAPD/W\MIG(]VXXX"[PASO\\CCU'`NBB1?1279V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:76;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:66;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:56;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:36;30Y=!F_OM\@+SXAEK$YR\\T.W\LDJSWQLN^"[PCMGBV7><]9%BSCAPD/W\MIG(]VXXX"[PH@NW[]@BZ&_THB[[289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PYCG\^;>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/T]GKPR6;<1^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#XQHEO]GAIG^S8W%YRHK349V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PY@MGUOIAOV[3_-QZ@C:01^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#XQ]FEPF6<=R8&CTBBQK.T]JHD)RW[Y_#XQGAMV\\CCU'\U_JI\J2e9V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+aoiWekoekk279V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+lEKZ;30Y=!F_OM\@+SXAEK$YR\\T.W\LDJSWQLN^"gKIO>3:7?<]9%BSCAPD/W\MIG(]VXXX"[PH@NW[]@BZ&cOEC2>>358Q5)NWGETH#[PIMC,QZTT\&_TDLB[_YDFV*oCG\^9i6[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ iEMVPZbkq5:5>h5Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/hFLQQYcdp692 I^LL[A(RW@FJ#XQ]SU-jV@UB\5:5>85Z0.K\JJYC&\UB@L!Z_RVBP*GD\[OXIYQumqf65=R8&CTBBQK.T]JHD)RWZ^JX"OLT^fppdr582_;#DQAO^F-QZOKI&_T_YO[/@PN[ausi}8>7X> I^LL[A(RW@FJ#XQ\T@V,GDVXZLYNXRjcy03e?P6(AVDDSI Z_HNB+PYT\H^$HD\[Y^F35c=R8&CTBBQK.T]JHD)RWZ^JX"JFRU[\@4473\:$ER@@_E,V[LJF'\UXXLZ DHPW]ZUBD;80Y=!F_OM\@+SXAEK$YR][AU-GMWR^Wmymy<;;T2,MZHHWM$^SDBN/T]PPDR(LZ^JXRka_enz572<]9%BSCAPD/W\MIG(]VY_MY!KSUCW[`hXles9>95Z0.K\JJYC&\UB@L!Z_RVBP*BT\H^TicQklx115>S7'@UECRJ!U^KOE*SX[]K_#I][AU]okdb512_;#DQAO^F-QZOKI&_T_YO[/DZWGDVXZLKOURj|t`v15>S7'@UECRJ!U^KOE*SX[]K_#K[CL^fppdr5n2_;#DQAO^F-QZOKI&_T_YO[/G]PWQGSS9W%ER][AU,V[VRF\::0Y=!F_OM\@+SXAEK$YR][AU-E[VUSI]Q:

k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV?R.H]PPDR)]VY_MYT$BS^ZNT/W\WQGS:o1^<"GPNN]G*PYNDH%^S^ZNT.D\WVRF\R=V"DQ\T@V-QZUSI]8m7X> I^LL[A(RW@FJ#XQ\T@V,BZUT\H^P4P F_RVBP+SX[]K_>k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV7R.H]PPDR)]VY_MY<;;T2,MZHHWM$^SDBN/T]PPDR(OVDXW=S!U^LPU72<]9%BSCAPD/W\MIG(]VY_MY!H_OQX5X(RWGYZ>95Z0.K\JJYC&\UB@L!Z_RVBP*AXFZQ9Q#[PNRS10>S7'@UECRJ!U^KOE*SX[]K_#JQASZ1^*PYI[X8?7X> I^LL[A(RW@FJ#XQ\T@V,CZHTS=W%YR@\Q368Q5)NWGETH#[PIMC,QZUSI]%LSC]T5\,V[KUV:=1^<"GPNN]G*PYNDH%^S^ZNT.E\JV]1U'_TB^_=4:W3+LYIGVN%YRGCA.W\WQGS'NUE_V9R.T]MWT433\:$ER@@_E,V[LJF'\UXXLZ G^LP_=[)]VDX]?:4U1-J[KIXL'_TEAO U^QWEQ)@WGYP5P Z_OQR6<=R8&CTBBQK.T]JHD)RWZ^JX"Cbuy]GMWR^Wmymy?>239V4*OXFFUO"XQFL@-V[VRF\&DXSi}{au>3:74<]9%BSCAPD/W\MIG(]VY_MY!AS^fppdr;97897X> I^LL[A(RW@FJ#XQ\T@V,JVYc{}k0?0=2:W3+LYIGVN%YRGCA.W\WQGS'GYTh~znt=1=67=R8&CTBBQK.T]JHD)RWZ^JX"@\_eqweq:36;80Y=!F_OM\@+SXAEK$YR][AU-MWZbt|h~793<=;T2,MZHHWM$^SDBN/T]PPDR(FZUoyo{<7<16>S7'@UECRJ!U^KOE*SX[]K_#C]Pdrvbp919:;1^<"GPNN]G*PYNDH%^S^ZNT.LP[ausi}632?<4U1-J[KIXL'_TEAO U^QWEQ)I[Vnxxlz39?3f?P6(AVDDSI Z_HNB+PYT\H^$B^Qco`f11>S7'@UECRJ!U^KOE*SX[]K_#^ZNTD]gwqgs494996[?/H]MKZB)]VCGM"[PSUCW+VRF\LUoyo{<0<2b>S7'@UECRJ!U^KOE*SX[]K_#YJ@_og{p72<]9%BSCAPD/W\MIG(]VY_MY![RHEDAWYc{}k=n5Z0.K\JJYC&\UB@L!Z_RVBP*SXI[G996[?/H]MKZB)]VCGM"[PSUCW+PYFZDUl`xkPsdv2f>S7'@UECRJ!U^KOE*SX[]K_#XQLR318Q5)NWGETH#[PIMC,QZUSI]%^SIG]TX]E@FC5;2_;#DQAO^F-QZOKI&_T_YO[/T]GMWR^WON[I?<4U1-J[KIXL'_TEAO U^QWEQ)RWMCYXTQCDB1b?P6(AVDDSI Z_HNB+PYT\H^$YRJBUY6,QZETWD_S#D=!U^OV\=)Je|rTCR=S7'@UECRJ!U^KOE*SX[]K_#XQKSM3,QZBH]]8>7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%^SIAZT106?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-V[AIR\89:7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%^SJKA_EGOE\]6U'_TJI<:;T2,MZHHWM$^SDBN/T]PPDR(]VNX@ I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bOA\=5:W3+LYIGVN%YRGCA.W\WQGS'\UO_A? iEKM8585=2_;#DQAO^F-QZOKI&_T_YO[/T]GWI7(aMCE0<0=a:W3+LYIGVN%YRGCA.W\WQGS'\UO_A? iEMVPZbkq5:5>l5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZF:#dJ@UU]gh|:668n0Y=!F_OM\@+SXAEK$YR][AU-V[AUK:8n0Y=!F_OM\@+SXAEK$YR][AU-V[AUK;8i0Y=!F_OM\@+SXAEK$YR][AU-V[AUU9j1^<"GPNN]G*PYNDH%^S^ZNT.W\AFT5=2_;#DQAO^F-QZOKI&_T_YO[/T]FGWY`d|oThz>d:W3+LYIGVN%YRGCA.W\WQGS'\UMYAB=6:W3+LYIGVN%YRGCA.W\WQGS'\UMYABPgmwf[vcs;>1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO01;?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:=>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J768:30Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N3256?<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?>22;8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;:?>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J76<:30Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N3216?<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?>62;8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;:;>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J760:n0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N32 I^LL[A(RW@FJ#XQ\T@V,QZKRP&_TO^QBUY-J5+SXE\R9#@czx^M264Y@;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0017<=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<<<389V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG88??45Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K442;11^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO010<>S7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=9=7;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI6=:20Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N357==R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<9<8:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH91937X> I^LL[A(RW@FJ#XQ\T@V,QZKRP&_TO^QBUY-J5+SXE\R9#@czx^M2=4e<]9%BSCAPD/W\MIG(]VY_MY!Z_OQO75=R8&CTBBQK.T]JHD)RWZ^JX"[PRDQFPZCCOL%BSES7'@UECRJ!U^KOE*SX[]K_#XQ]ERGW[@B@M&cOCXZ30?0`?P6(AVDDSI Z_HNB+PYT\H^$YR\JSDV\AAAB'`NDYY2>>0d8Q5)NWGETH#[PIMC,QZUSI]%^S_G\IOE14>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V@IA453\:$ER@@_E,V[LJF'\UXXLZ U^QWEQEJLVd:j6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^N<S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(K@682?94U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.AJ8185?2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$OD2:>358Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*EN4?49;6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ CH>4:71<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB050=7:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,GL:>6;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"J30?05?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)C4849:6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ D=0=63=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'M682?84U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.F?0;413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%O080=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,@909:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#I28>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*B;078=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!K<8<06>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR:V"J`G.T]NQ]E^:m1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU?]/W\BATB:j1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU?]/W\HPR5m2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV>R.T][KWE^;;1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU>]/EmL+SXE\RHU?j4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX5X(RWONYI?m4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX5X(RWE__>h5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY2Y+SXPFXHU><4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX6X(@fA$^S@[WCX0g?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S;W%YRHKRD0`?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S;W%YRBZT3g8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\:T$^SUA]CX11?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S:W%KcF!U^OV\F_5l2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV=R.T]E@WC5k2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV=R.T]OQQ4b3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW>S!U^ZLVF_4:2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV:R.FlK*PYJ]QIR>i5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY7Y+SXNMXN>n5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY7Y+SXD\^9i6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ6^*PY_G[IR??5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY6Y+Ai@'_TAXVLY3f8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\=T$^SKJ]E3a8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\=T$^SA[[2d9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]2U'_TTB\LY208Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\>T$LbE Z_LW[G\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW;S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW;S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP:P Z_YMQG\553\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW:S!GoJ-QZKRPJS9h6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ5^*PYAL[O9o6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ5^*PYK]]8n7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!H[6_-QZ^HZJS8>6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ:^*BhO&\UFYUMV2e9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]?U'_TJI\J2b9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]?U'_T@XZ=e:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^>Z&\USC_MV2e9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]>U'_TJI\J2b9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]>U'_T@XZ=e:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^?Z&\USC_MV279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+V:76;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"]31?05?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)T4;49:6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ S=1=63=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'Z6?2?84U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.Q?1;413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%X0;0=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,W919:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#^27>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*U;17;h7X> I^LL[A(RW@FJ#XQ\T@V,QZRCG;:0Y=!F_OM\@+SXAEK$YR][AU-V[QTNONOY>45Z0.K\JJYC&\UB@L!Z_RVBP*SX\[CLKH\Pgmwf[vcs9o1^<"GPNN]G*PYNDH%^S^ZNT.kPPDR;878;7X> I^LL[A(RW@FJ#XQ\T@V,mVRF\5;;2f:W3+LYIGVN%YRGCA.W\WQGS'`Y_MY2=>0d8Q5)NWGETH#[PIMC,QZUSI]%b_YO[<2<2b>S7'@UECRJ!U^KOE*SX[]K_#d][AU>7:4`<]9%BSCAPD/W\MIG(]VY_MY!fSUCW8086n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:168l0Y=!F_OM\@+SXAEK$YR][AU-jWQGS4>4:j6[?/H]MKZB)]VCGM"[PSUCW+lUSI]632318Q5)NWGETH#[PIMC,QZUSI]%b_YO[_BLW8485;2_;#DQAO^F-QZOKI&_T_YO[/hQWEQYDF]692?=4U1-J[KIXL'_TEAO U^QWEQ)n[]K_SN@[<2<17>S7'@UECRJ!U^KOE*SX[]K_#d][AU]@JQ:36;90Y=!F_OM\@+SXAEK$YR][AU-jWQGSWJD_080=3:W3+LYIGVN%YRGCA.W\WQGS'`Y_MYQLNU>5:75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4>49?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY27>318Q5)NWGETH#[PIMC,QZUSI]%b_YO[_BLW8<85>2_;#DQAO^F-QZOKI&_TX_GH/G]MKZRDEJ$^SKJ]339V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_RVLVDABWX_J@#[PC@R\F62<]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZUSG[KLIR_ZAM,V[FGWWMFR;h5Z0.K\JJYC&\UB@L!Z_UPJC*SX\J%BS^Z@R@EF[TSFD'_T_YA]AFG\UPGK'@UX^AZPND]2*LYIE\U:SYAP4/W\PFJ(AVDFYRK^1/W\mAIR\&CTUH]CUU4-QZUUDJ;=I;64U1-J[KIXL'_TEAO U^VQMB)RW]I$ER][OSCDAZWRIE$^S^Z@R@EF[TSFD&CT__B[_OG\5+OXFD_T=RZ@_5,V[QEK'@UDYY\JG/W\@JSS=l1^<"GPNN]G*PYNDH%^SY\FG.W\PF)NWZ^D^LIJ_PWBH+SX[]EYMJKPQTCO+LYTZE^TBHQ>.H]MIPY6W]ET8#[PTBN,mAIR\=1^<"GPNN]G*PYNDH%^SY\FG.W\PF)NW]YN]R@JQ3,V[QEXMX_JXDAA/H]PVIRXFLU:"DQAMT]2[QIX<'_TXNB I^MVPWC@&\UOCXZ:a:W3+LYIGVN%YRGCA.W\PWO@'\U_O"GPTRGR[KCV:'_TXNQJQTCWMJH(AVYY@YQAE^3-MZHJ]V;TXBQ;.T]WGI)nLF__9;5Z0.K\JJYC&\UB@L!Z_UPJC*SX\J%BSY]JQ^LFU7(RW]ITI\[NTHMM+LYTZE^TBHQ>.H]MIPY6W]ET8#[PTSKDU6c<]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZRTMXUEI\2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

[02^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[03^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[00^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[01^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[06^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[07^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[04^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[05^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[0:^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[0;^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nc:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW>[0_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:=]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:<]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:;]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V::]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:9]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:8]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:7]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:6]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mn5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR=V:R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8>R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8?R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8=R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8:R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8;R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W88R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W89R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W86R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W87R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jo6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES:W8S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP;P:=S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP;P: I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP;P:?S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP;P:>S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kh7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP;P:P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hi0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ8Q'_TO^QHAOF[[VTKWZ<$KRINNE]GH\4\8T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)@WNKEHRJCY3Y24X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U>1\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q:>P F_HL\VDH@M'_TKL@K_ENZ6474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U>5\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q::P F_HL\VDH@M'_TKL@K_ENZ6474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U>9\,J[LHXZHDLI#[PG@LG[AJ^:020Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q:Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&MTKL@K_ENZ6^47U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*AXOHDOSIBV2Z02Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR>V<=]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NWZ<%YRM\_FCM@]YTZEUX:"IPG@LG[AJ^:R88Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&MTKL@K_ENZ6^43U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*AXOHDOSIBV2Z06Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR>V<9]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NWZ<%YRM\_FCM@]YTZEUX:"IPG@LG[AJ^:R8&MTKL@K_ENZ6^4?U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*AXOHDOSIBV2Z0:Y+OXAGUYMCIJ.T]DEKBXLES9555Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR>V12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'NULMCJPDM[1_67Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW=[20^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES9W>=R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'NULMCJPDM[1_63Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW=[24^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES9W>9R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'NULMCJPDM[1_6?Z&@UBBR\NNFG-QZAFFMUO@T<68:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+BY@IGNTHAW=[2_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP8P8=S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$KRINNE]GH\4\<8W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(OVMJBIQKLX0X07[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQ\6/W\GVY@IGNSS^\C_R4,CZAFFMUO@T I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP8P89S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$KRINNE]GH\4\< I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 G^EBJAYCDP8P85S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$KRINNE]GH\4\<0W%ERGA_SCMC@(RWNKEHRJCY3;;?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(OVMJBIQKLX0X0X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U:0\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q>=P F_HL\VDH@M'_TKL@K_ENZ6474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U:4\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q>9P F_HL\VDH@M'_TKL@K_ENZ6T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)@WNKEHRJCY3Y63X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-D[BGILVNGU?U:8\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!H_FCM@ZBKQ;Q>5P F_HL\VDH@M'_TKL@K_ENZ6<><]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%LSJOAD^FO]7]2U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*AXOHDOSIBV2Z43Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.E\CDHCWMFR>V8>]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NWZ<%YRM\_FCM@]YTZEUX:"IPG@LG[AJ^:R<9Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&MTKL@K_ENZ6^04U'CTECQ]AOEF*PY@IGNTHAW=999V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*AXOHDOSIBV2Z4^*LYNFVXJBJK!U^EBJAYCDP8246[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CT_; Z_BQ\CDHCPVYY@R]9/F]DEKBXLES9W:S!I^KM[WGIOL$^SJOAD^FO]7??3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$KRINNE]GH\4\0T$BSD@PR@LDA+SXOHDOSIBV28:8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)@WNKEHRJCY3Y:Y+OXAGUYMCIJ.T]DEKBXLES9m=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.W\GVY@IGNT__BPS7-J[PUBW[ZFSCK?.T]DEKBX[[FT_HZ8f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><02=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?548?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~95;825>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:0<:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t?314<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>22;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz597061:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i648254=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp;7=408f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2>>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><32=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?648?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~958825>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:0?:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t?324<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>12;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz594061:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i64;254=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp;7>408f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2=>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><22=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?748?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~959825>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:0>:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t?334<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>02;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz595061:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i64:254=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp;7?408f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><52=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?048?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~95>825>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:09:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t?344<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>72;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz592061:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i64=254=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp;78408f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2;>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><42=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?148?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~95?825>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:08:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t?354<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>62;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz593061:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i64<254=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp;79408f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<2:>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><72=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[V0)]VIXSJOADY]PVIYT>&mjbiQklx3?248?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~95<82:h4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles:0;08f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu<28>6d8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^Q5*PYD[VMJBIVPSSN\W3)`ignThaw><9<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy0>::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1858?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:5;:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles90<<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<312<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>20;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz697261:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i548<54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp87=:070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu?2>8?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(ohdoSibv2=3::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1848?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:58:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles90?<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<322<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>10;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz694261:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i54;<54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp87>:070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu?2=8?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(ohdoSibv2=0::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1878?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:59:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles90><1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<332<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>00;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz695261:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i54:<54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp87?:070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu?2<8?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(ohdoSibv2=1::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1868?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:5>:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles909<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<342<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>70;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz692261:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i54=<54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp878:070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu?2;8?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(ohdoSibv2=6::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1818?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:5?:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles908<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<352<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>60;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYT>'_TO^QHAOF[[VTKWZ<$kl`k_enz693261:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i54<<54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS^8!U^AP[BGILQUX^AQ\6.ebjaYcdp879:070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPS7,V[FUXOHDOTR]]L^Q5+bgilVngu?2:8?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]P2+SXKZULMCJW_RPO[V0(ohdoSibv2=7::2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{1808?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@UX:#[PCR]DEKB_WZXGS^8 g`lg[aj~:5<:25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ER]9.T]@WZAFFMRT__BPS7-dekbXles90;<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_R4-QZETWNKEHUQ\RM]P2*affmUo`t<362<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\W3(RWJYTKL@KX^QQHZU1'nkehRjcy3>5:2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZU1&\UH_RINNEZ\WWJX[?%lmcjPdm{18280n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P

l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AVY="XQLS^EBJA^X[[FT_;!haof\`i5404?:6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERA]EF,J[\CTWFXNK#[POSGD74=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC dnww[qkw:81^<"GPNN]G*PYNDH%^SY\FG.vqmbEhfmCe>?5Z0.K\JJYC&\UB@L!Z_UPJC*ruanIdbiAzt068Q5)NWGETH#[PIMC,mDTJ911^<"GPNN]G*PYNDH%bOL^[USG2=>S7'@UECRJ!U^KOE*oDIYUOCCK=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>3:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT4849?6[?/H]MKZB)]VCGM"gLAQ]MQHYTIDZGI^2=>318Q5)NWGETH#[PIMC,mFGWWG_FS^OBPMGP8685;2_;#DQAO^F-QZOKI&cHM]QAUL]PEHVKMZ6?2?=4U1-J[KIXL'_TEAO iBCS[KSJWZKF\AK\<4<17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:16;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX0:0=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>;:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT404:h6[?/H]MKZB)]VCGM"gLAQ]PPDRB494:h6[?/H]MKZB)]VCGM"gLAQ]PPDRB4849<6[?/H]MKZB)]VCGM"gLAQ]WVLA@M[UDYY?i;T2,MZHHWM$^SDBN/hABTZQUWHNO^1>11g9V4*OXFFUO"XQFL@-jGDVX_[UJHI\31?3e?P6(AVDDSI Z_HNB+lEFXV]YSLJKR=0=5c=R8&CTBBQK.T]JHD)nKHZT[_QNDEP?7;7a3\:$ER@@_E,V[LJF'`IJ\RY]_@FGV9299o1^<"GPNN]G*PYNDH%bOL^PWS]B@AT;=7;m7X> I^LL[A(RW@FJ#dMNP^UQ[DBCZ5<5=k5Z0.K\JJYC&\UB@L!fC@R\SWYFLMX7;3?i;T2,MZHHWM$^SDBN/hABTZQUWHNO^1611g9V4*OXFFUO"XQFL@-jGDVX_[UJHI\39?3b?P6(AVDDSI Z_HNB+lEFXV]YSH@>8:W3+LYIGVN%YRGCA.kGEQG;87;27X> I^LL[A(RW@FJ#dJNT@>24;7>3\:$ER@@_E,V[LJF'`NJXL2>1?3:?P6(AVDDSI Z_HNB+lBF\H6:>3?6;T2,MZHHWM$^SDBN/hFBPD:6;7;27X> I^LL[A(RW@FJ#dJNT@>20;7>3\:$ER@@_E,V[LJF'`NJXL2>5?3:?P6(AVDDSI Z_HNB+lBF\H6::3?6;T2,MZHHWM$^SDBN/hFBPD:6?7;27X> I^LL[A(RW@FJ#dJNT@>2<;7>3\:$ER@@_E,V[LJF'`NJXL2>9?3;?P6(AVDDSI Z_HNB+lBF\H6:2<74U1-J[KIXL'_TEAO iECWE9476830Y=!F_OM\@+SXAEK$eIO[A=02:4?<]9%BSCAPD/W\MIG(aMK_M1<=>0;8Q5)NWGETH#[PIMC,mAGSI5882<74U1-J[KIXL'_TEAO iECWE9436830Y=!F_OM\@+SXAEK$eIO[A=06:4?<]9%BSCAPD/W\MIG(aMK_M1<9>0;8Q5)NWGETH#[PIMC,mAGSI58<2<74U1-J[KIXL'_TEAO iECWE94?6830Y=!F_OM\@+SXAEK$eIO[A=0::4><]9%BSCAPD/W\MIG(aMK_M1<1189V4*OXFFUO"XQFL@-j@DRF4::5=45Z0.K\JJYC&\UB@L!fD@VB8679901^<"GPNN]G*PYNDH%bHLZN<20=5<=R8&CTBBQK.T]JHD)nLH^J0>=1189V4*OXFFUO"XQFL@-j@DRF4:>5=45Z0.K\JJYC&\UB@L!fD@VB8639901^<"GPNN]G*PYNDH%bHLZN<24=5<=R8&CTBBQK.T]JHD)nLH^J0>91189V4*OXFFUO"XQFL@-j@DRF4:25=45Z0.K\JJYC&\UB@L!fD@VB86?9911^<"GPNN]G*PYNDH%bHLZN<2<2=>S7'@UECRJ!U^KOE*oCI]K78=0>9:W3+LYIGVN%YRGCA.kGEQG;<84:56[?/H]MKZB)]VCGM"gKAUC?078612_;#DQAO^F-QZOKI&cOMYO342<2=>S7'@UECRJ!U^KOE*oCI]K7890>9:W3+LYIGVN%YRGCA.kGEQG;<<4:56[?/H]MKZB)]VCGM"gKAUC?038612_;#DQAO^F-QZOKI&cOMYO346<2=>S7'@UECRJ!U^KOE*oCI]K7850>9:W3+LYIGVN%YRGCA.kGEQG;<04:46[?/H]MKZB)]VCGM"gKAUC?0;7>3\:$ER@@_E,V[LJF'`NJXL2:0?3:?P6(AVDDSI Z_HNB+lBF\H6>=3?6;T2,MZHHWM$^SDBN/hFBPD:2:7;27X> I^LL[A(RW@FJ#dJNT@>67;7>3\:$ER@@_E,V[LJF'`NJXL2:4?3:?P6(AVDDSI Z_HNB+lBF\H6>93?6;T2,MZHHWM$^SDBN/hFBPD:2>7;27X> I^LL[A(RW@FJ#dJNT@>63;7>3\:$ER@@_E,V[LJF'`NJXL2:8?3:?P6(AVDDSI Z_HNB+lBF\H6>53?7;T2,MZHHWM$^SDBN/hFBPD:26830Y=!F_OM\@+SXAEK$eIO[A=43:4?<]9%BSCAPD/W\MIG(aMK_M18>>0;8Q5)NWGETH#[PIMC,mAGSI5<92<74U1-J[KIXL'_TEAO iECWE9046820Y=!F_OM\@+SXAEK$eIO[A=4=5==R8&CTBBQK.T]JHD)nLH^J0:0>8:W3+LYIGVN%YRGCA.kGEQG;07;37X> I^LL[A(RW@FJ#dJNT@>::4g<]9%BSCAPD/W\MIG(aMK_MRJ@UU3:?P6(AVDDSI Z_HNB+lTB[L^7<3?6;T2,MZHHWM$^SDBN/hPFW@R;97;27X> I^LL[A(RW@FJ#d\JSDV?6;7>3\:$ER@@_E,V[LJF'`XN_HZ33?3:?P6(AVDDSI Z_HNB+lTB[L^783?6;T2,MZHHWM$^SDBN/hPFW@R;=7;27X> I^LL[A(RW@FJ#d\JSDV?2;7>3\:$ER@@_E,V[LJF'`XN_HZ37?3b?P6(AVDDSI Z_HNB+lUSI]UOCXZ>8:W3+LYIGVN%YRGCA.kWVLA@M[;>7X> I^VR4+AX\^Q;Q#[PTP35?P6(AV^Z<#IPTVY24X(RW][::6[?/H]WU5(@W]]P=!G^VT_44Z&\U_]<84U1-J[QW7&NU_[V?<]/W\PT713\:$ERZ^0/E\PR]66:W3+LYSY9$LSYYT14_-QZRV9?1^<"GPTP2-CZRPS8 I^VR4+AX\^Q:4P Z_US22>S7'@U_]= H_UUX5<[)]V^Z=85Z0.K\PT6)OV^\W!G^VT_76Z&\U_]<84U1-J[QW7&NU_[V<>]/W\PT713\:$ERZ^0/E\PR]5:T$^SY_>6:W3+LYSY9$LSYYT22_-QZRV9?1^<"GPTP2-CZRPS;>V"XQ[Q048Q5)NW][;"JQ[WZ06Y+SX\X;=7X> I^VR4+AX\^Q9:P Z_US22>S7'@U_]= H_UUX62[)]V^Z=;5Z0.K\PT6)OV^\W?6R.T]WU40<]9%BSY_?.F]WS^4>U'_TX\?:;T2,MZRV8'MTXZU=]/W\PT713\:$ERZ^0/E\PR]48T$^SY_>6:W3+LYSY9$LSYYT30_-QZRV9?1^<"GPTP2-CZRPS:8V"XQ[Q048Q5)NW][;"JQ[WZ10Y+SX\X;=7X> I^VR4+AX\^Q88P Z_US22>S7'@U_]= H_UUX70[)]V^Z=;5Z0.K\PT6)OV^\W>8R.T]WU40<]9%BSY_?.F]WS^50U'_TX\?9;T2,MZRV8'MTXZU<8\,V[QW6>2_;#DQ[Q1,D[QQ\;0W%YRZ^149V4*OX\X:%KRZX[2_-QZRV9?1^<"GPTP2-CZRPS=:V"XQ[Q048Q5)NW][;"JQ[WZ62Y+SX\X;=7X> I^VR4+AX\^Q?>P Z_US22>S7'@U_]= H_UUX06[)]V^Z=;5Z0.K\PT6)OV^\W9:R.T]WU40<]9%BSY_?.F]WS^22U'_TX\?9;T2,MZRV8'MTXZU;6\,V[QW6>2_;#DQ[Q1,D[QQ\<>W%YRZ^179V4*OX\X:%KRZX[5:^*PYSY8<0Y=!F_US3*BYS_R>2Q#[PTP36?P6(AV^Z<#IPTVY7Y+SX\X;=7X> I^VR4+AX\^Q>

S7'@U_]= H_UUX14[)]V^Z=;5Z0.K\PT6)OV^\W82_;#DQ[Q1,D[QQ\=!G^VT_0[)]V^Z=;5Z0.K\PT6)OV^\W;>R.T]WU40<]9%BSY_?.F]WS^06U'_TX\?9;T2,MZRV8'MTXZU92\,V[QW6>2_;#DQ[Q1,D[QQ\>:W%YRZ^149V4*OX\X:%KRZX[7_-QZRV9<1^<"GPTP2-CZRPS>W%YRZ^149V4*OX\X:%KRZX[9_-QZRV9<1^<"GPTP2-CZRPS0W%YRZ^e:W3+lRUANUBB1>1f:W3+lRUANUBB1??>g9V4*oSZ@MTEC2>1?d8Q5)n\[CLSD@313S7'`^YEJQFN=37:c=R8&c_^DIPIO>21;`<]9%bX_GH_HL?538a3\:$eY\FG^KM8419n2_;#dZ]IF]JJ97?6o1^<"g[RHE\MK:617o0Y=!fTSKD[LH;97l0Y=!fTSKD[LH;:94m7X> iUPJCZOI4;;5j6[?/hVQMBYNF5892k5Z0.kWVLAXAG69?3h4U1-jPWO@W@D7>90i;T2,mQTNOVCE0?;1f:W3+lRUANUBB1<9>g9V4*oSZ@MTEC2=7?d8Q5)n\[CLSD@329S7'`^YEJQFN=0=b>S7'`^YEJQFN=13:c=R8&c_^DIPIO>05;`<]9%bX_GH_HL?778a3\:$eY\FG^KM8659n2_;#dZ]IF]JJ9536o1^<"g[RHE\MK:4=7l0Y=!fTSKD[LH;;?4m7X> iUPJCZOI4:=5j6[?/hVQMBYNF5932k5Z0.kWVLAXAG6853k4U1-jPWO@W@D7?3h4U1-jPWO@W@D78=0i;T2,mQTNOVCE09?1f:W3+lRUANUBB1:=>g9V4*oSZ@MTEC2;3?d8Q5)n\[CLSD@345S7'`^YEJQFN=65:c=R8&c_^DIPIO>73;`<]9%bX_GH_HL?0=8a3\:$eY\FG^KM81?9m2_;#dZ]IF]JJ929n2_;#dZ]IF]JJ9376o1^<"g[RHE\MK:297l0Y=!fTSKD[LH;=;4m7X> iUPJCZOI4<95j6[?/hVQMBYNF5??2k5Z0.kWVLAXAG6>93h4U1-jPWO@W@D79;0i;T2,mQTNOVCE0891f:W3+lRUANUBB1;7>g9V4*oSZ@MTEC2:9?g8Q5)n\[CLSD@35?d8Q5)n\[CLSD@361S7'`^YEJQFN=41:c=R8&c_^DIPIO>57;c<]9%bX_GH_HL?2;c<]9%bX_GH_HL?3;c<]9%bX_GH_HL?<;c<]9%bX_GH_HL?=;e<]ZOYS[G\ICNF<>STMVXGCN84U^OV\D0<]VG^TO84U^OV\F0<]VG^TI84U^QQHD0<]VYY@O84U^QQHF0<]VYY@I=4VBA:?SOB_V^R\Hm4W@PMMKAXGGFR:6YJA=2=2>QBI5;5:6YJA=0=<>QBI591<384WDC?7;0<_LH7<384WD@?5;0<_LH7>364WD@?7?69>2]NN1=1b:UQMQCXN@XXXn5XRHVF[HICMVKh7Z\FTD]NKACXJ=1S;;Y2Z51=_8P8?7U>V359[4\233Q:R995W0X47?]6^?=1Sd:ZJHLH_%QNI,= > RVVF%6)9)KXODG:;YMQG\0RQPU1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J71:h1TSRVCNL]\[6YXW\:$ER@@_E,V[LJF'\UXXLZ U^LPH12h5P_^ZOJHYXW I^LL[A(RW@FJ#XQ\T@V,QZUSI]IFH?l4_^][HKKXWV0:cp}keX|{kekk}_2f8gmow{je{iRgca3f8gmow{je{iRgca-akmuudgyoTeaoPv0]30Zg+FFDN CAAE0052>eoayyhc}kPimc/gmow{je{iRgca^t2[52Xi%qhSum`_mkpp8EheyeeiczPN`of9fnnxzid|hQfl`9MqhdbzVEmSY|fgfgq[Uiu|z7:7@ow_Rgrq`hdmVFnzhb|=09Vw`YUXDy6x{j;DlbficX\{clkh|POtvsqqYWg{~6jlb|e:QbiujbWFd6^d}fnf9PehvkmVNjxlQKeqvk9465<2Oemobj_RvlvdabWXj`dhfc`vjkk;sz|o0Hlzn_RcnaZGtW]xbkjk}=upva>Bf|hU[czPWhfwl86<\{clkh|PPnpw[Roc|aU:1;:4M`v`lZSia}yT=0?4Cnwmp`tX_`ndR?2Dhqbficc3DkoeQ[yqg\58df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_0?eeiub3]xbkjk}_QmqpZQnl}bT>064M`v`lZSia}yT>0?4Cnwmp`tX_`ndR<2Dhqbficc3DkoeQ[yqg\68df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_3?eeiub3]xbkjk}_QmqpZQnl}bT?064M`v`lZSia}yT?0?4Cnwmp`tX_`ndR=2Dhqbficc3DkoeQ[yqg\78df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_2?eeiub3]xbkjk}_QmqpZQnl}bT8064M`v`lZSia}yT80?4Cnwmp`tX_`ndR:2Dhqbficc3DkoeQ[yqg\08df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_5?eeiub3]xbkjk}_QmqpZQnl}bT9064M`v`lZSia}yT90?4Cnwmp`tX_`ndR;2Dhqbficc3DkoeQ[yqg\18df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_4?eeiub3]xbkjk}_QmqpZQnl}bT:064M`v`lZSia}yT:0?4Cnwmp`tX_`ndR82Dhqbficc3DkoeQ[yqg\28df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_7?eeiub3]xbkjk}_QmqpZQnl}bT;064M`v`lZSia}yT;0?4Cnwmp`tX_`ndR92Dhqbficc3DkoeQ[yqg\38df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_6?eeiub3]xbkjk}_QmqpZQnl}bT4064M`v`lZSia}yT40?4Cnwmp`tX_`ndR62Dhqbficc3DkoeQ[yqg\<8df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_9?eeiub3]xbkjk}_QmqpZQnl}bT5064M`v`lZSia}yT50?4Cnwmp`tX_`ndR72Dhqbficc3DkoeQ[yqg\=8df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_8?eeiub3]xbkjk}_QmqpZQnl}bT==37;LcwgmYRf`~xS<>21:AlqkrbzV]bhyfP11?Gmvgedln0Alzlh^Vzt`Y684hjdmPwhvk[`b`mz1Ntnbzdd]EvjkXLh~jS^z`r`ef[46:nhfxi6Z}ifefvZVhz}U\eizg_03><>Kf|jbTYcg{s^3294=Dg|diQXievk[47:L`yjnakk;LcwgmYSqyoT=<3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV;:1kocsd9Wvla`m{U[czPWhfwlZ75511Fmymg_TljpvY6:4;0Ob{atdp\Slbs`V;91Ig|acnf`>Kf|jbTXt~j_00>fdunkV}bxeQjdfgp?@~dd|nnSK|`m^FbpdYT|fxjkhQ>23>;BmvjqcuW^coxeQ>35>Eh}g~n~RYfduj\51;Cazki`hj4M`v`lZR~xlU:80lnsha\slroWlnli~5Jxbnv``YAzfgTHlzn_RvlvdabW8>6jlb|e:VqmbabzVZd~yQXievk[43:02GjxnfPUokwwZ72581Hcx`{es]TmaroW8?6Hd}nbmgg?HgskaU_u}kP14?aevodW~cdRkkgdq8A}ek}moTJab_EcweZUsg{kliR?:=gcow`=Sz`mliQ_osv\Slbs`V;=155Bauak[Phn|zU::0?4Cnwmp`tX_`ndR?9=Ekpegjbl2GjxnfPTxrf[40:jhyboRyfti]f`bct3Lrh`xjj_GpliZBf|hUXxb|ngd]228`fdzo'oRvkewk`acgjaes6}o}t`l5(fYdg{oTxt~j=3.`[h``W`n6=!mPm`hlvZpbzzcdb0?<,b]nmkiuWoydaa=3.`[gsndmUyi{g|inl>4)eXkfxnS`oeos]uaw;6$jUhckPmhllvZpbz4>'oRm`rd]nmkiuWhf{dlQyes?:3)eXzhgTxt~j=0.`[vtk9?Uu}k22-a\qvcXag|Toae20-a\qvcXzyg6=!mPurg\pwo`Wf1="l_tqf[drdWjf`ec3?,b]vw`Yci}k64)eX}zoTxgh4<2/gZstmV~yej;20-a\qvcX|{cl:0>#c^wpaZruan=64)eX}zoTxgh15?3(fYr{lU~di>5<2/gZstmV~yejjnt`2>5)eX}zoTxghd`vb586+kVxiRz}iffbpd4:8%iTy~kPtskd`drf;4:'oR{|e^vqmbbf|h>6#c^wpaZruannjxl820-a\qvcX|{clhlzn7<2/gZstmV~yejjnt`:>4)eX}zoTxghd`vb=86+kVxiRz}iffbpd7759&hSx}j_upjcagsi8;63<2/gZstmV~yejjnt`3795*dW|ynSy|fgecwe43:8%iThlzn_vkgpm;6$jUomyoPddrwl877:=&hSx}j_fcs95*dW}cfi~znmq]w}uc:8%iTxdcjsucntZqnl}b6??"l_uknavrfeyUoi}zg=431(fYr{lUxxb|ngd]rqdj:9%iTx~k~_u{sa86+kVd~aRz|ep]`jq;7$jUhPcov2[roc|a7: nQ{sds\gkr7W~coxe3>,b]mqhYs{l{Tyo{er?2(fYr{lUoRclnu?3(fYskVghbyQxievk94*dWlrSno_scwaZkhll7; nQjxu]`euYwagUfcik20-a\jpkXmq~Tol~Pphlp9=*dWlrSno_tqf[wc`58&hSc{b_lcwgmYrf`~x1<"l_upjc5Ypam~c1;:#c^vqmb7X`nd0?#c^vqmb4X`nd0?#c^vqmb5X`nd0?#c^vqmb2X`nd0?#c^vqmb3X`nd0?#c^vqmb0X`nd0?#c^vqmb1X`nd0?#c^vqmb>X`nd0?#c^vqmb?X`nd0?#c^vqmb77W~coxe3>,b]wvla69V}bhyf21-a\pwo`9;U|eizg=0.`[qtno89T{dj{h<3/gZruan;?Szgkti?2(fYsz`m:9Ryfduj>5)eXe9U|dj20-a\i4Ysx`n6=!mPm3]wtlb::%iTa>Q{phf>7)eXe=U|dj24-a\i0Ysx`n69!mPm7]wtlb:>%iTa:Q{phf>3)eXe1U|dj28-a\i1^vsma;69%iTa<Tx}gk=06/gZk6=V~{ei3>5-a\i5Ysqyo6=!mPm0]w}uc:8%iTa?Q{yqg>4)eXe:Uu}k20-a\i1Ysqyo64)eXe>Uu}k20-a\i=Ysqyo6Ptxrf95*dWd;:Sywe<2/gZk6:V~r|h3?,b]n56Ysqyo64)eX}zoTan`{1<2/gZstmVghby<20-a\qvcXejd?0>#c^wpaZkdf}>64)eX}zoTan`{9<2/gZstmVghby??=1.`[pubWdiex#c^wpaZkdf};?1="l_tqf[hei|8?6,b]ngkr6;V}bhyf21-a\ifhs9=U|eizg=0.`[hei|8?T{dj{h<3/gZcidzgiRjjshem9cgk{l&v=l5lhhrpgjvbW`fjSYGBERRFGZHDN:;0oegsbmsaZokiV|:S=:Pa-"[mioip)ID^H.Heogqeqiu(89%>45lotlwawY612idyczjr^0e?fuXj{kfSno|c`ff57=d{Vhym`Qlarab``Yt>8;0o~Qmr`o\wlkwdlUx:<64cr]avdkX{`g{`hQ|6^pbig7?i2ixSnhhltv7e>etWjll`xz:c:ap[f``d|~=S6:ap[bgilVyy`R}9_rnjg`Y?9?1hRinne]pviYt>VygenkP9b9`wZaffmrTbi;bq\cdhcpVyy`R}97:ap[iss>01hRczx00;3>etWds>55ls^ov|3203jyTaxv78:ap[hsW820o~Qbuy]1<>etWdsS>64cr]nq}Y3j2ixSkhirvfv6=cldn0iiij_egwafrhzm1lmcjPc`pq}969l2mjbiQlaspz848c3nkehRmnrs{?6;b0:a=`ignTol|}y=6=`>affmUhm|v<4g9jhdYdiyUjhi|heo31?ljfWjk{Snz}l^e1[vwa3`fjSno_rvlvdab02cgmRm`rd;8migXeh~hd0:koeZruijoTnxhiesg8migX|{clS`o{cia8migX|{clob`k119jhdYsz`mhccjPltva?ljfW}xbkjk}c:n`hZuudV{7<3m4lbn\wwjXy5;5o6bll^qqhZw;:7h0axvly^nl858e3dsotQco=3=f>krpjsT`b2=>c9nq}e~Wee7?3l4mtz`}Zjh4=4h7`{wcx]pai:76j1fyumv_rgo848d3dsotQ|em>1:f=j}qirS~kc<2<;?kadj|cgh<<4psmdvdkjikfnSikcax:8wwjXy5;546}}l^s?6;><{{fT}1=18:qqhZw;<720bPq=7=<>uudV{7:364ssn\u919uIJ{>?6:;AB{=33=N3>1=v]n1;;61?40m3;8>ij70;15b46|f0?86<5a94692>">=8028o5rS6c9=03=:>o1=>455lm2;6>8i4b9P3d<>j>0;6<==de:3>60a=91o5;;50;395~Uf933>97<8e;306ab?839=jo1=>4=679U=04=:r9;<4>;t046?6<09jl4<,::>648:;[7f>7}5j38;6p*6518:2<=#>;02:;5+a18:22=#:0<1=6*=948:13=n:oh1<7*=8381bd=i:1;1<65f2g;94?"50;09jl5a29395>=n:o21<7*=8381bd=i:1;1>65f2g594?"50;09jl5a29397>=n:o?1<7*=8381bd=i:1;1865f2g694?"50;09jl5a29391>=n:o91<7*=8381bd=i:1;1:65f2g094?"50;09jl5a29393>=n:o;1<7*=8381bd=i:1;1465f2g294?"50;09jl5a2939=>=n:ll1<7*=8381bd=i:1;1m65f2dg94?"50;09jl5a2939f>=n:ln1<7*=8381bd=i:1;1o65f2da94?"50;09jl5a2939`>=n:lk1<7*=8381bd=i:1;1i65f2d;94?"50;09jl5a2939b>=n:l21<7*=8381bd=i:1;1==54i3g4>5<#:181>ko4n3:2>47<3`8n:7>5$3:1>7`f3g83=7?=;:k1a0<72-83>7h:50;&1<7<5nh1e>5?51598m7c4290/>5<52gc8j7>628?07d52;lj7c<71;35?>o5m80;6)<72;0ee>h5080:;65f2ed94?"50;09jl5a29395==b:9j6ad=83.94?4=f`9m6=7=9j10e?jn:18'6=4=:ok0b?6>:0f8?l4c13:1(?6=:3db?k4?93;n76g=d983>!4?:38mm6`=8082b>=n:m=1<7*=8381bd=i:1;1>=54i3f5>5<#:181>ko4n3:2>77<3`8o87>5$3:1>7`f3g83=7<=;:k1`6<72-83>7i<50;&1<7<5nh1e>5?52598m7b6290/>5<52gc8j7>62;?07d52;lj7c<71;05?>o5ko0;6)<72;0ee>h50809;65f2bg94?"50;09jl5a29396==:3f8?l4d?3:1(?6=:3db?k4?938n76g=c783>!4?:38mm6`=8081b>=n:j?1<7*=8381bd=i:1;1?=54i3a7>5<#:181>ko4n3:2>67<3`8h?7>5$3:1>7`f3g83=7==;:k1g7<72-83>7n?50;&1<7<5nh1e>5?53598m7e7290/>5<52gc8j7>62:?07d52;lj7c<71;15?>o5nl0;6)<72;0ee>h50808;65f2gf94?"50;09jl5a29397==74;h0e2?6=,;296?hn;o0;5?5f32c9io4?:%0;6?4ai2d94<4:2f8?l4di3:1(?6=:3db?k4?939n76g=bg83>!4?:38mm6`=8080b>=,110;6)<72;;4?k4?93:07&79:18'6=4=1>1e>5?51:9(=0<72-83>778;o0;5?4<3"3?6=4+2909=2=i:1;1?65$9283>!4?:33<7c<71;68?.?5290/>5<5969m6=7==21 5=4?:%0;6??03g83=784;*:e>5<#:1815:5a29393>=,0l0;6)<72;;4?k4?93207&6k:18'6=4=1>1e>5?59:9(778;o0;5?g<3"2i6=4+2909=2=i:1;1n65$8`83>!4?:33<7c<71;a8?.>>290/>5<5969m6=7=l21 454?:%0;6??03g83=7k4;*:4>5<#:1815:5a2939b>=,0<0;6)<72;;4?k4?93;;76%74;29 7>520=0b?6>:038?.>4290/>5<5969m6=7=9;10'5<50;&1<7<>?2d94<4>3:9(<4<72-83>778;o0;5?7332!3<7>5$3:1><15<#:1815:5a293953=<#>o1<7*=838:3>h5080:;65$7e83>!4?:33<7c<71;3;?>-0k3:1(?6=:858j7>628307&7i:18'6=4=1>1e>5?51`98/4b<3"3i6=4+2909=2=i:1;1=h54+8c94?"50;02;6`=8082b>=,180;6)<72;;4?k4?938:76%76;29 7>520=0b?6>:308?.1e290/>5<5969m6=7=::10e;:50;9(=<<72-83>778;o0;5?4732h28k4?:083>5}#;9?15><4H86g?M?502e9;k4?::a=1c=83;1<7>t$226>4`a3A3?h6F6299l534=831vn>m8:184>5<7s-9;97<9c:J:0a=O1;20(???:69j654=831b>==50;9j652=831b>=;50;9j650=831b>=950;9l62b=831vn>hm:180>5<7s-9;97<98:J:0a=O1;20(???:060?!4?;33>i6g=0383>>o58:0;66a=7e83>>{e;j21<7<50;2x 6622;<<7E7;d:J:6==#:8:1=45f21094?=h:>n1<75rb2a5>5<4290;w)=?5;05<>N>7`5<>o4;3:17d=;:188m37=831b:94?::kb6?6=3f83:7>5;n0;3?6=3th5}#;9?1>4j4H86g?M?502.9==4<;h12>5<>o4<3:17d8>:188m32=831bm?4?::m1<3<722e94:4?::a37b=8381<7>t$226>7003A3?h6F6299'646=9;1b>=<50;9l62b=831vn9mi:187>5<7s-9;97<99:J:0a=O1;20(???:728 7>420?n7d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118g?l47:3:17d3:17d2<729q/?=;527a8L<2c3A3946*=118215=n:981<75f21194?=n:9>1<75f21794?=n:9<1<75f21594?=h:>n1<75rb537>5<0290;w)=?5;05g>N>a=n:981<75f21194?=n:9>1<75f21794?=n:9<1<75f21594?=h:>n1<75rb534>5<0290;w)=?5;05g>N>a=n:981<75f21194?=n:9>1<75f21794?=n:9<1<75f21594?=h:>n1<75rb53;>5<0290;w)=?5;05g>N>a=n:981<75f21194?=n:9>1<75f21794?=n:9<1<75f21594?=h:>n1<75rb53`>5<0290;w)=?5;05g>N>a=n:981<75f21194?=n:9>1<75f21794?=n:9<1<75f21594?=h:>n1<75rb50;>5<0290;w)=?5;05g>N>4373`8;>7>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;h033?6=3f85;|`750<72>0;6=u+317963e<@0>o7E7=8:&1557>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;h033?6=3f85;|`75<<72>0;6=u+317963e<@0>o7E7=8:&1557>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;h033?6=3f85;|`75d<72>0;6=u+317963e<@0>o7E7=8:&1557>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;h033?6=3f85;|`75a<72>0;6=u+317963e<@0>o7E7=8:&1557>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;h033?6=3f85;|`76<<72>0;6=u+317963e<@0>o7E7=8:&155<6=91b>=<50;9j655=831b>=:50;9j653=831b>=850;9j651=831d>:j50;9~f17e290<6=4?{%131?41k2B28i5G93:8 7772m1b>=<50;9j655=831b>=:50;9j653=831b>=850;9j651=831d>:j50;9~f17b290<6=4?{%131?41k2B28i5G93:8 7772m1b>=<50;9j655=831b>=:50;9j653=831b>=850;9j651=831d>:j50;9~f17a290<6=4?{%131?41k2B28i5G93:8 7772m1b>=<50;9j655=831b>=:50;9j653=831b>=850;9j651=831d>:j50;9~f147290<6=4?{%131?41k2B28i5G93:8 7772m1b>=<50;9j655=831b>=:50;9j653=831b>=850;9j651=831d>:j50;9~f177290<6=4?{%131?41k2B28i5G93:8 77728?;7do58;0;66g=0283>>o51=0;66a=7e83>>{e<981<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f166290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl0<729q/?=;51448L<2c3A3946*=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi?kk50;794?6|,::>6<;9;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=n:131<75`29494?=zj:lo6=4::183!57=3;>:6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188m7>>2900c?69:188yg5ak3:197>50z&040<6=?1C59j4H80;?!468380e8h50;9j24<722cj>7>5;h0;=?6=3f83:7>5;|`470<72=0;6=u+3179503<@0>o7E7=8:&155<53`?m6=44i`094?=n:131<75`29494?=zj>9;6=4;:183!57=3;>96F64e9K=7><,;;;6?5f5g83>>of:3:17d<79;29?j4?>3:17pl83383>1<729q/?=;51478L<2c3A3946*=1181?l3a2900el<50;9j6=?=831d>5850;9~f250290?6=4?{%131?72=2B28i5G93:8 7772;1b9k4?::kb6?6=3`8357>5;n0;2?6=3th<>h4?:583>5}#;9?1=8;4H86g?M?502.9==4=;h7e>5<5<3290;w)=?5;363>N>44>o51=0;66a=8783>>{e?;i1<7:50;2x 66228?>7E7;d:J:6==#:8:1>6g:f;29?lg52900e?66:188k7>12900qo=8c;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;>k1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?:850;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg50:3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm36294?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a73e=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=9a;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;?21<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?;:50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg51:3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm37294?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<o7>57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a70g=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=:8;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;<<1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?8<50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg5283:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm35g94?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a71g=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=;6;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;=>1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?9>50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg54m3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm32a94?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a76>=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=<6;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;:>1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi??k50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg55k3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm33c94?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a770=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo==4;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;;81<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg56i3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm30:94?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a742=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=>2;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;8:1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?=m50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg57i3:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm31:94?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a7=4=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=70;293?6=8r.8<84=9c9K=1b<@0837)<>0;18m67=831b??4?::k07?6=3`9?6=44i7694?=ni;0;66a=8783>>{e;>o1<7950;2x 6622;3i7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c=87>5;hc1>5<>o4;3:17d=;:188m32=831bm?4?::m1<3<722wi?8k50;594?6|,::>6?7m;I;7`>N>:11/><>53:k05?6=3`996=44i2194?=n;=0;66g94;29?lg52900c?69:188yg5303:1;7>50z&040<51k1C59j4H80;?!468390e>?50;9j77<722c8?7>5;h17>5<1<75fa383>>i50?0;66sm32094?1=83:p(>>::3;a?M?3l2B2>55+20297>o493:17d==:188m65=831b?94?::k50?6=3`k96=44o3:5>5<57;294~"48<095o5G95f8L<4?3-8:<7=4i2394?=n;;0;66g<3;29?l532900e;:50;9je7<722e94;4?::a750=83=1<7>t$226>7?e3A3?h6F6299'646=;2c8=7>5;h11>5<>o1<3:17do=:188k7>12900qo=8d;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?:l50;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;>=1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg50;3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm37f94?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=9b;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?;750;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;??1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg51;3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm34`94?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=:9;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?8950;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<97>53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;<91<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg5293:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm35`94?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=;7;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?9;50;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;=;1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg54n3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm32;94?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=<7;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?>;50;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;;l1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg55l3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm33594?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo==5;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi??=50;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;8l1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg56j3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm30794?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=>3;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;9n1<7=50;2x 66228>m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg57j3:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm39194?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo=71;297?6=8r.8<84>4g9K=1b<@0837)<>0;08m0`=831bm?4?::m1<3<722wi?:h50;194?6|,::>6<:i;I;7`>N>:11/><>52:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7<4i4d94?=ni;0;66a=8783>>{e;m7E7;d:J:6==#:8:1>6g:f;29?lg52900c?69:188yg5313:1?7>50z&040<6t$226>42a3A3?h6F6299'646=:2c>j7>5;hc1>5<>i50?0;66sm31594?5=83:p(>>::06e?M?3l2B2>55+20296>o2n3:17do=:188k7>12900qo9md;29=ci7?t168~ <4>2::;7d?6e;29 7>5283o7c<71;28?l7>k3:1(?6=:0;g?k4?93;07d?6a;29 7>5283o7c<71;08?l7>13:1(?6=:0;g?k4?93907d?68;29 7>5283o7c<71;68?l7>?3:1(?6=:0;g?k4?93?07d?66;29 7>5283o7c<71;48?l7>=3:1(?6=:0;g?k4?93=07d?64;29 7>5283o7c<71;:8?l7>;3:1(?6=:0;g?k4?93307d?62;29 7>5283o7c<71;c8?l7>93:1(?6=:0;g?k4?93h07d?7f;29 7>5283o7c<71;a8?l7?m3:1(?6=:0;g?k4?93n07d?7d;29 7>5283o7c<71;g8?l7?k3:1(?6=:0;g?k4?93l07d?7b;29 7>5283o7c<71;33?>o60h0;6)<72;3:`>h5080:=65f19;94?"50;0:5i5a293957=l2d94<4>5:9j5=2=83.94?4>9e9m6=7=9?10e<6<:18'6=4=90n0b?6>:058?l7?:3:1(?6=:0;g?k4?93;376g>8083>!4?:3;2h6`=8082=>=n91:1<7*=8382=a=i:1;1=l54i05e>5<#:181=4j4n3:2>4d<3`;5$3:1>4?c3g83=7?l;:k23a<72-83>7?6d:l1<4<6l21b=:m50;&1<7<61m1e>5?51d98m41e290/>5<518f8j7>628l07d?89;29 7>5283o7c<71;03?>o6?10;6)<72;3:`>h50809=65f16594?"50;0:5i5a293967=l2d94<4=5:9j525=83.94?4>9e9m6=7=:?10e<9=:18'6=4=90n0b?6>:358?l7093:1(?6=:0;g?k4?938376g>7183>!4?:3;2h6`=8081=>=n9?o1<7*=8382=a=i:1;1>l54i04g>5<#:181=4j4n3:2>7d<3`;=o7>5$3:1>4?c3g83=77?6d:l1<4<5l21b=;o50;&1<7<61m1e>5?52d98m40>290/>5<518f8j7>62;l07d?98;29 7>5283o7c<71;13?>o6>>0;6)<72;3:`>h50808=65f17494?"50;0:5i5a293977=6=4+29095=4;h3ef?6=,;296<7k;o0;5?5332c:jl4?:%0;6?7>l2d94<4<5:9j5c?=83.94?4>9e9m6=7=;?10e:258?l7a?3:1(?6=:0;g?k4?939376g>f783>!4?:3;2h6`=8080=>=n9o?1<7*=8382=a=i:1;1?l54i0d7>5<#:181=4j4n3:2>6d<3`;m?7>5$3:1>4?c3g83=7=l;:k2b7<72-83>7?6d:l1<4<4l21b=k>50;&1<7<61m1e>5?53d98m4ca290/>5<518f8j7>62:l07d?je;29 7>5283o7c<71;63?>o6mm0;6)<72;3:`>h5080?=65f1da94?"50;0:5i5a293907=l2d94<4;5:9j5`>=83.94?4>9e9m6=7=:558?l7b=3:1(?6=:0;g?k4?93>376g>e583>!4?:3;2h6`=8087=>=n9l91<7*=8382=a=i:1;18l54i0g1>5<#:181=4j4n3:2>1d<3`;n=7>5$3:1>4?c3g83=7:l;:k2a5<72-83>7?6d:l1<4<3l21b=ih50;&1<7<61m1e>5?54d98m4bb290/>5<518f8j7>62=l07d?kd;29 7>5283o7c<71;73?>o6lj0;6)<72;3:`>h5080>=65f1ec94?"50;0:5i5a293917=l2d94<4:5:9j5a0=83.94?4>9e9m6=7==?10e:458?l7c<3:1(?6=:0;g?k4?93?376g>d283>!4?:3;2h6`=8086=>=n9m81<7*=8382=a=i:1;19l54i0f2>5<#:181=4j4n3:2>0d<3`;hj7>5$3:1>4?c3g83=7;l;:k2g`<72-83>7?6d:l1<4<2l21b=nj50;&1<7<61m1e>5?55d98m4ed290/>5<518f8j7>625283o7c<71;43?>o6kh0;6)<72;3:`>h5080==65f1b;94?"50;0:5i5a293927=l2d94<495:9j5f2=83.94?4>9e9m6=7=>?10e:758?l7d:3:1(?6=:0;g?k4?93<376g>c083>!4?:3;2h6`=8085=>=n9j:1<7*=8382=a=i:1;1:l54i0`e>5<#:181=4j4n3:2>3d<3`;ii7>5$3:1>4?c3g83=78l;:k2fa<72-83>7?6d:l1<4<1l21b=om50;&1<7<61m1e>5?56d98m4de290/>5<518f8j7>62?l07d?m9;29 7>5283o7c<71;53?>o6j10;6)<72;3:`>h5080<=65f1c594?"50;0:5i5a293937=l2d94<485:9j5g5=83.94?4>9e9m6=7=??10e:658?l7e93:1(?6=:0;g?k4?93=376g>b183>!4?:3;2h6`=8084=>=n9ho1<7*=8382=a=i:1;1;l54i0cg>5<#:181=4j4n3:2>2d<3`;jo7>5$3:1>4?c3g83=79l;:k2eg<72-83>7?6d:l1<4<0l21b=lo50;&1<7<61m1e>5?57d98m4g>290/>5<518f8j7>62>l07d?n8;29 7>5283o7c<71;:3?>o6i>0;6)<72;3:`>h50803=65f1`494?"50;0:5i5a2939<7=6=4+29095332c:m?4?:%0;6?7>l2d94<475:9j5d7=83.94?4>9e9m6=7=0?10e:958?l7>n3:1(?6=:0;g?k4?932376g>9c83>!4?:3;2h6`=808;=>=n90:1<7*=8382=a=i:1;14l54i0:6>5<#:181=4j4n3:2>=d<3`;5$3:1>4?c3g83=76l;:k22c<72-83>7?6d:l1<45?58d98m4`6290/>5<518f8j7>621l07d?j6;29 7>5283o7c<71;;3?>o6lk0;6)<72;3:`>h50802=65f1e294?"50;0:5i5a2939=7=6=4+29095l2d94<465:9j5d2=83.94?4>9e9m6=7=1?10e<8;:18'6=4=90n0b?6>:858?l1?2900e?6k:188m7d32900e?l<:188m7d22900c?l9:188k4`b2900n?;7:182f?g=:=qC5?64$226><1d3S?n68;'656=:?n0e?o6:18'6=4=:h20b?6>:198m7g0290/>5<52`:8j7>62810e?o9:18'6=4=:h20b?6>:398m7g2290/>5<52`:8j7>62:10e?o;:18'6=4=:h20b?6>:598m7g4290/>5<52`:8j7>62<10e?o=:18'6=4=:h20b?6>:798m7g6290/>5<52`:8j7>62>10e?o?:18'6=4=:h20b?6>:998m7d5290/>5<52`:8j7>62010e?l>:18'6=4=:h20b?6>:`98m7d7290/>5<52`:8j7>62k10e?oi:18'6=4=:h20b?6>:b98m7gb290/>5<52`:8j7>62m10e?ok:18'6=4=:h20b?6>:d98m7gd290/>5<52`:8j7>62o10e?om:18'6=4=:h20b?6>:028?l4fi3:1(?6=:3c;?k4?93;:76g=9g83>!4?:38j46`=80826>=n?10;66g=8e83>>o6>:0;66g=b583>>o5j:0;66g=b483>>i5j?0;66a>fd83>>d>i5?o0;66sm95g94?7=83:p(>>::0de?M?3l2B2>55`17094?=zj09:6=46:183!57=382h6F64e9K=7><,;2n64:=;%024?5>o4;3:17d=;:188m37=831b:94?::kb6?6=3f83:7>5;n0;3?6=3th2?=4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7>b20>97)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj08m6=4n:183!57=382i6F64e9K=7><;1/><>54:k50?6=3`k96=44i7394?=h:1<1<75`29:94?=n;k0;6)<72;1b?k4?93:07d=6:18'6=4=;h1e>5?51:9j7=<72-83>7=n;o0;5?4<3`9<6=4+29097d=i:1;1?65f3783>!4?:39j7c<71;68?xd>:l0;6l4?:1y'753=:0o0D4:k;I;1<>\2m3;p>l4r$3:f><253-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f<4c290?6=4?{%131?41m2B28i5G93:8 7>b20>97d8<:188md1=831b>4:50;9l635=831vn45<7s-9;97<9e:J:0a=O1;20(?6j:861?l042900el950;9j6<2=831d>;=50;9~f<4e290?6=4?{%131?41m2B28i5G93:8 7>b20>97d8<:188md1=831b>4:50;9l635=831vn45<7s-9;97<9e:J:0a=O1;20(?6j:861?l042900el950;9j6<2=831d>;=50;9~w7g22909wSl850;0xZ7g13438=7==;|q1e2<72;qU>l94=812>6552z\1e<=:1:;1?95rs3c7>5<5sW8j86363180f>{t:h91<77}Y:h8014=?:2:8yv4f93:1>vP=a09>=66=;>1v?o?:181[4f8272?=4<6:p6g4=838pR?l=;<;1b?5e3ty9n<4?:3y]6g7<508m6>74}r0a4?6=:rT9n=5293d97==z{;km6=4={_0bb>;>:o08;6s|2`g94?4|V;kn707=f;15?xu5im0;6?uQ2`f89<4b2:h0q~lo50;0xZ7gf3439i7=8;|q1=c<72;qU>4h4=80f>6055z\1f1=:1:;1:952922921=:1;l1:95293g921=z{;h86=4:{_0a7>;>;80==63631855>;>:o0==6362d855>{t:k?1<77}:1:;1>584=80g>7?33ty2mi4?:3y>=67=:1=014=?:`08yv?e=3:1>v363181<3=:1;i1>4:4}r;bg?6=:r72?=4=899>=7`=i;1v4l;:1818?5n383:6362c81=1=z{0ki6=4={<;1b?4?0272>h4n2:p=g5=838p14{t9oo1<77043ty2mk4?:3y>=7e=>:165?l52718yv?fm3:1>v362c857>;>:h09:>5rs040>5<5s43?j7<8f:?:6d<1;2wx>::50;7x9<2b28<9707=d;c4?8?5k3k<707=b;c4?8?5i3k<7psm24;94?7e20098vF6299'753=1>n0V8k51z3;>x"58909:i5f2`;94?"50;09m55a29394>=n:h=1<7*=8381e==i:1;1=65f2`494?"50;09m55a29396>=n:h?1<7*=8381e==i:1;1?65f2`694?"50;09m55a29390>=n:h91<7*=8381e==i:1;1965f2`094?"50;09m55a29392>=n:h;1<7*=8381e==i:1;1;65f2`294?"50;09m55a2939<>=n:k81<7*=8381e==i:1;1565f2c394?"50;09m55a2939e>=n:k:1<7*=8381e==i:1;1n65f2`d94?"50;09m55a2939g>=n:ho1<7*=8381e==i:1;1h65f2`f94?"50;09m55a2939a>=n:hi1<7*=8381e==i:1;1j65f2``94?"50;09m55a293955=5;h0;`?6=3`;=?7>5;h0a0?6=3`8i?7>5;h0a1?6=3f8i:7>5;n3ea?6=3k3?i7>51;294~"48<0:jk5G95f8L<4?3f;=>7>5;|`:6d<72=0;6=u+317963c<@0>o7E7=8:&1<`<><:1b:>4?::kb3?6=3`8287>5;n057?6=3th2?<4?:883>5}#;9?1>4j4H86g?M?502.94h46429'646=;2c8=7>5;h11>5<>o193:17d8;:188md4=831d>5850;9l6=1=831vn4=?:18b>5<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"50l028>5+20290>o1<3:17do=:188m37=831d>5850;9l6=>=831b?o4?:%0;6?5f3g83=7>4;h1:>5<#:181?l5a29395>=n;10;6)<72;1b?k4?93807d=8:18'6=4=;h1e>5?53:9j73<72-83>7=n;o0;5?2<3th2>k4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7>b20>87)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj08n6=4n:183!57=382i6F64e9K=7><:1/><>54:k50?6=3`k96=44i7394?=h:1<1<75`29:94?=n;k0;6)<72;1b?k4?93:07d=6:18'6=4=;h1e>5?51:9j7=<72-83>7=n;o0;5?4<3`9<6=4+29097d=i:1;1?65f3783>!4?:39j7c<71;68?xd>:k0;694?:1y'753=:?o0D4:k;I;1<>"50l028>5f6283>>of?3:17d<64;29?j41;3:17pl62e83>1<729q/?=;527g8L<2c3A3946*=8d8:06=n>:0;66gn7;29?l4><3:17b<93;29?xd>:j0;694?:1y'753=:?o0D4:k;I;1<>"50l028>5f6283>>of?3:17d<64;29?j41;3:17p}=a483>7}Y:h?014=>:238yv4f>3:1>vP=a79>=67=;;1v?o8:181[4f?272?<4<3:p6d?=838pR?o6;<;05?533ty9m94?:3y]6d2<509;6>l4}r0b7?6=:rT9m>5292297<=z{;k96=4={_0b6>;>;90846s|2`394?4|V;k:707<0;14?xu5i90;6?uQ2`289<572:<0q~o>50;0xZ7d73439j7=7;|q1ec<72;qU>lh4=80e>6152z\1e`=:1;l1?;5rs3cg>5<5sW8jh6362d80f>{t:hi1<77}Y:hh014vP=a`9>=7c=;>1v?7i:181[4>n272>h4<6:p535=838pR<8<;<;1e?043ty9n94?:4y]6g2<509:6;:4=813>32<508m6;:4=80f>3255z\1f6=:1:;1:<52922924=:1;l1:<5293g924=z{;h>6=4={_0a1>;>;80j>6s|9`g94?4|508j6?8<;<;1f?043ty2n;4?:3y>=67=:1<014im0;6?u292396=1<509;6l<4}r;a1?6=:r72?=4=879>=7e=:0>0q~7nc;296~;>;909455293d9e7=z{0h?6=4={<;1b?4?>272>o4=959~w;>:l0j>6s|9c194?4|508j6?7;;<;1a?4?>2wx>o850;0xZ7d13439i7<78:p=d`=838p14fd83>7}Y9oo014j90;6?u293f926=:1;i1>;=4}r040?6==r728h4>639>=7g=i>165?l5a69>=7b=i>165?m5a69~yg42i3:1=o46:36xL<4?3-9;9778e:X6a?7|910v(?>?:34g?l4f13:1(?6=:3c;?k4?93:07d52;k37c<71;38?l4f>3:1(?6=:3c;?k4?93807d52;k37c<71;18?l4f<3:1(?6=:3c;?k4?93>07d52;k37c<71;78?l4f:3:1(?6=:3c;?k4?93<07d52;k37c<71;58?l4f83:1(?6=:3c;?k4?93207d52;k37c<71;;8?l4e93:1(?6=:3c;?k4?93k07d52;k37c<71;`8?l4fn3:1(?6=:3c;?k4?93i07d52;k37c<71;f8?l4fl3:1(?6=:3c;?k4?93o07d52;k37c<71;d8?l4fj3:1(?6=:3c;?k4?93;;76g=a`83>!4?:38j46`=80825>=n:0l1<7*=8381e==i:1;1=?54i6:94?=n:1n1<75f17194?=n:k>1<75f2c194?=n:k?1<75`2c494?=h9oo1<75m95g94?7=83:p(>>::0de?M?3l2B2>55`17094?=zj08j6=4;:183!57=38=i6F64e9K=7><,;2n64:;;h40>5<5<>290;w)=?5;0:`>N><233-8:<7=4i2394?=n;;0;66g<3;29?l532900e;?50;9j21<722cj>7>5;n0;2?6=3f83;7>5;|`:75<72h0;6=u+31796o7E7=8:X6a?7|:h0v(?6j:867?!4683>0e;:50;9je7<722c==7>5;n0;2?6=3f8347>5;h1a>5<#:181?l5a29394>=n;00;6)<72;1b?k4?93;07d=7:18'6=4=;h1e>5?52:9j72<72-83>7=n;o0;5?5<3`9=6=4+29097d=i:1;1865rb80e>5N>5;hc1>5<!4?:39j7c<71;28?l5>290/>5<53`9m6=7=921b?54?:%0;6?5f3g83=7<4;h14>5<#:181?l5a29397>=n;?0;6)<72;1b?k4?93>07pl62d83>d<729q/?=;528g8L<2c3A3946T:e;3x6d1<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn45<7s-9;97<9e:J:0a=O1;20(?6j:867?l042900el950;9j6<2=831d>;=50;9~f<4c290?6=4?{%131?41m2B28i5G93:8 7>b20>?7d8<:188md1=831b>4:50;9l635=831vn45<7s-9;97<9e:J:0a=O1;20(?6j:867?l042900el950;9j6<2=831d>;=50;9~w7g22909wSl850;0xZ7g13438=7==;|q1e2<72;qU>l94=812>6552z\1e<=:1:;1?95rs3c7>5<5sW8j86363180f>{t:h91<77}Y:h8014=?:2:8yv4f93:1>vP=a09>=66=;>1v?o?:181[4f8272?=4<6:p6g4=838pR?l=;<;1b?5e3ty9n<4?:3y]6g7<508m6>74}r0a4?6=:rT9n=5293d97==z{;km6=4={_0bb>;>:o08;6s|2`g94?4|V;kn707=f;15?xu5im0;6?uQ2`f89<4b2:h0q~lo50;0xZ7gf3439i7=8;|q1=c<72;qU>4h4=80f>6052z\226=:1;k1:>5rs3`7>5<2sW8i863630850>;>;90=86362g850>;>:l0=86s|2c194?3|V;h8707<1;42?8?483<:707=f;42?8?5m3<:7p}=b483>7}Y:k?014=>:`08yv?fm3:1>v362`8126=:1;h1:>5rs8`5>5<5s438=7<76:?:6a<51=1v4ok:1818?49383;636318b6>{t1k?1<77>13439o7<64:p=de=838p14=?:3:;?8?5n3k97p}6b583>7}:1;l1>584=80a>7?33ty2mo4?:3y>=7`=:12014v362`81=1=:1;o1>584}r0a2?6=:rT9n;5293g96=>52z?:6g<5>:165?m5629~w4`b2909wS?ie:?:6a<5>:1v4l?:1818?5l3<8707=c;057>{t:>>1<7;t=86f>4053439m7o8;<;1f?g03439h7o8;<;1g?g03twi>8l50;3a><<555+3179=2`m1b>l750;&1<7<5i11e>5?50:9j6d1=83.94?4=a99m6=7=921b>l850;&1<7<5i11e>5?52:9j6d3=83.94?4=a99m6=7=;21b>l:50;&1<7<5i11e>5?54:9j6d5=83.94?4=a99m6=7==21b>l<50;&1<7<5i11e>5?56:9j6d7=83.94?4=a99m6=7=?21b>l>50;&1<7<5i11e>5?58:9j6g4=83.94?4=a99m6=7=121b>o?50;&1<7<5i11e>5?5a:9j6g6=83.94?4=a99m6=7=j21b>lh50;&1<7<5i11e>5?5c:9j6dc=83.94?4=a99m6=7=l21b>lj50;&1<7<5i11e>5?5e:9j6de=83.94?4=a99m6=7=n21b>ll50;&1<7<5i11e>5?51198m7gf290/>5<52`:8j7>628;07d<6f;29 7>52;k37c<71;31?>o003:17d<7d;29?l71;3:17d3:17b?ie;29?g?3m3:1=7>50z&040<6no1C59j4H80;?j71:3:17pl62`83>1<729q/?=;527g8L<2c3A3946*=8d8:00=n>:0;66gn7;29?l4><3:17b<93;29?xd>;80;644?:1y'753=:0n0D4:k;I;1<>"50l02885+20297>o493:17d==:188m65=831b?94?::k55?6=3`<<1/><>54:k50?6=3`k96=44i7394?=h:1<1<75`29:94?=n;k0;6)<72;1b?k4?93:07d=6:18'6=4=;h1e>5?51:9j7=<72-83>7=n;o0;5?4<3`9<6=4+29097d=i:1;1?65f3783>!4?:39j7c<71;68?xd>:o0;6l4?:1y'753=:0o0D4:k;I;1<>\2m3;p>l4r$3:f><223-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f<4b290j6=4?{%131?4>m2B28i5G93:8^0c=9r8j6p*=8d8:00=#:8:186g94;29?lg52900e;?50;9l6=0=831d>5650;9j7g<72-83>7=n;o0;5?6<3`926=4+29097d=i:1;1=65f3983>!4?:39j7c<71;08?l50290/>5<53`9m6=7=;21b?;4?:%0;6?5f3g83=7:4;|`:6g<72=0;6=u+317963c<@0>o7E7=8:&1<`<><<1b:>4?::kb3?6=3`8287>5;n057?6=3th2>i4?:583>5}#;9?1>;k4H86g?M?502.94h46449j26<722cj;7>5;h0:0?6=3f8=?7>5;|`:6f<72=0;6=u+317963c<@0>o7E7=8:&1<`<><<1b:>4?::kb3?6=3`8287>5;n057?6=3ty9m84?:3y]6d3<509:6>?4}r0b2?6=:rT9m;52923977=z{;k<6=4={_0b3>;>;808?6s|2`;94?4|V;k2707<1;17?xu5i=0;6?uQ2`689<572:h0q~>5389~w7g52909wSl?50;0xZ7g63438<7=8;|q1e5<72;qU>l>4=813>607>52z\1f7=:1;l1?o5rs3`2>5<5sW8i=6362g80=>{t:k:1<77}Y:hl014vP=ad9>=7`=;?1v?ok:181[4fl272>h43ty9mo4?:3y]6dd<508n6>64}r0be?6=:rT9ml5293g972=z{;3m6=4={_0:b>;>:l08:6s|17194?4|V8<8707=a;40?xu5j=0;68uQ2c689<562?>014=?:7689<4a2?>014=67=>8165>>5609>=7`=>8165?k5609~w7d22909wSj?0;6?u292396=0<508o6?7;;|q:ea<72;q65>?529589<572h80q~7m5;296~;>;9094;5293a96<252z?:75<501165?h5a39~w;>:k09595rs8ca>5<5s439j7<78:?:6`{t:k<1<7=7e=:?90q~<84;291~;>5$3:1>7g?3g83=7?4;h0b2?6=,;296?o7;o0;5?4<3`8j97>5$3:1>7g?3g83=7=4;h0b0?6=,;296?o7;o0;5?2<3`8j?7>5$3:1>7g?3g83=7;4;h0b6?6=,;296?o7;o0;5?0<3`8j=7>5$3:1>7g?3g83=794;h0b4?6=,;296?o7;o0;5?><3`8i>7>5$3:1>7g?3g83=774;h0a5?6=,;296?o7;o0;5?g<3`8i<7>5$3:1>7g?3g83=7l4;h0bb?6=,;296?o7;o0;5?e<3`8ji7>5$3:1>7g?3g83=7j4;h0b`?6=,;296?o7;o0;5?c<3`8jo7>5$3:1>7g?3g83=7h4;h0bf?6=,;296?o7;o0;5?7732c9ml4?:%0;6?4f02d94<4>1:9j6<`=83.94?4=a99m6=7=9;10e:650;9j6=b=831b=;=50;9j6g2=831b>o=50;9j6g3=831d>o850;9l5cc=831i59k50;394?6|,::>6N>:11d=;<50;9~f<4f290?6=4?{%131?41m2B28i5G93:8 7>b20>=7d8<:188md1=831b>4:50;9l635=831vn4=>:18:>5<7s-9;97<6d:J:0a=O1;20(?6j:865?!468390e>?50;9j77<722c8?7>5;h17>5<>of:3:17b<76;29?j4??3:17pl63183>d<729q/?=;528g8L<2c3A3946T:e;3x6d1<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn45<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"50l028;5+20290>o1<3:17do=:188m37=831d>5850;9l6=>=831b?o4?:%0;6?5f3g83=7>4;h1:>5<#:181?l5a29395>=n;10;6)<72;1b?k4?93807d=8:18'6=4=;h1e>5?53:9j73<72-83>7=n;o0;5?2<3th2>h4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7>b20>=7)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj08i6=4;:183!57=38=i6F64e9K=7><,;2n64:9;h40>5<5<3290;w)=?5;05a>N><213`<86=44i`594?=n:0>1<75`27194?=zj08h6=4;:183!57=38=i6F64e9K=7><,;2n64:9;h40>5<5<5sW8j963630805>{t:h<1<77}Y:h=014=>:218yv4f13:1>vP=a89>=67=;=1v?o;:181[4f<272?=43ty9m?4?:3y]6d4<509;6>64}r0b5?6=:rT9m<52922972=z{;k;6=4={_0b4>;>;908:6s|2c094?4|V;h9707=f;1a?xu5j80;6?uQ2c389<4a2:30q~lk50;0xZ7gb3439j7=9;|q1ea<72;qU>lj4=80f>6d52z\1ef=:1;o1?45rs3ca>5<5sW8jn6362d80<>{t:hk1<77}Y:0l014vP>629>=7g=>:1v?l;:186[4e<272?<494:?:75<1<272>k494:?:6`<1<2wx>o=50;7xZ7d43438=78>;<;04?063439j78>;<;1a?063ty9n84?:3y]6g3<509:6l<4}r;ba?6=:r72>l4=629>=7d=>:1v4l9:1818?49383:6362e81=1=z{0ko6=4={<;05?4??272?=4n2:p=g3=838p14=?:3:5?8?5k38286s|9`a94?4|509;6?67;<;1b?g53ty2n94?:3y>=7`=:1<014ik0;6?u293d96=><508n6l<4}r;a7?6=:r72>l4=959>=7c=:1<0q~v362c8126=:1;i1:>5rs0df>5<5sW;mi6362e8126=z{0h;6=4={<;1`?043439o7<93:p622=83?p14:j:041?8?5i3k<707=b;c4?8?5l3k<707=c;c4?x{e::11/?=;59938^0c=9r;36p*=01812a=n:h31<7*=8381e==i:1;1<65f2`594?"50;09m55a29395>=n:h<1<7*=8381e==i:1;1>65f2`794?"50;09m55a29397>=n:h>1<7*=8381e==i:1;1865f2`194?"50;09m55a29391>=n:h81<7*=8381e==i:1;1:65f2`394?"50;09m55a29393>=n:h:1<7*=8381e==i:1;1465f2c094?"50;09m55a2939=>=n:k;1<7*=8381e==i:1;1m65f2c294?"50;09m55a2939f>=n:hl1<7*=8381e==i:1;1o65f2`g94?"50;09m55a2939`>=n:hn1<7*=8381e==i:1;1i65f2`a94?"50;09m55a2939b>=n:hh1<7*=8381e==i:1;1==54i3cb>5<#:181>l64n3:2>47<3`82j7>5$3:1>7g?3g83=7?=;:k45;h357?6=3`8i87>5;h0a7?6=3`8i97>5;n0a2?6=3f;mi7>5;c;7a?6=93:1l4?:583>5}#;9?1>;k4H86g?M?502.94h46469j26<722cj;7>5;h0:0?6=3f8=?7>5;|`:74<7200;6=u+31796o7E7=8:&1<`<><>1/><>53:k05?6=3`996=44i2194?=n;=0;66g91;29?l032900el<50;9l6=0=831d>5950;9~f<57290j6=4?{%131?4>m2B28i5G93:8^0c=9r8j6p*=8d8:02=#:8:186g94;29?lg52900e;?50;9l6=0=831d>5650;9j7g<72-83>7=n;o0;5?6<3`926=4+29097d=i:1;1=65f3983>!4?:39j7c<71;08?l50290/>5<53`9m6=7=;21b?;4?:%0;6?5f3g83=7:4;|`:6c<72h0;6=u+31796o7E7=8:X6a?7|:h0v(?6j:864?!4683>0e;:50;9je7<722c==7>5;n0;2?6=3f8347>5;h1a>5<#:181?l5a29394>=n;00;6)<72;1b?k4?93;07d=7:18'6=4=;h1e>5?52:9j72<72-83>7=n;o0;5?5<3`9=6=4+29097d=i:1;1865rb80f>5N>5;hc1>5<!4?:39j7c<71;28?l5>290/>5<53`9m6=7=921b?54?:%0;6?5f3g83=7<4;h14>5<#:181?l5a29397>=n;?0;6)<72;1b?k4?93>07pl62c83>1<729q/?=;527g8L<2c3A3946*=8d8:02=n>:0;66gn7;29?l4><3:17b<93;29?xd>:m0;694?:1y'753=:?o0D4:k;I;1<>"50l028:5f6283>>of?3:17d<64;29?j41;3:17pl62b83>1<729q/?=;527g8L<2c3A3946*=8d8:02=n>:0;66gn7;29?l4><3:17b<93;29?xu5i<0;6?uQ2`789<562:;0q~?5339~w7g02909wSl750;0xZ7g>3438=7=;;|q1e1<72;qU>l:4=813>6d52z\1e6=:1::1?45rs3c1>5<5sW8j>6363180<>{t:h;1<77}Y:h:014=?:248yv4e:3:1>vP=b39>=7`=;k1v?l>:181[4e9272>k4<9:p6g6=838pR?l?;<;1b?5?3ty9mk4?:3y]6d`<508m6>94}r0ba?6=:rT9mh5293d973=z{;ko6=4={_0b`>;>:l08n6s|2`a94?4|V;kh707=e;1:?xu5ik0;6?uQ2``89<4b2:20q~2wx=;=50;0xZ4043439m78<;|q1f1<72o:4=812>32<509;6;:4=80e>32<508n6;:4}r0a7?6==rT9n>52923924=:1::1:<5293d924=:1;o1:<5rs3`6>5<5sW8i9636308b6>{t1ho1<77043439n78<;|q:f3<72;q65>?529489<4c2;3?7p}6ae83>7}:1:;1>594=813>d452z?:75<50?165?m52868yv?fk3:1>v363181<==:1;l1m?5rs8`7>5<5s439j7<76:?:6g<51=1v4om:1818?5n38346362d8b6>{t1k91<77?33439i7<76:p6g0=838pR?l9;<;1a?4?02wx5lh50;0x9<4e2;<8707=c;40?xu6nl0;6?uQ1gg89<4c2;<87p}6b183>7}:1;n1:>5293a963555z?:0`<6>;165?o5a69>=7d=i>165?j5a69>=7e=i>1vqo<:e;295g<>2;>pD4<7;%131???:2P>i7?t198~ 7672;52;k37c<71;28?l4f?3:1(?6=:3c;?k4?93;07d52;k37c<71;08?l4f=3:1(?6=:3c;?k4?93907d52;k37c<71;68?l4f;3:1(?6=:3c;?k4?93?07d52;k37c<71;48?l4f93:1(?6=:3c;?k4?93=07d52;k37c<71;:8?l4e:3:1(?6=:3c;?k4?93307d52;k37c<71;c8?l4e83:1(?6=:3c;?k4?93h07d52;k37c<71;a8?l4fm3:1(?6=:3c;?k4?93n07d52;k37c<71;g8?l4fk3:1(?6=:3c;?k4?93l07d52;k37c<71;33?>o5ih0;6)<72;0b<>h5080:=65f28d94?"50;09m55a293957=21<75f29f94?=n9?91<75f2c694?=n:k91<75f2c794?=h:k<1<75`1gg94?=e1=o1<7?50;2x 66228lm7E7;d:J:6==h9?81<75rb80b>5<3290;w)=?5;05a>N><2?3`<86=44i`594?=n:0>1<75`27194?=zj09:6=46:183!57=382h6F64e9K=7><,;2n64:7;%024?5>o4;3:17d=;:188m37=831b:94?::kb6?6=3f83:7>5;n0;3?6=3th2?=4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7>b20>37)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj08m6=4n:183!57=382i6F64e9K=7><11/><>54:k50?6=3`k96=44i7394?=h:1<1<75`29:94?=n;k0;6)<72;1b?k4?93:07d=6:18'6=4=;h1e>5?51:9j7=<72-83>7=n;o0;5?4<3`9<6=4+29097d=i:1;1?65f3783>!4?:39j7c<71;68?xd>:l0;6l4?:1y'753=:0o0D4:k;I;1<>\2m3;p>l4r$3:f><2?3-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f<4e290?6=4?{%131?41m2B28i5G93:8 7>b20>37d8<:188md1=831b>4:50;9l635=831vn45<7s-9;97<9e:J:0a=O1;20(?6j:86;?l042900el950;9j6<2=831d>;=50;9~f<4d290?6=4?{%131?41m2B28i5G93:8 7>b20>37d8<:188md1=831b>4:50;9l635=831v?o::181[4f=272?<4<1:p6d0=838pR?o9;<;05?553ty9m:4?:3y]6d1<509:6>=4}r0b=?6=:rT9m452923971=z{;k?6=4={_0b0>;>;908n6s|2`194?4|V;k8707<0;1:?xu5i;0;6?uQ2`089<572:20q~>5369~w7g72909wS2wx>o<50;0xZ7d53439j7=m;|q1f4<72;qU>o?4=80e>6?52z\1f5=:1;l1?55rs3ce>5<5sW8jj6362g803>{t:ho1<77}Y:hn014vP=ab9>=7c=;01v?om:181[4fj272>h4<8:p6dg=838pR?on;<;1a?503ty95k4?:3y]6<`<508n6>84}r357?6=:rT::>5293c926=z{;h?6=4:{_0a0>;>;80=863631850>;>:o0=86362d850>{t:k91<7;t^3`0?8?493<:707<0;42?8?5n3<:707=e;42?xu5j<0;6?uQ2c789<562h80q~7ne;296~;>:h09:>5293`926=z{0h=6=4={<;05?4?>272>i4=959~w;>;90j>6s|9c794?4|509;6?69;<;1g?4><2wx5lm50;0x9<572;23707=f;c1?xu>j=0;6?u293d96=0<508i6?7;;|q:eg<72;q65?h529:89<4b2h80q~7m3;296~;>:h09595293g96=052z\1f3=:1;o1>564}r;bb?6=:r72>o4=629>=7e=>:1vi4=629~wn6<8=;<;1e?g03439n7o8;<;1`?g03439o7o8;|a60`=83;i6n4=9zJ:6==#;9?155=4Z4g95~7?2t.9<=4=6e9j6d?=83.94?4=a99m6=7=821b>l950;&1<7<5i11e>5?51:9j6d0=83.94?4=a99m6=7=:21b>l;50;&1<7<5i11e>5?53:9j6d2=83.94?4=a99m6=7=<21b>l=50;&1<7<5i11e>5?55:9j6d4=83.94?4=a99m6=7=>21b>l?50;&1<7<5i11e>5?57:9j6d6=83.94?4=a99m6=7=021b>o<50;&1<7<5i11e>5?59:9j6g7=83.94?4=a99m6=7=i21b>o>50;&1<7<5i11e>5?5b:9j6d`=83.94?4=a99m6=7=k21b>lk50;&1<7<5i11e>5?5d:9j6db=83.94?4=a99m6=7=m21b>lm50;&1<7<5i11e>5?5f:9j6dd=83.94?4=a99m6=7=9910e?on:18'6=4=:h20b?6>:038?l4>n3:1(?6=:3c;?k4?93;976g88;29?l4?l3:17d?93;29?l4e<3:17di6>;0;66sm24794?2=83:p(>>::074?M?3l2B2>55+29g9=1g<,;;;6<<4i4d94?=ni;0;66g=9583>>i50?0;66sm93c94?2=83:p(>>::34f?M?3l2B2>55+29g9=1?>o51=0;66a=6283>>{e1:;1<7750;2x 6622;3o7E7;d:J:6==#:1o15974$333>6=n;80;66g<2;29?l542900e>:50;9j24<722c=87>5;hc1>5<5<5a;294~"48<095h5G95f8L<4?3S?n67>5;h42>5<5<h5080;76g<9;29 7>52:k0b?6>:098m6>=83.94?45$3:1>6g54i2494?"50;08m6`=8087?>{e1;l1<7o50;2x 6622;3n7E7;d:J:6==]=l0:w?o5}%0;a??312.9==4;;h47>5<>i50?0;66a=8983>>o4j3:1(?6=:2c8j7>62910e>750;&1<7<4i2d94<4>;:k0o4n3:2>7=h5080876g<6;29 7>52:k0b?6>:598yg?5m3:1m7>50z&040<51l1C59j4H80;?_3b28q9m7s+29g9=1?<,;;;695f6583>>of:3:17d8>:188k7>12900c?67:188m6d=83.94?45$3:1>6go4?3:1(?6=:2c8j7>62:10e>850;&1<7<4i2d94<4;;:a=7d=83>1<7>t$226>70b3A3?h6F6299'6=c=1=30e;=50;9je2<722c9594?::m126<722wi5?j50;694?6|,::>6?8j;I;7`>N>:11/>5k595;8m35=831bm:4?::k1=1<722e9:>4?::a=7e=83>1<7>t$226>70b3A3?h6F6299'6=c=1=30e;=50;9je2<722c9594?::m126<722wi>8850;694?6|,::>6?8j;I;7`>N>:11/>5k595c8m35=831bm:4?::k1=1<722e9:>4?::p6d3=838pR?o:;<;05?563ty9m;4?:3y]6d0<509:6><4}r0b3?6=:rT9m:52923976=z{;k26=4={_0b=>;>;80886s|2`694?4|V;k?707<0;1a?xu5i:0;6?uQ2`189<572:30q~>5399~w7g62909wSl>50;0xZ7g73438<7=9;|q1f7<72;qU>o<4=80e>6d52z\1f4=:1;l1?45rs3`3>5<5sW8i<6362g80<>{t:hl1<77}Y:ho014vP=ae9>=7c=;k1v?ol:181[4fk272>h4<9:p6dd=838pR?om;<;1a?5?3ty9ml4?:3y]6dg<508n6>94}r0:b?6=:rT95k5293g973=z{>21<78;52868yv71;3:1>vP>629>=7g=>:1v?l;:186[4e<272?<494:?:75<1<272>k494:?:6`<1<2wx>o=50;7xZ7d43438=78>;<;04?063439j78>;<;1a?063ty9n84?:3y]6g3<509:6l<4}r3ea?6=:rT:jh5224796=052z?:6d<5>:165?l5629~w;>:m09595rs8cg>5<5s438=7<77:?:75{t1hi1<77>?3439j7o=;|q:f1<72;q65?h529489<4e2;3?7p}6ac83>7}:1;l1>564=80f>d452z?:6d<51=165?k52948yv4e>3:1>vP=b79>=7c=:120q~7nf;296~;>:k09:>5293a926=z{0h:6=4={<;1`?41;2799;493:p=g6=838p147}::52z?:0c<5?o16>8852868yv40<3:1:v364d8227=:1;k1m:5293`9e2=:1;n1m:5293a9e2=::<<1m:5r}r3b6?6=:rT:m?5224:96d?52z\2e4=::<21>l94}r3b4?6=:rT:m=5224:96d052z\2=c=::<21>l;4}r3:f?6=:rT:5o5224:96d252z\2=5=::<21>l=4}r3;1?6=:rT:485224:96d452z\23d=::<21>l?4}r35b?6=:rT::k5224:96d652z\2ba=::<21>o<4}r3e5?6=:rT:j<5224:96g752z\2a3=::<21>o>4}r3gf?6=:rT:ho5224:96d`52z\2`5=::<21>lk4}r3`1?6=:rT:o85224:96db52z\2fd=::<21>lm4}r3bb?6=:rT:mk5224:96dd52z\2e1=::<21>lo4}r350?6=:rT::95224:96<`52z\2f2=::<31>l74}r3a2?6=:rT:n;5224;96d152z\2f0=::<31>l84}r3a0?6=:rT:n95224;96d352z\2f6=::<31>l:4}r3a6?6=:rT:n?5224;96d552z\2f4=::<31>l<4}r3a4?6=:rT:n=5224;96d752z\2e`=::<31>l>4}r3b`?6=:rT:mi5224;96g452z\2ef=::<31>o?4}r3bf?6=:rT:mo5224;96g652z\2ed=::<31>lh4}r3b=?6=:rT:m45224;96dc52z\2e==::<31>lj4}r3b3?6=:rT:m:5224;96de52z\2e3=::<31>ll4}r3b1?6=:rT:m85224;96dg52z\2e6=::<31>4h4}r3`g?6=:rT:on5224c96d?52z\2gg=::l94}r3`e?6=:rT:ol5224c96d052z\2g<=::l;4}r3`52z\2g2=::l=4}r3`2?6=:rT:o;5224c96d452z\2g1=::l?4}r3`7?6=:rT:o>5224c96d67>52z\2g7=::o<4}r3`5?6=:rT:o<5224c96g752z\2g5=::o>4}r3ab?6=:rT:nk5224c96d`52z\2f`=::lk4}r3a`?6=:rT:ni5224c96db52z\2ff=::lm4}r3af?6=:rT:no5224c96dd52z\2f<=::lo4}r3a52z\2a4=::

l74}r3f4?6=:rT:i=5224`96d152z\2`c=::
l84}r3ga?6=:rT:hh5224`96d352z\2`a=::
l:4}r3gg?6=:rT:hn5224`96d552z\2`d=::
l<4}r3g=?6=:rT:h45224`96d752z\2`==::
l>4}r3g3?6=:rT:h:5224`96g452z\2`3=::
o?4}r3g1?6=:rT:h85224`96g652z\2`1=::
lh4}r3g7?6=:rT:h>5224`96dc7>52z\2`7=::
lj4}r3g5?6=:rT:h<5224`96de52z\2gc=::
ll4}r3`a?6=:rT:oh5224`96dg52z\2ga=::
4h4}r3e2?6=:rT:j;5224a96d?52z\2b0=::l94}r3e0?6=:rT:j95224a96d052z\2b6=::l;4}r3e6?6=:rT:j?5224a96d252z\2b5=::l=4}r3fb?6=:rT:ik5224a96d452z\2a`=::l?4}r3f`?6=:rT:ii5224a96d652z\2af=::o<4}r3ff?6=:rT:io5224a96g752z\2ad=::o>4}r3f=?6=:rT:i45224a96d`52z\2a==::lk4}r3f3?6=:rT:i:5224a96db52z\2a0=::lm4}r3f0?6=:rT:i95224a96dd52z\2a6=::lo4}r3f6?6=:rT:i?5224a96<`52z\236=::l74}r346?6=:rT:;?5224f96d152z\234=::l84}r344?6=:rT:;=5224f96d352z\22`=::l:4}r35`?6=:rT::i5224f96d552z\22f=::l<4}r35f?6=:rT::o5224f96d752z\22d=::l>4}r35=?6=:rT::45224f96g452z\22==::o?4}r353?6=:rT:::5224f96g652z\223=::lh4}r351?6=:rT::85224f96dc52z\2bg=::lj4}r3ee?6=:rT:jl5224f96de52z\2b<=::ll4}r3e52z\2b2=::4h4}r3;52z\2<2=::l94}r3;2?6=:rT:4;5224g96d052z\2<1=::l;4}r3;7?6=:rT:4>5224g96d27>52z\2<7=::l=4}r3;5?6=:rT:4<5224g96d452z\2<5=::l?4}r34b?6=:rT:;k5224g96d652z\23`=::o<4}r34`?6=:rT:;i5224g96g752z\23f=::o>4}r34f?6=:rT:;o5224g96d`52z\23<=::lk4}r3452z\232=::lm4}r342?6=:rT:;;5224g96dd52z\230=::lo4}r340?6=:rT:;95224g96<`52z\2=`=::l74}r3:g?6=:rT:5n5224d96d152z\2=d=::l84}r3:=?6=:rT:545224d96d352z\2===::l:4}r3:3?6=:rT:5:5224d96d552z\2=3=::l<4}r3:1?6=:rT:585224d96d752z\2=1=::l>4}r3:7?6=:rT:5>5224d96g47>52z\2=7=::o?4}r3:5?6=:rT:5<5224d96g652z\2lh4}r3;a?6=:rT:4h5224d96dc52z\2lj4}r3;g?6=:rT:4n5224d96de52z\2ll4}r3;e?6=:rT:4l5224d96dg52z\2<<=::4h4}r5;>5<>sW=370<:8;5;?84213=370<:a;5;?842j3=370<:c;5;?842l3=370<:e;5;?842n3=37p}=8e83><}Y:1n01?;7:3:g?8421383h63=5`815j4=37`>7>c348>h7<7d:?11`<50m16>8h529f8yv4e<3:15vP=b59>60>=:k>01?;6:3`7?842i38i863=5c81f1=::o:4=37g>7d3348>i760?=:k901?;n:3`0?842j38i?63=5b81f6=::o=4=37f>7d4348>j7o850;0xZ7d1348>472wx54;50;0x973>28ln70<:a;357>{t1kk1<77d2348>m72wx54950;0x973e28ln70<:c;357>{t1ki1<77d2348>o7=838p1?;l:0df?842l3;=?6s|9cf94?4|5;?h6?l:;<06`?4e>2wx54750;0x973c28ln70<:e;357>{t1ko1<77d2348>i72wx=kk50;0xZ4`b348>j7?ie:~f3?529086=4?{%131?4102B28i5G93:8 7772830e?>=:188m7642900c?9k:188yg01<3:197>50z&040<5>h1C59j4H80;?!4683h0e?>=:188m7642900e?>;:188m7622900c?9k:188yg01>3:197>50z&040<5>h1C59j4H80;?!4683k87)<73;;63>o58;0;66g=0283>>o58=0;66g=0483>>i5?m0;66sm67594?3=83:p(>>::34b?M?3l2B2>55+202967=n:981<75f21194?=n:9>1<75f21794?=h:>n1<75rb74;>5<2290;w)=?5;05e>N>42c3`8;>7>5;h037?6=3`8;87>5;h031?6=3f85;|`52<<72<0;6=u+317963g<@0>o7E7=8:&155<6=<50;9j655=831b>=:50;9j653=831d>:j50;9~f30f290>6=4?{%131?41i2B28i5G93:8 7772h1/>5=59458m7652900e?><:188m7632900e?>::188k71c2900qo89b;291?6=8r.8<84=6`9K=1b<@0837)<>0;18m7652900e?><:188m7632900e?>::188k71c2900qo89c;291?6=8r.8<84=6`9K=1b<@0837)<>0;;8m7652900e?><:188m7632900e?>::188k71c2900qo89d;291?6=8r.8<84=6`9K=1b<@0837)<>0;36<>o58;0;66g=0283>>o58=0;66g=0483>>i5?m0;66sm67g94?3=83:p(>>::34b?M?3l2B2>55+202951=n:981<75f21194?=n:9>1<75f21794?=h:>n1<75rb746>5<2290;w)=?5;05e>N>c=n:981<75f21194?=n:9>1<75f21794?=h:>n1<75rb7aa>5<5290;w)=?5;060>N>5<3`8;>7>5;h037?6=3f85;|`5=4<72:0;6=u+317963><@0>o7E7=8:&155<592.94>465`9j654=831b>==50;9l62b=831vn;mn:180>5<7s-9;97<98:J:0a=O1;20(???:060?!4?;33>o6g=0383>>o58:0;66a=7e83>>{e>j91<7;50;2x 6622;5<5<t$226>70d3A3?h6F6299'646=9=h0e?>=:188m7642900e?>;:188m7622900e?>9:188m7602900c?9k:188yg0d=3:187>50z&040<6=:1C59j4H80;?!468380e8h50;9j24<722cj>7>5;n0;2?6=3th=o;4?:583>5}#;9?1=8=4H86g?M?502.9==4=;h7e>5<>i50?0;66sm6b694?2=83:p(>>::076?M?3l2B2>55+20296>o2n3:17do=:188m7>>2900c?69:188yg0>03:197>50z&040<6=;1C59j4H80;?!468380e8h50;9j24<722c<57>5;hc1>5<>o5000;66a=8783>>{e>0=1<7;50;2x 66228?97E7;d:J:6==#:8:1>6g:f;29?l062900e:750;9je7<722e94;4?::a2<0=83>1<7>t$226>4343A3?h6F6299'646=:2c>j7>5;h42>5<;96=4;:183!57=3;>?6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188k7>12900qo87e;290?6=8r.8<84=609K=1b<@0837)<>0;08^7dc28qj87sU17395~4el3wb;44?::kb6?6=3`;=>7>5;n0;2?6=3th=on4?:483>5}#;9?1=884H86g?M?502.9==4=;h7e>5<>o5000;66a=8783>>{e>jn1<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f30a290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl97083>0<729q/?=;51448L<2c3A3946=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi::<50;794?6|,::>6<;9;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=n:131<75`29494?=zj?=86=4::183!57=3;>:6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188m7>>2900c?69:188yg00<3:197>50z&040<6=?1C59j4H80;?!468380e8h50;9j24<722cj>7>5;h0;=?6=3f83:7>5;|`530<72<0;6=u+3179500<@0>o7E7=8:&155<53`?m6=44i7394?=ni;0;66g=8883>>i50?0;66sm66494?3=83:p(>>::075?M?3l2B2>55+20296>o2n3:17d8>:188md4=831b>5750;9l6=0=831vn;98:186>5<7s-9;97?:6:J:0a=O1;20(???:39j1c<722c==7>5;hc1>5<5<55;294~"48<0:9;5G95f8L<4?3-8:<7<4i4d94?=n>80;66gn2;29?l4?13:17b<76;29?xd10k0;694?:1y'753=9<90D4:k;I;1<>"599097d;i:188m37=831bm?4?::m1<3<722wi:l>50;694?6|,::>6<;<;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=h:1<1<75rb7;e>5<3290;w)=?5;367>N>7=n=o0;66g91;29?lg52900c?69:188yg0b<3:1?7>50z&040<>4:50;9l635=831vn;k7:180>5<7s-9;977;c:J:0a=O1;20e;=50;9j634=831d>:j50;9~f3c2290?6=4?{%131?41m2B28i5G93:8m35=831bm:4?::k1=1<722e9:>4?::a2`e=8391<7>t$226><2d3A3?h6F6299j26<722c9:?4?::m13a<722wi:h750;694?6|,::>6?8j;I;7`>N>:11b:>4?::kb3?6=3`8287>5;n057?6=3th=j=4?:283>5}#;9?159m4H86g?M?502c=?7>5;h056?6=3f85;|`5aa<72=0;6=u+317963c<@0>o7E7=8:k57?6=3`k<6=44i3;7>5<5<5<54;294~"48<09:h5G95f8L<4?3`<86=44i`594?=n:0>1<75`27194?=zj?l36=4<:183!57=33?o6F64e9K=7>n1<75rb7d6>5<3290;w)=?5;05a>N>0;66g=9583>>i5>:0;66sm6ga94?5=83:p(>>::86`?M?3l2B2>55f6283>>o5>;0;66a=7e83>>{e>o31<7:50;2x 6622;:0;66gn7;29?l4><3:17b<93;29?xd0890;6>4?:1y'753=1=i0D4:k;I;1<>o1;3:17d<92;29?j40l3:17pl9fe83>1<729q/?=;527g8L<2c3A3946g93;29?lg02900e?7;:188k7042900qo9?4;297?6=8r.8<8464b9K=1b<@0837d8<:188m7052900c?9k:188yg1793:187>50z&040<5>l1C59j4H80;?l042900el950;9j6<2=831d>;=50;9~f26029086=4?{%131??3k2B28i5G93:8m35=831b>;<50;9l62b=831vn;k<:181>5<7s-9;97<97:J:0a=O1;20(???:0;8m7652900c?9k:188yg0b?3:1>7>50z&040<5>>1C59j4H80;?!4683;27d7<729q/?=;52758L<2c3A3946=1182=>o58;0;66a=7e83>>{e>ll1<7<50;2x 6622;<<7E7;d:J:6==#:8:1=45f21094?=h:>n1<75rb7d0>5<5290;w)=?5;053>N>4?5<52;294~"48<09::5G95f8L<4?3-8:<7?6;h036?6=3f85;|`5bg<72;0;6=u+3179631<@0>o7E7=8:&155<612c96?88;I;7`>N>:11/><>5189j654=831d>:j50;9~f26429096=4?{%131?41?2B28i5G93:8 7772830e?>=:188k71c2900qo9?6;296?6=8r.8<84=669K=1b<@0837)<>0;3:?l47:3:17b<8d;29?xd1m;0;684?:1y'753=9<<0D4:k;I;1<>"599097d;i:188m37=831bm?4?::k1<<<722e94;4?::a2`0=83?1<7>t$226>4313A3?h6F6299'646=:2c>j7>5;h42>5<5<2290;w)=?5;362>N>7=n=o0;66g91;29?lg52900e?66:188k7>12900qo8je;291?6=8r.8<84>579K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3`8357>5;n0;2?6=3th=j?4?:483>5}#;9?1=884H86g?M?502.9==4=;h7e>5<>o5000;66a=8783>>{e>o<1<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f3`f290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl80383>0<729q/?=;51448L<2c3A3946=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi;=;50;794?6|,::>6<;9;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=n:131<75`29494?=zj=>;6=4<:183!57=33?o6F64e9K=7>n1<75rb51g>5<3290;w)=?5;05a>N>0;66g=9583>>i5>:0;66sm45694?5=83:p(>>::86`?M?3l2B2>55f6283>>o5>;0;66a=7e83>>{e<=;1<7:50;2x 6622;:0;66gn7;29?l4><3:17b<93;29?xd3<10;6>4?:1y'753=1=i0D4:k;I;1<>o1;3:17d<92;29?j40l3:17pl;4483>1<729q/?=;527g8L<2c3A3946g93;29?lg02900e?7;:188k7042900qo:;c;297?6=8r.8<8464b9K=1b<@0837d8<:188m7052900c?9k:188yg2313:187>50z&040<5>l1C59j4H80;?l042900el950;9j6<2=831d>;=50;9~f13729086=4?{%131??3k2B28i5G93:8m35=831b>;<50;9l62b=831vn9:k:187>5<7s-9;97<9e:J:0a=O1;20e;=50;9je2<722c9594?::m126<722wi88:50;194?6|,::>64:l;I;7`>N>:11b:>4?::k127<722e9;i4?::a007=83>1<7>t$226>70b3A3?h6F6299j26<722cj;7>5;h0:0?6=3f8=?7>5;|`71=<72:0;6=u+3179=1e<@0>o7E7=8:k57?6=3`8=>7>5;n04`?6=3th?984?:583>5}#;9?1>;k4H86g?M?502c=?7>5;hc4>5<5<>o7>53;294~"48<028n5G95f8L<4?3`<86=44i341>5<5<5<4290;w)=?5;;7g>N>>o51=0;66a=6283>>{eh7E7;d:J:6==n>:0;66g=6383>>i5?m0;66sm42d94?4=83:p(>>::344?M?3l2B2>55+20295<=n:981<75`26f94?=zj=>86=4=:183!57=38=;6F64e9K=7><,;;;6<74i321>5<3`8;>7>5;n04`?6=3th?8o4?:383>5}#;9?1>;94H86g?M?502.9==4>9:k147<722e9;i4?::a01`=8381<7>t$226>7003A3?h6F6299'646=901b>=<50;9l62b=831vn9;<:181>5<7s-9;97<97:J:0a=O1;20(???:0;8m7652900c?9k:188yg22?3:1>7>50z&040<5>>1C59j4H80;?!4683;27d7<729q/?=;52758L<2c3A3946=1182=>o58;0;66a=7e83>>{e<n1<75rb541>5<5290;w)=?5;053>N>4?5<8i7>55;294~"48<0:9;5G95f8L<4?3-8:<7<4i4d94?=n>80;66gn2;29?l4?13:17b<76;29?xd3<;0;684?:1y'753=9<<0D4:k;I;1<>"599097d;i:188m37=831bm?4?::k1<<<722e94;4?::a010=83?1<7>t$226>4313A3?h6F6299'646=:2c>j7>5;h42>5<5<2290;w)=?5;362>N>7=n=o0;66g91;29?lg52900e?66:188k7>12900qo:;e;291?6=8r.8<84>579K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3`8357>5;n0;2?6=3th?9?4?:483>5}#;9?1=884H86g?M?502.9==4=;h7e>5<>o5000;66a=8783>>{e<<<1<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f13f290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl;6083>0<729q/?=;51448L<2c3A3946=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi:8:50;194?6|,::>6?87;I;7`>N>:11/><>5209j654=831b>==50;9l62b=831vn;;<:187>5<7s-9;97<99:J:0a=O1;20(???:066?l47:3:17d"5990:945+2919=0b5<5<1<75`29494?=zj?826=4;:183!57=3;>;6F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=9583>>i50?0;66sm63:94?2=83:p(>>::074?M?3l2B2>55+202957=n=o0;66gn2;29?l4><3:17b<76;29?xd1:>0;694?:1y'753=9<=0D4:k;I;1<>"5990:>6g:f;29?lg52900e?7;:188k7>12900qo8=6;290?6=8r.8<84>569K=1b<@0837)<>0;31?l3a2900el<50;9j6<2=831d>5850;9~f342290?6=4?{%131?72?2B28i5G93:8 7772880e8h50;9je7<722c9594?::m1<3<722wi:?:50;694?6|,::>6<;8;I;7`>N>:11/><>5139j1c<722cj>7>5;h0:0?6=3f83:7>5;|`566<72=0;6=u+3179501<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<7>53;294~"48<09:55G95f8L<4?3-8:<7?6;h036?6=3`8;?7>5;n04`?6=3th=8:4?:583>5}#;9?1=8=4H86g?M?502.9==4=;h7e>5<>i50?0;66sm65494?2=83:p(>>::070?M?3l2B2>55+20296>o2n3:17d8>:188md4=831d>5850;9~f32?290>6=4?{%131?72:2B28i5G93:8 7772;1b9k4?::k55?6=3`=26=44i`094?=h:1<1<75rb760>5<3290;w)=?5;361>N>7=n=o0;66gn2;29?l4?13:17b<76;29?xd1<00;684?:1y'753=9<80D4:k;I;1<>"599097d;i:188m37=831b;44?::kb6?6=3f83:7>5;|`56c<72:0;6=u+317963><@0>o7E7=8:&155<612c91<7>t$226>4343A3?h6F6299'646=:2c>j7>5;h42>5<6=4;:183!57=3;>?6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188k7>12900qo8<4;290?6=8r.8<84>529K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3f83:7>5;|`576<72=0;6=u+3179505<@0>o7E7=8:&155<53`?m6=44i7394?=ni;0;66a=8783>>{e>:=1<7;50;2x 66228?97E7;d:J:6==#:8:1>6g:f;29?l062900e:750;9je7<722e94;4?::a266=83>1<7>t$226>4323A3?h6F6299'646=:2c>j7>5;hc1>5<5<55;294~"48<0:9?5G95f8L<4?3-8:<7<4i4d94?=n>80;66g89;29?lg52900c?69:188yg37>3:1m7>50z&040<51l1C59j4H80;?_3b28q9m7s+20290>o1<3:17do=:188m37=831d>5850;9l6=>=831b?o4?:%0;6?5f3g83=7>4;h1:>5<#:181?l5a29395>=n;10;6)<72;1b?k4?93807d=8:18'6=4=;h1e>5?53:9j73<72-83>7=n;o0;5?2<3th>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7772=1b:94?::kb6?6=3`<:6=44o3:5>5<o413:1(?6=:2c8j7>62810e>650;&1<7<4i2d94<4=;:k03?6=,;296>o4n3:2>6=h5080?76sm51g94?g=83:p(>>::3;f?M?3l2B2>55U5d827g=u-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f1b1290j6=4?{%131?4>m2B28i5G93:8^0c=9r8j6p=01855`=#:1o159<4$333>1=n>=0;66gn2;29?l062900c?69:188k7>?2900e>l50;&1<7<4i2d94<4?;:k0=?6=,;296>o4n3:2>4=h5080976g<7;29 7>52:k0b?6>:298m60=83.94?46?7j;I;7`>N>:11Q9h4>{3c9y!4783<:i6=8d8:07=#:8:186g94;29?lg52900e;?50;9l6=0=831d>5650;9j7g<72-83>7=n;o0;5?6<3`926=4+29097d=i:1;1=65f3983>!4?:39j7c<71;08?l50290/>5<53`9m6=7=;21b?;4?:%0;6?5f3g83=7:4;|`7`1<72=0;6=u+317963`<@0>o7E7=8:&145<19l1/>5k59508m7652900e?><:188m7?32900c?9k:188yg3713:1m7>50z&040<51l1C59j4H80;?_3b28q9m7s+2129274<,;2n64:=;%024?21<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn8>7:18b>5<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"5890=>?5+29g9=14<,;;;695f6583>>of:3:17d8>:188k7>12900c?67:188m6d=83.94?45$3:1>6go4?3:1(?6=:2c8j7>62:10e>850;&1<7<4i2d94<4;;:a151=83>1<7>t$226>70a3A3?h6F6299'656=>;80(?6j:861?l47:3:17d<3:17b<8d;29?xd3lm0;6l4?:1y'753=:0o0D4:k;I;1<>\2m3;p>l4r$323>37a3-83i77;2:&155<33`80;66a=8783>>i5010;66g52:k0b?6>:198m6?=83.94?45$3:1>6go4>3:1(?6=:2c8j7>62=10qo:kc;29e?6=8r.8<84=9d9K=1b<@0837W;j:0y1e?{#:9:1:<253-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f1be290?6=4?{%131?41n2B28i5G93:8 7672?;m7)<7e;;76>o58;0;66g=0283>>o51=0;66a=7e83>>{e5;hc1>5<!4?:39j7c<71;28?l5>290/>5<53`9m6=7=921b?54?:%0;6?5f3g83=7<4;h14>5<#:181?l5a29397>=n;?0;6)<72;1b?k4?93>07pl;f883>d<729q/?=;528g8L<2c3A3946T:e;3x6d;%0;a??3:2.9==4;;h47>5<>i50?0;66a=8983>>o4j3:1(?6=:2c8j7>62910e>750;&1<7<4i2d94<4>;:k0o4n3:2>7=h5080876g<6;29 7>52:k0b?6>:598yg2a03:1m7>50z&040<51l1C59j4H80;?_3b28q9m7s+2129277<,;2n64:=;%024?21<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn9h8:18b>5<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"5890=><5+29g9=14<,;;;695f6583>>of:3:17d8>:188k7>12900c?67:188m6d=83.94?45$3:1>6go4?3:1(?6=:2c8j7>62:10e>850;&1<7<4i2d94<4;;:a0c2=83>1<7>t$226>70a3A3?h6F6299'656=>;;0(?6j:861?l47:3:17d<3:17b<8d;29?xd3n<0;694?:1y'753=:?l0D4:k;I;1<>"5890=><5+29g9=145<5<m:7>54;294~"48<09;=5G95f8L<4?3-8;<78=1:&1<`<><;1b>=<50;9j655=831b>4:50;9l62b=831vn9k7:18b>5<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"5890=>=5+29g9=14<,;;;695f6583>>of:3:17d8>:188k7>12900c?67:188m6d=83.94?45$3:1>6go4?3:1(?6=:2c8j7>62:10e>850;&1<7<4i2d94<4;;:a0`1=83k1<7>t$226>7?b3A3?h6F6299Y1`<6s;k1q)"50l028?5+20290>o1<3:17do=:188m37=831d>5850;9l6=>=831b?o4?:%0;6?5f3g83=7>4;h1:>5<#:181?l5a29395>=n;10;6)<72;1b?k4?93807d=8:18'6=4=;h1e>5?53:9j73<72-83>7=n;o0;5?2<3th?i;4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7672?8;7)<7e;;76>"5990?7d8;:188md4=831b:<4?::m1<3<722e9454?::k0f?6=,;296>o4n3:2>5=h5080:76g<8;29 7>52:k0b?6>:398m61=83.94?45$3:1>6g4}5i3w/>=>56328 7>b20>97)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj=o96=4;:183!57=38=j6F64e9K=7><,;:;6;6?8i;I;7`>N>:11/>=>56328 7>b20>97d1<729q/?=;52628L<2c3A3946=018565=#:1o159<4i321>5<5<>o4;3:17d=;:188m37=831b:94?::kb6?6=3f83:7>5;n0;3?6=3th><84?:883>5}#;9?1>4j4H86g?M?502.9==4<;h12>5<>o4<3:17d8>:188m32=831bm?4?::m1<3<722e94:4?::a253=83>1<7>t$226>70>3A3?h6F6299'646=9h1b>=<50;9j655=831b>=:50;9l62b=831vn9j<:187>5<7s-9;97?:5:J:0a=O1;20(?>?:73f?!4?m33??6=1181?l3a2900el<50;9j6=?=831d>5850;9~f1`4290?6=4?{%131?72=2B28i5G93:8 7672?8:7)<7e;;77>"599097d;i:188md4=831b>5750;9l6=0=831vn9k>:187>5<7s-9;97?:5:J:0a=O1;20(?>?:703?!4?m33??6=1181?l3a2900el<50;9j6=?=831d>5850;9~f360290?6=4?{%131?72=2B28i5G93:8 7772;1b9k4?::kb6?6=3`8357>5;n0;2?6=3th=<;4?:583>5}#;9?1=8;4H86g?M?502.9==4=;h7e>5<5<3290;w)=?5;361>N>7=n=o0;66gn2;29?l4?13:17b<76;29?xd3l80;694?:1y'753=9"599097d;i:188md4=831b>5750;9l6=0=831vn;>;:186>5<7s-9;97?:6:J:0a=O1;20(???:39j1c<722c==7>5;hc1>5<5<55;294~"48<0:9;5G95f8L<4?3-8:<7<4i4d94?=n>80;66gn2;29?l4?13:17b<76;29?xd1810;684?:1y'753=9<<0D4:k;I;1<>"599097d;i:188m37=831bm?4?::k1<<<722e94;4?::a1=3=83?1<7>t$226>4313A3?h6F6299'646=:2c>j7>5;h42>5<5<2290;w)=?5;362>N>7=n=o0;66g91;29?lg52900e?66:188k7>12900qo;8e;291?6=8r.8<84>579K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3`8357>5;n0;2?6=3th>;l4?:483>5}#;9?1=884H86g?M?502.9==4=;h7e>5<>o5000;66a=8783>>{e=><1<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f015290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl:6`83>0<729q/?=;51448L<2c3A3946=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi9;850;794?6|,::>6<;9;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=n:131<75`29494?=zj<<96=4::183!57=3;>:6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188m7>>2900c?69:188yg3?>3:1>7>50z&040<5>>1C59j4H80;?!4683;27d7<729q/?=;52758L<2c3A3946=1182=>o58;0;66a=7e83>>{e=>l1<7<50;2x 6622;<<7E7;d:J:6==#:8:1=45f21094?=h:>n1<75rb45a>5<5290;w)=?5;053>N>4?5<52;294~"48<09::5G95f8L<4?3-8:<7?6;h036?6=3f85;|`636<72;0;6=u+3179631<@0>o7E7=8:&155<612c96?88;I;7`>N>:11/><>5189j654=831d>:j50;9~f00e29096=4?{%131?41?2B28i5G93:8 7772830e?>=:188k71c2900qo;97;296?6=8r.8<84=669K=1b<@0837)<>0;3:?l47:3:17b<8d;29?xd2>:0;6?4?:1y'753=:?=0D4:k;I;1<>"5990:56g=0383>>i5?m0;66sm59594?5=83:p(>>::86`?M?3l2B2>55f6283>>o5>;0;66a=7e83>>{e=1;1<7:50;2x 6622;:0;66gn7;29?l4><3:17b<93;29?xd20=0;6>4?:1y'753=1=i0D4:k;I;1<>o1;3:17d<92;29?j40l3:17pl:7e83>1<729q/?=;527g8L<2c3A3946g93;29?lg02900e?7;:188k7042900qo;70;297?6=8r.8<8464b9K=1b<@0837d8<:188m7052900c?9k:188yg3013:187>50z&040<5>l1C59j4H80;?l042900el950;9j6<2=831d>;=50;9~f01d29086=4?{%131??3k2B28i5G93:8m35=831b>;<50;9l62b=831vn89::187>5<7s-9;97<9e:J:0a=O1;20e;=50;9je2<722c9594?::m126<722wi9:650;194?6|,::>64:l;I;7`>N>:11b:>4?::k127<722e9;i4?::a127=83>1<7>t$226>70b3A3?h6F6299j26<722cj;7>5;h0:0?6=3f8=?7>5;|`631<72:0;6=u+3179=1e<@0>o7E7=8:k57?6=3`8=>7>5;n04`?6=3th>:i4?:583>5}#;9?1>;k4H86g?M?502c=?7>5;hc4>5<5<53;294~"48<028n5G95f8L<4?3`<86=44i341>5<5<5<4290;w)=?5;;7g>N>6=4;:183!57=38=i6F64e9K=7>>o51=0;66a=6283>>{e=?21<7=50;2x 66220>h7E7;d:J:6==n>:0;66g=6383>>i5?m0;66sm57394?2=83:p(>>::34f?M?3l2B2>55f6283>>of?3:17d<64;29?j41;3:17pl:6583>6<729q/?=;595a8L<2c3A3946g93;29?l41:3:17b<8d;29?xd2k00;684?:1y'753=9<<0D4:k;I;1<>"599097d;i:188m37=831bm?4?::k1<<<722e94;4?::a1f0=83?1<7>t$226>4313A3?h6F6299'646=:2c>j7>5;h42>5<5<2290;w)=?5;362>N>7=n=o0;66g91;29?lg52900e?66:188k7>12900qo;me;291?6=8r.8<84>579K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3`8357>5;n0;2?6=3th>nl4?:483>5}#;9?1=884H86g?M?502.9==4=;h7e>5<>o5000;66a=8783>>{e=k<1<7;50;2x 66228?=7E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9j6=?=831d>5850;9~f0d5290>6=4?{%131?72>2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44i3::>5<>of:3:17d<79;29?j4?>3:17pl:a`83>0<729q/?=;51448L<2c3A3946=1181?l3a2900e;?50;9je7<722c9444?::m1<3<722wi9l850;794?6|,::>6<;9;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=n:131<75`29494?=zj<,;;;6<74i321>5<3`8;>7>5;n04`?6=3th>o>4?:383>5}#;9?1>;94H86g?M?502.9==4>9:k147<722e9;i4?::a1g`=8381<7>t$226>7003A3?h6F6299'646=901b>=<50;9l62b=831vn8lm:181>5<7s-9;97<97:J:0a=O1;20(???:0;8m7652900c?9k:188yg3e?3:1>7>50z&040<5>>1C59j4H80;?!4683;27d7<729q/?=;52758L<2c3A3946=1182=>o58;0;66a=7e83>>{e=hl1<7<50;2x 6622;<<7E7;d:J:6==#:8:1=45f21094?=h:>n1<75rb4ca>5<5290;w)=?5;053>N>4?5<52;294~"48<09::5G95f8L<4?3-8:<7?6;h036?6=3f85;|`6gg<72:0;6=u+3179=1e<@0>o7E7=8:k57?6=3`8=>7>5;n04`?6=3th>o84?:583>5}#;9?1>;k4H86g?M?502c=?7>5;hc4>5<5<53;294~"48<028n5G95f8L<4?3`<86=44i341>5<5<5<4290;w)=?5;;7g>N>>o51=0;66a=6283>>{e=j:1<7=50;2x 66220>h7E7;d:J:6==n>:0;66g=6383>>i5?m0;66sm5c;94?2=83:p(>>::34f?M?3l2B2>55f6283>>of?3:17d<64;29?j41;3:17pl:bb83>6<729q/?=;595a8L<2c3A3946g93;29?l41:3:17b<8d;29?xd2j<0;694?:1y'753=:?o0D4:k;I;1<>o1;3:17do8:188m7?32900c?8<:188yg3e03:1?7>50z&040<>4:50;9l635=831vn8l;:180>5<7s-9;977;c:J:0a=O1;20e;=50;9j634=831d>:j50;9~f0gc290?6=4?{%131?41m2B28i5G93:8m35=831bm:4?::k1=1<722e9:>4?::a1g6=8391<7>t$226><2d3A3?h6F6299j26<722c9:?4?::m13a<722wi9l750;694?6|,::>6?8j;I;7`>N>:11b:>4?::kb3?6=3`8287>5;n057?6=3th>mn4?:283>5}#;9?159m4H86g?M?502c=?7>5;h056?6=3f85;|`6e0<72=0;6=u+317963c<@0>o7E7=8:k57?6=3`k<6=44i3;7>5<5<5<54;294~"48<09:45G95f8L<4?3-8:<78?;h036?6=3`8;?7>5;h030?6=3f85;|`60<<72=0;6=u+317963?<@0>o7E7=8:&155<182c96?86;I;7`>N>:11/><>5619j654=831b>==50;9j652=831d>:j50;9~f024290?6=4?{%131?4112B28i5G93:8 7772?:0e?>=:188m7642900e?>;:188k71c2900qo;;0;290?6=8r.8<84=689K=1b<@0837)<>0;43?l47:3:17d"5990=<6g=0383>>o58:0;66g=0583>>i5?m0;66sm52c94?2=83:p(>>::34:?M?3l2B2>55+202925=n:981<75f21194?=n:9>1<75`26f94?=zj<9<6=4;:183!57=38=56F64e9K=7><,;;;6;>4i321>5<5<7>5;h037?6=3`8;87>5;n04`?6=3th>?<4?:583>5}#;9?1>;74H86g?M?502.9==490:k147<722c9<>4?::k141<722e9;i4?::a1a1=8391<7>t$226>70?3A3?h6F6299'646=:o1/>5=594`8m7652900e?><:188k71c2900qo;k6;297?6=8r.8<84=699K=1b<@0837)<>0;0e?!4?;33>n6g=0383>>o58:0;66a=7e83>>{e=;l1<7650;2x 6622;3h7E7;d:J:6==#:8:1?6g<1;29?l552900e>=50;9j71<722c==7>5;h47>5<6=4;:183!57=3;>?6F64e9K=7><,;;;6?5f5g83>>o193:17do=:188k7>12900qo;=4;290?6=8r.8<84>529K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3f83:7>5;|`666<72=0;6=u+3179505<@0>o7E7=8:&155<53`?m6=44i7394?=ni;0;66a=8783>>{e=;81<7:50;2x 66228?87E7;d:J:6==#:8:1>6g:f;29?l062900el<50;9l6=0=831vn8<>:187>5<7s-9;97?:3:J:0a=O1;20(???:39j1c<722c==7>5;hc1>5<>of:3:17b<76;29?xd2:l0;694?:1y'753=9<90D4:k;I;1<>"599097d;i:188m37=831bm?4?::m1<3<722wi9?j50;694?6|,::>6<;<;I;7`>N>:11/><>52:k6b?6=3`<:6=44i`094?=h:1<1<75rb40`>5<3290;w)=?5;367>N>7=n=o0;66g91;29?lg52900c?69:188yg35j3:187>50z&040<6=:1C59j4H80;?!468380e8h50;9j24<722cj>7>5;n0;2?6=3th>>l4?:583>5}#;9?1=8=4H86g?M?502.9==4=;h7e>5<>i50?0;66sm53;94?2=83:p(>>::070?M?3l2B2>55+20296>o2n3:17d8>:188md4=831d>5850;9~f04?290?6=4?{%131?72;2B28i5G93:8 7772;1b9k4?::k55?6=3`k96=44o3:5>5<54;294~"48<0:9>5G95f8L<4?3-8:<7<4i4d94?=n>80;66gn2;29?j4?>3:17pl:2783>1<729q/?=;51418L<2c3A3946=1181?l3a2900e;?50;9je7<722e94;4?::a14`=83>1<7>t$226>4343A3?h6F6299'646=:2c>j7>5;h42>5<i6=4;:183!57=3;>96F64e9K=7><,;;;6?5f5g83>>of:3:17d<79;29?j4?>3:17pl:4e83>1<729q/?=;51478L<2c3A3946=1181?l3a2900el<50;9j6=?=831d>5850;9~f02?290?6=4?{%131?72=2B28i5G93:8 7772;1b9k4?::kb6?6=3`8357>5;n0;2?6=3th>8l4?:583>5}#;9?1=8;4H86g?M?502.9==4=;h7e>5<5<3290;w)=?5;361>N>7=n=o0;66gn2;29?l4?13:17b<76;29?xd2<>0;694?:1y'753=9"599097d;i:188md4=831b>5750;9l6=0=831vn8:=:187>5<7s-9;97?:5:J:0a=O1;20(???:39j1c<722cj>7>5;h0;=?6=3f83:7>5;|`601<72=0;6=u+3179503<@0>o7E7=8:&155<53`?m6=44i`094?=n:131<75`29494?=zj<9m6=4;:183!57=3;>96F64e9K=7><,;;;6?5f5g83>>of:3:17d<79;29?j4?>3:17pl:4083>1<729q/?=;51478L<2c3A3946=1181?l3a2900el<50;9j6=?=831d>5850;9~f05d290?6=4?{%131?72=2B28i5G93:8 7772;1b9k4?::kb6?6=3`8357>5;n0;2?6=3th>?h4?:583>5}#;9?1=8;4H86g?M?502.9==4=;h7e>5<5<3290;w)=?5;361>N>7=n=o0;66gn2;29?l4?13:17b<76;29?xd2;k0;694?:1y'753=9"599097d;i:188md4=831b>5750;9l6=0=831vn8=9:187>5<7s-9;97?:5:J:0a=O1;20(???:39j1c<722cj>7>5;h0;=?6=3f83:7>5;|`67=<72=0;6=u+3179503<@0>o7E7=8:&155<53`?m6=44i`094?=n:131<75`29494?=zj<986=4;:183!57=3;>96F64e9K=7><,;;;6?5f5g83>>of:3:17d<79;29?j4?>3:17pl:3483>1<729q/?=;51478L<2c3A3946=1181?l3a2900el<50;9j6=?=831d>5850;9~f057290?6=4?{%131?72=2B28i5G93:8 7772;1b9k4?::kb6?6=3`8357>5;n0;2?6=3th>??4?:583>5}#;9?1=8;4H86g?M?502.9==4=;h7e>5<5<69381=?uG93:8 66220=i7W;j:0y27?{#1;31?=>4i0dg>5<#:181=km4n3:2>5=5<#:181=km4n3:2>7=54i0f3>5<#:181=km4n3:2>1=6=4+29095ce5<#:181=km4n3:2>3=5<#:181=km4n3:2>==l1<75rb374>5<6j3h1>8uG93:8 662202?7W;j:0y2;j4i3c:>5<#:181>l64n3:2>5=5<#:181>l64n3:2>7=6=4+29096d>54i3c7>5<#:181>l64n3:2>1=5<#:181>l64n3:2>3=5<#:181>l64n3:2>==5<#:181>l64n3:2>d=5<#:181>l64n3:2>f=5<#:181>l64n3:2>`=5<#:181>l64n3:2>46<3`8jm7>5$3:1>7g?3g83=7?>;:k1=c<72-83>74?::k1f1<722c9n>4?::k1f0<722e9n;4?::m2b`<722h28k4?:083>5}#;9?15><4H86g?M?502e9;k4?::a=1c=83;1<7>t$226>4`a3A3?h6F6299l534=831vn4=>:18:>5<7s-9;97<6d:J:0a=O1;20(?6j:861?!468390e>?50;9j77<722c8?7>5;h17>5<>of:3:17b<76;29?j4??3:17pl63183>d<729q/?=;528g8L<2c3A3946T:e;3x6d1<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn45<7s-9;97<6e:J:0a=O1;20V8k51z0b>x"50l028?5+20290>o1<3:17do=:188m37=831d>5850;9l6=>=831b?o4?:%0;6?5f3g83=7>4;h1:>5<#:181?l5a29395>=n;10;6)<72;1b?k4?93807d=8:18'6=4=;h1e>5?53:9j73<72-83>7=n;o0;5?2<3th2>h4?:`83>5}#;9?1>4k4H86g?M?502P>i7?t2`8~ 7>b20>97)<>0;68m32=831bm?4?::k55?6=3f83:7>5;n0;!4?:39j7c<71;38?l5?290/>5<53`9m6=7=:21b?:4?:%0;6?5f3g83=7=4;h15>5<#:181?l5a29390>=zj08o6=4;:183!57=38=i6F64e9K=7><,;2n64:=;h40>5<5<3290;w)=?5;05a>N><253`<86=44i`594?=n:0>1<75`27194?=zj08i6=4;:183!57=38=i6F64e9K=7><,;2n64:=;h40>5<5<3290;w)=?5;05a>N><253`<86=44i`594?=n:0>1<75`27194?=zj;?=6=4;:183!57=38=i6F64e9K=7><,;2n64:<;h40>5<5<5sW8j963630805>{t:h<1<77}Y:h=014=>:218yv4f13:1>vP=a89>=67=;=1v?o;:181[4f<272?=43ty9m?4?:3y]6d4<509;6>64}r0b5?6=:rT9m<52922972=z{;k;6=4={_0b4>;>;908:6s|2c094?4|V;h9707=f;1a?xu5j80;6?uQ2c389<4a2:30q~lk50;0xZ7gb3439j7=9;|q1ea<72;qU>lj4=80f>6d52z\1ef=:1;o1?45rs3ca>5<5sW8jn6362d80<>{t:hk1<77}Y:0l014=67=>=165>>5659>=7`=>=165?k5659~w7d4290>wSh491:p6g3=838pR?l:;<;05?g53ty2n;4?:3y>=67=:1<014im0;6?u292396=1<509;6l<4}r;a1?6=:r72?=4=879>=7e=:0>0q~7nc;296~;>;909455293d9e7=z{0h?6=4={<;1b?4?>272>o4=959~w;>:l0j>6s|9c194?4|508n6?69;<;1e?4><2wx>o850;0xZ7d13439i7<78:p=g7=838p143<87p}6b183>7}:1;n1:>5293a963552z?:6f<1;272>o4=629~w{t9?91<7=t=86e>71a3439m78<;<062?4><2wx>::50;4x9<2b28<9707=d;c4?8?5k3k<707=b;c4?8?5i3k<70<:6;c4?x{t9on1<76s|1g394?4|V8l:70<:7;0a5>{t9l<1<7{t9m:1<770<:7;0b`>{t9kk1<7{t9h>1<7{t?10;6?uQ799>601=?11v?6k:181[4?l2799:4=8e9~w7d32909wS2799:4=b79~w4`b2909wS?ie:?112<6nl1v47<:18a8?3n38l94=374>7g1348>;78952`1897302;k970<:7;0b5>;5=>09m=522459535h44?:0396?75sA3946<048:3g=]=l0:w<=5}%;1=?5782c:ji4?:%0;6?7ak2d94<4?;:k2b4<72-83>7?ic:l1<4<632c:i;4?:%0;6?7ak2d94<4=;:k2`g<72-83>7?ic:l1<4<432c:h=4?:%0;6?7ak2d94<4;;:k2g0<72-83>7?ic:l1<4<232c:nl4?:%0;6?7ak2d94<49;:k2ec<72-83>7?ic:l1<4<032c:m94?:%0;6?7ak2d94<47;:k221<72-83>7?ic:l1<4<>32c<47>5;h0;`?6=3`8i87>5;h0a7?6=3`8i97>5;n0a2?6=3f;mi7>5;c;7b?6=93:17777732c9n<4?:%0;6?4f02d94<4n;:k1f5<72-83>7770:9j6dg=83.94?4=a99m6=7=9810e?7i:18'6=4=:h20b?6>:008?l1?2900e?6k:188m4042900e?l;:188m7d42900e?l::188k7d12900cfg9K=1b<@0837b?92;29?xd>;80;644?:1y'753=:0n0D4:k;I;1<>"50l028?5+20297>o493:17d==:188m65=831b?94?::k55?6=3`<;1/><>54:k50?6=3`k96=44i7394?=h:1<1<75`29:94?=n;k0;6)<72;1b?k4?93:07d=6:18'6=4=;h1e>5?51:9j7=<72-83>7=n;o0;5?4<3`9<6=4+29097d=i:1;1?65f3783>!4?:39j7c<71;68?xd>:o0;6l4?:1y'753=:0o0D4:k;I;1<>\2m3;p>l4r$3:f><253-8:<7:4i7694?=ni;0;66g91;29?j4?>3:17b<78;29?l5e290/>5<53`9m6=7=821b?44?:%0;6?5f3g83=7?4;h1;>5<#:181?l5a29396>=n;>0;6)<72;1b?k4?93907d=9:18'6=4=;h1e>5?54:9~f<4b290j6=4?{%131?4>m2B28i5G93:8^0c=9r8j6p=8d8:07=#:8:186g94;29?lg52900e;?50;9l6=0=831d>5650;9j7g<72-83>7=n;o0;5?6<3`926=4+29097d=i:1;1=65f3983>!4?:39j7c<71;08?l50290/>5<53`9m6=7=;21b?;4?:%0;6?5f3g83=7:4;|`:6a<72=0;6=u+317963c<@0>o7E7=8:&1<`<><;1b:>4?::kb3?6=3`8287>5;n057?6=3th2>n4?:583>5}#;9?1>;k4H86g?M?502.94h46439j26<722cj;7>5;h0:0?6=3f8=?7>5;|`:6g<72=0;6=u+317963c<@0>o7E7=8:&1<`<><;1b:>4?::kb3?6=3`8287>5;n057?6=3th2>l4?:583>5}#;9?1>;k4H86g?M?502.94h46439j26<722cj;7>5;h0:0?6=3f8=?7>5;|`113<72=0;6=u+317963c<@0>o7E7=8:&1<`<><:1b:>4?::kb3?6=3`8287>5;n057?6=3ty9m84?:3y]6d3<509:6>?4}r0b2?6=:rT9m;52923977=z{;k<6=4={_0b3>;>;808?6s|2`;94?4|V;k2707<1;17?xu5i=0;6?uQ2`689<572:h0q~>5389~w7g52909wSl?50;0xZ7g63438<7=8;|q1e5<72;qU>l>4=813>607>52z\1f7=:1;l1?o5rs3`2>5<5sW8i=6362g80=>{t:k:1<77}Y:hl014vP=ad9>=7`=;?1v?ok:181[4fl272>h43ty9mo4?:3y]6dd<508n6>64}r0be?6=:rT9ml5293g972=z{;3m6=4={_0:b>;>:l08:6s|2c694?3|V;h?707<1;47?8?4830}Y:k9014=>:7389<572?;014?5a39~w;>:m09595rs8cg>5<5s438=7<77:?:75{t1hi1<77>?3439j7o=;|q:f1<72;q65?h529489<4e2;3?7p}6ac83>7}:1;l1>564=80f>d452z?:6`<50?165?o52868yv4e>3:1>vP=b79>=7c=:120q~7m1;296~;>:m09:>52244926=z{0h;6=4={<;1`?043439o7<93:p=d`=838p147}:1;h1:>5293c963552z\2b`=::<<1>;=4}r357?6=;r728k4=7g9>=7g=>:16>8852868yv40<3:1:v364d8227=:1;n1m:5293a9e2=:1;h1m:5293c9e2=::<<1m:5r}r3e`?6=:rT:ji5224596g452z\2b4=::<=1>o?4}r3f2?6=:rT:i;5224596g652z\2`g=::<=1>lh4}r3g4?6=:rT:h=5224596dc52z\2g0=::<=1>lj4}r3ae?6=:rT:nl5224596de52z\2ec=::<=1>ll4}r3b0?6=:rT:m95224596dg52z\221=::<=1>4h4}r5;>5<5sW=370<:7;5;?xu50m0;6?uQ29f897302;2o7p}=b583>7}Y:k>01?;8:3`7?xu5j:0;6?uQ2c1897302;h87p}=b483>7}Y:k?01?;8:3`6?xu5j?0;6?uQ2c4897302;h=7p}>fd83>7}Y9oo01?;8:0df?xu>1:0;6ou295d962`<5;?<6?o6;<063?4f?2799:4=a79>601=:h?01?;8:3c7?842?38j?63=5681e7=::<=1>l?4=374>7g7348>;7?93:~f0bf290:=7<513yK=7><,::>649m;[7f>4}6;3w/5?753128m4`c290/>5<51ga8j7>62910e:18'6=4=9oi0b?6>:098m4c1290/>5<51ga8j7>62;10e:298m4b7290/>5<51ga8j7>62=10e:498m4df290/>5<51ga8j7>62?10e:698m4g3290/>5<51ga8j7>62110e<8;:18'6=4=9oi0b?6>:898m2>=831b>5j50;9j6g2=831b>o=50;9j6g3=831d>o850;9l5cc=831i59h50;394?6|,::>64==;I;7`>N>:11d>:h50;9~f730290:n7l524yK=7><,::>646;;[7f>4}603w/>=>527f8m7g>290/>5<52`:8j7>62910e?o8:18'6=4=:h20b?6>:098m7g1290/>5<52`:8j7>62;10e?o::18'6=4=:h20b?6>:298m7g3290/>5<52`:8j7>62=10e?o<:18'6=4=:h20b?6>:498m7g5290/>5<52`:8j7>62?10e?o>:18'6=4=:h20b?6>:698m7g7290/>5<52`:8j7>62110e?l=:18'6=4=:h20b?6>:898m7d6290/>5<52`:8j7>62h10e?l?:18'6=4=:h20b?6>:c98m7ga290/>5<52`:8j7>62j10e?oj:18'6=4=:h20b?6>:e98m7gc290/>5<52`:8j7>62l10e?ol:18'6=4=:h20b?6>:g98m7ge290/>5<52`:8j7>628:07d52;k37c<71;32?>o51o0;6)<72;0b<>h5080:>65f7983>>o50m0;66g>6283>>o5j=0;66g=b283>>o5j<0;66a=b783>>i6nl0;66l64g83>4<729q/?=;59208L<2c3A3946a=7g83>>{e1=o1<7?50;2x 66228lm7E7;d:J:6==h9?81<75rb812>5<>290;w)=?5;0:`>N><253-8:<7=4i2394?=n;;0;66g<3;29?l532900e;?50;9j21<722cj>7>5;n0;2?6=3f83;7>5;|`:75<72h0;6=u+31796o7E7=8:X6a?7|:h0v(?6j:861?!4683>0e;:50;9je7<722c==7>5;n0;2?6=3f8347>5;h1a>5<#:181?l5a29394>=n;00;6)<72;1b?k4?93;07d=7:18'6=4=;h1e>5?52:9j72<72-83>7=n;o0;5?5<3`9=6=4+29097d=i:1;1865rb80e>5N>5;hc1>5<!4?:39j7c<71;28?l5>290/>5<53`9m6=7=921b?54?:%0;6?5f3g83=7<4;h14>5<#:181?l5a29397>=n;?0;6)<72;1b?k4?93>07pl62d83>d<729q/?=;528g8L<2c3A3946T:e;3x6d1<75fa383>>o193:17b<76;29?j4?03:17d=m:18'6=4=;h1e>5?50:9j7<<72-83>7=n;o0;5?7<3`936=4+29097d=i:1;1>65f3683>!4?:39j7c<71;18?l51290/>5<53`9m6=7=<21vn45<7s-9;97<9e:J:0a=O1;20(?6j:861?l042900el950;9j6<2=831d>;=50;9~f<4d290?6=4?{%131?41m2B28i5G93:8 7>b20>97d8<:188md1=831b>4:50;9l635=831vn45<7s-9;97<9e:J:0a=O1;20(?6j:861?l042900el950;9j6<2=831d>;=50;9~f<4f290?6=4?{%131?41m2B28i5G93:8 7>b20>97d8<:188md1=831b>4:50;9l635=831vn?;9:187>5<7s-9;97<9e:J:0a=O1;20(?6j:860?l042900el950;9j6<2=831d>;=50;9~w7g22909wSl850;0xZ7g13438=7==;|q1e2<72;qU>l94=812>6552z\1e<=:1:;1?95rs3c7>5<5sW8j86363180f>{t:h91<77}Y:h8014=?:2:8yv4f93:1>vP=a09>=66=;>1v?o?:181[4f8272?=4<6:p6g4=838pR?l=;<;1b?5e3ty9n<4?:3y]6g7<508m6>74}r0a4?6=:rT9n=5293d97==z{;km6=4={_0bb>;>:o08;6s|2`g94?4|V;kn707=f;15?xu5im0;6?uQ2`f89<4b2:h0q~lo50;0xZ7gf3439i7=8;|q1=c<72;qU>4h4=80f>6055z\1f1=:1:;1:952922921=:1;l1:95293g921=z{;h86=4:{_0a7>;>;80==63631855>;>:o0==6362d855>{t:k?1<77}:1:;1>584=80g>7?33ty2mi4?:3y>=67=:1=014=?:`08yv?e=3:1>v363181<3=:1;i1>4:4}r;bg?6=:r72?=4=899>=7`=i;1v4l;:1818?5n383:6362c81=1=z{0ki6=4={<;1b?4?0272>h4n2:p=g5=838p14{t1k;1<7704348>:78<;|q:f5<72;q65?j5629>=7e=:?90q~7nf;296~;>:j0=?6362c8126=z{0kn6=4={<;1f?043439m7<93:p5cc=838pR38286s|26694?0|50>n6<8=;<;1`?g03439o7o8;<;1f?g03439m7o8;<062?g03twx=kj50;0xZ4`c348>;7;<063?4e92wx=h850;0xZ4c1348>;750;0xZ4b7348>;7;7;7n2wx;54?:3y]3==::<=1;55rs3:g>5<5sW83h63=5681;5=>09n95rs3`0>5<5sW8i?63=5681f6=z{;h>6=4={_0a1>;5=>09n85rs3`5>5<5sW8i:63=5681f3=z{8ln6=4={_3ea>;5=>0:jh5rs8;0>58952`5897302;k=70<:7;0b1>;5=>09m95224596d5<5;?<6?o=;<063?4f92799:4=a19>601=9?90qpl6<729q/?=;595a8L<2c3A3946g93;29?l41:3:17b<8d;29?xd4l00;694?:1y'753=:?o0D4:k;I;1<>o1;3:17do8:188m7?32900c?8<:188yg5b83:1?7>50z&040<>4:50;9l635=831vn>k;:180>5<7s-9;977;c:J:0a=O1;20e;=50;9j634=831d>:j50;9~f6c6290?6=4?{%131?41m2B28i5G93:8m35=831bm:4?::k1=1<722e9:>4?::a7`>=8391<7>t$226><2d3A3?h6F6299j26<722c9:?4?::m13a<722wi?h;50;694?6|,::>6?8j;I;7`>N>:11b:>4?::kb3?6=3`8287>5;n057?6=3th8in4?:283>5}#;9?159m4H86g?M?502c=?7>5;h056?6=3f85;|`0a<<72=0;6=u+317963c<@0>o7E7=8:k57?6=3`k<6=44i3;7>5<5<5<54;294~"48<09:h5G95f8L<4?3`<86=44i`594?=n:0>1<75`27194?=zj:l86=4<:183!57=33?o6F64e9K=7>n1<75rb2fa>5<5290;w)=?5;053>N>4?5<52;294~"48<09::5G95f8L<4?3-8:<7?6;h036?6=3f85;|`0a6<72;0;6=u+3179631<@0>o7E7=8:&155<612c96?88;I;7`>N>:11/><>5189j654=831d>:j50;9~f6ce29096=4?{%131?41?2B28i5G93:8 7772830e?>=:188k71c2900qo=jf;296?6=8r.8<84=669K=1b<@0837)<>0;3:?l47:3:17b<8d;29?xd4n;0;6?4?:1y'753=:?=0D4:k;I;1<>"5990:56g=0383>>i5?m0;66sm3ec94?3=83:p(>>::075?M?3l2B2>55+20296>o2n3:17d8>:188md4=831b>5750;9l6=0=831vn>jj:186>5<7s-9;97?:6:J:0a=O1;20(???:39j1c<722c==7>5;hc1>5<5<7>55;294~"48<0:9;5G95f8L<4?3-8:<7<4i4d94?=n>80;66gn2;29?l4?13:17b<76;29?xd4m?0;684?:1y'753=9<<0D4:k;I;1<>"599097d;i:188m37=831bm?4?::k1<<<722e94;4?::a7`g=83?1<7>t$226>4313A3?h6F6299'646=:2c>j7>5;h42>5<5<2290;w)=?5;362>N>7=n=o0;66g91;29?lg52900e?66:188k7>12900qo=i1;291?6=8r.8<84>579K=1b<@0837)<>0;08m0`=831b:<4?::kb6?6=3`8357>5;n0;2?6=3th=;44?:583>5}#;9?1>;74H86g?M?502.9==4>459j654=831b>==50;9j652=831d>:j50;9~f3g029086=4?{%131?4102B28i5G93:8 7772;;0(?6<:87;?l47:3:17d2<729q/?=;527a8L<2c3A3946=11801>o58;0;66g=0283>>o58=0;66g=0483>>o58?0;66g=0683>>i5?m0;66sm6ca94?3=83:p(>>::34b?M?3l2B2>55+202955=#:1915864i321>5<5<6=44o35g>5<57;294~"48<09:n5G95f8L<4?3-8:<7?:0:k147<722c9<>4?::k141<722c9<84?::k143<722c9<:4?::m13a<722wi:ok50;594?6|,::>6?8l;I;7`>N>:11/><>53d9j654=831b>==50;9j652=831b>=;50;9j650=831b>=950;9l62b=831vn;li:180>5<7s-9;97<98:J:0a=O1;20(???:0;8 7>420?27d"5990:n6g=0383>>o58:0;66g=0583>>o58<0;66g=0783>>o58>0;66a=7e83>>{e>j;1<7950;2x 6622;h5f21094?=n:991<75f21694?=n:9?1<75f21494?=n:9=1<75`26f94?=zj?i96=48:183!57=38=o6F64e9K=7><,;;;6?k4i321>5<5<6=44i325>5<5<57;294~"48<09:n5G95f8L<4?3-8:<75;h030?6=3`8;97>5;h032?6=3`8;;7>5;n04`?6=3th=m44?:683>5}#;9?1>;m4H86g?M?502.9==4=e:k147<722c9<>4?::k141<722c9<84?::k143<722c9<:4?::m13a<722wi:lo50;594?6|,::>6?8l;I;7`>N>:11/><>52d9j654=831b>==50;9j652=831b>=;50;9j650=831b>=950;9l62b=831vn;om:186>5<7s-9;97<9a:J:0a=O1;20(???:3f8m7652900e?><:188m7632900e?>::188k71c2900qo8nc;293?6=8r.8<84=6b9K=1b<@0837)<>0;36a>o58;0;66g=0283>>o58=0;66g=0483>>o58?0;66g=0683>>i5?m0;66sm6`f94?1=83:p(>>::34`?M?3l2B2>55+202950b5<5<5<4?::k141<722e9;i4?::a2g>=83=1<7>t$226>70d3A3?h6F6299'646=9=:188m7642900e?>;:188m7622900e?>9:188m7602900c?9k:188yg0e13:1;7>50z&040<5>j1C59j4H80;?!4683i0e?>=:188m7642900e?>;:188m7622900e?>9:188m7602900c?9k:188yg0ei3:1;7>50z&040<5>j1C59j4H80;?!4683827d"5990:9l5f21094?=n:991<75f21694?=n:9?1<75f21494?=n:9=1<75`26f94?=zj?k96=4;:183!57=3;>96F64e9K=7><,;;;6?5f5g83>>of:3:17d<79;29?j4?>3:17pl9a583>1<729q/?=;51478L<2c3A3946=1181?l3a2900el<50;9j6=?=831d>5850;9~f3g229086=4?{%131?4102B28i5G93:8 77728>87)<73;;6`>o58;0;66g=0283>>i5?m0;66sm70194?2=83:p(>>::076?M?3l2B2>55+20296>o2n3:17do=:188m7>>2900c?69:188yg16<3:1?7>50z&040<5>11C59j4H80;?!4683;??6g=0383>>o58:0;66a=7e83>>{e>131<7:50;2x 66228?>7E7;d:J:6==#:8:1>6g:f;29?lg52900e?66:188k7>12900qo87a;297?6=8r.8<84=699K=1b<@0837)<>0;377>o58;0;66g=0283>>i5?m0;66sm6c394?1=83:p(>>::34`?M?3l2B2>55+202950e5<5<5<4?::m13a<722wi:o>50;594?6|,::>6?8l;I;7`>N>:11/><>5e:k147<722c9<>4?::k141<722c9<84?::k143<722c9<:4?::m13a<722wi4>k50;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`;a6<72:0;6=u+317951`<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<4290;w)=?5;37b>N>44>i50?0;66sm8d294?5=83:p(>>::06e?M?3l2B2>55+202957=n=o0;66gn2;29?j4?>3:17pl7dd83>6<729q/?=;515d8L<2c3A3946=11826>o2n3:17do=:188k7>12900qo6kd;297?6=8r.8<84>4g9K=1b<@0837)<>0;31?l3a2900el<50;9l6=0=831vn5jl:180>5<7s-9;97?;f:J:0a=O1;20(???:008m0`=831bm?4?::m1<3<722wi4il50;194?6|,::>6<:i;I;7`>N>:11/><>5139j1c<722cj>7>5;n0;2?6=3th3hl4?:283>5}#;9?1=9h4H86g?M?502.9==4>2:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7?=;h7e>5<<,;;;6<<4i4d94?=ni;0;66a=8783>>{e0m=1<7=50;2x 66228>m7E7;d:J:6==#:8:1=?5f5g83>>of:3:17b<76;29?xd?l?0;6>4?:1y'753=9=l0D4:k;I;1<>"5990:>6g:f;29?lg52900c?69:188yg>c=3:1?7>50z&040<65850;9~f=b429086=4?{%131?73n2B28i5G93:8 7772880e8h50;9je7<722e94;4?::at$226>42a3A3?h6F6299'646=9;1b9k4?::kb6?6=3f83:7>5;|`;`4<72:0;6=u+317951`<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<4290;w)=?5;37b>N>44>i50?0;66sm8bg94?5=83:p(>>::06e?M?3l2B2>55+202957=n=o0;66gn2;29?j4?>3:17pl7ce83>6<729q/?=;515d8L<2c3A3946=11826>o2n3:17do=:188k7>12900qo6lc;297?6=8r.8<84>4g9K=1b<@0837)<>0;31?l3a2900el<50;9l6=0=831vn5mm:180>5<7s-9;97?;f:J:0a=O1;20(???:008m0`=831bm?4?::m1<3<722wi4no50;194?6|,::>6<:i;I;7`>N>:11/><>5139j1c<722cj>7>5;n0;2?6=3th3o54?:283>5}#;9?1=9h4H86g?M?502.9==4>2:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7?=;h7e>5<<,;;;6<<4i4d94?=ni;0;66a=8783>>{e0j?1<7=50;2x 66228>m7E7;d:J:6==#:8:1=?5f5g83>>of:3:17b<76;29?xd?k=0;6>4?:1y'753=9=l0D4:k;I;1<>"5990:>6g:f;29?lg52900c?69:188yg>d;3:1?7>50z&040<65850;9~f=e529086=4?{%131?73n2B28i5G93:8 7772880e8h50;9je7<722e94;4?::at$226>42a3A3?h6F6299'646=9;1b9k4?::kb6?6=3f83:7>5;|`;g5<72:0;6=u+317951`<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<4290;w)=?5;37b>N>44>i50?0;66sm8ca94?5=83:p(>>::06e?M?3l2B2>55+202957=n=o0;66gn2;29?j4?>3:17pl7bc83>6<729q/?=;515d8L<2c3A3946=11826>o2n3:17do=:188k7>12900qo6ma;297?6=8r.8<84>4g9K=1b<@0837)<>0;31?l3a2900el<50;9l6=0=831vn5l6:180>5<7s-9;97?;f:J:0a=O1;20(???:008m0`=831bm?4?::m1<3<722wi4o650;194?6|,::>6<:i;I;7`>N>:11/><>5139j1c<722cj>7>5;n0;2?6=3th3n:4?:283>5}#;9?1=9h4H86g?M?502.9==4>2:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7?=;h7e>5<6=4<:183!57=3;?j6F64e9K=7><,;;;6<<4i4d94?=ni;0;66a=8783>>{e0k>1<7=50;2x 66228>m7E7;d:J:6==#:8:1=?5f5g83>>of:3:17b<76;29?xd?j;0;6>4?:1y'753=9=l0D4:k;I;1<>"5990:>6g:f;29?lg52900c?69:188yg>e93:1?7>50z&040<65850;9~f=d729086=4?{%131?73n2B28i5G93:8 7772880e8h50;9je7<722e94;4?::at$226>42a3A3?h6F6299'646=9;1b9k4?::kb6?6=3f83:7>5;|`;e`<72:0;6=u+317951`<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<4290;w)=?5;37b>N>44>i50?0;66sm8``94?5=83:p(>>::06e?M?3l2B2>55+202957=n=o0;66gn2;29?j4?>3:17pl7a`83>6<729q/?=;515d8L<2c3A3946=11826>o2n3:17do=:188k7>12900qo6n9;297?6=8r.8<84>4g9K=1b<@0837)<>0;31?l3a2900el<50;9l6=0=831vn5k8:180>5<7s-9;97?;f:J:0a=O1;20(???:008m0`=831bm?4?::m1<3<722wi4h850;194?6|,::>6<:i;I;7`>N>:11/><>5139j1c<722cj>7>5;n0;2?6=3th3i84?:283>5}#;9?1=9h4H86g?M?502.9==4>2:k6b?6=3`k96=44o3:5>5<53;294~"48<0:8k5G95f8L<4?3-8:<7?=;h7e>5<<,;;;6<<4i4d94?=ni;0;66a=8783>>{e0m>1<7=50;2x 66228>m7E7;d:J:6==#:8:1=?5f5g83>>of:3:17b<76;29?xd?k00;6>4?:1y'753=9=l0D4:k;I;1<>"5990:>6g:f;29?lg52900c?69:188yg>em3:1?7>50z&040<65850;9~f=d429086=4?{%131?73n2B28i5G93:8 7772880e8h50;9je7<722e94;4?::a=8391<7>t$226>42a3A3?h6F6299'646=9;1b9k4?::kb6?6=3f83:7>5;|`43a<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?0o1<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl8a883>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg1e<3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:l6:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a3gg=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>=n6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm76d94?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0090;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo971;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f2>5290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;5=50;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`4<1<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?1=1<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl88883>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg1?i3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:6m:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a3=e=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<4i4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>2m6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm78294?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0180;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo962;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f2?3290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;4;50;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`4=3<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?031<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl89`83>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg1>j3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:7l:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a31<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<5k4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>k:6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm7`094?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0i:0;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo9n4;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f2g2290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;l850;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`4e2<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?hh1<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl8ab83>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg1fl3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:oj:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a3d`=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>h96=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm7c194?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0j<0;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo9m6;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f2d0290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;o650;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`47a<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?>of:3:17d<74;29?j4?>3:17pl86883>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg10<3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:96:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a32g=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<;o4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>9n6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm72d94?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0<90;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo9;1;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f225290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;9=50;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`401<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?==1<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl84883>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg13i3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn::m:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a31e=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<8i4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>>m6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm74294?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0=80;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo9:2;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f233290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;8;50;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`413<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<;7>54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e?<31<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl85`83>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg12j3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:;l:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a30b=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<9k4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj><:6=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm77094?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0>:0;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo994;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f202290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;;850;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`422<72=0;6=u+3179502<@0>o7E7=8:&155<6:2c>j7>5;hc1>5<5<54;294~"48<0:995G95f8L<4?3-8:<7?=;h7e>5<5<3290;w)=?5;360>N>44>o50=0;66a=8783>>{e??h1<7:50;2x 66228??7E7;d:J:6==#:8:1=?5f5g83>>of:3:17d<74;29?j4?>3:17pl86b83>1<729q/?=;51468L<2c3A3946=11826>o2n3:17do=:188m7>32900c?69:188yg11l3:187>50z&040<6==1C59j4H80;?!4683;97d;i:188md4=831b>5:50;9l6=0=831vn:8j:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a33`=83>1<7>t$226>4333A3?h6F6299'646=9;1b9k4?::kb6?6=3`8387>5;n0;2?6=3th<;=4?:583>5}#;9?1=8:4H86g?M?502.9==4>2:k6b?6=3`k96=44i3:7>5<1<75`29494?=zj>=96=4;:183!57=3;>86F64e9K=7><,;;;6<<4i4d94?=ni;0;66g=8583>>i50?0;66sm76194?2=83:p(>>::077?M?3l2B2>55+202957=n=o0;66gn2;29?l4?<3:17b<76;29?xd0?<0;694?:1y'753=9<>0D4:k;I;1<>"5990:>6g:f;29?lg52900e?6;:188k7>12900qo986;290?6=8r.8<84>559K=1b<@0837)<>0;31?l3a2900el<50;9j6=2=831d>5850;9~f210290?6=4?{%131?72<2B28i5G93:8 7772880e8h50;9je7<722c9494?::m1<3<722wi;:650;694?6|,::>6<;;;I;7`>N>:11/><>5139j1c<722cj>7>5;h0;0?6=3f83:7>5;|`5=1<72=0;6=u+3179507<@0>o7E7=8:&155<53`?m6=44i6;94?=ni;0;66a=8783>>{e>0?1<7:50;2x 66228?:7E7;d:J:6==#:8:1>6g:f;29?l1>2900el<50;9l6=0=831vn;6k:187>5<7s-9;97?:4:J:0a=O1;20(???:008m0`=831bm?4?::k1<1<722e94;4?::a2=e=83>1<7>t$226>4363A3?h6F6299'646=:2c>j7>5;h5:>5<=6F64e9K=7><,;;;6?5f5g83>>o013:17do=:188k7>12900qo8:1;297?6=8r.8<84>4g9K=1b<@0837)<>0;31?l3a2900el<50;9l6=0=831vn;:::187>5<7s-9;97?:1:J:0a=O1;20(???:39j1c<722c<57>5;hc1>5<>of:3:17b<76;29?xd1;;0;694?:1y'753=9<;0D4:k;I;1<>"599097d;i:188m2?=831bm?4?::m1<3<722wi:>?50;694?6|,::>6<;>;I;7`>N>:11/><>52:k6b?6=3`=26=44i`094?=h:1<1<75rb7`6>5<3290;w)=?5;05b>N>5<5<3:17>5;h037?6=3`8;87>5;h031?6=3`8;:7>5;n04`?6=3th=n:4?:683>5}#;9?1>;m4H86g?M?502.9==44?::k141<722c9<84?::k143<722c9<:4?::m13a<722wi8==50;``>5<7s-9;97<7a:J:0a=O1;20V8k5cz36>40=::09;7<;:3:960<6m3;o66`n6;31?k76=3:0b<=8:19'51>=9=o0(<:6:06f?!4703<0(?>6:79'65g=>2.9"58o0=7)<>1;48 7752?1/><=56:&151<13-8:9784$335>3=#:8=1:6=1985?!4613<0(??n:79'64d=>2.9=n49;%02`?0<,;;n6;5+20d92>"5:90=7)<=1;48 7452?1/>?=56:&161<13-899784$305>3=#:;=1:6=2985?!4513<0(?2.9>n49;%01`?0<,;8n6;5+23d92>"5;90=7)<<1;48 7552?1/>>=56:&171<13-889784$315>3=#::=1:6=3985?!4413<0(?=n:79'66d=>2.9?n49;%00`?0<,;9n6;5+22d92>"5<90=7)<;1;48 7252?1/>9=56:&101<13-8?9784$365>3=#:==1:6=4985?!4313<0(?:n:79'61d=>2.98n49;%07`?0<,;>n6;5+25d92>"5=90=7)<:1;78 7352<1/>8=526a8 7?62;hj7)<62;42?!4>;3<:7)<67;;00>"511095l5+2c591>"5j10>7)7;0;;0b>"><802?k5f29`94?=n>k0;66g>4683>>o5190;66g80;29?l4?k3:17d<7f;29?l73>3:17dkj:18'6=4=mm1e>5?50:9jaf<72-83>7kk;o0;5?7<3`oi6=4+2909aa=i:1;1>65fe`83>!4?:3oo7c<71;18?l?413:1(?6=:81;?k4?93:07d7<7;29 7>520937c<71;38?l?4>3:1(?6=:81;?k4?93807d7<5;29 7>520937c<71;18?j77l3:1(?6=:02`?k4?93:07b??b;29 7>528:h7c<71;38?j7713:1(?6=:02`?k4?93807b??8;29 7>528:h7c<71;18?j77?3:1(?6=:02`?k4?93>07b??6;29 7>528:h7c<71;78?j77=3:1(?6=:02`?k4?93<07b??4;29 7>528:h7c<71;58?j77;3:1(?6=:02`?k4?93207b??2;29 7>528:h7c<71;;8?j7793:1(?6=:02`?k4?93k07b??0;29 7>528:h7c<71;`8?j`b290/>5<511a8j7>62j10ckj50;&1<7<68j1e>5?5d:9lbf<72-83>7??c:l1<45$3:1>46d3g83=7h4;ndb>5<#:181==m4n3:2>46<3fl26=4+290955e5<#:181==m4n3:2>44<3fl<6=4+290955e5<#:181==m4n3:2>42<3fl>6=4+290955el;o0;5?7132e:=>4?:%0;6?77k2d94<4>7:9l544=83.94?4>0b9m6=7=9110c:18'6=4=99i0b?6>:0;8?j7683:1(?6=:02`?k4?93;j76a>0g83>!4?:3;;o6`=8082f>=h99o1<7=83824f=i:1;1=n54o02b>5<#:181==m4n3:2>4b<3flm6=4+290955e5<#:181==m4n3:2>4`<3`>?6=4+290906=i:1;1<65f4383>!4?:3>87c<71;38?l26290/>5<5429m6=7=:21b8=4?:%0;6?243g83=7=4;h6g>5<#:1818>5a29390>=n5?56:9j0d<72-83>7:<;o0;5?1<3`>26=4+290906=i:1;1465f4983>!4?:3>87c<71;;8?l20290/>5<5429m6=7=i21b8;4?:%0;6?243g83=7l4;h66>5<#:1818>5a2939g>=n;o0;6)<72;60?k4?93n07d;<:18'6=4==;1e>5?50:9j14<72-83>7;=;o0;5?7<3`?;6=4+290917=i:1;1>65f4g83>!4?:3?97c<71;18?l3d290/>5<5539m6=7=<21b9o4?:%0;6?353g83=7;4;h7b>5<#:1819?5a29392>=n=00;6)<72;71?k4?93=07d;7:18'6=4==;1e>5?58:9j12<72-83>7;=;o0;5??<3`?=6=4+290917=i:1;1m65f5483>!4?:3?97c<71;`8?l33290/>5<5539m6=7=k21b8h4?:%0;6?353g83=7j4;hg1>5<#:181i<5a29394>=nm90;6)<72;g2?k4?93;07djj:18'6=4=m81e>5?52:9j`a<72-83>7k>;o0;5?5<3`nh6=4+2909a4=i:1;1865fdc83>!4?:3o:7c<71;78?lbf290/>5<5e09m6=7=>21bh44?:%0;6?c63g83=794;hf;>5<#:181i<5a2939<>=nl>0;6)<72;g2?k4?93307dj9:18'6=4=m81e>5?5a:9j`0<72-83>7k>;o0;5?d<3`n86=4+2909a4=i:1;1o65fd383>!4?:3o:7c<71;f8?lb6290/>5<5e09m6=7=m21bh=4?:%0;6?c63g83=7h4;hae>5<#:181i<5a293955=h5080:=65fce83>!4?:3o:7c<71;31?>odk3:1(?6=:d38j7>628907dmm:18'6=4=m81e>5?51598mfg=83.94?4j1:l1<4<6=21bi44?:%0;6?c63g83=7?9;:kf41<3`o<6=4+2909a4=i:1;1=554id494?"50;0n=6`=8082=>=nm<0;6)<72;g2?k4?93;j76gj4;29 7>52l;0b?6>:0`8?lc4290/>5<5e09m6=7=9j10eih50;&1<7d:9j`1<72-83>7k>;o0;5?7b32ch57>5$3:1>`75$3:1>45e3g83=7?4;n30=?6=,;296<=m;o0;5?4<3f;847>5$3:1>45e3g83=7=4;hd0>5<#:181j?5a29394>=nn80;6)<72;d1?k4?93;07dh?:18'6=4=n;1e>5?52:9jac<72-83>7h=;o0;5?5<3f;?=7>5$3:1>4273g83=7>4;n30b?6=,;296<:?;o0;5?7<3f;8i7>5$3:1>4273g83=7<4;n30`?6=,;296<:?;o0;5?5<3f;9j7>5$3:1>44b3g83=7>4;n31`?6=,;296<5$3:1>44b3g83=7<4;n31e?6=,;296<5$3:1>44b3g83=7:4;n315$3:1>44b3g83=784;n312?6=,;296<5$3:1>44b3g83=764;n310?6=,;296<5$3:1>44b3g83=7o4;n316?6=,;296<5$3:1>44b3g83=7m4;n32b?6=,;296<5$3:1>44b3g83=7k4;n32`?6=,;296<5$3:1>44b3g83=7??;:m25g<72-83>7?=e:l1<4<6921d=5?51398k47>290/>5<513g8j7>628907b?>8;29 7>5288n7c<71;37?>i69>0;6)<72;31a>h5080:965`12494?"50;0:>h5a293953=6=4+290957c4?:%0;6?75m2d94<4>9:9l564=83.94?4>2d9m6=7=9h10c<=>:18'6=4=9;o0b?6>:0`8?j7483:1(?6=:00f?k4?93;h76a>2b83>!4?:3;9i6`=8082`>=h9;;1<7=83826`=i:1;1=h54o035>5<#:181=?k4n3:2>4`<3`38i7>5$3:1><5c3g83=7>4;h;0g?6=,;2964=k;o0;5?7<3`38n7>5$3:1><5c3g83=7<4;h;0e?6=,;2964=k;o0;5?5<3`i:6=4+2909g5=i:1;1<65fbg83>!4?:3i;7c<71;38?ldc290/>5<5c19m6=7=:21bnn4?:%0;6?e73g83=7=4;h`a>5<#:181o=5a29390>=njh0;6)<72;a3?k4?93?07dl6:18'6=4=k91e>5?56:9jf=<72-83>7m?;o0;5?1<3`h<6=4+2909g5=i:1;1465fb783>!4?:3i;7c<71;;8?ld2290/>5<5c19m6=7=i21bn94?:%0;6?e73g83=7l4;h`1>5<#:181o=5a2939g>=nj80;6)<72;a3?k4?93n07dl?:18'6=4=k91e>5?5e:9jec<72-83>7m?;o0;5?`<3`kn6=4+2909g5=i:1;1==54i`f94?"50;0h<6`=80825>=nij0;6)<72;a3?k4?93;976gnb;29 7>52j:0b?6>:018?lgf290/>5<5c19m6=7=9=10el750;&1<75:9jg=<72-83>7m?;o0;5?7132ch;7>5$3:1>f65<#:181o=5a29395==h5080:565fc583>!4?:3i;7c<71;3b?>od;3:1(?6=:b28j7>628h07dm=:18'6=4=k91e>5?51b98mgc=83.94?4l0:l1<4<6l21bn>4?:%0;6?e73g83=7?j;:kb4n3:2>4`<3th?<;4?:ca94?6|,::>6?6n;I;7`>N>:11Q9h4l{07953<5;38<6?:529811?7b28n1=k4=6;3`>xhf=3;97co9:008j472291e=>950:&20=<6=756:&14d<13-8;n784$32`>3=#:9n1:6=0d85?!47n3<0(??>:79'644=>2.9=>49;%020?0<,;;>6;5+20492>"59>0=7)<>8;48 77>2?1/>3=#:8o1:6=1g85?!4583<0(?<>:79'674=>2.9>>49;%010?0<,;8>6;5+23492>"5:>0=7)<=8;48 74>2?1/>?o56:&16g<13-89o784$30g>3=#:;o1:6=2g85?!4483<0(?=>:79'664=>2.9?>49;%000?0<,;9>6;5+22492>"5;>0=7)<<8;48 75>2?1/>>o56:&17g<13-88o784$31g>3=#::o1:6=3g85?!4383<0(?:>:79'614=>2.98>49;%070?0<,;>>6;5+25492>"5<>0=7)<;8;48 72>2?1/>9o56:&10g<13-8?o784$36g>3=#:=o1:6=4g85?!4283<0(?;>:49'604==2.99>4=7b9'6<7=:kk0(?7=:738 7?42?;0(?78:817?!4>0382m6=b686?!4e03?0(4:?:81e?!?39338j6g=8c83>>o1j3:17d?;7;29?l4>83:17d9?:188m7>d2900e?6i:188m4212900ehk50;&1<74=h5080976gja;29 7>52ln0b?6>:298m<5>290/>5<592:8j7>62910e4=8:18'6=4=1:20b?6>:098m<51290/>5<592:8j7>62;10e4=::18'6=4=1:20b?6>:298k46c290/>5<511a8j7>62910c<>m:18'6=4=99i0b?6>:098k46>290/>5<511a8j7>62;10c<>7:18'6=4=99i0b?6>:298k460290/>5<511a8j7>62=10c<>9:18'6=4=99i0b?6>:498k462290/>5<511a8j7>62?10c<>;:18'6=4=99i0b?6>:698k464290/>5<511a8j7>62110c<>=:18'6=4=99i0b?6>:898k466290/>5<511a8j7>62h10c<>?:18'6=4=99i0b?6>:c98kcc=83.94?4>0b9m6=7=k21dji4?:%0;6?77k2d94<4k;:meg?6=,;296<>l;o0;5?c<3fli6=4+290955e54og494?"50;0:5<#:181==m4n3:2>40<3f;:?7>5$3:1>46d3g83=7?8;:m257<72-83>7??c:l1<4<6021d=5?51898k477290/>5<511a8j7>628k07b??f;29 7>528:h7c<71;3a?>i68l0;6)<72;33g>h5080:o65`11c94?"50;0:1<7=83877>h5080;76g;2;29 7>52=90b?6>:098m17=83.94?4;3:l1<4<532c?<7>5$3:1>1554i5f94?"50;0??6`=8087?>o3k3:1(?6=:518j7>62<10e9l50;&1<7<3;2d94<49;:k7e?6=,;2969=4n3:2>2=h5080376g;8;29 7>52=90b?6>:898m11=83.94?4;3:l1<45$3:1>15o4n3:1(?6=:518j7>62m10e8=50;&1<7<2:2d94<4?;:k65?6=,;2968<4n3:2>4=h5080976g;f;29 7>52<80b?6>:298m0e=83.94?4:2:l1<4<332c>n7>5$3:1>04>6`=8085?>o213:1(?6=:408j7>62>10e8650;&1<7<2:2d94<47;:k63?6=,;2968<4n3:2><=h5080j76g:5;29 7>52<80b?6>:c98m02=83.94?4:2:l1<45$3:1>04ob83:1(?6=:d38j7>62810eik50;&1<76=h5080?76gkb;29 7>52l;0b?6>:498mag=83.94?4j1:l1<4<132co57>5$3:1>`7oc?3:1(?6=:d38j7>62010ei850;&1<7g=h5080h76gk2;29 7>52l;0b?6>:e98ma7=83.94?4j1:l1<45$3:1>`7=nkl0;6)<72;g2?k4?93;:76gld;29 7>52l;0b?6>:008?led290/>5<5e09m6=7=9:10enl50;&1<74:9jgd<72-83>7k>;o0;5?7232cn57>5$3:1>`75<#:181i<5a293952=h5080:465fe783>!4?:3o:7c<71;3:?>ob=3:1(?6=:d38j7>628k07dk;:18'6=4=m81e>5?51c98m`5=83.94?4j1:l1<4<6k21bhk4?:%0;6?c63g83=7?k;:kg0?6=,;296h?4n3:2>4c<3`i26=4+2909a4=i:1;1=k54o01`>5<#:181=>l4n3:2>5=5<#:181=>l4n3:2>7=54ig194?"50;0m>6`=8083?>oa93:1(?6=:g08j7>62810ek>50;&1<76=:6=4+29095165<#:181=9>4n3:2>4=5<#:181=9>4n3:2>6=5<#:181=?k4n3:2>4=5<#:181=?k4n3:2>6=5<#:181=?k4n3:2>0=5<#:181=?k4n3:2>2=6=4+290957c5<#:181=?k4n3:2><=5<#:181=?k4n3:2>g=5<#:181=?k4n3:2>a=5<#:181=?k4n3:2>c=4;n32f?6=,;296<2:9l54?=83.94?4>2d9m6=7=9:10c:068?j76?3:1(?6=:00f?k4?93;>76a>3783>!4?:3;9i6`=80822>=h9:?1<7=83826`=i:1;1=:54o017>5<#:181=?k4n3:2>4><3f;8?7>5$3:1>44b3g83=7?6;:m277<72-83>7?=e:l1<4<6i21d=>?50;&1<7<6:l1e>5?51c98k457290/>5<513g8j7>628i07b?=c;29 7>5288n7c<71;3g?>i6:80;6)<72;31a>h5080:i65`10494?"50;0:>h5a29395c=5<#:1815>j4n3:2>4=5<#:1815>j4n3:2>6=h5080;76gmf;29 7>52j:0b?6>:098mgb=83.94?4l0:l1<4<532cio7>5$3:1>f654ic`94?"50;0h<6`=8087?>oei3:1(?6=:b28j7>62<10eo750;&1<74n3:2>2=h5080376gm6;29 7>52j:0b?6>:898mg3=83.94?4l0:l1<45$3:1>f6oe93:1(?6=:b28j7>62m10eo>50;&1<74n3:2>c=h5080:<65fae83>!4?:3i;7c<71;32?>ofk3:1(?6=:b28j7>628807dom:18'6=4=k91e>5?51298mdg=83.94?4l0:l1<4<6<21bm44?:%0;6?e73g83=7?:;:k`4n3:2>40<3`i<6=4+2909g5=i:1;1=:54ib494?"50;0h<6`=8082<>=nk<0;6)<72;a3?k4?93;276gl4;29 7>52j:0b?6>:0c8?le4290/>5<5c19m6=7=9k10en<50;&1<7c:9jf`<72-83>7m?;o0;5?7c32ci?7>5$3:1>f65<#:181o=5a29395c=;57>5bb83>5}#;9?1>5o4H86g?M?502P>i7mt14822?442;=1>94=8;06>4c=9m0:j7<9:0a9ykg22880bl85139m543=82d:?:4?;%374d9'65>=>2.9<449;%03e?0<,;:i6;5+21a92>"58m0=7)3=#:8?1:6=1785?!46?3<0(??7:79'64?=>2.9=l49;%02f?0<,;;h6;5+20f92>"59l0=7)<>f;48 7472?1/>??56:&167<13-89?784$307>3=#:;?1:6=2785?!45?3<0(?<7:79'67?=>2.9>l49;%01f?0<,;8h6;5+23f92>"5:l0=7)<=f;48 7572?1/>>?56:&177<13-88?784$317>3=#::?1:6=3785?!44?3<0(?=7:79'66?=>2.9?l49;%00f?0<,;9h6;5+22f92>"5;l0=7)<9?56:&107<13-8??784$367>3=#:=?1:6=4785?!43?3<0(?:7:79'61?=>2.98l49;%07f?0<,;>h6;5+25f92>"58?55:&117<23-8>?7<8c:&1=4<5jh1/>4<5609'6<5=>81/>4959268 7??2;3j7)592d8 <26209m7d<7b;29?l0e2900e<:8:188m7?72900e:>50;9j6=e=831b>5h50;9j510=831bih4?:%0;6?cc3g83=7>4;hg`>5<#:181ii5a29395>=nmk0;6)<72;gg?k4?93807dkn:18'6=4=mm1e>5?53:9j=6?=83.94?46399m6=7=821b5>950;&1<7<>;11e>5?51:9j=60=83.94?46399m6=7=:21b5>;50;&1<7<>;11e>5?53:9l55b=83.94?4>0b9m6=7=821d==l50;&1<7<68j1e>5?51:9l55?=83.94?4>0b9m6=7=:21d==650;&1<7<68j1e>5?53:9l551=83.94?4>0b9m6=7=<21d==850;&1<7<68j1e>5?55:9l553=83.94?4>0b9m6=7=>21d==:50;&1<7<68j1e>5?57:9l555=83.94?4>0b9m6=7=021d==<50;&1<7<68j1e>5?59:9l557=83.94?4>0b9m6=7=i21d==>50;&1<7<68j1e>5?5b:9lb`<72-83>7??c:l1<45$3:1>46d3g83=7j4;nd`>5<#:181==m4n3:2>`=!4?:3;;o6`=80824>=hn00;6)<72;33g>h5080:=65`f983>!4?:3;;o6`=80826>=hn>0;6)<72;33g>h5080:?65`f783>!4?:3;;o6`=80820>=hn<0;6)<72;33g>h5080:965`10694?"50;0:l;o0;5?7?32e:=<4?:%0;6?77k2d94<4>9:9l546=83.94?4>0b9m6=7=9h10c<>i:18'6=4=99i0b?6>:0`8?j77m3:1(?6=:02`?k4?93;h76a>0`83>!4?:3;;o6`=8082`>=hno0;6)<72;33g>h5080:i65`f583>!4?:3;;o6`=8082b>=n<=0;6)<72;60?k4?93:07d:=:18'6=4=<:1e>5?51:9j04<72-83>7:<;o0;5?4<3`>;6=4+290906=i:1;1?65f4e83>!4?:3>87c<71;68?l2d290/>5<5429m6=7==21b8o4?:%0;6?243g83=784;h6b>5<#:1818>5a29393>=n<00;6)<72;60?k4?93207d:7:18'6=4=<:1e>5?59:9j02<72-83>7:<;o0;5?g<3`>=6=4+290906=i:1;1n65f4483>!4?:3>87c<71;a8?l5a290/>5<5429m6=7=l21b9>4?:%0;6?353g83=7>4;h72>5<#:1819?5a29395>=n=90;6)<72;71?k4?93807d:i:18'6=4==;1e>5?53:9j1f<72-83>7;=;o0;5?2<3`?i6=4+290917=i:1;1965f5`83>!4?:3?97c<71;48?l3>290/>5<5539m6=7=?21b954?:%0;6?353g83=764;h74>5<#:1819?5a2939=>=n=?0;6)<72;71?k4?93k07d;::18'6=4==;1e>5?5b:9j11<72-83>7;=;o0;5?e<3`>n6=4+290917=i:1;1h65fe383>!4?:3o:7c<71;28?lc7290/>5<5e09m6=7=921bhh4?:%0;6?c63g83=7<4;hfg>5<#:181i<5a29397>=nlj0;6)<72;g2?k4?93>07djm:18'6=4=m81e>5?55:9j`d<72-83>7k>;o0;5?0<3`n26=4+2909a4=i:1;1;65fd983>!4?:3o:7c<71;:8?lb0290/>5<5e09m6=7=121bh;4?:%0;6?c63g83=7o4;hf6>5<#:181i<5a2939f>=nl:0;6)<72;g2?k4?93i07dj=:18'6=4=m81e>5?5d:9j`4<72-83>7k>;o0;5?c<3`n;6=4+2909a4=i:1;1j65fcg83>!4?:3o:7c<71;33?>odm3:1(?6=:d38j7>628;07dmk:18'6=4=m81e>5?51398mfe=83.94?4j1:l1<4<6;21boo4?:%0;6?c63g83=7?;;:k`e?6=,;296h?4n3:2>43<3`o26=4+2909a4=i:1;1=;54id:94?"50;0n=6`=80823>=nm>0;6)<72;g2?k4?93;376gj6;29 7>52l;0b?6>:0;8?lc2290/>5<5e09m6=7=9h10eh:50;&1<7b:9ja6<72-83>7k>;o0;5?7d32coj7>5$3:1>`75<#:181i<5a29395`=h5080:j65`12a94?"50;0:?o5a29394>=h9:k1<7=83827g=i:1;1=65`12;94?"50;0:?o5a29396>=h9:21<7=83827g=i:1;1?65ff283>!4?:3l97c<71;28?l`6290/>5<5f39m6=7=921bj=4?:%0;6?`53g83=7<4;hge>5<#:181j?5a29397>=h9=;1<7=838205=i:1;1<65`12d94?"50;0:8=5a29395>=h9:o1<7=838205=i:1;1>65`12f94?"50;0:8=5a29397>=h9;l1<7=83826`=i:1;1<65`13f94?"50;0:>h5a29395>=h9;h1<7=83826`=i:1;1>65`13c94?"50;0:>h5a29397>=h9;31<7=83826`=i:1;1865`13:94?"50;0:>h5a29391>=h9;=1<7=83826`=i:1;1:65`13494?"50;0:>h5a29393>=h9;?1<7=83826`=i:1;1465`13694?"50;0:>h5a2939=>=h9;91<7=83826`=i:1;1m65`13094?"50;0:>h5a2939f>=h9;:1<7=83826`=i:1;1o65`10d94?"50;0:>h5a2939`>=h98o1<7=83826`=i:1;1i65`10f94?"50;0:>h5a2939b>=h98i1<7=83826`=i:1;1==54o03a>5<#:181=?k4n3:2>47<3f;:m7>5$3:1>44b3g83=7?=;:m25<<72-83>7?=e:l1<4<6;21d=<650;&1<7<6:l1e>5?51598k470290/>5<513g8j7>628?07b?<6;29 7>5288n7c<71;35?>i6;<0;6)<72;31a>h5080:;65`12694?"50;0:>h5a29395==b:9l566=83.94?4>2d9m6=7=9j10c<:0f8?j7593:1(?6=:00f?k4?93;n76a>1783>!4?:3;9i6`=8082b>=n1:o1<7=838:7a=i:1;1<65f92a94?"50;02?i5a29395>=n1:h1<7=838:7a=i:1;1>65f92c94?"50;02?i5a29397>=nk80;6)<72;a3?k4?93:07dli:18'6=4=k91e>5?51:9jfa<72-83>7m?;o0;5?4<3`hh6=4+2909g5=i:1;1?65fbc83>!4?:3i;7c<71;68?ldf290/>5<5c19m6=7==21bn44?:%0;6?e73g83=784;h`;>5<#:181o=5a29393>=nj>0;6)<72;a3?k4?93207dl9:18'6=4=k91e>5?59:9jf0<72-83>7m?;o0;5?g<3`h?6=4+2909g5=i:1;1n65fb383>!4?:3i;7c<71;a8?ld6290/>5<5c19m6=7=l21bn=4?:%0;6?e73g83=7k4;hce>5<#:181o=5a2939b>=nil0;6)<72;a3?k4?93;;76gnd;29 7>52j:0b?6>:038?lgd290/>5<5c19m6=7=9;10ell50;&1<73:9jed<72-83>7m?;o0;5?7332cj57>5$3:1>f65<#:181o=5a293953=h5080:;65fc783>!4?:3i;7c<71;3;?>od=3:1(?6=:b28j7>628307dm;:18'6=4=k91e>5?51`98mf5=83.94?4l0:l1<4<6j21bo?4?:%0;6?e73g83=7?l;:kaa?6=,;296n>4n3:2>4b<3`h86=4+2909g5=i:1;1=h54i`:94?"50;0h<6`=8082b>=zj=:h6=4mc;294~"48<094l5G95f8L<4?3S?n6nu>5;35>75=:>0987<7:3795`<6l3;m6?851b8~jd3=9;1em;4>2:l250<73g;8;7>4$06;>42b3-;?57?;e:&14=<13-8;5784$32b>3=#:9h1:6=0b85?!47l3<0(?>j:79'65`=>2.9=<49;%026?0<,;;86;5+20692>"59<0=7)<>6;48 7702?1/><656:&15<<13-8:m784$33a>3=#:8i1:6=1e85?!46m3<0(??i:79'676=>2.9><49;%016?0<,;886;5+23692>"5:<0=7)<=6;48 7402?1/>?656:&16<<13-89m784$30a>3=#:;i1:6=2e85?!45m3<0(?2.9?<49;%006?0<,;986;5+22692>"5;<0=7)<<6;48 7502?1/>>656:&17<<13-88m784$31a>3=#::i1:6=3e85?!44m3<0(?=i:79'616=>2.98<49;%076?0<,;>86;5+25692>"5<<0=7)<;6;48 7202?1/>9656:&10<<13-8?m784$36a>3=#:=i1:6=4e85?!43m3<0(?:i:79'606=>2.99<4:;%066?3<,;?86?9l;%0:5?4ei2.95?491:&1=6<192.95:46359'6<>=:0k0(?l8:49'6g>==2.28=463g9'=17=1:l0e?6m:188m3d=831b=9950;9j6<6=831b;=4?::k15$3:1>`bobj3:1(?6=:df8j7>62;10eho50;&1<777<8:l1<4<732c2?:4?:%0;6??402d94<4>;:k:73<72-83>77<8:l1<4<532c2?84?:%0;6??402d94<4<;:m24a<72-83>7??c:l1<4<732e:;:m24<<72-83>7??c:l1<4<532e:<54?:%0;6?77k2d94<4<;:m242<72-83>7??c:l1<4<332e:<;4?:%0;6?77k2d94<4:;:m240<72-83>7??c:l1<4<132e:<94?:%0;6?77k2d94<48;:m246<72-83>7??c:l1<47??c:l1<4l;o0;5?e<3flo6=4+290955e=hnk0;6)<72;33g>h5080m76aia;29 7>528:h7c<71;33?>ia13:1(?6=:02`?k4?93;:76ai8;29 7>528:h7c<71;31?>ia?3:1(?6=:02`?k4?93;876ai6;29 7>528:h7c<71;37?>ia=3:1(?6=:02`?k4?93;>76a>1583>!4?:3;;o6`=80822>=h9891<7=83824f=i:1;1=:54o031>5<#:181==m4n3:2>4><3f;:=7>5$3:1>46d3g83=7?6;:m255<72-83>7??c:l1<4<6i21d==h50;&1<7<68j1e>5?51c98k46b290/>5<511a8j7>628i07b??a;29 7>528:h7c<71;3g?>ian3:1(?6=:02`?k4?93;n76ai4;29 7>528:h7c<71;3e?>o3<3:1(?6=:518j7>62910e9<50;&1<7<3;2d94<4>;:k75?6=,;2969=4n3:2>7=h5080876g;d;29 7>52=90b?6>:598m1e=83.94?4;3:l1<4<232c?n7>5$3:1>15o313:1(?6=:518j7>62110e9650;&1<7<3;2d94<46;:k73?6=,;2969=4n3:2>d=h5080i76g;5;29 7>52=90b?6>:b98m6`=83.94?4;3:l1<4?7>5$3:1>04>6`=8082?>o283:1(?6=:408j7>62;10e9h50;&1<7<2:2d94<4<;:k6g?6=,;2968<4n3:2>1=h5080>76g:a;29 7>52<80b?6>:798m0?=83.94?4:2:l1<4<032c>47>5$3:1>04>6`=808:?>o2>3:1(?6=:408j7>62h10e8;50;&1<7<2:2d94<4m;:k60?6=,;2968<4n3:2>f=h5080o76gj2;29 7>52l;0b?6>:198m`6=83.94?4j1:l1<4<632coi7>5$3:1>`7ock3:1(?6=:d38j7>62=10eil50;&1<73=h5080<76gk8;29 7>52l;0b?6>:998ma1=83.94?4j1:l1<4<>32co:7>5$3:1>`7oc;3:1(?6=:d38j7>62j10ei<50;&1<7`=h5080m76glf;29 7>52l;0b?6>:028?leb290/>5<5e09m6=7=9810enj50;&1<72:9jgf<72-83>7k>;o0;5?7432chn7>5$3:1>`75<#:181i<5a293950=h5080::65fe983>!4?:3o:7c<71;34?>ob?3:1(?6=:d38j7>628207dk9:18'6=4=m81e>5?51898m`3=83.94?4j1:l1<4<6i21bi94?:%0;6?c63g83=7?m;:kf7?6=,;296h?4n3:2>4e<3`nm6=4+2909a4=i:1;1=i54ie694?"50;0n=6`=8082a>=nk00;6)<72;g2?k4?93;m76a>3b83>!4?:3;8n6`=8083?>i6;h0;6)<72;30f>h5080:76a>3883>!4?:3;8n6`=8081?>i6;10;6)<72;30f>h5080876gi3;29 7>52o80b?6>:198mc7=83.94?4i2:l1<4<632cm<7>5$3:1>c46`=8080?>i6<80;6)<72;374>h5080;76a>3g83>!4?:3;?<6`=8082?>i6;l0;6)<72;374>h5080976a>3e83>!4?:3;?<6`=8080?>i6:o0;6)<72;31a>h5080;76a>2e83>!4?:3;9i6`=8082?>i6:k0;6)<72;31a>h5080976a>2`83>!4?:3;9i6`=8080?>i6:00;6)<72;31a>h5080?76a>2983>!4?:3;9i6`=8086?>i6:>0;6)<72;31a>h5080=76a>2783>!4?:3;9i6`=8084?>i6:<0;6)<72;31a>h5080376a>2583>!4?:3;9i6`=808:?>i6::0;6)<72;31a>h5080j76a>2383>!4?:3;9i6`=808a?>i6:90;6)<72;31a>h5080h76a>1g83>!4?:3;9i6`=808g?>i69l0;6)<72;31a>h5080n76a>1e83>!4?:3;9i6`=808e?>i69j0;6)<72;31a>h5080:<65`10`94?"50;0:>h5a293954=4:9l541=83.94?4>2d9m6=7=9<10c<=9:18'6=4=9;o0b?6>:048?j74=3:1(?6=:00f?k4?93;<76a>3583>!4?:3;9i6`=8082<>=h9:91<7=83826`=i:1;1=454o011>5<#:181=?k4n3:2>4g<3f;8=7>5$3:1>44b3g83=7?m;:m275<72-83>7?=e:l1<4<6k21d=?m50;&1<7<6:l1e>5?51e98k446290/>5<513g8j7>628o07b?>6;29 7>5288n7c<71;3e?>o>;l0;6)<72;;0`>h5080;76g63b83>!4?:338h6`=8082?>o>;k0;6)<72;;0`>h5080976g63`83>!4?:338h6`=8080?>od93:1(?6=:b28j7>62910eoh50;&1<7;:ka`?6=,;296n>4n3:2>7=h5080876gmb;29 7>52j:0b?6>:598mgg=83.94?4l0:l1<4<232ci57>5$3:1>f6oe?3:1(?6=:b28j7>62110eo850;&1<74n3:2>d=1<7*=838`4>h5080i76gm2;29 7>52j:0b?6>:b98mg7=83.94?4l0:l1<45$3:1>f6ofm3:1(?6=:b28j7>628:07dok:18'6=4=k91e>5?51098mde=83.94?4l0:l1<4<6:21bmo4?:%0;6?e73g83=7?<;:kbe?6=,;296n>4n3:2>42<3`k26=4+2909g5=i:1;1=854ib:94?"50;0h<6`=80822>=nk>0;6)<72;a3?k4?93;<76gl6;29 7>52j:0b?6>:0:8?le2290/>5<5c19m6=7=9010en:50;&1<7a:9jg6<72-83>7m?;o0;5?7e32ch>7>5$3:1>f65<#:181o=5a29395a=h5080:i65fa983>!4?:3i;7c<71;3e?>{e<;?1<7950;2x 6622;>o58:0;66g=0583>>o58<0;66g=0783>>o58>0;66a=7e83>>{e<;91<7950;2x 6622;>o58:0;66g=0583>>o58<0;66g=0783>>o58>0;66a=7e83>>{e1?21<7>50;2x 6622;hh7E91/?==51728 66328<;7ps|2g`94?4|V;li706j3;c1?xu5n00;6?uQ2g;89=c52h80q~k;50;0xZ7`2342oi7o=;|q1b1<72;qU>k:4=9fg>d452z\1b6=:0mi1m?5rs3d1>5<5sW8m>637dc8b6>{t:o;1<7ci3k97p}=f183>7}Y:o:015j6:`08yv4bn3:1>vP=eg9>=i;1v?kj:181[4bm273h:4n2:p6`b=838pR?kk;<:g2?g53ty9in4?:3y]6`e<51n>6l<4}r0fe?6=:rT9il528e19e7=z{;o26=4={_0f=>;?l;0j>6s|2d:94?4|V;o3706k1;c1?xu5m>0;6?uQ2d589=b72h80q~h:50;0xZ7c3342hh7o=;|q1a6<72;qU>h=4=9a`>d47>52z\1a7=:0jh1m?5rs3g2>5<5sW8n=637c`8b6>{t:ml1<7d03k97p}=dd83>7}Y:mo015m8:`08yv4cl3:1>vP=de9>;?k80j>6s|2e594?4|V;n<706l0;c1?xu5l?0;6?uQ2e489=da2h80q~i<50;0xZ7b5342in7o=;|q1`4<72;qU>i?4=9`b>d452z\1`5=:0k31m?5rs3ae>5<5sW8hj637b98b6>{t:jo1<7e?3k97p}=ce83>7}Y:jn015l9:`08yv4dk3:1>vP=cb9><51h:6l<4}r0`3?6=:rT9o:528c29e7=z{;i=6=4={_0`2>;?io0j>6s|2b794?4|V;i>706ne;c1?xu5k=0;6?uQ2b689=gc2h80q~n?50;0xZ7e6342jm7o=;|q1g5<72;qU>n>4=9c:>d452z\1bc=:0l=1m?5rs3df>5<5sW8mi637e78b6>{t:on1<7b=3k97p}=fb83>7}Y:oi015k;:`08yv4a>3:1>vP=f79>;?i10j>6s|9983>7}Y1116:ll52178yv?12909wS79;<4bf?47<2wx584?:3y]=0=:>hh1>=<4}r;7>5<5sW3?708nb;037>{t1:0;6?uQ929>2dg=:9=0q~7=:181[?5347}Y0l16:lo52108yv>c2909wS6k;<4be?47;2wx4n4?:3y]j81>=94}r:a>5<5sW2i708l2;032>{t0h0;6?uQ8`9>2f4=:9?0q~66:181[>>347;0jm09n>526b09655<5>=o6?6;;<5;4=859>301:o6:3:7?81e<3838638b881<1=:?kk1>5:4=6`a>7>334=io7<74:?43`<50=16;:h5296892>72;2?70971;0;0>;00;09495279196=2<5>2?6?6;;<5;1?4?<27<4;4=859>3=1=:1>01:66:3:7?81?i38386388c81<1=:?1i1>5:4=6:g>7>334=3i7<74:?45296892?62;2?70962;0;0>;01=09495278796=2<5>3=6?6;;<5:3?4?<27<554=859>301:7n:3:7?81>j38386389b81<1=:?0n1>5:4=6;e>7>334=j<7<74:?4e4<50=16;l<5296892g42;2?709n4;0;0>;0i<0949527`496=2<5>k<6?6;;<5b3dd=:1>01:ol:3:7?81fl3838638ad81<1=:?hl1>5:4=6`3>7>334=i=7<74:?4f7<50=16;o=5296892d22;2?709m6;0;0>;0j>0949527c:96=2<5>9o6?6;;<574=859>30c=:1>01:86:3:7?810<38386387881<1=:?>k1>5:4=65a>7>334=h5296892272;2?709;1;0;0>;0<;09495275196=2<5>>?6?6;;<571?4?<27<8;4=859>311=:1>01::6:3:7?813i38386384c81<1=:?=i1>5:4=66g>7>334=?i7<74:?40c<50=16;8>5296892362;2?709:2;0;0>;0==09495274796=2<5>?=6?6;;<563?4?<27<954=859>30?=:1>01:;n:3:7?812j38386385b81<1=:?5:4=67e>7>334==<7<74:?424<50=16;;<5296892042;2?70994;0;0>;0><09495277496=2<5><<6?6;;<5533d=:1>01:8l:3:7?811l38386386d81<1=:??l1>5:4=653>7>334=<=7<74:?437<50=16;:=5296892122;2?70986;0;0>;0?>09495276:96=26=4={_:6?80d938;;6s|8583>7}Y0=16:n?52148yv>42909wS6<;<4`5?47=2wx4?4?:3y]<7=:>j;1>=:4}r:2>5<5sW2:708l1;036>{t090;6<:t^92891652;2270:?1;0;=>;3890944523gd96=?<5:ln6?66;<1e`?4?1278jn4=889>7cd=:990198>:3::?822m383563;5`81<<=:<<<1>574=571>7>>34>?i7<79:?70d<50016898529;891252;2270:;1k809<>5rs6d94?1|V>l01;6j:041?80313<:708;9;c1?803:38;?639a88142=:>1n1>5:4}r5f>5<2sW=n708<8;42?80403k9708=f;037>;1i009<;5rs6f94?4|V>n01;o6:326?xu0k3:1>vP8c:?5e<<58=1v4h50;0a[?a34?;978>;<73`?0634>n978>;<6f2?0634>n;78>;<6fm;78>;<6em578>;<6ee?0634>oo78>;<6g`?0634?;478>;<73=?0634>o978>;<6g2?0634?;i78>;<73b?0634?;:78>;<72b?0634?9:78>;<713?0634?9478>;<71=?0634?9m78>;<71f?0634?9o78>;<71`?0634?9i78>;<714?0634?9=78>;<716?0634?9?78>;<710?0634?9978>;<71b?0634?o:72;h870;ka;0a7>;1i009l3:1>vP6d:?5e=<58>1v4m50;36[?d34>;>78>;<635?0634>;<78>;<1eb?06349mi78>;<1e`?06349mo78>;<6`b?47<278j<491:?0a`<19278il491:?0a3<19278i?491:?0``<19278hl491:?5e=<58?168==51548916128>=70:?9;372>;38j0:8;5rs8`94?1|V0h01;77:73893??2h801;m::`0893ef2;:870862;037>;1i109<85rs8c94?0|V0k01;mn:321?80em38;>639a98141=:>ho1>==4=7`b>7653ty2=7>52z\:5>;1i10970;>f;c1?80f038;?6s|7c83>0g|V>h019>=:4d891662?:4d896`a2hj:4d896`c2hl:4d892532?>01:2;7e?80>03?m708l5;7e?80d>3?m708l4;7e?817=3?m709?2;7e?80am3?m708ia;7e?80a>3?m708i2;7e?80bm3?m708ja;7e?80b>3?m708j2;7e?82193?m70::e;7e?822i3?m70::6;7e?822:3?m70:;e;7e?823i3?m70:;6;7e?823:3?m70:3f;7e?835>3?m70;=7;7e?83503?m70;=9;7e?835i3?m70;=b;7e?835k3?m70;=d;7e?835m3?m70;=0;7e?83593?m70;=2;7e?835;3?m70;=4;7e?835=3?m70;=f;47?83c038i863:d881f1=:=mk1>o:4=2d2>0`<5:on68h4=2gb>0`<5:o=68h4=2g1>0`<5:nn68h4=2fb>0`<5?2o68h4=7:`>0`<5=:86;l4=525>3d<5=:26;l4=52`>3db2y]21=:?;i19k5272`91c=:?;o19k5272591c=:?:819k5272291c=:?:?19k5231591c=:;8n19k5232191c=:;=319k5234d91c=:;>?19k5236d91c=:;1;19k5239191c=:;1?19k5231;91c=:;9h19k5231f91c=:;9l19k5230391c=:;8919k5230791c=:;8=19k5230;91c=:;8h19k5230d91c=:;;;19k5233191c=:;;?19k5233591c=:;;319k5233`91c=:;;n19k5233d91c=:;:;19k5232791c=:;:=19k5232;91c=:;:h19k5232f91c=:;:l19k5235391c=:;=919k5235791c=:;==19k5235`91c=:;=n19k5235d91c=:;<;19k5234191c=:;919k5236591c=:;>319k5236`91c=:;>n19k52314921=:;8i1:952320921=:;=21:95234g921=:;>>1:95236g921=:;1:1:952390921=:;1>1:95231:921=:;9k1:95231a921=:;9o1:952302921=:;881:952306921=:;8<1:95230:921=:;8k1:95230g921=:;;:1:952330921=:;;>1:952334921=:;;21:95233c921=:;;i1:95233g921=:;::1:952326921=:;:<1:95232:921=:;:k1:95232a921=:;:o1:952352921=:;=81:952356921=:;=<1:95235c921=:;=i1:95235g921=:;<:1:952340921=:;<>1:952344921=:;<21:95234c921=:;81:952364921=:;>21:95236c921=:;>i1:9527cf93==:>0l19k526`291c=:>1h19k5266:91c=:>>=19k5266491c=:>>?19k5266691c=:>>919k5266091c=:>>;19k5266291c=:>?l19k526bf91c=:>ji19k5268191c=:>0=19k5268491c=:>;919k5263691c=:>;?19k5263491c=:>;=19k5263:91c=:>;319k5263c91c=:>=919k5265:91c=:>=<19k5265591c=:>::19k5262591c=:>:919k5262691c=:>:?19k5262491c=:>9219k5261;91c=:>9>19k524e391c=:9=19k524d391c=:19k5255091c=:===19k5255791c=:==k19k5255:91c=:==n19k5255`91c=:=j319k525b491c=:=j819k525cg91c=:=kk19k525c491c=:=k819k525`g91c=:=hk19k525`491c=:=1?19k5259091c=:=>o19k5256c91c=:=><19k5256091c=:=?o19k5257c91c=:=?<19k5257091c=:=m21;5525e;93==:=mk1;5526`091c=:>h>19k5270191c=:>1319k5282g91c=:0l919k528d091c=:0l;19k528d291c=:0mo19k528ef91c=:0mi19k528e`91c=:0mk19k528e;91c=:0m219k528e591c=:0m<19k528e791c=:0m919k528e091c=:0m;19k528e291c=:0jl19k528bg91c=:0jn19k528ba91c=:0jh19k528bc91c=:0j219k528b591c=:0j<19k528b791c=:0j>19k528b191c=:0j819k528b391c=:0j:19k528cd91c=:0kn19k528ca91c=:0kh19k528cc91c=:0k319k528c:91c=:0k=19k528c491c=:0k?19k528c691c=:0k819k528c391c=:0k:19k528`d91c=:0ho19k528`f91c=:0hi19k528``91c=:0hk19k528`;91c=:0l=19k528d491c=:0l?19k528d691c=:0ml19k528e691c=:0j319k528cg91c=:0k919k528`:91c=:?>n19k5279:91c=:?0919k5278g91c=:?h319k527c691c=:?k319k527cc91c=:?kh19k527ca91c=:?>o19k5276d91c=:?1:19k5279391c=:?1819k5279191c=:?1>19k5279791c=:?1<19k5279591c=:?1319k5279c91c=:?1h19k5279a91c=:?1n19k5279g91c=:?1l19k5278291c=:?0;19k5278091c=:?0>19k5278791c=:?0<19k5278591c=:?0219k5278;91c=:?0k19k5278`91c=:?0i19k5278f91c=:?0l19k527`291c=:?h;19k527`091c=:?h919k527`691c=:?h?19k527`491c=:?h=19k527`:91c=:?hk19k527``91c=:?hi19k527`f91c=:?ho19k527`d91c=:?k:19k527c391c=:?k819k527c191c=:?k?19k527c491c=:?k=19k527c:91c=:?:n19k5275:91c=:?<919k5274g91c=:??319k5276691c=:?>319k5276c91c=:?>h19k5276a91c=:?:o19k5272d91c=:?=:19k5275391c=:?=819k5275191c=:?=>19k5275791c=:?=<19k5275591c=:?=319k5275c91c=:?=h19k5275a91c=:?=n19k5275g91c=:?=l19k5274291c=:?<;19k5274091c=:?<>19k5274791c=:?<<19k5274591c=:?<219k5274;91c=:?:19k5276391c=:?>819k5276191c=:?>?19k5276491c=:?>=19k5276:91c=:>0>19k5268791c=:>j319k5264391c=:>=?19k5265691c=:>:819k5262391c=:<991;=52414935=:<931;=5241a935=z{031<7=c|50>n6<8=;<132?53349:o7=;;<106?53349?47=;;<16a?53349<87=;;<14a?533493<7=;;<1;6?53349387=;;<137=;;<120?53349::7=;;<127=;;<170?53349?:7=;;<17e?53349?o7=;;<17a?53349><7=;;<166?53349>87=;;<162?53349>47=;;<16e?53349>o7=;;<154?53349=>7=;;<150?53349=:7=;;<157=;;<142?53349<47=;;<14e?53349>h7o8;<66=?g034>>97o8;<665?g034>?h7o8;<67=?g034>?97o8;<675?g034>8h7o8;<466?47:27=9?4=059>0a5=:13018m::`5890e62h=018lk:`5890d>2h=018l::`5890d62h=018ok:`5890g>2h=018o::`5890>62h=0189k:`58901>2h=0189::`5890162h=0188k:`58900>2h=0188::`5890062h=01>kk:`5896c>2h=01>k::`5896c62h=01>jk:`5896b>2h=01;;>:`089164209270:?3;;03>;38:02?;524119=63<5=:86?6i;<637?4>827?<;46389>050=1:=019>9:815?827>338963;07814>4=52:><5>34>;577<7:?74<<>;?168=759278916>2;2m70:?9;0:4>;38j0hj63;0b8`a>;38j0hh63;0b8`g>;38j0hn63;0b8`e>;38j0m<63;0b8:7<=:<9i15>94=52`><5134>;o77<5:?74f<50o168=m52828yv25?3:1>v3;26813a=:<;91>=84}r63b?6=:r7?075=:9=0q~:=2;296~;3:809<>52431962b:=7>52z?754<5?m168?852158yv26:3:1>v3;13813a=:<;<1>=84}r627?6=:r7?=>4=7e9>070=:9>0q~:>6;296~;39?09;i5243496539:7>52z?763<5?m168?;52158yv26<3:1>v3;15813a=:<;21>=94}r623?6=:r7?=:4=7e9>07>=:9<0q~:>8;296~;39109;i5243:9652:o7>52z?75f<5?m168?652178yv2503:1>v3;29813a=:<;?1>=84}r621?6=:r7?=84=7e9>07?=:9=0q~:>9;296~;39009;i5243;9650:m7>52z?75d<5?m168?752168yv26l3:1>v3;1e813a=:<;31>=;4}r61=?6=:r7?>44=7e9>073=:9>0q~:>b;296~;39k09;i524029651:i7>52z?75`<5?m168<>52148yv26n3:1>v3;1g813a=:<8:1>=:4}r614?6=:r7?>=4=7e9>046=:9?0q~:>0;296~;39909;i524379653987>52z?764<58;168?;526f8yv5d13:14v3574=2gf>7>>349nm7<79:?0a3<50016?h<529;896bb2;2270=ka;0;=>{t;jk1<7765349h;7<8d:p7fd=838p1>m9:320?85d038:;<63g?7412wx8oh50;0x916a2;:=70:?c;db?xu3jm0;6?u241d9652<5=:h6k74}r6ag?6=:r7?05e=n11v9lm:181825?38;963;0b8e3>{t76134>;o7h9;|q7f<<72;q68?952168916d2o?0q~:m8;296~;3:>09<:5241a9542i;7>52z?765<58<168=m51018yv2e>3:1>v3;218143=:<9i1=>64}r6a1?6=:r7?>=4=059>05e=9880q~:m4;296~;3:909<:5241a9547i>7>52z?75c<58<168=m51028yv2e93:1>v3;1g8143=:<9i1==h4}r6a4?6=:r7?=k4=059>05e=99o0q~:nf;296~;39o09<:5241a955gji7>52z?75`<58<168=m5fg9~w1gc2909w0:>e;032>;38j0m86s|4`a94?4|5=;n6?>;;<63=?7412wx8ll50;0x917b2;:<70:?9;db?xu3ih0;6?u240`9653<5=:26k74}r6b=?6=:r7?=o4=079>05?=n11v9o8:181826j38;863;088e3>{t76034>;57h9;|q7e0<72;q682o?0q~:n4;296~;39m09<;5241;9542j?7>52z?75a<58=168=751018yv2f:3:1>v3;1e8142=:<931=>64}r6b5?6=:r7?=l4=049>05?=9880q~:n0;296~;39h09<;5241;95472j7>52z?75d<58=168=751028yv2>m3:1>v3;1`8142=:<931==h4}r6:g?6=:r7?=44=049>05?=99o0q~:6b;296~;39009<;5241;955g2m7>52z?75<<58=168=75fg9~w1?>2909w0:>9;033>;3800m86s|48:94?4|5=;>6?>:;<632?7412wx84950;0x91722;:=70:?6;db?xu31?0;6?u24079652<5=:=6k74}r6:1?6=:r7?=84=069>050=n11v97;:181826k38;963;078e3>{t<091<776134>;:7h9;|q7=4<72;q683j7>52z?75=<58<168=851018yv2?m3:1>v3;198143=:<9<1=>64}r6;`?6=:r7?=54=059>050=9880q~:7c;296~;39109<:5241495473n7>52z?752<58<168=851028yv2?i3:1>v3;168143=:<9<1==h4}r6;=?6=:r7?=:4=059>050=99o0q~:78;296~;39>09<:52414955g3:7>52z?751<58<168=85fg9~w1>22909w0:>4;032>;38?0m86s|49694?4|5=;?6?>;;<637?7412wx85=50;0x91732;:<70:?3;db?xu30;0;6?u24049653<5=:86k74}r6;5?6=:r7?=;4=079>055=n11v96?:181826>38;863;028e3>{t<>l1<776034>;?7h9;|q73`<72;q68<=5217891642o?0q~:8d;296~;39:09<;524119542h?7>52z?756<58=168==51018yv2d:3:1>v3;128142=:<991=>64}r6`5?6=:r7?=?4=049>055=9880q~:me;296~;39;09<;524119547i?7>52z?757<58=168==51028yv2f03:1>v3;138142=:<991==h4}r6:`?6=:r7?=<4=049>055=99o0q~:62;296~;39809<;52411955g3;7>52z?754<58=168==5fg9~w11d2909w0:>1;033>;38:0m86s|4bf94?0|5=<:6?69;<656?47:27?<>4;4:?743<3<27?<44;4:?74f<3<2wx8nm50;4x913b2;2=70::f;036>;38:0?>63;07876>;3800?>63;0b876>{t7>134>>n763;02874>;38?0?<63;08874>;38j0?<6s|4b;94?0|5=?96?69;<667?47:27?<>4;d:?743<3l27?<44;d:?74f<3l2wx8n650;4x912b2;2=70:;f;036>;38:0?o63;0787g>;3800?o63;0b87g>{t7>134>?n763;0287e>;38?0?m63;0887e>;38j0?m6s|4b794?0|5=>96?69;<677?47:27?<>4;9:?743<3127?<44;9:?74f<312wx8n:50;4x915b2;2=70:;38:0?463;0787<>;3800?463;0b87<>{t<>>1<7:t=521>d4<5:i36?>=;<1e5?4?>278j?4=039~w114290?w0:?1;c1?85d?38;;63=<4}r646?6=1}:;ol1m?523b59653<5:o=6?69;<1f3?47:2wx8:>50;6x96`b2h801>m8:327?85b:383:63;4k>09=;|q7g`<72jq6?n8526f896`e2;:970:91;42?822m3<:70::a;42?822>3<:70::2;42?823m3<:70:;a;42?823>3<:70:;2;42?824m3<:7p};7c83>7}:<981>584=502>7?33ty?;l4?:2y>057=:1<019<::321?825;38;?6s|46;94?5|5=:;6?69;<611?47;27?>>4=039~w11?290=w0=if;0;2>;3:?09=;<624?47:27?>>4=059~w110290=w0=ie;0;2>;3:?09<>5243:9655<5=826?><;<624?47;27?>>4=049~w111290:?v3==4=52e>76434>:=74;037>;39>09<>5240:9655<5=;h6?><;<621?47;27?=44=029>04g=:99019?k:320?826j38;?63;1d8146=:<8l1>==4=503>7643ty?;84?:01x96`d2;2=70:=7;036>;38o09=;<627?47:27?=;4=039>042=:98019?8:321?826038;>63;1b8147=:<8?1>=<4=53:>76534>:m7f;036>;3:9095<5s4=897o=;<500?4?>2wx;>?50;0x92572h801:584}r50;0:m095<5s4=887<77:?46cm50;0x92dc28ln706584}r:74?6=;r7362=;816;?h5309~w=262909w09=c;c1?814?383:6s|88:94?4|5:=o6?69;<63g?c>3ty35:4?:3y>72d=:1<019>l:d:8yv>>>3:1>v3<7881<3=:<9i1ik5rs9;6>5<5s49<;7<76:?74f05e=m=1v57?:181851l383:63;0b8f7>{t01l1<77>134>;o7ji;|q;<`<72;q6?;752948916d2m>0q~67d;296~;4>>094;5241a9g<=z{12h6=4={<151?4?>27?<44i0:p<=d=838p1>8<:3:5?82713im7p}78`83>7}:;?;1>584=52:>fc52z?01a<50?168=75ce9~w=>02909w0=:b;0;2>;3800ho6s|89494?4|5:?26?69;<63=?ee3ty3484?:3y>701=:1<019>6:bc8yv>?<3:1>v3<5481<3=:<931i45rs9:0>5<5s49>?7<76:?74<05?=m?1v59i:181853j383:63;088f1>{t0>n1<77>134>;57k;;|q;3f<72;q6?9;52948916>2l90q~68b;296~;4<:094;5241;9`c=z{1=j6=4={<175?4?>27?<44k4:p<2?=838p1>=i:3:5?82713i27p}77983>7}:;:n1>584=525>c652z?07g<50?168=85cg9~w=112909w0=<9;0;2>;38?0hi6s|86794?4|5:9<6?69;<632?ec3ty3;94?:3y>763=:1<019>9:ba8yv>0:3:1>v3<3081<3=:<9<1oo5rs952>5<5s499j7<76:?74350;0x964c2;2=70:?6;g:?xu?>o0;6?u233`96=0<5=:=6h64}r:5a?6=:r78>44=879>050=mo1v58k:181855?383:63;078f3>{t0?i1<77>134>;:7k9;|q;2g<72;q6??=5294891612l?0q~69a;296~;4:8094;524149a1=z{1<26=4={<12b?4?>27?<;4j3:p<31=838p1>?m:3:5?827>3nm7p}76783>7}:;831>584=525>a252z?052<50?168=85c89~w=032909w0=>5;0;2>;38:0m<6s|87194?4|5:;86?69;<637?ea3ty3:?4?:3y>747=:1<019><:bg8yv>193:1>v3<0g81<3=:<991oi5rs943>5<5s49;h7<76:?746055=m01v57m:18185?;383:63;028f<>{t00k1<77>134>;?7ki;|q;=<<72;q6?:h5294891642l=0q~664;296~;4?<094;524119a3=z{1226=4={<16b?4?>27?<>4j5:p<2c=838p1>:6:3:5?827;3o?7p}77283>7}:;:91>584=520>`552z?05a<50?168==5dg9~w=3c2909w0=?7;0;2>;38:0o86s|8`594?72s4=9o7<76:?540<58;169=;5329>15b=;:168h;5399>0`0=;1168h95399>0`>=;1168k95399>0c>=;1168k75399>0cg=;1168im5399>0ab=;1169=65399>15?=;1168i;5399>0a0=;1169=k5399>15`=;1169=85399~w=24290:8v382d81<3=:=9?1?95251f971=:5<5s4>hj7;31m?5rs9c1>5<3s4=8;7<79:?477<50016:?952948934?2h80q~6n1;291~;0:l09445272296=?<5>9>6?66;<412?4?>27=>:4n2:p{t00l1<7=t=707>7>134<997o=;<:0a?4?<2wx44k50;:x92dc2;2o7087b;c1?80d;38;96392281<3=:>;>1m?526469655<5>;86?66;<4;=?4?12wx4l;50;1x934f2;2=70:k2;0;=>;18>09445rs9c7>5<5?r7=>44=879>27g=i;168i?529;893612;2270:j1;0;=>;3n:09445252096=?<5<9;6?66;<701?4?127>?>4=889>16>=:13018=9:3::?834j383563:3881<<=:=:o1>574=41`>7>>34??=7<79:?67c<5001699:529;890252;2270;;7;0;=>;2<<09445255c96=?<5<>36?66;<77`?4?127>8o4=889>1f?=:13018m9:3::?83d:383563:bd81<<=:=kk1>574=4`5>7>>34?i>7<79:?6e`<500169lo529;890g12;2270;k8;0;`>;2l0094i525ec96=b7>515y>22>=:1301;98:3::?800>38356397481<<=:>>>1>574=750>7>>34<<>7<79:?534<50016::>529;8930a2;22708ld;0;=>;1kj09445269g93<=:><>1>=<4=716>7>134<8:7o=;<4b6?4?127=m94=889>2=g=:9901;6l:6;8yv>2j3:19v3:4c81<3=:<9919>52414916=:<9319>5241a916=z{1?j6=4:{<7727?<>4:1:?743<2927?<44:1:?74f<292wx48750;7x90222;2=70:?3;73?827>3?;70:?9;73?827k3?;7p}75983>0}:==81>584=520>1`<5=:=69h4=52:>1`<5=:h69h4}r:63?6==r7>?k4=879>055==j168=855b9>05?==j168=m55b9~w=31290>w0;;38:0>n63;0786f>;3800>n63;0b86f>{t07>134>;?7;n;<632?3f34>;57;n;<63g?3f3ty3994?:4y>160=:1<019><:4;891612<3019>6:4;8916d2<30q~6:3;291~;2;:094;5241191==:<9<1955241;91==:<9i1955rs971>5<2s4?8<7<76:?746<2?27?<;4:7:?74<<2?27?5<6>r7=on4n2:?7a4<50?16:=;5211890622:;018>k:23891c22:<019k9:24891c02:<019k7:24891`02:<019h7:24891`>2:<019hn:24891bd2:<019jk:248906?2:<018>6:24891b22:<019j9:248906b2:<018>i:24890612:<0q~6;e;292~;1?10j>63:4b8147=:=j31>584=4ab>76534?o57?id:?6`d<6nm1v5:k:185800?3k970;;9;036>;2k?094;525b59654<5;<7ge?7a92wx49m50;4x93112h8018:9:321?83d:383:63:c28147=:=m31=h84=4fb>4c13ty38o4?:7y>223=i;1699=5210890db2;2=70;mf;036>;2l00:ho525ec95ad56z?5318=4=039>1gg=:1<018lm:321?83c13;o<63:d`82`5=z{1>26=49{<447?g534?8h728i>70;ka;3`1>{t0=21<78t=751>d4<5<9j6?>=;<7a6?4?>27>n>4=039>1a?=9kk018jn:0`b?xu?<>0;6;u26639e7=:=:=1>=<4=4cf>7>134?jj73>3:1:v39718b6>;2;=09=;<7g=?7f<27>hl4>a59~w=22290=w089f;c1?834938;>63:a781<3=:=h=1>=<4=4f:>40334?om7?94:p<0e=83;:w0:k2;0;2>;38:02?h524119=6e<5=:864=m;<637??4i27?<;463d9>050=1:i019>9:81a?827>338m63;088:7`=:<9315>m4=52:><5e34>;577;l168=m592a8916d209i70:?c;;0e>{t0<;1<7=t=724>7>134=:87;1i<09<>5rs9;g>5<5s4>hj7;0?10j>6s|93094?5|5:=j6l<4=9g1>7>134=<;7o=;|q:64<72:q6?:65a39><`7=:1<01:99:`08yv?583:1?v3<778b6>;?m9094;527679e7=z{0;n6=4<{<146?g5342oi7<76:?4366}:;?o1m?528ea96=0<5>=:6l<4}r;2f?6=;r78:n4n2:?;`g<50?16;:>5a39~w<7f2908w0=9a;c1?8>ci383:6386g8b6>{t1831<7=t=24;>d4<51n26?69;<55a?g53ty2=54?:2y>730=i;164i652948920c2h80q~7>7;297~;4>=0j>637d681<3=:??i1m?5rs835>5<4s49=>7o=;<:g2?4?>27<:o4n2:p=43=839p1>8?:`089=b22;2=7099a;c1?xu>9:0;6>u234a9e7=:0m91>584=64;>d47>53z?01d331=i;1v4?>:18085203k9706k1;0;2>;0>?0j>6s|90294?5|5:?=6l<4=9f3>7>134==97o=;|q:4c<72:q6?8:5a39>;?kl094;527719e7=z{0:o6=4<{<164?g5342hh7<76:?4276}:;=i1m?528b`96=0<5><;6l<4}r;3e?6=;r788l4n2:?;gd<50?16;8h5a39~w<6?2908w0=;6;c1?8>d0383:6385e8b6>{t19=1<7=t=267>d4<51i<6?69;<56g?g53ty2<;4?:2y>714=i;164n852948923e2h80q~7?5;297~;4<90j>637c481<3=:?5<4s498i7o=;<:`0?4?>27<944n2:p=55=839p1>=l:`089=e42;2=709:8;c1?xu>8;0;6>u232c9e7=:0j81>584=674>d453z?07=300=i;1v4>?:180854>3k9706l0;0;2>;0=<0j>6s|8gd94?5|5:9?6l<4=9`e>7>134=>87o=;|q;ba<72:q6?>>5a39>ak3:1?v3<2d8b6>;?jj094;527439e7=z{1li6=4<{<11g?g5342in7<76:?4156}:;;21m?528c;96=0<5>>n6l<4}r:e;4n2:?;f=<50?16;9j5a39~w=`02908w0==4;c1?8>e?383:6384b8b6>{t0o<1<7=t=201>d4<51h=6?69;<57f?g53ty3j84?:2y>776=i;164o;52948922f2h80q~6i4;297~;49l0j>637b581<3=:?=31m?5rs9d1>5<4s49:m7o=;<:a6?4?>27<8:4n2:p?7:`089=d62;2=709;6;c1?xu?n90;6>u23049e7=:0k:1>584=666>d453z?051312=i;1v5kj:180856:3k9706ne;0;2>;0<:0j>6s|8df94?5|5:;;6l<4=9cg>7>134=?>7o=;|q;af<72:q6?=k5a39>:`08yv>bj3:1?v3<0b8b6>;?ik094;527529e7=z{1oj6=4<{<13e?g5342jm7<76:?47c6}:;1>1m?528d596=0<5>=h6l<4}r;12?6=;r784?4n2:?;a3<50?16;:l5a39~w<422908w0=70;c1?8>b=383:6387`8b6>{t1;>1<7=t=25f>d4<51o?6?69;<54=?g53ty2=k4?:2y>722=i;164ih5294892132h80q~7>4;297~;4=l0j>637d581<3=:??31m?5rs82:>5<4s49?47o=;<:`=?4?>27<9h4n2:p==:`089=db2;2=709:3;c1?xu?n:0;6>u230a9e7=:0k91>584=66;>d453z?04336b=i;1v>m>:181850l3k970=8c;0;2>{t;j:1<7d4<5:=j6?69;|q0fc<72;q6?:75a39>72>=:1<0q~=me;296~;4?>0j>63<7781<3=z{:hh6=4={<147?g5349<>7<76:p7gd=838p1>9>:`0896172;2=7p}7}:;?l1m?5237g96=052z?02a7>13ty8n;4?:3y>731=i;16?;852948yv5e=3:1>v3<648b6>;4>=094;5rs2`7>5<5s49=?7o=;<156?4?>2wx?o=50;0x96062h801>8?:3:5?xu4j80;6?u234f9e7=:;584}r1a4?6=:r789o4n2:?01d<50?1v>oi:18185213k970=:8;0;2>{t;ho1<7d4<5:?=6?69;|q0ea<72;q6?8;5a39>702=:1<0q~=nc;296~;4=:0j>63<5381<3=z{:ki6=4={<165?g5349><7<76:p7dg=838p1>:i:`08962b2;2=7p}7}:;=n1m?5235a96=052z?00g383:6s|3`794?4|5:>>6l<4=267>7>13ty8m94?:3y>715=i;16?9<52948yv5f;3:1>v3<408b6>;4<9094;5rs2c1>5<5s498j7o=;<10a?4?>2wx?l?50;0x965c2h801>=l:3:5?xu4i90;6?u232`9e7=:;:k1>584}r1:b?6=:r78?44n2:?07=<50?1v>7j:181854?3k970=<6;0;2>{t;0n1<7d4<5:9?6?69;|q0=g<72;q6?>?5a39>766=:1<0q~=6a;296~;4:o0j>63<2d81<3=z{:326=4={<11`?g53499o7<76:p7<>=838p1>7}:;;31m?5233:96=052z?062;4=879~w6?22909w0==5;c1?855<383:6s|38694?4|5:886l<4=201>7>13ty85>4?:3y>777=i;16??>52948yv5>:3:1>v3<1g8b6>;49l094;5rs2;3>5<5s49:n7o=;<12e?4?>2wx?5h50;0x967>2h801>?7:3:5?xu40l0;6?u23059e7=:;8<1>584}r1;`?6=:r78=84n2:?051<50?1v>6l:181856;3k970=>2;0;2>{t;1h1<7d4<5:;;6?69;|q075c=:1<0q~=79;296~;48m0j>63<0b81<3=z{:236=4={<13f?g5349;m7<76:p7=1=838p1>>6:`08966?2;2=7p}7}:;1?1m?5239696=052z?0<67>13ty8ni4?:3y>723=i;16?::52948yv5e:3:1>v3<5g8b6>;4=l094;5rs2c4>5<5s49?57o=;<172wx?4m50;0x96542h801>==:3:5?xu4180;6?u230f9e7=:;8i1>584}r1;2?6=:r78<:4n2:?043<50?1v:hj:18181el3;j86387e81<3=z{1:26=4={<5a`?7ei27<454=879~w=732909w09md;3gf>;01:094;5rs93e>5<5s4=ih7?i1:?4=`<50?1v56=4={<5a`?7>827;0j0094;5rs91a>5<5s4=ih7?n2:?4fd<50?1v5=l:18181el3;j9638bc81<3=z{19o6=4={<5a`?7f?27;0?l094;5rs923>5<5s4=ih7?nc:?43c<50?1v5>>:18181el3;i<6388181<3=z{1:96=4={<5a`?7e:27<4<4=879~w=642909w09md;3a1>;00;094;5rs927>5<5s4=ih7?m7:?4<6<50?1v5>::18181el3;i56388581<3=z{1:=6=4={<5a`?7ek27<484=879~w=602909w09md;3ab>;00?094;5rs92;>5<5s4=ih7?l1:?4<2<50?1v5>n:18181el3;h86388881<3=z{1:i6=4={<5a`?7d?27<4l4=879~w=6d2909w09md;3`e>;00k094;5rs92g>5<5s4=ih7?lc:?4j:18181el3;hi6388e81<3=z{1:m6=4={<5a`?7c927<4h4=879~w=772909w09md;3g0>;00o094;5rs932>5<5s4=ih7?k6:?4=5<50?1v5?=:18181el3;o56389081<3=z{1;86=4={<5a`?7ck27<5?4=879~w=722909w09md;3gb>;01=094;5rs935>5<5s4=ih7?j1:?4=0<50?1v5?8:18181el3;n?6389781<3=z{1;36=4={<5a`?7b=27<5:4=879~w=7>2909w09md;3f=>;011094;5rs93b>5<5s4=ih7?jb:?4=<<50?1v5?m:18181el3;ni6389`81<3=z{1;h6=4={<5a`?7a827<5o4=879~w=7c2909w09md;3e0>;01j094;5rs93f>5<5s4=ih7?i6:?4=a<50?1v5;0i8094;5rs900>5<5s4=ih7?98:?4e7<50?1v5<;:18181el3;=n638a281<3=z{18>6=4={<5a`?71l27;0i<094;5rs904>5<5s4=ih7?83:?4e3<50?1v5<7:18181el3;<9638a681<3=z{1826=4={<5a`?70?27;0ih094;5rs90`>5<5s4=ih7?8d:?4eg<50?1v5;0il094;5rs913>5<5s4=ih7?78:?4ec<50?1v5=>:18181el3;3m638b181<3=z{1996=4={<5a`?7?k27;0j;094;5rs917>5<5s4=ih7?62:?4f6<50?1v5=9:18181el3;29638b481<3=z{19<6=4={<5a`?7>?27;0j>094;5rs91:>5<5s4=ih7?6e:?4f=<50?1v:lj:18081el3;=86387e8b6>;0;m094;5rs6a:>5<4s4=ih7?nf:?4<=;01:0j>6385281<3=z{>nm6=4<{<5a`?7b>27<5h4n2:?41`<50?1v:kn:18081el3;=j638a88b6>;0>0094;5rs6d6>5<4s4=ih7?75:?4f1;0j00j>6387881<3=z{>li6=4<{<5a`?7f927;0?k094;5rs6dg>5<4s4=ih7?n6:?4ff;0?l0j>6383d81<3=z{>i;6=4<{<5a`?7fj27<;k4n2:?47c<50?1v:m>:18081el3;ji638818b6>;0<9094;5rs6a1>5<4s4=ih7?m1:?4<4;00;0j>6384381<3=z{>i?6=4<{<5a`?7e>27<4>4n2:?406<50?1v:m::18081el3;i4638858b6>;0<=094;5rs6a5>5<4s4=ih7?mb:?4<0;00?0j>6384781<3=z{>i36=4<{<5a`?7d827<4:4n2:?402<50?1v:mn:18081el3;h?638888b6>;0<0094;5rs6aa>5<4s4=ih7?l6:?4;00k0j>6384c81<3=z{>io6=4<{<5a`?7dj27<4n4n2:?40f<50?1v:mj:18081el3;hh6388e8b6>;05<4s4=ih7?lf:?4<`;00o0j>6384g81<3=z{>n:6=4<{<5a`?7c=27<5=4n2:?415<50?1v:j=:18081el3;o4638908b6>;0=8094;5rs6f0>5<4s4=ih7?ka:?4=7;01=0j>6385581<3=z{>n=6=4<{<5a`?7b827<584n2:?410<50?1v:j8:18081el3;n>638978b6>;0=?094;5rs6f;>5<4s4=ih7?j4:?4=22908w09md;3f<>;0110j>6385981<3=z{>nj6=4<{<5a`?7bi27<544n2:?41<<50?1v:jm:18081el3;nh6389`8b6>;0=h094;5rs6f`>5<4s4=ih7?jf:?4=g;01j0j>6385b81<3=z{>nn6=4<{<5a`?7a=27<5i4n2:?41a<50?1v:k?:18081el3;m;6389g8b6>;0=o094;5rs6g2>5<4s4=ih7?i9:?4e5;0i80j>6386081<3=z{>o86=4<{<5a`?71?27;0>:094;5rs6g6>5<4s4=ih7?9c:?4e1;0i<0j>6386481<3=z{>o<6=4<{<5a`?70:27;0>>094;5rs6g:>5<4s4=ih7?86:?4e=;0ih0j>6386`81<3=z{>oh6=4<{<5a`?70k27;0>j094;5rs6gf>5<4s4=ih7?71:?4ea;0il0j>6386d81<3=z{>l;6=4<{<5a`?7??27:18081el3;35638b18b6>;0?9094;5rs6d1>5<4s4=ih7?7b:?4f4;0j;0j>6387381<3=z{>l?6=4<{<5a`?7>9274n2:?436<50?1v:h9:18081el3;28638b48b6>;0?<094;5rs6d4>5<4s4=ih7?66:?4f3;0j>0j>6387681<3=z{>l26=4<{<5a`?7>k27;1k?0j>639c581<<=z{?i36=4={<4`2?4?>27=o94n2:p2<3k97p}99c83>6}:>091m?5268696=0<5?3>6l<4}r4:g?6=:r7=5>4=889>2<3=:1<0q~86d;296~;11>094;526849e7=z{?3n6=4={<4:2?4?>27=5?4=039~w3?f290>w0868;5:?80>?3=270862;04`>;11=0<56399484=>{t?8?1<771c34{t?8k1<771c34{t?8o1<771c346?9k;<4a`?47=2wx;??50;`x93ee2;=o709?5;0;=>;08;0944526gg96=?<5?lj6?66;<4e2?4?127=j?4=889>2`c=:1301;kn:3::?80b>3835639e381<<=z{??o6=4;{<44=?40l27=4i4n2:?5{t>1=1<7d4<5?hi6?9k;|q465<72;q6:no526f893ee2;::7p}95783>7}:>j>1>584=7a:>2?57z?5bd<50?16:kl5210893d42;:?708l0;037>;1im09<8526ca9655<5?hn6?><;|q46<<72>q6:kk5294893`a2;:9708md;037>;1k909<9526`f9654<5?k<6?>=;<4ag?47:2wx;?o50;6x92652;2=709?3;036>;1im09<;526c`965554z?440<50?16;=85210893gc2;:<708mb;036>{t?;?1<7?={<451?47=27=:h4=049>23b=:9?01;8l:326?801j38;96396`8140=:>?31>=;4=74;>76234<=;7;1j109<;<4a3?47=27=n=4=029~w2412902w08i2;0;2>;1n:09=;<4b`?47;27=n54=069>2g4=:9801;lj:327?80e938;86s|73594?g|5?l=6?69;<4e3?47:27=ni4=039>2g`=:9901;ok:327?80ei38;?639b38146=:>h=1>==4=7``>76334;1>l09=;<45f?47:27=:l4=039>23?=:9801;87:321?801?38;>639678147=:>?>1>=<4=7g1>7>134;11909<:526c39650515y>233=:9901;8j:320?801l38;?6396b8146=:>?h1>==4=74b>76434<=57;1m?094;526d59654<5?h36?>;;<4a=?47<27=n;4=039>2g1=:9801;6i:324?80>838;:639b08142=z{>8?6=4>2z?520<58=16:;k52168930c2;:?7089c;030>;1>k09<95267c9652<5?<26?>;;<45230=:9>01;8;:327?80bi383:639ec8147=:>k21>==4=7`:>7623452108yv02j3:1>v39788141=:>1n1>584}r46g?6=:r7=4h4=879>22?=:980q~8:a;296~;1?009<>5269a96=05bz?53=<1927=;:491:?533<1927=;8491:?531<1927=;>491:?537<1927=;<491:?535<1927=:k491:?5g6<5?m1v;;8:18180d1383:639b68142=z{?<96=4={<4a;1i=094;526`7965453z?456<50?16;<:5210893d02;:=7p}95983>6}:>k31>=94=7::>7>134<3m738;:6s|69494?4|5?io6?69;<4a3?47<2wx::o50;0x930a2;2=70860;036>{t>>h1<77>134<2<7:3:5?80>838;96s|66f94?4|5?=96?69;<4:4?47<2wx::k50;0x93142;2=7087f;036>{t>>l1<77>134<3j7{t>191<77>1342d7=:980q~8:f;291~;11o094;526`29e7=:>j91>==4=7;2>76434p1;7i:`0893?42;2=70867;42?80>?3k97p}9d683>7}:>l81m?526d6962b53z?5a0<1;27=i5493:?5a4<5>:1v;j7:18180b>3k9708j8;04`>{t>jl1<7=t=7g:>35<5?oh6;=4=7g6>7043ty=h44?:3y>2`g=i;16:hm526f8yv0c83:1?v39ee857>;1n90=?639e88126=z{?nj6=4={<4fa?g534:71893`32?901;kk:340?xu1lk0;6?u26g09e7=:>o>1>:j4}r4g6?6=;r7=j8493:?5b=<1;27=j<4=629~w3bd2909w08i6;c1?80a03835<5?l>6?8<;|q5`a<72;q6:ko5a39>2ce=:>n0q~8k4;297~;1nm0=?63801857>;1n009:>5rs7ff>5<5s4;:71893`c2;<87p}9dg83>7}:?981m?52716962b52z?442<1;27<<<4=629~w3c72909w09?5;c1?817?38<27=i94=639~w26>2908w08j7;04`>;1m<0959526d:963453z?5ag<5?m16:h75286893cd2;<97p}80c83>6}:>ll1>:j4=7gg>7?334:o6=4<{<4e3?40l27=j84=959>2c>=:?80q~9?e;297~;1nk09;i526g;96<2<5?lh6?8=;|q44c<72:q6:kh526f893`c2;3?709?0;056>{t?8:1<7=t=620>71c34=;=7<64:?441<5>;1v:?>:181817>38?<7<8d:p07g=839p19:>:71891232?9019=k:340?xu3;=0;6?u24509e7=:<=>1>:j4}r61f?6=;r7?88493:?70=<1;27?8<4=629~w1522909w0:;6;c1?82303826;=4=56`>35<5=>>6?8<;|q773<72;q689o5a39>01e=:>n0q~:=d;297~;3;3<009:>5rs514>5<5s4>?i7o=;<664?40l2wx8?k50;1x91362?9019;;:718912c2;<87p};3983>7}:<<81m?52446962b9j7>53z?710<1;27?95493:?714<5>:1v9=6:181822>3k970::8;04`>{t<::1<7=t=57:>35<5=?h6;=4=576>7043ty??l4?:3y>00g=i;1688m526f8yv2493:1?v3;5e857>;3>90=?63;588126=z{=9i6=4={<66a?g534>=<7<8d:p064=838p198<:718913c2;<87p};3b83>7}:=87>53z?77c<5?m168>j5286891272;<97p};6483>6}:<=91>:j4=562>7?334>?87<92:p030=839p19:8:35g?823=382863;498127=z{=<<6=4<{<67f?40l27?844=959>01e=:?80q~:98;297~;3{t71c34>>97<64:?71=<5>;1v98m:180822j38;<4}r65g?6=;r7?9k4=7e9>00b=:0>0198?:341?xu3>m0;6?u2470962b<5=<86?8=;|q510<72;q6:?=5a39>202=:>n0q~8=e;296~;1=;09<852641962b59z?566<51=16:?:5286893422;3?708=6;0:0>;1:>09595263:96<2<5?826?7;;<41e?4><27=9?4=7e9~w34e2908w08:3;036>;1w08;9;5:?80303=2708;2;04`>;1<<0<56394584=>{t><:1<77>13473k97p}94d83>6}:>=91>584=76;>37<5?>36l<4}r47`?6=:r7=8>4=889>213=:1<0q~8;c;297~;1<:0j>639448b6>;1<=094;5rs76b>5<5s4o50;7x935?2>301;=8:6;8934a2;=o708<2;5:?80493=27p}94083>7}:>:<1>584=70e>7653ty=8=4?:3y>262=:1<01;=::`08yv04n3:1>v393281<3=:>:>1m?5rs71f>5<5s4<8;7<76:?576j50;1x93572;2=708<7;42?804?3k97p}93b83>7}:>::1>574=711>7>13ty=?o4?:2y>266=i;16:><5a39>267=:1<0q~8<9;296~;1;1094;526239e7=z{=n26=4={<6g0?47:27?h;4=879~w1b?2909w0:k5;c1?82c>38346s|4ec94?4|5=n?6?><;<6g1?4?>2wx8i950;0x91b42h8019j;:35g?xu28k0;6?u25159654<5<:26?69;|q64d<72;q69=65a39>15?=:120q~;?c;296~;28>09<>5251:96=0oj7>52z?7`g<58;168ij52948yv2cm3:1>v3;db8b6>;3lm09455rs5g3>5<5s4>on7>:18182a<38;>63;f`81<3=z{=ln6=4={<6e=?g534>mm7<78:p154=838p19h;:320?82a1383:6s|4gd94?4|5=l36l<4=5d:>7>?3ty><>4?:3y>0c3=:98019h7:3:5?xu2890;6?u24g59e7=:564}r730?6=:r7?j84=029>0c1=:1<0q~:ib;296~;3n?09mo7>52z?7b3<58:168k;526f8yv2al3:1>v3;f28b6>;3n?09;i5rs5ge>5<5s4>n>7{t76434>n;7<76:p0`b=838p19k9:`0891c02;237p};f083>7}:=<4=5g5>7>13ty?ih4?:3y>0`3=i;168h8529:8yv2a:3:1>v3;e28146=:584}r6f=?6=:r7?i94=039>0`4=:>n0q~:ja;296~;3m=09<>524d1962bnn7>52z?7a4;20;0==63:7d855>;2?h0==63:77855>;2?;0==63:6d855>;2>h0==63:67855>;2>;0==6s|60494?4|5<:>6?68;<6g`?g53ty=15b=:1<018m6:73890e12?;018m=:73890db2?;018ln:73890d12?;018l=:73890gb2?;018on:73890g12?;0q~8>5;296~;28<0j>63:0e81<2=z{?;h6=4={<432?g534<;97<8d:p24b=838p1;>9:3:5?807?3k97p}91c83>7}:584=5f1>d452z?54=<1927>7>?3ty>=?4?:3y>252=>8169=852948yv0613:1>v3:0g8b6>;28?09455rs73;>5<5s4>o97<78:?64350;6x936?2;22708?9;0;=>;18=0944524e`962b52z?7`f<501168i85a39~w073290iw0;?7;04`>;20<09445259096=?<5<=n6?66;<74e?4?127>;;4=889>124=:130188j:3::?831i383563:6781<<=:=?81>574}r420?6=:r7>{t>881<7d4<5=l<6?67;|q656<72jq6:=:5294891c22:h019k9:2`891c02:h019k7:2`891`02:h019h7:2`891`>2:h019hn:2`891be2;3?70;?7;0:0>;28?08n6s|60294?e|5?:26?69;<6f7?4><27?i?4=959>0c3=:0>019h;:3;7?82ck39i70:kd;1a?837039i70;?9;1a?82c=39i70:k6;1a?837n39i7p}90e83>0}:>921>584=5g7>7?334>m:7<64:?7`1<51=169=k53c9~w3762909w0:ia;c1?83ci38i:6s|61g94?4|5?:26l<4=4fb>4`b3ty=25>=i;169i751gg8yv3693:1>v39058b6>;2l10:jh5rs4;2>5<5s4?3:7<8d:?6<2<5>;1v87?:18083?;381>;<4}r7;b?6=;r7>;k4=7e9>12b=:0>0186?:341?xu20l0;6>u256`962b<5<=26?7;;<74g?41:2wx95j50;1x90102;=o70;85;0:0>;2?109:?5rs4:`>5<4s4?4:4=453>7053ty>4l4?:2y>13d=:>n01886:3;7?831k38=>6s|59;94?5|5<<<6?9k;<751?4><27>:54=639~w0>?2908w0;93;04`>;2>8095952576963452z?6<04:4=7e9~w0312909w0;77;40?83?938=?6s|54d94?4|5<296l<4=4:7>71c3ty>984?:2y>1=7=>:1695:5629>12b=:?90q~;:e;296~;2?l0j>63:81813a=z{u256;926=:=>i1:>525679635o7>52z?633;54=7e9~w0352908w0;85;40?83003<870;81;057>{t=d4<5<=?6?9k;|q614<72:q69:?5629>122=>:169;j52718yv32i3:1>v3:6d8b6>;2?909;i5rs473>5<4s4?=h78<;<744?0434?=57<93:p10?=838p188n:`08900d2;=o7p}:4g83>6}:=?31:>5257a926=:=??1>;=4}r76:;4n2:?62=<5?m1v8:j:180831=3<870;98;40?831938=?6s|54594?4|5<<96l<4=447>71c3ty>h84?:3y>1fg=:>n018mm:341?xu2l=0;6>u25b5962b<56?7;;<7`;2k=09:?5rs4f1>5<4s4?ij7<8d:?6fa<51=169n>52708yv3c93:1?v3:bc813a=:=k31>4:4=4``>7053ty>h=4?:2y>1g1=:>n018l::3;7?83e038=>6s|5bd94?5|5<27>n94=639~w0eb2908w0;nf;04`>;2im0959525c2963453z?6eg<5?m169l75286890gd2;<97p}:cb83>6}:=h=1>:j4=4c6>7?334?j47<92:p1d2=838p18m6:`0890ee2;=o7p}:9`83>7}:=jh1:>525b7963552z?6g3o54=7e9~w0?>2908w0;l5;40?83d03<870;l1;057>{t=h81<7d4<51f2=>:169oj52718yv3f93:1>v3:bd8b6>;2k909;i5rs4;4>5<4s4?ih78<;<7`4?0434?i57<93:p1d6=838p18ln:`0890dd2;=o7p}:9783>6}:=k31:>525ca926=:=k?1>;=4}r7:b?6=:r7>n;4n2:?6f=<5?m1v87::18083e=3<870;m8;40?83e938=?6s|58g94?4|571c3ty>594?:2y>1g7=>:169o:5629>1db=:?90q~;6d;296~;2il0j>63:b1813a=z{<386=4<{<7b`?0434?i<78<;<7b=?41;2wx94m50;0x90gf2h8018ol:35g?xu21;0;6>u25`;926=:=hi1:>525`7963552z?6e3m54=7e9~w07b2909w0;;d;c1?833k38j6l<4=46:>71c3ty>=n4?:3y>111=i;16998526f8yv36j3:1>v3:458b6>;2<:09;i5rs43b>5<5s4??=7o=;<774?40l2wx9<750;0x905b2h8018=k:35g?xu2910;6?u252`9e7=:=:k1>:j4}r723?6=:r7>?54n2:?672<5?m1v8?9:181834=3k970;<4;04`>{t=8?1<7d4<5<9:6?9k;|q6`c<72;q69i9526f890bf2;h>7p}:de83>7}:=m<1>:j4=4f:>7d23ty>ho4?:3y>17`=:1<018j7:3`6?xu2m?0;6?u253796=0<5<8m6l<4}r7f1?6=:r7>>94=879>173=i;1v8k;:181835;383:63:258b6>{t=l91<77>134?9?7o=;|q6a7<72;q69??5294890452h80q~;j1;296~;2:9094;525339e7=z{27>>=4n2:?60f<58=1v8ki:180835l383:63:2d8b6>;2<009<95rs4gf>5<4s4?9o7<76:?66a8;4=059~w0cc2908w0;=b;0;2>;2:j0j>63:428141=z{27>>o4n2:?605<58=1v8km:1808351383:63:2`8b6>;2;m09<95rs4gb>5<4s4?947<76:?66<?l4=059~w0c>2908w0;=7;0;2>;2:10j>63:368141=z{27>>:4n2:?671<58=1v8k8:180836n383:63:278b6>;2;809<95rs4ff>5<5s4?o;738;>63:d981f3=z{?:86=4;{<77g?47;27>484=879>1=0=:98018j7:0dg?xu18;0;69u255;9655<5<296?69;<7;7?47:27>h54>f09~w366290?w0;;6;037>;2?l094;5256d9654<5;2l10:ho5rs4de>5<3s4??<71}:=:n1>==4=451>7>134?=<4=4f;>4df3ty>jn4?:5y>161=:990188n:3:5?831j38;>63:d982ec=z{:;4=879>131=:98018j7:0c7?xu2nh0;69u25239655<5<<96?69;<757?47:27>h54>659~w0`>2909w0;;d;0;2>;26s|5g:94?4|5<>j6?69;<77j:4?:3y>111=:1<018:::`08yv3a>3:1>v3:4581<3=:==81m?5rs4d6>5<5s4??=7<76:?67c?54=879>160=i;1v8h>:181834=383:63:328b6>{t=o:1<77>134?8<7o=;|q0`7<72;q6?io5a39>7ae=:>n0q~=lc;297~;4lm0=?63;4l009:>5rs2f0>5<5s49oi7o=;<1f4?40l2wx?nj50;1x96c62?901>k;:71896bc2;<87p}7}:;l81m?523d6962b53z?0a0<1;278i5493:?0a4<5>:1v>j::18185b>3k970=j8;04`>{t;jl1<7=t=2g:>35<5:oh6;=4=2g6>7043ty8h;4?:3y>7`g=i;16?hm526f8yv5c83:1?v3;4n90=?63h<:71896cc2;<87p}7}:;o;1m?523g1962b53z?0`g<5?m16?i75286896bd2;<97p}6}:;ml1>:j4=2fg>7?3349n<7<92:p7c0=839p1>k<:35g?85b93828637`>=:?80q~=i8;297~;4mk09;i523d;96<2<5:oh6?8=;|q0b<<72:q6?hh526f896cc2;3?70=i0;056>{t;ok1<771c349m?7<92:p2d0=838p1;o8:35g?80e;38;>6s|6`594?4|5?h86?9k;<4aa?47>2wx:o=50;0x93dd2;=o708me;031>{t>ki1<771c34{t>j:1<771c342;=o708nc;031>{t>h31<771c34{t>hn1<771c346?9k;<4ae?47>2wx:o;50;0x93d?2;=o708ma;030>{t>k21<771c34:5339>362=;:16;>:5359>37`=;;16;?h5329>37`=;=16?=85309>750=;;16?=85329>74e=;816?74e=;:16?><5309>764=;;16?><5329>71>=;816?965339>71>=;:16?8k5309>70c=;;16?8k5329>722=;816?::5339>722=;:16?:k5309>72c=;;16?:k5329>7=6=;816?5>5339>7=6=;:16?5<5309>7=4=;;16?5<5329>7=2=;816?5:5339>7=2=;:16?=65309>75>=;;16?=65329>75g=;816?=o5339>75g=;:16?=m5309>75e=;;16?=m5329>75c=;816?=k5339>75c=;:16?<>5309>746=;;16?<>5329>744=;816?<<5339>744=;:16?<:5309>742=;;16?<:5329>740=;816?<85339>740=;:16?<65309>74>=;;16?<65329>74g=;816?74g=;:16?74c=;;16?776=;816??>5339>776=;:16??<5309>774=;;16??<5329>772=;816??:5339>772=;:16??85309>770=;;16??85329>77>=;816??65339>77>=;:16??o5309>77g=;;16??o5329>77e=;816??m5339>77e=;:16??k5309>77c=;;16??k5329>766=;816?>>5339>766=;:16?>:5309>762=;;16?>:5329>760=;816?>85339>760=;:16?>65309>76>=;;16?>65329>76g=;816?>o5339>76g=;:16?>m5309>76e=;;16?>m5329>76c=;816?>k5339>76c=;:16?9>5309>716=;;16?9>5329>714=;816?9<5339>714=;:16?9:5309>712=;;16?9:5329>710=;816?985339>710=;:16?9o5309>71g=;;16?9o5329>71e=;816?9m5339>71e=;:16?9k5309>71c=;;16?9k5329>706=;816?8>5339>706=;:16?8<5309>704=;;16?8<5329>702=;816?8:5339>702=;:16?885309>700=;;16?885329>70>=;816?865339>70>=;:16?8o5309>70g=;;16?8o5329>70e=;816?8m5339>70e=;:16?;>5309>736=;;16?;>5329>734=;816?;<5339>734=;:16?;:5309>732=;;16?;:5329>730=;816?;85339>730=;:16?;65309>73>=;;16?;65329>73g=;816?;o5339>73g=;:16?;m5309>73e=;;16?;m5329>73c=;816?;k5339>73c=;:16?:>5309>726=;;16?:>5329>724=;816?:<5339>724=;:16?:85309>720=;;16?:85329>72>=;816?:65339>72>=;:16?:o5309>72g=;;16?:o5329>72e=;816?:m5339>72e=;:16;oj518:892dc2838709md;3;`>;0jm0:4>527cf952c<5>ho6<97;<5a`?71m27689>3gb=9oh01:lk:0d1?81el3;no638be82a2=:?kn1=ij4=6`g>4b034=ih7?k2:?4fa<6k116;oj51b0892dc28ho709md;3a7>;0jm0:mi527cf95d><5>ho6<7m;<5a`?7al27c49>2<`=>816:l>5609>2=d=>816:5k5a39>344=>816:485609>2f3=>816:n85609>353=>816;=<5609>2cc=>816:ko5609>2c0=>816:k<5609>2`c=>816:ho5609>2`0=>816:h<5609>2`7=>:16:h:5629>06b=>:1689>5629>205=:9>01;:9:73893202?;01;=<:73893532?;01;=::73893512?;018018o::71890g?2?90188>:71890032?901>j6:71896bd2?901;m6:`0891642==019><:54891642=?019><:2d891642<<019><:47891642<>019><:5g891642j;019><:cd891642kn019><:ca891642kh019><:cc891642k3019><:c:891642k=019><:c4891642k?019><:c6891642k8019><:c3891642k:019><:`d891642ho019><:`f891642hi019><:``891642hk019><:`;891642j2019><:b5891642j<019><:b7891642j>019><:b1891642j8019><:cg891642k9019><:`:891642l8019><:d2891642mo019><:ef891642mi019><:e`891642mk019><:e;891642m2019><:e5891642m<019><:e7891642m9019><:e0891642m;019><:e2891642lo019><:da891642lh019><:dc891642o9019><:g38916428><70:?3;0;f>;38:094n52414902=:<9<18;52414900=:<9<1?k52414913=:<9<19852414911=:<9<18h524149g4=:<9<1nk524149fa=:<9<1nn524149fg=:<9<1nl524149f<=:<9<1n5524149f2=:<9<1n;524149f0=:<9<1n9524149f7=:<9<1n<524149f5=:<9<1mk524149e`=:<9<1mi524149ef=:<9<1mo524149ed=:<9<1m4524149g==:<9<1o:524149g3=:<9<1o8524149g1=:<9<1o>524149g7=:<9<1nh524149f6=:<9<1m5524149a7=:<9<1i=524149``=:<9<1hi524149`f=:<9<1ho524149`d=:<9<1h4524149`==:<9<1h:524149`3=:<9<1h8524149`6=:<9<1h?524149`4=:<9<1h=524149a`=:<9<1in524149ag=:<9<1il524149b6=:<9<1j<524149511<5=:=6?6m;<632?4?k27?<44;7:?74<<3>27?<44;5:?74<<4n27?<44:6:?74<<2=27?<44:4:?74<<3m27?<44l1:?74<27?<44m5:?74<469>05?=:1h019>6:3:`?827k3><70:?c;65?827k3>>70:?c;1e?827k3?=70:?c;76?827k3??70:?c;6f?827k3i:70:?c;`e?827k3ho70:?c;``?827k3hi70:?c;`b?827k3h270:?c;`;?827k3h<70:?c;`5?827k3h>70:?c;`7?827k3h970:?c;`2?827k3h;70:?c;ce?827k3kn70:?c;cg?827k3kh70:?c;ca?827k3kj70:?c;c:?827k3i370:?c;a4?827k3i=70:?c;a6?827k3i?70:?c;a0?827k3i970:?c;`f?827k3h870:?c;c;?827k3o970:?c;g3?827k3nn70:?c;fg?827k3nh70:?c;fa?827k3nj70:?c;f:?827k3n370:?c;f4?827k3n=70:?c;f6?827k3n870:?c;f1?827k3n:70:?c;f3?827k3on70:?c;g`?827k3oi70:?c;gb?827k3l870:?c;d2?827k3;?;63;0b815m4}r4b1?6=:r7=m84=7e9>2d2=i;1v:?;:181816<38{t>1k1<771c34<357o=;|q130<72;q6:o?526f893d72;:>7p}=7783>7}:>k81>:j4=7`3>7633ty9;:4?:3y>2g0=:>n01;l::321?xu5?10;6?u26c5962b<5?h>6?><;|m5d>1290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?n8683>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9h236=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3b<<<728qC5?64H35b?_71938p>4:52729yM40j2we=l6n:182M?502B9;l5U17396~4><38=<7sG26`8yk7f0k0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5d>b290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?n8g83>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9h3;6=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3b=4<728qC5?64H35b?_71938p>4:52729yM40j2we=l7=:182M?502B9;l5U17396~4><38=<7sG26`8yk7f1:0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5d?1290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?n9683>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9h336=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3b=<<728qC5?64H35b?_71938p>4:52729yM40j2we=l7n:182M?502B9;l5U17396~4><38=<7sG26`8yk7f1k0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5d?b290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?n9g83>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9hk;6=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3be4<728qC5?64H35b?_71938p>4:52729yM40j2we=lo=:182M?502B9;l5U17396~4><38=<7sG26`8yk7fi:0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5dg1290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?na683>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9hk36=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3be<<728qC5?64H35b?_71938p>4:52729yM40j2we=lon:182M?502B9;l5U17396~4><38=<7sG26`8yk7fik0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5dgb290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?nag83>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9hh;6=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3bf4<728qC5?64H35b?_71938p>4:52729yM40j2we=ll=:182M?502B9;l5U17396~4><38=<7sG26`8yk7fj:0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5dd1290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?nb683>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9hh36=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3bf<<728qC5?64H35b?_71938p>4:52729yM40j2we=lln:182M?502B9;l5U17396~4><38=<7sG26`8yk7fjk0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5ddb290:wE7=8:J13d=]9?;1>v<64;054?{O:>h0qc?nbg83>4}O1;20D?9n;[355?4|:0>1>;>5}I04f>{i9hi;6=4>{I;1<>N5?h1Q=;?52z0:0?4183wC>:l4}o3bg4<728qC5?64H35b?_71938p>4:52729yM40j2we=lm=:182M?502B9;l5U17396~4><38=<7sG26`8yk7fk:0;65<6sA3946F=7`9Y537=:r8287<90;K62d<@;=j7W?91;0x6<2=:?:1qE<8b:m5de1290:wE7=8:m5de0290:wE7=8:m5de?290:wE7=8:m5de>290:wE7=8:m5def290:wE7=8:m5dee290:wE7=8:m5ded290:wE7=8:m5dec290:wE7=8:m5deb290:wE7=8:m5dea290:wE7=8:m5db7290:wE7=8:m5db6290:wE7=8:m5db5290:wE7=8:m5db4290:wE7=8:m5db3290:wE7=8:m5db2290jwE7=8:m5db1290:wE7=8:m5db0290:wE7=8:m5db?290:wE7=8:m5db>290:wE7=8:m5dbf290:wE7=8:m5dbe290:wE7=8:m5dbd290:wE7=8:m5dbc290:wE7=8:m5dbb290:wE7=8:m5dba290:wE7=8:m5dc72907sU17395~4em3wvb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb0;295~N>:11vb1;295~N>:11vb2;295~N>:11vb3;295~N>:11vb4;295~N>:11vb5;295~N>:11vb6;295~N>:11vb7;295~N>:11vb8;295~N>:11vb9;295~N>:11vba;295~N>:11vbb;295~N>:11vbc;295~N>:11vbd;295~N>:11vbe;295~N>:11vbf;295~N>:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb0;295~N>:11vb1;295~N>:11vb2;295~N>:11vb3;295~N>:11vb4;295~N>:11vb5;295~N>:11vb6;295~N>:11vb7;295~N>:11vb8;295~N>:11vb9;295~N>:11vba;295~N>:11vbb;295~N>:11vbc;295~N>:11vbd;295~N>:11vbe;295~N>:11vbf;295~N>:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb0;295~N>:11vb1;295~N>:11vb2;295~N>:11vb3;295~N>:11vb4;295~N>:11vb5;295~N>:11vb6;295~N>:11vb7;295~N>:11vb8;295~N>:11vb9;295~N>:11vba;295~N>:11vbb;295~N>:11vbc;295~N>:11vbd;295~N>:11vbe;295~N>:11vbf;295~N>:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb0;295~N>:11vb1;295~N>:11vb2;295~N>:11vb3;295~N>:11vb4;295~N>:11vb5;295~N>:11vb6;295~N>:11vb7;295~N>:11vb8;295~N>:11vb9;295~N>:11vba;295~N>:11vbb;295~N>:11vbc;295~N>:11vbd;295~N>:11vbe;295~N>:11vbf;295~N>:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb:11vb4}O1;20qc?j3483>4}O1;20qc?j3783>4}O1;20qc?j3683>4}O1;20qc?j3983>4}O1;20qc?j3883>4}O1;20qc?j3`83>4}O1;20qc7id;296~N>:11vb4hj:180M?502we5kh50;1xL<4?3tdj<=4?:2yK=7>53zJ:6==zfh:96=4<{I;1<>{ii991<7=tH80;?xhf8=0;6>uG93:8ykg7=3:1?vF6299~jd612908wE7=8:me51=839pD4<7;|lb4=<72:qC5?64}oc3=?6=;rB2>55rn`2b>5<4sA3946saa1`94?5|@0837p`:b`83>4}O1;20qc;mb;295~N>:11vb8ll:182M?502we9oj50;3xL<4?3td>nh4?:0yK=7>51zJ:6==zf{I;1<>{i=j91<7?tH80;?xh2k=0;655rn71f>5<6sA3946sa62d94?7|@0837p`94183>4}O1;20qc8;1;295~N>:11vb;:=:182M?502we:9=50;3xL<4?3td=884?:0yK=7>51zJ:6==zf?>36=4>{I;1<>{i>kn1<7?tH80;?xh1jl0;655rn7a7>5<6sA3946sa6b494?7|@0837p`9c983>4}O1;20qc8l9;295~N>:11vb:=j:182M?502we;>h50;3xL<4?3td<8=4?:0yK=7>51zJ:6==zf>>96=4>{I;1<>{i?=91<7?tH80;?xh0<=0;655rn6a3>5<6sA3946sa7b394?7|@0837p`8c383>4}O1;20qc9l3;295~N>:11vb:m;:182M?502we;n;50;3xL<4?3td51zJ:6==zf>ij6=4>{I;1<>{i?jh1<7?tH80;?xh?<90;6393:1=vF6299~j=25290:wE7=8:m<15=83;pD4<7;|l;01<728qC5?64}o:71?6=9rB2>55rn965>5<6sA3946sa85594?7|@0837p`74883>4}O1;20qc6;b;295~N>:11vb5:l:182M?502we4n?50;3xL<4?3td3o?4?:0yK=7>51zJ:6==zf1i?6=4>{I;1<>{i0j?1<7?tH80;?xh?k?0;6d?3:1=vF6299~j=e?290:wE7=8:m55rn872>5<6sA3946sa94094?7|@0837p`65283>4}O1;20qc7:4;295~N>:11vb4;::182M?502we58850;3xL<4?3td29:4?:0yK=7>47>51zJ:6==zf0?j6=4>{I;1<>{i1=j0;6=83;pD4<7;|l24c?=83;pD4<7;|l24cg=83;pD4<7;|l24ce=83;pD4<7;|l24cb=83;pD4<7;|l24cc=83;pD4<7;|l24c`=83;pD4<7;|l2557=83;pD4<7;|l2554=83;pD4<7;|l25f5=83kpD4<7;|l25d5=83;pD4<7;|l25d2=83;pD4<7;|l25d3=83;pD4<7;|l25d0=83;pD4<7;|l25d1=83;pD4<7;|l25d>=83;pD4<7;|l25d?=83;pD4<7;|l25dd=83;pD4<7;|l25de=83;pD4<7;|l25db=83;pD4<7;|l25dc=83;pD4<7;|l25g6=83;pD4<7;|l25g7=83;pD4<7;|l2624=83kpD4<7;|l2604=83;pD4<7;|l2605=83;pD4<7;|l2602=83;pD4<7;|l2603=83;pD4<7;|l2600=83;pD4<7;|l2601=83;pD4<7;|l260>=83;pD4<7;|l260g=83;pD4<7;|l260d=83;pD4<7;|l260e=83;pD4<7;|l260b=83;pD4<7;|l260`=83;pD4<7;|l2636=83;pD4<7;|~yEFDs;8397:k6ga5f`{GHKq;qMN_{|BC \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise (nonexistent) @@ -1,398 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise (nonexistent) @@ -1,32 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v (nonexistent) @@ -1,179 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2011 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// You must compile the wrapper file rom_8x2k.v when simulating -// the core, rom_8x2k. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -`timescale 1ns/1ps - -module rom_8x2k( - clka, - ena, - wea, - addra, - dina, - douta -); - -input clka; -input ena; -input [0 : 0] wea; -input [10 : 0] addra; -input [15 : 0] dina; -output [15 : 0] douta; - -// synthesis translate_off - - BLK_MEM_GEN_V6_2 #( - .C_ADDRA_WIDTH(11), - .C_ADDRB_WIDTH(11), - .C_ALGORITHM(1), - .C_AXI_ID_WIDTH(4), - .C_AXI_SLAVE_TYPE(0), - .C_AXI_TYPE(1), - .C_BYTE_SIZE(9), - .C_COMMON_CLK(0), - .C_DEFAULT_DATA("0"), - .C_DISABLE_WARN_BHV_COLL(0), - .C_DISABLE_WARN_BHV_RANGE(0), - .C_FAMILY("spartan6"), - .C_HAS_AXI_ID(0), - .C_HAS_ENA(1), - .C_HAS_ENB(0), - .C_HAS_INJECTERR(0), - .C_HAS_MEM_OUTPUT_REGS_A(0), - .C_HAS_MEM_OUTPUT_REGS_B(0), - .C_HAS_MUX_OUTPUT_REGS_A(0), - .C_HAS_MUX_OUTPUT_REGS_B(0), - .C_HAS_REGCEA(0), - .C_HAS_REGCEB(0), - .C_HAS_RSTA(0), - .C_HAS_RSTB(0), - .C_HAS_SOFTECC_INPUT_REGS_A(0), - .C_HAS_SOFTECC_OUTPUT_REGS_B(0), - .C_INIT_FILE_NAME("no_coe_file_loaded"), - .C_INITA_VAL("0"), - .C_INITB_VAL("0"), - .C_INTERFACE_TYPE(0), - .C_LOAD_INIT_FILE(0), - .C_MEM_TYPE(0), - .C_MUX_PIPELINE_STAGES(0), - .C_PRIM_TYPE(1), - .C_READ_DEPTH_A(2048), - .C_READ_DEPTH_B(2048), - .C_READ_WIDTH_A(16), - .C_READ_WIDTH_B(16), - .C_RST_PRIORITY_A("CE"), - .C_RST_PRIORITY_B("CE"), - .C_RST_TYPE("SYNC"), - .C_RSTRAM_A(0), - .C_RSTRAM_B(0), - .C_SIM_COLLISION_CHECK("ALL"), - .C_USE_BYTE_WEA(0), - .C_USE_BYTE_WEB(0), - .C_USE_DEFAULT_DATA(0), - .C_USE_ECC(0), - .C_USE_SOFTECC(0), - .C_WEA_WIDTH(1), - .C_WEB_WIDTH(1), - .C_WRITE_DEPTH_A(2048), - .C_WRITE_DEPTH_B(2048), - .C_WRITE_MODE_A("WRITE_FIRST"), - .C_WRITE_MODE_B("WRITE_FIRST"), - .C_WRITE_WIDTH_A(16), - .C_WRITE_WIDTH_B(16), - .C_XDEVICEFAMILY("spartan6") - ) - inst ( - .CLKA(clka), - .ENA(ena), - .WEA(wea), - .ADDRA(addra), - .DINA(dina), - .DOUTA(douta), - .RSTA(), - .REGCEA(), - .CLKB(), - .RSTB(), - .ENB(), - .REGCEB(), - .WEB(), - .ADDRB(), - .DINB(), - .DOUTB(), - .INJECTSBITERR(), - .INJECTDBITERR(), - .SBITERR(), - .DBITERR(), - .RDADDRECC(), - .S_ACLK(), - .S_ARESETN(), - .S_AXI_AWID(), - .S_AXI_AWADDR(), - .S_AXI_AWLEN(), - .S_AXI_AWSIZE(), - .S_AXI_AWBURST(), - .S_AXI_AWVALID(), - .S_AXI_AWREADY(), - .S_AXI_WDATA(), - .S_AXI_WSTRB(), - .S_AXI_WLAST(), - .S_AXI_WVALID(), - .S_AXI_WREADY(), - .S_AXI_BID(), - .S_AXI_BRESP(), - .S_AXI_BVALID(), - .S_AXI_BREADY(), - .S_AXI_ARID(), - .S_AXI_ARADDR(), - .S_AXI_ARLEN(), - .S_AXI_ARSIZE(), - .S_AXI_ARBURST(), - .S_AXI_ARVALID(), - .S_AXI_ARREADY(), - .S_AXI_RID(), - .S_AXI_RDATA(), - .S_AXI_RRESP(), - .S_AXI_RLAST(), - .S_AXI_RVALID(), - .S_AXI_RREADY(), - .S_AXI_INJECTSBITERR(), - .S_AXI_INJECTDBITERR(), - .S_AXI_SBITERR(), - .S_AXI_DBITERR(), - .S_AXI_RDADDRECC() - ); - -// synthesis translate_on - -endmodule

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco (nonexistent) @@ -1,52 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 13.2 -# Date: Wed Jul 20 21:00:37 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.05.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.05.a -# END Select -# BEGIN Parameters -CSET component_name=chipscope_icon -CSET enable_jtag_bufg=true -CSET example_design=false -CSET number_control_ports=1 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 12195cd5

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo (nonexistent) @@ -1,28 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2011 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 13.2 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_icon.veo -// /___/ /\ Timestamp : Wed Jul 20 23:01:08 CEST 2011 -// \ \ / \ -// \___\/\___\ -// -// Design Name: ISE Instantiation template -/////////////////////////////////////////////////////////////////////////////// - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -chipscope_icon YourInstanceName ( - .CONTROL0(CONTROL0) // INOUT BUS [35:0] -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log (nonexistent) @@ -1,19 +0,0 @@ - -User Configuration -------------------------------------- -Algorithm : Minimum_Area -Memory Type : Single_Port_RAM -Port A Read Width : 16 -Port A Write Width : 16 -Memory Depth : 2048 --------------------------------------------------------------- - -Block RAM resource(s) (9K BRAMs) : 0 -Block RAM resource(s) (18K BRAMs) : 2 --------------------------------------------------------------- -Clock A Frequency : 100 -Port A Enable Rate : 100 -Port A Write Rate : 50 ----------------------------------------------------------- -Estimated Power for IP : 3.06393 mW -----------------------------------------------------------

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco (nonexistent) @@ -1,105 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 13.2 -# Date: Wed Jul 20 21:26:03 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 -# END Select -# BEGIN Parameters -CSET additional_inputs_for_power_estimation=false -CSET algorithm=Minimum_Area -CSET assume_synchronous_clk=false -CSET axi_id_width=4 -CSET axi_slave_type=Memory_Slave -CSET axi_type=AXI4_Full -CSET byte_size=9 -CSET coe_file=no_coe_file_loaded -CSET collision_warnings=ALL -CSET component_name=ram_8x512 -CSET disable_collision_warnings=false -CSET disable_out_of_range_warnings=false -CSET ecc=false -CSET ecctype=No_ECC -CSET enable_a=Use_ENA_Pin -CSET enable_b=Always_Enabled -CSET error_injection_type=Single_Bit_Error_Injection -CSET fill_remaining_memory_locations=false -CSET interface_type=Native -CSET load_init_file=false -CSET memory_type=Single_Port_RAM -CSET operating_mode_a=WRITE_FIRST -CSET operating_mode_b=WRITE_FIRST -CSET output_reset_value_a=0 -CSET output_reset_value_b=0 -CSET pipeline_stages=0 -CSET port_a_clock=100 -CSET port_a_enable_rate=100 -CSET port_a_write_rate=50 -CSET port_b_clock=100 -CSET port_b_enable_rate=100 -CSET port_b_write_rate=50 -CSET primitive=8kx2 -CSET read_width_a=8 -CSET read_width_b=8 -CSET register_porta_input_of_softecc=false -CSET register_porta_output_of_memory_core=false -CSET register_porta_output_of_memory_primitives=false -CSET register_portb_output_of_memory_core=false -CSET register_portb_output_of_memory_primitives=false -CSET register_portb_output_of_softecc=false -CSET remaining_memory_locations=0 -CSET reset_memory_latch_a=false -CSET reset_memory_latch_b=false -CSET reset_priority_a=CE -CSET reset_priority_b=CE -CSET reset_type=SYNC -CSET softecc=false -CSET use_axi_id=false -CSET use_byte_write_enable=false -CSET use_error_injection_pins=false -CSET use_regcea_pin=false -CSET use_regceb_pin=false -CSET use_rsta_pin=false -CSET use_rstb_pin=false -CSET write_depth_a=512 -CSET write_width_a=8 -CSET write_width_b=8 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2011-03-11T08:24:14.000Z -# END Extra information -GENERATE -# CRC: fb8647a1

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo (nonexistent) @@ -1,68 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2011 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 * -* * -* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * -* Block Memory and Single Port Block Memory LogiCOREs, but is not a * -* direct drop-in replacement. It should be used in all new Xilinx * -* designs. The core supports RAM and ROM functions over a wide range of * -* widths and depths. Use this core to generate block memories with * -* symmetric or asymmetric read and write port widths, as well as cores * -* which can perform simultaneous write operations to separate * -* locations, and simultaneous read operations from the same location. * -* For more information on differences in interface and feature support * -* between this core and the Dual Port Block Memory and Single Port * -* Block Memory LogiCOREs, please consult the data sheet. * -*******************************************************************************/ - -// Interfaces: -// AXI_SLAVE_S_AXI -// AXILite_SLAVE_S_AXI - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -ram_8x512 your_instance_name ( - .clka(clka), // input clka - .ena(ena), // input ena - .wea(wea), // input [0 : 0] wea - .addra(addra), // input [8 : 0] addra - .dina(dina), // input [7 : 0] dina - .douta(douta) // output [7 : 0] douta -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file ram_8x512.v when simulating -// the core, ram_8x512. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise (nonexistent) @@ -1,398 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy (nonexistent) @@ -1,9 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 chipscope_icon -RECTANGLE Normal 32 32 544 864 -LINE Wide 576 112 544 112 -PIN 576 112 RIGHT 36 -PINATTR PinName control0[35:0] -PINATTR Polarity BOTH -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy (nonexistent) @@ -1,29 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 ram_8x512 -RECTANGLE Normal 32 32 544 1376 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName addra[8:0] -PINATTR Polarity IN -LINE Wide 0 112 32 112 -PIN 0 112 LEFT 36 -PINATTR PinName dina[7:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName ena -PINATTR Polarity IN -LINE Wide 0 208 32 208 -PIN 0 208 LEFT 36 -PINATTR PinName wea[0:0] -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName clka -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName douta[7:0] -PINATTR Polarity OUT -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt (nonexistent) @@ -1,12 +0,0 @@ -# Output products list for -chipscope_ila.asy -chipscope_ila.cdc -chipscope_ila.gise -chipscope_ila.ngc -chipscope_ila.v -chipscope_ila.veo -chipscope_ila.xco -chipscope_ila.xise -chipscope_ila_flist.txt -chipscope_ila_readme.txt -chipscope_ila_xmdf.tcl

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl (nonexistent) @@ -1,119 +0,0 @@ -# The package naming convention is _xmdf -package provide ram_8x512_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::ram_8x512_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::ram_8x512_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name ram_8x512 -} -# ::ram_8x512_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::ram_8x512_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type text -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/example_design/bmg_wrapper.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/example_design/ram_8x512_top.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/example_design/ram_8x512_top.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/example_design/ram_8x512_top.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/planAhead_rdn.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/planAhead_rdn.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/planAhead_rdn.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_ste/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram_8x512 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise (nonexistent) @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - -

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v (nonexistent) @@ -1,27 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2011 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 13.2 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_icon.v -// /___/ /\ Timestamp : Wed Jul 20 23:01:08 CEST 2011 -// \ \ / \ -// \___\/\___\ -// -// Design Name: Verilog Synthesis Wrapper -/////////////////////////////////////////////////////////////////////////////// -// This wrapper is used to integrate with Project Navigator and PlanAhead - -`timescale 1ns/1ps - -module chipscope_icon( - CONTROL0); - - -inout [35 : 0] CONTROL0; - -endmodule

trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf (nonexistent) @@ -1,52 +0,0 @@ - -#Created by Constraints Editor (xc6slx9-csg324-2) - 2011/07/20 -NET "CLK_66MHz" TNM_NET = "CLK_66MHz"; -TIMESPEC TS_CLK_66MHz = PERIOD "CLK_66MHz" 66666 KHz HIGH 50 % INPUT_JITTER 1000 ps; - -# PlanAhead Generated physical constraints - -NET "BTN0" LOC = V4; -NET "CLK_66MHz" LOC = K15; -NET "LED0" LOC = P4; -NET "LED1" LOC = L6; -NET "LED2" LOC = F5; -NET "LED3" LOC = C2; -NET "SW0" LOC = B3; -NET "SW1" LOC = A3; -NET "SW2" LOC = B4; -NET "SW3" LOC = A4; -NET "UART_RXD" LOC = R7; -NET "UART_TXD" LOC = T7; -NET "DBG_OFF" LOC = C18; -NET "MCLK" LOC = F15; - -# PlanAhead Generated IO constraints - -NET "BTN0" IOSTANDARD = LVCMOS33; -NET "CLK_66MHz" IOSTANDARD = LVCMOS33; -NET "LED0" IOSTANDARD = LVCMOS18; -NET "LED1" IOSTANDARD = LVCMOS18; -NET "LED2" IOSTANDARD = LVCMOS18; -NET "LED3" IOSTANDARD = LVCMOS18; -NET "SW0" IOSTANDARD = LVCMOS33; -NET "SW1" IOSTANDARD = LVCMOS33; -NET "SW2" IOSTANDARD = LVCMOS33; -NET "SW3" IOSTANDARD = LVCMOS33; -NET "UART_RXD" IOSTANDARD = LVCMOS33; -NET "UART_TXD" IOSTANDARD = LVCMOS33; -NET "DBG_OFF" IOSTANDARD = LVCMOS33; -NET "MCLK" IOSTANDARD = LVCMOS33; -NET "LED0" DRIVE = 8; -NET "LED1" DRIVE = 8; -NET "LED2" DRIVE = 8; -NET "LED3" DRIVE = 8; -NET "BTN0" PULLDOWN; -NET "SW0" PULLDOWN; -NET "SW1" PULLDOWN; -NET "SW2" PULLDOWN; -NET "SW3" PULLDOWN; -NET "DBG_OFF" PULLUP; - -CONFIG VCCAUX = "3.3"; - -PIN "buf_sys_clock.O" CLOCK_DEDICATED_ROUTE = FALSE; \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit (nonexistent)

trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf (nonexistent)

trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf (nonexistent)

trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf (nonexistent)

trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h (nonexistent) @@ -1,78 +0,0 @@ -#ifndef HARDWARE_H -#define HARDWARE_H - -#define __msp430_have_port3 -#define __MSP430_HAS_PORT3__ - -#include -#include -#include - - -//PINS -//PORT1 -#define TX BIT1 - -//PORT2 -#define RX BIT2 -#define LED BIT1 - -//Port Output Register 'P1OUT, P2OUT': -#define P1OUT_INIT TX //Init Output data of port1 -#define P2OUT_INIT 0 //Init Output data of port2 -#define P3OUT_INIT 0 //Init Output data of port3 - -//Port Direction Register 'P1DIR, P2DIR': -#define P1DIR_INIT TX //Init of Port1 Data-Direction Reg (Out=1 / Inp=0) -#define P2DIR_INIT ~RX //Init of Port2 Data-Direction Reg (Out=1 / Inp=0) -#define P3DIR_INIT 0xff //Init of Port3 Data-Direction Reg (Out=1 / Inp=0) - -//Selection of Port or Module -Function on the Pins 'P1SEL, P2SEL' -#define P1SEL_INIT 0 //P1-Modules: -#define P2SEL_INIT RX //P2-Modules: -#define P3SEL_INIT 0 //P3-Modules: - -//Interrupt capabilities of P1 and P2 -#define P1IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) -#define P2IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) -#define P1IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) -#define P2IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) - -#define IE_INIT 0 -#define WDTCTL_INIT WDTPW|WDTHOLD - -#define BCSCTL1_FLL XT2OFF|DIVA1|RSEL2|RSEL0 -#define BCSCTL2_FLL 0 -#define TACTL_FLL TASSEL_2|TACLR -#define CCTL2_FLL CM0|CCIS0|CAP - -#define TACTL_AFTER_FLL TASSEL_2|TACLR|ID_0 - -//#define BAUD 40 //9600 @3MHz div 8 -//#define BAUD 20 //19200 @3MHz div 8 -//#define BAUD 20 //9600 @1.5MHz div 8 -//#define BAUD 140 //9600 @1.5MHz div 8 - -//#define BAUD 2083 //9600 @20.0MHz div 1 -//#define BAUD 1042 //19200 @20.0MHz div 1 -//#define BAUD 521 //38400 @20.0MHz div 1 -//#define BAUD 347 //57600 @20.0MHz div 1 -#define BAUD 174 //115200 @20.0MHz div 1 -//#define BAUD 87 //230400 @20.0MHz div 1 - -//Selection of 'Digitally Controlled Oszillator' (desired frquency in HZ, 1..3 MHz) -#define DCO_FREQ 1536000 //3072000/2 makes 9600 a bit more precise - -#ifndef P3DIR -#define P3IN_ 0x0018 /* Port 3 Input */ -const_sfrb(P3IN, P3IN_); -#define P3OUT_ 0x0019 /* Port 3 Output */ -sfrb(P3OUT, P3OUT_); -#define P3DIR_ 0x001A /* Port 3 Direction */ -sfrb(P3DIR, P3DIR_); -#define P3SEL_ 0x001B /* Port 3 Selection */ -sfrb(P3SEL, P3SEL_); -#endif - - -#endif //HARDWARE_H

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c (nonexistent) @@ -1,101 +0,0 @@ -/* -see README.txt for details. - -chris -*/ -#include "hardware.h" -#include -#include -#include "swuart.h" - -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - nop(); - nop(); - } -} - -/** -Main function with init an an endless loop that is synced with the -interrupts trough the lowpower mode. -*/ -int main(void) { - int reading = 0; - int pos = 0; - char buf[40]; - int led = 0; - - WDTCTL = WDTCTL_INIT; //Init watchdog timer - - P1OUT = P1OUT_INIT; //Init output data of port1 - P1SEL = P1SEL_INIT; //Select port or module -function on port1 - P1DIR = P1DIR_INIT; //Init port direction register of port1 - P1IES = P1IES_INIT; //init port interrupts - P1IE = P1IE_INIT; - - P2OUT = P2OUT_INIT; //Init output data of port2 - P2SEL = P2SEL_INIT; //Select port or module -function on port2 - P2DIR = P2DIR_INIT; //Init port direction register of port2 - P2IES = P2IES_INIT; //init port interrupts - P2IE = P2IE_INIT; - - P3DIR = 0xff; - P3OUT = 0xff; //light LED during init - delay(65535); //Wait for watch crystal startup - delay(65535); - P3OUT = 0x00; //switch off LED - - TACTL = TACTL_AFTER_FLL; //setup timer (still stopped) - CCTL0 = CCIE|CAP|CM_2|CCIS_1|SCS; //select P2.2 with UART signal - CCTL1 = 0; // - CCTL2 = 0; // - TACTL |= MC1; //start timer - - eint(); //enable interrupts - - printf("\r\n====== openMSP430 in action ======\r\n"); //say hello - printf("\r\nSimple Line Editor Ready\r\n"); //say hello - - while (1) { //main loop, never ends... - printf("> "); //show prompt - reading = 1; - while (reading) { //loop and read characters - LPM0; //sync, wakeup by irq - - led++; // Some lighting... - P3OUT = led&0xf; - - switch (rxdata) { - //process RETURN key - case '\r': - //case '\n': - printf("\r\n"); //finish line - buf[pos++] = 0; //to use printf... - printf(":%s\r\n", buf); - reading = 0; //exit read loop - pos = 0; //reset buffer - break; - //backspace - case '\b': - if (pos > 0) { //is there a char to delete? - pos--; //remove it in buffer - putchar('\b'); //go back - putchar(' '); //erase on screen - putchar('\b'); //go back - } - break; - //other characters - default: - //only store characters if buffer has space - if (pos < sizeof(buf)) { - putchar(rxdata); //echo - buf[pos++] = rxdata; //store - } - } - } - } -} -

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s (nonexistent) @@ -1,79 +0,0 @@ -#include "hardware.h" - -;variables -.data - .comm rxdata,1,1 ;char var - .comm rxshift,1,1 ;char var - .comm rxbit,2,2 ;short var, aligned - -.text - -;interrupt(TIMERA0_VECTOR) ;register interrupt vector -interrupt(18) ;register interrupt vector -;interrupt handler to receive as Timer_A UART -.global ccr0 ;place a label afterwards so -ccr0: ;that it is used in the listing - add rxbit, r0 - jmp .Lrxstart ;start bit - jmp .Lrxdatabit ;D0 - jmp .Lrxdatabit ;D1 - jmp .Lrxdatabit ;D2 - jmp .Lrxdatabit ;D3 - jmp .Lrxdatabit ;D4 - jmp .Lrxdatabit ;D5 - jmp .Lrxdatabit ;D6 -; jmp .Lrxlastbit ;D7 that one is following anyway - -.Lrxlastbit: ;last bit, handle byte - bit #SCCI, &CCTL0 ;read last bit - rrc.b rxshift ;and save it - clr rxbit ;reset state - mov #CCIE|CAP|CM_2|CCIS_1|SCS, &CCTL0 ;restore capture mode - mov.b rxshift, rxdata ;copy received data - bic #CPUOFF|OSCOFF|SCG0|SCG1, 0(r1) ;exit all lowpower modes - ;here you might do other things too, like setting a flag - ;that the wakeup comes from the Timer_A UART. however - ;it should not take longer than one bit time, otherwise - ;charcetrs will be lost. - reti - -.Lrxstart: ;startbit, init - clr rxshift ;clear input buffer - add #(BAUD/2), &CCR0 ;startbit + 1.5 bits -> first bit - mov #CCIE|CCIS_1|SCS, &CCTL0;set compare mode, sample bits - jmp .Lrxex ;set state,... - -.Lrxdatabit: ;save databit - bit #SCCI, &CCTL0 ;measure databit - rrc.b rxshift ;rotate in databit - -.Lrxex: add #BAUD, &CCR0 ;one bit delay - incd rxbit ;setup next state - reti - -; void serPutc(char) -;use an other Capture/Compare than for receiving (full duplex). -;this one is without interrupts and OUTMOD, because only -;this way P1.1 can be used. P1.1 is prefered because the -;BSL is on that pin too. -.global putchar - .type putchar, @function -putchar: ;send a byte - mov #0, &CCTL1 ;select compare mode - mov #10, r13 ;ten bits: Start, 8 Data, Stop - rla r15 ;shift in start bit (0) - bis #0x0200, r15 ;set tenth bit (1), thats the stop bit - mov &TAR, &CCR1 ;set up start time -.Lt1lp: add #BAUD, &CCR1 ;set up for one bit - rrc r15 ;shift data trough carry - jc .Lt1 ;test carry bit -.Lt0: bic.b #TX, &P1OUT ;generate pulse - jmp .Ltc ; -.Lt1: bis.b #TX, &P1OUT ;just use the same amount of time as for a zero - jmp .Ltc ; -.Ltc: bit #CCIFG, &CCTL1 ;wait for compare - jz .Ltc ;loop until the bit is set - bic #CCIFG, &CCTL1 ;clear for next loop - dec r13 ;decrement bit counter - jnz .Lt1lp ;loop until all bits are transmitted - ret

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt (nonexistent) @@ -1,47 +0,0 @@ -what's this? ------------- -it's a simple example project for the MSP430 series MCU and the GCC port -of the mspgcc project. the project contains a makefile and uses assembler -and C sources. this time it is a software UART with Timer_A. - -this example shows the following features: - - Timer_A uart, full duplex - o same pins as BSL (P1.1 TX, P2.2 RX) - o it contains a reusable code - - - software FLL - the watch crystal is used as reference and the main clock - is adjusted to 1.536MHz on startup - - - use uprintf to print formated strings and do a printf - emulation that prints to the serial port. - - - the main loop is a simple line editor. when a return character - ('\r', usualy RETURN key) is received, it writes the received - characters from the buffer to the serial port. - connect a terminal at 9600,N,8,1 to try it out. - - - makefile - o compile and link - o include assembler files - o convert to intel hex format - o generate a listing with mixed C / assembly - -required hardware ------------------ - - - a MSP430F1121 or larger device (any from the F1x series) - connect pins P1.1 (TX) and P2.2 (RX) through level converters - to a terminal. you can also use a BSL hardware, the same pins - are used. - - - watch crystal 32.768kHz - - - optionaly a LED on P2.5 (470 Ohms series resistor to GND) - -disclaimer ----------- -this example is part of the mspgcc project http://mspgcc.sf.net -see license.txt for details. - -chris \ No newline at end of file

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h (nonexistent) @@ -1,6 +0,0 @@ -#ifndef SWUART_H -#define SWUART_H - -void serPutc(char); //send one character over timer_a uart -extern char rxdata; -#endif //SWUART_H

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile (nonexistent) @@ -1,54 +0,0 @@ -# makfile configuration -NAME = ta_uart -OBJECTS = main.o swuart.o -CPU = msp430x1121 - -ASFLAGS = -mmcu=${CPU} -mforce-hwmul -x assembler-with-cpp -D_GNU_ASSEMBLER_ -c -CFLAGS = -mmcu=${CPU} -mforce-hwmul -O2 -Wall -g - -#switch the compiler (for the internal make rules) -CC = msp430-gcc -AS = msp430-gcc - -.PHONY: all FORCE clean download download-jtag download-bsl dist - -#all should be the first target. it's built when make is runwithout args -all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst - -#confgigure the next line if you want to use the serial download -download: download-uart -#download: download-jtag -#download: download-bsl - -#additional rules for files -${NAME}.elf: ${OBJECTS} - ${CC} -mmcu=${CPU} -o $@ ${OBJECTS} - -${NAME}.a43: ${NAME}.elf - msp430-objcopy -O ihex $^ $@ - -${NAME}.lst: ${NAME}.elf - msp430-objdump -dSt $^ > $@ - -download-jtag: all - msp430-jtag -e ${NAME}.elf - -download-bsl: all - msp430-bsl -e ${NAME}.elf - -download-uart: all - openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf - -clean: - rm -f ${NAME} ${NAME}.a43 ${NAME}.lst *.o - -#backup archive -dist: - tar czf dist.tgz *.c *.h *.txt makefile - -#dummy target as dependecy if something has to be build everytime -FORCE: - -#project dependencies -main.o: main.c hardware.h -swuart.o: swuart.s hardware.h

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst (nonexistent) @@ -1,1403 +0,0 @@ - -ta_uart.elf: file format elf32-msp430 - -SYMBOL TABLE: -0000f000 l d .text 00000000 .text -00000200 l d .bss 00000000 .bss -0000ffe0 l d .vectors 00000000 .vectors -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_pubnames 00000000 .debug_pubnames -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l *ABS* 00000000 IE1 -00000002 l *ABS* 00000000 IFG1 -00000120 l *ABS* 00000000 WDTCTL -00000020 l *ABS* 00000000 P1IN -00000021 l *ABS* 00000000 P1OUT -00000022 l *ABS* 00000000 P1DIR -00000023 l *ABS* 00000000 P1IFG -00000024 l *ABS* 00000000 P1IES -00000025 l *ABS* 00000000 P1IE -00000026 l *ABS* 00000000 P1SEL -00000028 l *ABS* 00000000 P2IN -00000029 l *ABS* 00000000 P2OUT -0000002a l *ABS* 00000000 P2DIR -0000002b l *ABS* 00000000 P2IFG -0000002c l *ABS* 00000000 P2IES -0000002d l *ABS* 00000000 P2IE -0000002e l *ABS* 00000000 P2SEL -0000012e l *ABS* 00000000 TAIV -00000160 l *ABS* 00000000 TACTL -00000162 l *ABS* 00000000 TACCTL0 -00000164 l *ABS* 00000000 TACCTL1 -00000166 l *ABS* 00000000 TACCTL2 -00000170 l *ABS* 00000000 TAR -00000172 l *ABS* 00000000 TACCR0 -00000174 l *ABS* 00000000 TACCR1 -00000176 l *ABS* 00000000 TACCR2 -00000056 l *ABS* 00000000 DCOCTL -00000057 l *ABS* 00000000 BCSCTL1 -00000058 l *ABS* 00000000 BCSCTL2 -00000128 l *ABS* 00000000 FCTL1 -0000012a l *ABS* 00000000 FCTL2 -0000012c l *ABS* 00000000 FCTL3 -00000059 l *ABS* 00000000 CACTL1 -0000005a l *ABS* 00000000 CACTL2 -0000005b l *ABS* 00000000 CAPD -00000002 l *ABS* 00000000 PUSH_BYTES -0000f030 l .text 00000000 _branch_to_unexpected_ -00000000 l df *ABS* 00000000 main.c -00000130 l *ABS* 00000000 __MPY -00000132 l *ABS* 00000000 __MPYS -00000134 l *ABS* 00000000 __MAC -00000136 l *ABS* 00000000 __MACS -00000138 l *ABS* 00000000 __OP2 -0000013a l *ABS* 00000000 __RESLO -0000013c l *ABS* 00000000 __RESHI -0000013e l *ABS* 00000000 __SUMEXT -00000000 l *ABS* 00000000 IE1 -00000002 l *ABS* 00000000 IFG1 -00000120 l *ABS* 00000000 WDTCTL -00000020 l *ABS* 00000000 P1IN -00000021 l *ABS* 00000000 P1OUT -00000022 l *ABS* 00000000 P1DIR -00000023 l *ABS* 00000000 P1IFG -00000024 l *ABS* 00000000 P1IES -00000025 l *ABS* 00000000 P1IE -00000026 l *ABS* 00000000 P1SEL -00000028 l *ABS* 00000000 P2IN -00000029 l *ABS* 00000000 P2OUT -0000002a l *ABS* 00000000 P2DIR -0000002b l *ABS* 00000000 P2IFG -0000002c l *ABS* 00000000 P2IES -0000002d l *ABS* 00000000 P2IE -0000002e l *ABS* 00000000 P2SEL -0000012e l *ABS* 00000000 TAIV -00000160 l *ABS* 00000000 TACTL -00000162 l *ABS* 00000000 TACCTL0 -00000164 l *ABS* 00000000 TACCTL1 -00000166 l *ABS* 00000000 TACCTL2 -00000170 l *ABS* 00000000 TAR -00000172 l *ABS* 00000000 TACCR0 -00000174 l *ABS* 00000000 TACCR1 -00000176 l *ABS* 00000000 TACCR2 -00000056 l *ABS* 00000000 DCOCTL -00000057 l *ABS* 00000000 BCSCTL1 -00000058 l *ABS* 00000000 BCSCTL2 -00000128 l *ABS* 00000000 FCTL1 -0000012a l *ABS* 00000000 FCTL2 -0000012c l *ABS* 00000000 FCTL3 -00000059 l *ABS* 00000000 CACTL1 -0000005a l *ABS* 00000000 CACTL2 -0000005b l *ABS* 00000000 CAPD -00000018 l *ABS* 00000000 P3IN -00000019 l *ABS* 00000000 P3OUT -0000001a l *ABS* 00000000 P3DIR -0000001b l *ABS* 00000000 P3SEL -00000000 l df *ABS* 00000000 printf.c -00000000 l df *ABS* 00000000 vuprintf.c -00000200 l O .bss 00000002 __write_char -00000202 l O .bss 00000002 total_len -0000f276 l F .text 00000044 PRINT -0000f2ba l F .text 00000040 __write_pad -00000000 l df *ABS* 00000000 puts.c -00000000 l df *ABS* 00000000 memchr.c -00000000 l df *ABS* 00000000 strlen.c -0000f20e g F .text 00000000 putchar -00000000 g *ABS* 00000000 __data_size -0000f248 g F .text 0000002e printf -0000fa9c g .text 00000000 _etext -00000009 g *ABS* 00000000 __bss_size -0000f030 w .text 00000000 vector_ffe0 -0000f9c2 g F .text 0000004a puts -0000f1b0 g .text 00000000 ccr0 -00000204 g O .bss 00000001 rxshift -00000206 g O .bss 00000002 rxbit -0000f030 w .text 00000000 vector_ffec -0000f030 w .text 00000000 vector_fff0 -0000fa9c g *ABS* 00000000 __data_load_start -0000f030 g .text 00000000 __dtors_end -0000f030 w .text 00000000 vector_fffc -0000f030 w .text 00000000 vector_ffe4 -0000ffe0 g O .vectors 00000020 InterruptVectors -00000208 g O .bss 00000001 rxdata -0000fa0e g F .text 0000003a memchr -0000f01c w .text 00000000 __do_clear_bss -0000f030 w .text 00000000 vector_ffe2 -0000f030 w .text 00000000 vector_ffe8 -0000fa0c w .text 00000000 _unexpected_ -0000f030 w .text 00000000 vector_fffa -0000f2fa g F .text 000006c8 vuprintf -0000f000 w .text 00000000 _reset_vector__ -0000f030 g .text 00000000 __ctors_start -0000f00a w .text 00000000 __do_copy_data -00000200 g .bss 00000000 __bss_start -0000f030 w .text 00000000 vector_ffee -0000f030 w .text 00000000 vector_fff4 -0000f090 g F .text 00000120 main -0000f030 w .text 00000000 vector_fff8 -0000f1b0 g .text 00000000 vector_fff2 -00010000 g .vectors 00000000 _vectors_end -0000f030 w .text 00000000 vector_ffe6 -0000f034 g F .text 0000000e delay -0000f000 w .text 00000000 __init_stack -0000f030 g .text 00000000 __dtors_start -0000f030 g .text 00000000 __ctors_end -00000300 g *ABS* 00000000 __stack -00000200 g .text 00000000 _edata -00000209 g .bss 00000000 _end -0000fa72 g .text 00000000 __udivmodsi4 -0000f030 w .text 00000000 vector_fff6 -0000fa48 g F .text 0000002a strlen -0000f004 w .text 00000000 __low_level_init -0000f02c w .text 00000000 __jump_to_main -00000200 g .text 00000000 __data_start -00000120 w *ABS* 00000000 __WDTCTL -0000f030 w .text 00000000 vector_ffea - - - -Disassembly of section .text: - -0000f000 <__init_stack>: - .weak __init_stack - - .func __init_stack - -__init_stack: - mov #__stack, r1 - f000: 31 40 00 03 mov #768, r1 ;#0x0300 - -0000f004 <__low_level_init>: - f004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 - f008: 20 01 - -0000f00a <__do_copy_data>: - .weak __do_copy_data - - .func __do_copy_data - -__do_copy_data: - mov #__data_size, r15 - f00a: 3f 40 00 00 mov #0, r15 ;#0x0000 - tst r15 - f00e: 0f 93 tst r15 - f010: 05 24 jz $+12 ;abs 0xf01c - jz .L__copy_data_end -.L__copy_data_loop: - decd r15 - f012: 2f 83 decd r15 - mov.w __data_load_start(r15), __data_start(r15) ; data section is word-aligned, so word transfer is acceptable - f014: 9f 4f 9c fa mov -1380(r15),512(r15);0xfa9c(r15), 0x0200(r15) - f018: 00 02 - f01a: fb 23 jnz $-8 ;abs 0xf012 - -0000f01c <__do_clear_bss>: - .weak __do_clear_bss - - .func __do_clear_bss - -__do_clear_bss: - mov #__bss_size, r15 - f01c: 3f 40 09 00 mov #9, r15 ;#0x0009 - tst r15 - f020: 0f 93 tst r15 - f022: 04 24 jz $+10 ;abs 0xf02c - jz .L__clear_bss_end -.L__clear_bss_loop: - dec r15 - f024: 1f 83 dec r15 - clr.b __bss_start(r15) - f026: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15) - f02a: fc 23 jnz $-6 ;abs 0xf024 - -0000f02c <__jump_to_main>: - .weak __jump_to_main - - .func __jump_to_main - -__jump_to_main: - br #main - f02c: 30 40 90 f0 br #0xf090 - -0000f030 <__ctors_end>: - f030: 30 40 0c fa br #0xfa0c - -0000f034 : - f034: 03 3c jmp $+8 ;abs 0xf03c -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - nop(); - f036: 03 43 nop - nop(); - f038: 03 43 nop - f03a: 3f 53 add #-1, r15 ;r3 As==11 - -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - f03c: 0f 93 tst r15 - f03e: fb 23 jnz $-8 ;abs 0xf036 - f040: 30 41 ret - f042: 0d 0a .word 0x0a0d; ???? - f044: 3d 3d jmp $+636 ;abs 0xf2c0 - f046: 3d 3d jmp $+636 ;abs 0xf2c2 - f048: 3d 3d jmp $+636 ;abs 0xf2c4 - f04a: 20 6f addc @r15, r0 - f04c: 70 65 addc.b @r5+, r0 - f04e: 6e 4d mov.b @r13, r14 - f050: 53 50 .word 0x5053; ???? Illegal as 2-op instr - f052: 34 33 jn $-406 ;abs 0xeebc - f054: 30 20 jnz $+98 ;abs 0xf0b6 - f056: 69 6e addc.b @r14, r9 - f058: 20 61 addc @r1, r0 - f05a: 63 74 .word 0x7463; ???? Illegal as 2-op instr - f05c: 69 6f addc.b @r15, r9 - f05e: 6e 20 jnz $+222 ;abs 0xf13c - f060: 3d 3d jmp $+636 ;abs 0xf2dc - f062: 3d 3d jmp $+636 ;abs 0xf2de - f064: 3d 3d jmp $+636 ;abs 0xf2e0 - f066: 0d 00 .word 0x000d; ???? - f068: 0d 0a .word 0x0a0d; ???? - f06a: 53 69 .word 0x6953; ???? Illegal as 2-op instr - f06c: 6d 70 subc.b @r0, r13 - f06e: 6c 65 addc.b @r5, r12 - f070: 20 4c br @r12 - f072: 69 6e addc.b @r14, r9 - f074: 65 20 jnz $+204 ;abs 0xf140 - f076: 45 64 addc.b r4, r5 - f078: 69 74 subc.b @r4, r9 - f07a: 6f 72 subc.b #4, r15 ;r2 As==10 - f07c: 20 52 add #4, r0 ;r2 As==10 - f07e: 65 61 addc.b @r1, r5 - f080: 64 79 subc.b @r9, r4 - f082: 0d 00 .word 0x000d; ???? - f084: 3e 20 jnz $+126 ;abs 0xf102 - f086: 00 0d .word 0x0d00; ???? - f088: 00 3a jl $-1022 ;abs 0xec8a - f08a: 25 73 subc #2, r5 ;r3 As==10 - f08c: 0d 0a .word 0x0a0d; ???? - ... - -0000f090
: - -/** -Main function with init an an endless loop that is synced with the -interrupts trough the lowpower mode. -*/ -int main(void) { - f090: 31 40 d8 02 mov #728, r1 ;#0x02d8 - int reading = 0; - int pos = 0; - char buf[40]; - int led = 0; - - WDTCTL = WDTCTL_INIT; //Init watchdog timer - f094: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 - f098: 20 01 - - P1OUT = P1OUT_INIT; //Init output data of port1 - f09a: e2 43 21 00 mov.b #2, &0x0021 ;r3 As==10 - P1SEL = P1SEL_INIT; //Select port or module -function on port1 - f09e: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 - P1DIR = P1DIR_INIT; //Init port direction register of port1 - f0a2: e2 43 22 00 mov.b #2, &0x0022 ;r3 As==10 - P1IES = P1IES_INIT; //init port interrupts - f0a6: c2 43 24 00 mov.b #0, &0x0024 ;r3 As==00 - P1IE = P1IE_INIT; - f0aa: c2 43 25 00 mov.b #0, &0x0025 ;r3 As==00 - - P2OUT = P2OUT_INIT; //Init output data of port2 - f0ae: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 - P2SEL = P2SEL_INIT; //Select port or module -function on port2 - f0b2: e2 42 2e 00 mov.b #4, &0x002e ;r2 As==10 - P2DIR = P2DIR_INIT; //Init port direction register of port2 - f0b6: f2 40 fb ff mov.b #-5, &0x002a ;#0xfffb - f0ba: 2a 00 - P2IES = P2IES_INIT; //init port interrupts - f0bc: c2 43 2c 00 mov.b #0, &0x002c ;r3 As==00 - P2IE = P2IE_INIT; - f0c0: c2 43 2d 00 mov.b #0, &0x002d ;r3 As==00 - - P3DIR = 0xff; - f0c4: f2 43 1a 00 mov.b #-1, &0x001a ;r3 As==11 - P3OUT = 0xff; //light LED during init - f0c8: f2 43 19 00 mov.b #-1, &0x0019 ;r3 As==11 - f0cc: 3f 40 fe ff mov #-2, r15 ;#0xfffe -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - nop(); - f0d0: 03 43 nop - nop(); - f0d2: 03 43 nop - -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - f0d4: 3f 53 add #-1, r15 ;r3 As==11 - f0d6: 3f 93 cmp #-1, r15 ;r3 As==11 - f0d8: fb 23 jnz $-8 ;abs 0xf0d0 - f0da: 3f 53 add #-1, r15 ;r3 As==11 - nop(); - f0dc: 03 43 nop - nop(); - f0de: 03 43 nop - -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - f0e0: 3f 53 add #-1, r15 ;r3 As==11 - f0e2: 3f 93 cmp #-1, r15 ;r3 As==11 - f0e4: fb 23 jnz $-8 ;abs 0xf0dc - - P3DIR = 0xff; - P3OUT = 0xff; //light LED during init - delay(65535); //Wait for watch crystal startup - delay(65535); - P3OUT = 0x00; //switch off LED - f0e6: c2 43 19 00 mov.b #0, &0x0019 ;r3 As==00 - - TACTL = TACTL_AFTER_FLL; //setup timer (still stopped) - f0ea: b2 40 04 02 mov #516, &0x0160 ;#0x0204 - f0ee: 60 01 - CCTL0 = CCIE|CAP|CM_2|CCIS_1|SCS; //select P2.2 with UART signal - f0f0: b2 40 10 99 mov #-26352,&0x0162 ;#0x9910 - f0f4: 62 01 - CCTL1 = 0; // - f0f6: 82 43 64 01 mov #0, &0x0164 ;r3 As==00 - CCTL2 = 0; // - f0fa: 82 43 66 01 mov #0, &0x0166 ;r3 As==00 - TACTL |= MC1; //start timer - f0fe: b2 d0 20 00 bis #32, &0x0160 ;#0x0020 - f102: 60 01 - - eint(); //enable interrupts - f104: 32 d2 eint - - printf("\r\n====== openMSP430 in action ======\r\n"); //say hello - f106: 3f 40 42 f0 mov #-4030, r15 ;#0xf042 - f10a: b0 12 c2 f9 call #0xf9c2 - printf("\r\nSimple Line Editor Ready\r\n"); //say hello - f10e: 3f 40 68 f0 mov #-3992, r15 ;#0xf068 - f112: b0 12 c2 f9 call #0xf9c2 - f116: 0a 43 clr r10 - } - break; - //other characters - default: - //only store characters if buffer has space - if (pos < sizeof(buf)) { - f118: 39 40 27 00 mov #39, r9 ;#0x0027 - - printf("\r\n====== openMSP430 in action ======\r\n"); //say hello - printf("\r\nSimple Line Editor Ready\r\n"); //say hello - - while (1) { //main loop, never ends... - printf("> "); //show prompt - f11c: 30 12 84 f0 push #-3964 ;#0xf084 - f120: b0 12 48 f2 call #0xf248 - f124: 0b 43 clr r11 - f126: 21 53 incd r1 - f128: 5f 42 08 02 mov.b &0x0208,r15 - reading = 1; - while (reading) { //loop and read characters - LPM0; //sync, wakeup by irq - f12c: 32 d0 10 00 bis #16, r2 ;#0x0010 - - led++; // Some lighting... - f130: 1a 53 inc r10 - P3OUT = led&0xf; - f132: 4e 4a mov.b r10, r14 - f134: 7e f0 0f 00 and.b #15, r14 ;#0x000f - f138: c2 4e 19 00 mov.b r14, &0x0019 - - switch (rxdata) { - f13c: 7f 92 cmp.b #8, r15 ;r2 As==11 - f13e: 19 24 jz $+52 ;abs 0xf172 - f140: 7f 90 0d 00 cmp.b #13, r15 ;#0x000d - f144: 26 24 jz $+78 ;abs 0xf192 - } - break; - //other characters - default: - //only store characters if buffer has space - if (pos < sizeof(buf)) { - f146: 09 9b cmp r11, r9 - f148: f1 2b jnc $-28 ;abs 0xf12c - putchar(rxdata); //echo - f14a: 8f 11 sxt r15 - f14c: b0 12 0e f2 call #0xf20e - buf[pos++] = rxdata; //store - f150: 0f 41 mov r1, r15 - f152: 0f 5b add r11, r15 - f154: df 42 08 02 mov.b &0x0208,0(r15) ;0x0000(r15) - f158: 00 00 - f15a: 1b 53 inc r11 - f15c: 6f 4f mov.b @r15, r15 - - while (1) { //main loop, never ends... - printf("> "); //show prompt - reading = 1; - while (reading) { //loop and read characters - LPM0; //sync, wakeup by irq - f15e: 32 d0 10 00 bis #16, r2 ;#0x0010 - - led++; // Some lighting... - f162: 1a 53 inc r10 - P3OUT = led&0xf; - f164: 4e 4a mov.b r10, r14 - f166: 7e f0 0f 00 and.b #15, r14 ;#0x000f - f16a: c2 4e 19 00 mov.b r14, &0x0019 - - switch (rxdata) { - f16e: 7f 92 cmp.b #8, r15 ;r2 As==11 - f170: e7 23 jnz $-48 ;abs 0xf140 - reading = 0; //exit read loop - pos = 0; //reset buffer - break; - //backspace - case '\b': - if (pos > 0) { //is there a char to delete? - f172: 0b 93 tst r11 - f174: db 27 jz $-72 ;abs 0xf12c - pos--; //remove it in buffer - f176: 3b 53 add #-1, r11 ;r3 As==11 - putchar('\b'); //go back - f178: 3f 42 mov #8, r15 ;r2 As==11 - f17a: b0 12 0e f2 call #0xf20e - putchar(' '); //erase on screen - f17e: 3f 40 20 00 mov #32, r15 ;#0x0020 - f182: b0 12 0e f2 call #0xf20e - putchar('\b'); //go back - f186: 3f 42 mov #8, r15 ;r2 As==11 - f188: b0 12 0e f2 call #0xf20e - f18c: 5f 42 08 02 mov.b &0x0208,r15 - f190: cd 3f jmp $-100 ;abs 0xf12c - - switch (rxdata) { - //process RETURN key - case '\r': - //case '\n': - printf("\r\n"); //finish line - f192: 3f 40 87 f0 mov #-3961, r15 ;#0xf087 - f196: b0 12 c2 f9 call #0xf9c2 - buf[pos++] = 0; //to use printf... - f19a: 0b 51 add r1, r11 - f19c: cb 43 00 00 mov.b #0, 0(r11) ;r3 As==00, 0x0000(r11) - printf(":%s\r\n", buf); - f1a0: 04 41 mov r1, r4 - f1a2: 04 12 push r4 - f1a4: 30 12 89 f0 push #-3959 ;#0xf089 - f1a8: b0 12 48 f2 call #0xf248 - f1ac: 21 52 add #4, r1 ;r2 As==10 - f1ae: b6 3f jmp $-146 ;abs 0xf11c - -0000f1b0 : - f1b0: 10 50 54 10 add 0x1054, r0 ;PC rel. 0x10208 - f1b4: 18 3c jmp $+50 ;abs 0xf1e6 - f1b6: 20 3c jmp $+66 ;abs 0xf1f8 - f1b8: 1f 3c jmp $+64 ;abs 0xf1f8 - f1ba: 1e 3c jmp $+62 ;abs 0xf1f8 - f1bc: 1d 3c jmp $+60 ;abs 0xf1f8 - f1be: 1c 3c jmp $+58 ;abs 0xf1f8 - f1c0: 1b 3c jmp $+56 ;abs 0xf1f8 - f1c2: 1a 3c jmp $+54 ;abs 0xf1f8 - f1c4: b2 b0 00 04 bit #1024, &0x0162 ;#0x0400 - f1c8: 62 01 - f1ca: 50 10 38 10 rrc.b 0x1038 ;PC rel. 0x10206 - f1ce: 80 43 36 10 mov #0, 0x1036 ;r3 As==00, PC rel. 0x10208 - f1d2: b2 40 10 99 mov #-26352,&0x0162 ;#0x9910 - f1d6: 62 01 - f1d8: d0 40 2a 10 mov.b 0x102a, 0x102c ;PC rel. 0x10206, PC rel. 0x1020a - f1dc: 2c 10 - f1de: b1 c0 f0 00 bic #240, 0(r1) ;#0x00f0, 0x0000(r1) - f1e2: 00 00 - f1e4: 00 13 reti - f1e6: 80 43 1c 10 mov #0, 0x101c ;r3 As==00, PC rel. 0x10206 - f1ea: b2 50 57 00 add #87, &0x0172 ;#0x0057 - f1ee: 72 01 - f1f0: b2 40 10 18 mov #6160, &0x0162 ;#0x1810 - f1f4: 62 01 - f1f6: 05 3c jmp $+12 ;abs 0xf202 - f1f8: b2 b0 00 04 bit #1024, &0x0162 ;#0x0400 - f1fc: 62 01 - f1fe: 50 10 04 10 rrc.b 0x1004 ;PC rel. 0x10206 - f202: b2 50 ae 00 add #174, &0x0172 ;#0x00ae - f206: 72 01 - f208: a0 53 fc 0f incd 0x0ffc ;PC rel. 0x10208 - f20c: 00 13 reti - -0000f20e : - f20e: 82 43 64 01 mov #0, &0x0164 ;r3 As==00 - f212: 3d 40 0a 00 mov #10, r13 ;#0x000a - f216: 0f 5f rla r15 - f218: 3f d0 00 02 bis #512, r15 ;#0x0200 - f21c: 92 42 70 01 mov &0x0170,&0x0174 - f220: 74 01 - f222: b2 50 ae 00 add #174, &0x0174 ;#0x00ae - f226: 74 01 - f228: 0f 10 rrc r15 - f22a: 03 2c jc $+8 ;abs 0xf232 - f22c: e2 c3 21 00 bic.b #2, &0x0021 ;r3 As==10 - f230: 03 3c jmp $+8 ;abs 0xf238 - f232: e2 d3 21 00 bis.b #2, &0x0021 ;r3 As==10 - f236: 00 3c jmp $+2 ;abs 0xf238 - f238: 92 b3 64 01 bit #1, &0x0164 ;r3 As==01 - f23c: fd 27 jz $-4 ;abs 0xf238 - f23e: 92 c3 64 01 bic #1, &0x0164 ;r3 As==01 - f242: 1d 83 dec r13 - f244: ee 23 jnz $-34 ;abs 0xf222 - f246: 30 41 ret - -0000f248 : - f248: 04 12 push r4 - f24a: 21 82 sub #4, r1 ;r2 As==10 - f24c: 04 41 mov r1, r4 - f24e: 0f 44 mov r4, r15 - f250: 3f 50 0a 00 add #10, r15 ;#0x000a - f254: 84 4f 02 00 mov r15, 2(r4) ;0x0002(r4) - f258: 1f 44 02 00 mov 2(r4), r15 ;0x0002(r4) - f25c: 0d 4f mov r15, r13 - f25e: 1e 44 08 00 mov 8(r4), r14 ;0x0008(r4) - f262: 3f 40 0e f2 mov #-3570, r15 ;#0xf20e - f266: b0 12 fa f2 call #0xf2fa - f26a: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - f26e: 2f 44 mov @r4, r15 - f270: 21 52 add #4, r1 ;r2 As==10 - f272: 34 41 pop r4 - f274: 30 41 ret - -0000f276 : - f276: 04 12 push r4 - f278: 21 82 sub #4, r1 ;r2 As==10 - f27a: 04 41 mov r1, r4 - f27c: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - f280: 84 4e 02 00 mov r14, 2(r4) ;0x0002(r4) - f284: 13 3c jmp $+40 ;abs 0xf2ac - f286: 1e 42 00 02 mov &0x0200,r14 - f28a: 2f 44 mov @r4, r15 - f28c: 6f 4f mov.b @r15, r15 - f28e: 8f 11 sxt r15 - f290: 94 53 00 00 inc 0(r4) ;0x0000(r4) - f294: 8e 12 call r14 - f296: 0f 93 tst r15 - f298: 02 34 jge $+6 ;abs 0xf29e - f29a: 3f 43 mov #-1, r15 ;r3 As==11 - f29c: 0b 3c jmp $+24 ;abs 0xf2b4 - f29e: 1f 42 02 02 mov &0x0202,r15 - f2a2: 1f 53 inc r15 - f2a4: 82 4f 02 02 mov r15, &0x0202 - f2a8: b4 53 02 00 add #-1, 2(r4) ;r3 As==11, 0x0002(r4) - f2ac: 84 93 02 00 tst 2(r4) ;0x0002(r4) - f2b0: ea 23 jnz $-42 ;abs 0xf286 - f2b2: 1f 43 mov #1, r15 ;r3 As==01 - f2b4: 21 52 add #4, r1 ;r2 As==10 - f2b6: 34 41 pop r4 - f2b8: 30 41 ret - -0000f2ba <__write_pad>: - f2ba: 04 12 push r4 - f2bc: 21 83 decd r1 - f2be: 04 41 mov r1, r4 - f2c0: c4 4f 00 00 mov.b r15, 0(r4) ;0x0000(r4) - f2c4: c4 4e 01 00 mov.b r14, 1(r4) ;0x0001(r4) - f2c8: 10 3c jmp $+34 ;abs 0xf2ea - f2ca: 1e 42 00 02 mov &0x0200,r14 - f2ce: 6f 44 mov.b @r4, r15 - f2d0: 8f 11 sxt r15 - f2d2: 8e 12 call r14 - f2d4: 0f 93 tst r15 - f2d6: 02 34 jge $+6 ;abs 0xf2dc - f2d8: 3f 43 mov #-1, r15 ;r3 As==11 - f2da: 0c 3c jmp $+26 ;abs 0xf2f4 - f2dc: 1f 42 02 02 mov &0x0202,r15 - f2e0: 1f 53 inc r15 - f2e2: 82 4f 02 02 mov r15, &0x0202 - f2e6: f4 53 01 00 add.b #-1, 1(r4) ;r3 As==11, 0x0001(r4) - f2ea: d4 93 01 00 cmp.b #1, 1(r4) ;r3 As==01, 0x0001(r4) - f2ee: ed 37 jge $-36 ;abs 0xf2ca - f2f0: 6f 44 mov.b @r4, r15 - f2f2: 7f f3 and.b #-1, r15 ;r3 As==11 - f2f4: 21 53 incd r1 - f2f6: 34 41 pop r4 - f2f8: 30 41 ret - -0000f2fa : - f2fa: 0b 12 push r11 - f2fc: 0a 12 push r10 - f2fe: 09 12 push r9 - f300: 08 12 push r8 - f302: 07 12 push r7 - f304: 06 12 push r6 - f306: 05 12 push r5 - f308: 04 12 push r4 - f30a: 31 50 ba ff add #-70, r1 ;#0xffba - f30e: 04 41 mov r1, r4 - f310: 84 4f 3c 00 mov r15, 60(r4) ;0x003c(r4) - f314: 84 4e 3e 00 mov r14, 62(r4) ;0x003e(r4) - f318: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f31c: 84 43 08 00 mov #0, 8(r4) ;r3 As==00, 0x0008(r4) - f320: 84 43 0a 00 mov #0, 10(r4) ;r3 As==00, 0x000a(r4) - f324: c4 43 02 00 mov.b #0, 2(r4) ;r3 As==00, 0x0002(r4) - f328: 82 43 02 02 mov #0, &0x0202 ;r3 As==00 - f32c: 92 44 3c 00 mov 60(r4), &0x0200 ;0x003c(r4) - f330: 00 02 - f332: 94 44 3e 00 mov 62(r4), 68(r4) ;0x003e(r4), 0x0044(r4) - f336: 44 00 - f338: 05 3c jmp $+12 ;abs 0xf344 - f33a: 03 43 nop - f33c: 03 3c jmp $+8 ;abs 0xf344 - f33e: 03 43 nop - f340: 01 3c jmp $+4 ;abs 0xf344 - f342: 03 43 nop - f344: 94 44 44 00 mov 68(r4), 14(r4) ;0x0044(r4), 0x000e(r4) - f348: 0e 00 - f34a: 02 3c jmp $+6 ;abs 0xf350 - f34c: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f350: 1d 44 44 00 mov 68(r4), r13 ;0x0044(r4) - f354: 66 4d mov.b @r13, r6 - f356: 46 93 tst.b r6 - f358: 03 24 jz $+8 ;abs 0xf360 - f35a: 76 90 25 00 cmp.b #37, r6 ;#0x0025 - f35e: f6 23 jnz $-18 ;abs 0xf34c - f360: 1e 44 44 00 mov 68(r4), r14 ;0x0044(r4) - f364: 1f 44 0e 00 mov 14(r4), r15 ;0x000e(r4) - f368: 0b 4e mov r14, r11 - f36a: 0b 8f sub r15, r11 - f36c: 09 24 jz $+20 ;abs 0xf380 - f36e: 0e 4b mov r11, r14 - f370: 1f 44 0e 00 mov 14(r4), r15 ;0x000e(r4) - f374: b0 12 76 f2 call #0xf276 - f378: 0f 93 tst r15 - f37a: 02 34 jge $+6 ;abs 0xf380 - f37c: 30 40 8a f9 br #0xf98a - f380: 46 93 tst.b r6 - f382: 02 20 jnz $+6 ;abs 0xf388 - f384: 30 40 8e f9 br #0xf98e - f388: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f38c: 47 43 clr.b r7 - f38e: c4 43 05 00 mov.b #0, 5(r4) ;r3 As==00, 0x0005(r4) - f392: c4 43 0d 00 mov.b #0, 13(r4) ;r3 As==00, 0x000d(r4) - f396: f4 43 0c 00 mov.b #-1, 12(r4) ;r3 As==11, 0x000c(r4) - f39a: c4 43 10 00 mov.b #0, 16(r4) ;r3 As==00, 0x0010(r4) - f39e: 05 3c jmp $+12 ;abs 0xf3aa - f3a0: 03 43 nop - f3a2: 03 3c jmp $+8 ;abs 0xf3aa - f3a4: 03 43 nop - f3a6: 01 3c jmp $+4 ;abs 0xf3aa - f3a8: 03 43 nop - f3aa: 1e 44 44 00 mov 68(r4), r14 ;0x0044(r4) - f3ae: 66 4e mov.b @r14, r6 - f3b0: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f3b4: 76 90 75 00 cmp.b #117, r6 ;#0x0075 - f3b8: 06 24 jz $+14 ;abs 0xf3c6 - f3ba: 4f 46 mov.b r6, r15 - f3bc: 7f d0 20 00 bis.b #32, r15 ;#0x0020 - f3c0: 7f 90 78 00 cmp.b #120, r15 ;#0x0078 - f3c4: 1b 20 jnz $+56 ;abs 0xf3fc - f3c6: 4f 47 mov.b r7, r15 - f3c8: 1f f3 and #1, r15 ;r3 As==01 - f3ca: 4f 93 tst.b r15 - f3cc: 0c 24 jz $+26 ;abs 0xf3e6 - f3ce: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f3d2: 0d 4f mov r15, r13 - f3d4: 2d 52 add #4, r13 ;r2 As==10 - f3d6: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f3da: b4 4f 08 00 mov @r15+, 8(r4) ;0x0008(r4) - f3de: b4 4f 0a 00 mov @r15+, 10(r4) ;0x000a(r4) - f3e2: 2f 82 sub #4, r15 ;r2 As==10 - f3e4: 0b 3c jmp $+24 ;abs 0xf3fc - f3e6: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f3ea: 0e 4f mov r15, r14 - f3ec: 2e 53 incd r14 - f3ee: 84 4e 40 00 mov r14, 64(r4) ;0x0040(r4) - f3f2: 2b 4f mov @r15, r11 - f3f4: 84 4b 08 00 mov r11, 8(r4) ;0x0008(r4) - f3f8: 84 43 0a 00 mov #0, 10(r4) ;r3 As==00, 0x000a(r4) - f3fc: 76 90 20 00 cmp.b #32, r6 ;#0x0020 - f400: 08 20 jnz $+18 ;abs 0xf412 - f402: 5f 44 10 00 mov.b 16(r4), r15 ;0x0010(r4) - f406: 4f 93 tst.b r15 - f408: cb 23 jnz $-104 ;abs 0xf3a0 - f40a: f4 40 20 00 mov.b #32, 16(r4) ;#0x0020, 0x0010(r4) - f40e: 10 00 - f410: cc 3f jmp $-102 ;abs 0xf3aa - f412: 76 90 23 00 cmp.b #35, r6 ;#0x0023 - f416: 02 20 jnz $+6 ;abs 0xf41c - f418: 77 d2 bis.b #8, r7 ;r2 As==11 - f41a: c7 3f jmp $-112 ;abs 0xf3aa - f41c: 76 90 2a 00 cmp.b #42, r6 ;#0x002a - f420: 03 24 jz $+8 ;abs 0xf428 - f422: 76 90 2d 00 cmp.b #45, r6 ;#0x002d - f426: 1a 20 jnz $+54 ;abs 0xf45c - f428: 76 90 2a 00 cmp.b #42, r6 ;#0x002a - f42c: 12 20 jnz $+38 ;abs 0xf452 - f42e: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f432: 0d 4f mov r15, r13 - f434: 2d 53 incd r13 - f436: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f43a: 2f 4f mov @r15, r15 - f43c: c4 4f 0d 00 mov.b r15, 13(r4) ;0x000d(r4) - f440: c4 93 0d 00 tst.b 13(r4) ;0x000d(r4) - f444: af 37 jge $-160 ;abs 0xf3a4 - f446: 5f 44 0d 00 mov.b 13(r4), r15 ;0x000d(r4) - f44a: 7f e3 xor.b #-1, r15 ;r3 As==11 - f44c: 5f 53 inc.b r15 - f44e: c4 4f 0d 00 mov.b r15, 13(r4) ;0x000d(r4) - f452: 77 d0 10 00 bis.b #16, r7 ;#0x0010 - f456: 77 f0 df ff and.b #-33, r7 ;#0xffdf - f45a: a7 3f jmp $-176 ;abs 0xf3aa - f45c: 76 90 2b 00 cmp.b #43, r6 ;#0x002b - f460: 04 20 jnz $+10 ;abs 0xf46a - f462: f4 40 2b 00 mov.b #43, 16(r4) ;#0x002b, 0x0010(r4) - f466: 10 00 - f468: a0 3f jmp $-190 ;abs 0xf3aa - f46a: 76 90 2e 00 cmp.b #46, r6 ;#0x002e - f46e: 3a 20 jnz $+118 ;abs 0xf4e4 - f470: 1e 44 44 00 mov 68(r4), r14 ;0x0044(r4) - f474: 66 4e mov.b @r14, r6 - f476: 4f 43 clr.b r15 - f478: 76 90 2a 00 cmp.b #42, r6 ;#0x002a - f47c: 01 20 jnz $+4 ;abs 0xf480 - f47e: 5f 43 mov.b #1, r15 ;r3 As==01 - f480: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f484: 4f 93 tst.b r15 - f486: 0e 24 jz $+30 ;abs 0xf4a4 - f488: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f48c: 0d 4f mov r15, r13 - f48e: 2d 53 incd r13 - f490: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f494: 2b 4f mov @r15, r11 - f496: 0f 4b mov r11, r15 - f498: 0f 93 tst r15 - f49a: 01 34 jge $+4 ;abs 0xf49e - f49c: 3f 43 mov #-1, r15 ;r3 As==11 - f49e: c4 4f 0c 00 mov.b r15, 12(r4) ;0x000c(r4) - f4a2: 83 3f jmp $-248 ;abs 0xf3aa - f4a4: 0b 43 clr r11 - f4a6: 11 3c jmp $+36 ;abs 0xf4ca - f4a8: 0f 4b mov r11, r15 - f4aa: 0f 5f rla r15 - f4ac: 0f 5f rla r15 - f4ae: 0f 5b add r11, r15 - f4b0: 0f 5f rla r15 - f4b2: 0e 4f mov r15, r14 - f4b4: 4f 46 mov.b r6, r15 - f4b6: 8f 11 sxt r15 - f4b8: 3f 50 d0 ff add #-48, r15 ;#0xffd0 - f4bc: 0b 4e mov r14, r11 - f4be: 0b 5f add r15, r11 - f4c0: 1e 44 44 00 mov 68(r4), r14 ;0x0044(r4) - f4c4: 66 4e mov.b @r14, r6 - f4c6: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f4ca: 76 90 3a 00 cmp.b #58, r6 ;#0x003a - f4ce: 03 34 jge $+8 ;abs 0xf4d6 - f4d0: 76 90 30 00 cmp.b #48, r6 ;#0x0030 - f4d4: e9 37 jge $-44 ;abs 0xf4a8 - f4d6: 0f 4b mov r11, r15 - f4d8: 0f 93 tst r15 - f4da: 01 34 jge $+4 ;abs 0xf4de - f4dc: 3f 43 mov #-1, r15 ;r3 As==11 - f4de: c4 4f 0c 00 mov.b r15, 12(r4) ;0x000c(r4) - f4e2: 68 3f jmp $-302 ;abs 0xf3b4 - f4e4: 76 90 30 00 cmp.b #48, r6 ;#0x0030 - f4e8: 07 20 jnz $+16 ;abs 0xf4f8 - f4ea: 4f 47 mov.b r7, r15 - f4ec: 3f f0 10 00 and #16, r15 ;#0x0010 - f4f0: 5b 23 jnz $-328 ;abs 0xf3a8 - f4f2: 77 d0 20 00 bis.b #32, r7 ;#0x0020 - f4f6: 59 3f jmp $-332 ;abs 0xf3aa - f4f8: 76 90 31 00 cmp.b #49, r6 ;#0x0031 - f4fc: 1e 38 jl $+62 ;abs 0xf53a - f4fe: 76 90 3a 00 cmp.b #58, r6 ;#0x003a - f502: 1b 34 jge $+56 ;abs 0xf53a - f504: 0b 43 clr r11 - f506: 0f 4b mov r11, r15 - f508: 0f 5f rla r15 - f50a: 0f 5f rla r15 - f50c: 0f 5b add r11, r15 - f50e: 0f 5f rla r15 - f510: 0e 4f mov r15, r14 - f512: 4f 46 mov.b r6, r15 - f514: 8f 11 sxt r15 - f516: 3f 50 d0 ff add #-48, r15 ;#0xffd0 - f51a: 0b 4e mov r14, r11 - f51c: 0b 5f add r15, r11 - f51e: 1f 44 44 00 mov 68(r4), r15 ;0x0044(r4) - f522: 66 4f mov.b @r15, r6 - f524: 94 53 44 00 inc 68(r4) ;0x0044(r4) - f528: 76 90 3a 00 cmp.b #58, r6 ;#0x003a - f52c: 03 34 jge $+8 ;abs 0xf534 - f52e: 76 90 30 00 cmp.b #48, r6 ;#0x0030 - f532: e9 37 jge $-44 ;abs 0xf506 - f534: c4 4b 0d 00 mov.b r11, 13(r4) ;0x000d(r4) - f538: 3d 3f jmp $-388 ;abs 0xf3b4 - f53a: 76 90 68 00 cmp.b #104, r6 ;#0x0068 - f53e: 02 20 jnz $+6 ;abs 0xf544 - f540: 67 d2 bis.b #4, r7 ;r2 As==10 - f542: 33 3f jmp $-408 ;abs 0xf3aa - f544: 76 90 6c 00 cmp.b #108, r6 ;#0x006c - f548: 02 20 jnz $+6 ;abs 0xf54e - f54a: 57 d3 bis.b #1, r7 ;r3 As==01 - f54c: 2e 3f jmp $-418 ;abs 0xf3aa - f54e: 76 90 63 00 cmp.b #99, r6 ;#0x0063 - f552: 11 20 jnz $+36 ;abs 0xf576 - f554: 05 44 mov r4, r5 - f556: 35 50 11 00 add #17, r5 ;#0x0011 - f55a: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f55e: 0d 4f mov r15, r13 - f560: 2d 53 incd r13 - f562: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f566: 2f 4f mov @r15, r15 - f568: c5 4f 00 00 mov.b r15, 0(r5) ;0x0000(r5) - f56c: d4 43 02 00 mov.b #1, 2(r4) ;r3 As==01, 0x0002(r4) - f570: c4 43 10 00 mov.b #0, 16(r4) ;r3 As==00, 0x0010(r4) - f574: 6b 3d jmp $+728 ;abs 0xf84c - f576: 76 90 44 00 cmp.b #68, r6 ;#0x0044 - f57a: 06 24 jz $+14 ;abs 0xf588 - f57c: 76 90 64 00 cmp.b #100, r6 ;#0x0064 - f580: 03 24 jz $+8 ;abs 0xf588 - f582: 76 90 69 00 cmp.b #105, r6 ;#0x0069 - f586: 42 20 jnz $+134 ;abs 0xf60c - f588: 76 90 44 00 cmp.b #68, r6 ;#0x0044 - f58c: 01 20 jnz $+4 ;abs 0xf590 - f58e: 57 d3 bis.b #1, r7 ;r3 As==01 - f590: 4f 47 mov.b r7, r15 - f592: 1f f3 and #1, r15 ;r3 As==01 - f594: 4f 93 tst.b r15 - f596: 0d 24 jz $+28 ;abs 0xf5b2 - f598: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f59c: 0e 4f mov r15, r14 - f59e: 2e 52 add #4, r14 ;r2 As==10 - f5a0: 84 4e 40 00 mov r14, 64(r4) ;0x0040(r4) - f5a4: 3e 4f mov @r15+, r14 - f5a6: 2f 4f mov @r15, r15 - f5a8: 84 4e 08 00 mov r14, 8(r4) ;0x0008(r4) - f5ac: 84 4f 0a 00 mov r15, 10(r4) ;0x000a(r4) - f5b0: 14 3c jmp $+42 ;abs 0xf5da - f5b2: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f5b6: 0d 4f mov r15, r13 - f5b8: 2d 53 incd r13 - f5ba: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f5be: 2b 4f mov @r15, r11 - f5c0: 84 4b 08 00 mov r11, 8(r4) ;0x0008(r4) - f5c4: 94 44 08 00 mov 8(r4), 10(r4) ;0x0008(r4), 0x000a(r4) - f5c8: 0a 00 - f5ca: 94 54 0a 00 rla 10(r4) ;0x000a(r4) - f5ce: 0a 00 - f5d0: 94 74 0a 00 subc 10(r4), 10(r4) ;0x000a(r4), 0x000a(r4) - f5d4: 0a 00 - f5d6: b4 e3 0a 00 xor #-1, 10(r4) ;r3 As==11, 0x000a(r4) - f5da: 1e 44 08 00 mov 8(r4), r14 ;0x0008(r4) - f5de: 1f 44 0a 00 mov 10(r4), r15 ;0x000a(r4) - f5e2: 0f 93 tst r15 - f5e4: 0f 34 jge $+32 ;abs 0xf604 - f5e6: 1e 44 08 00 mov 8(r4), r14 ;0x0008(r4) - f5ea: 1f 44 0a 00 mov 10(r4), r15 ;0x000a(r4) - f5ee: 3e e3 inv r14 - f5f0: 3f e3 inv r15 - f5f2: 1e 53 inc r14 - f5f4: 0f 63 adc r15 - f5f6: 84 4e 08 00 mov r14, 8(r4) ;0x0008(r4) - f5fa: 84 4f 0a 00 mov r15, 10(r4) ;0x000a(r4) - f5fe: f4 40 2d 00 mov.b #45, 16(r4) ;#0x002d, 0x0010(r4) - f602: 10 00 - f604: f4 40 0a 00 mov.b #10, 6(r4) ;#0x000a, 0x0006(r4) - f608: 06 00 - f60a: a5 3c jmp $+332 ;abs 0xf756 - f60c: 76 90 4f 00 cmp.b #79, r6 ;#0x004f - f610: 03 24 jz $+8 ;abs 0xf618 - f612: 76 90 6f 00 cmp.b #111, r6 ;#0x006f - f616: 07 20 jnz $+16 ;abs 0xf626 - f618: 76 90 4f 00 cmp.b #79, r6 ;#0x004f - f61c: 01 20 jnz $+4 ;abs 0xf620 - f61e: 57 d3 bis.b #1, r7 ;r3 As==01 - f620: f4 42 06 00 mov.b #8, 6(r4) ;r2 As==11, 0x0006(r4) - f624: 96 3c jmp $+302 ;abs 0xf752 - f626: 76 90 70 00 cmp.b #112, r6 ;#0x0070 - f62a: 13 20 jnz $+40 ;abs 0xf652 - f62c: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f630: 0e 4f mov r15, r14 - f632: 2e 53 incd r14 - f634: 84 4e 40 00 mov r14, 64(r4) ;0x0040(r4) - f638: 2f 4f mov @r15, r15 - f63a: 84 4f 08 00 mov r15, 8(r4) ;0x0008(r4) - f63e: 84 43 0a 00 mov #0, 10(r4) ;r3 As==00, 0x000a(r4) - f642: f4 40 10 00 mov.b #16, 6(r4) ;#0x0010, 0x0006(r4) - f646: 06 00 - f648: 77 d0 40 00 bis.b #64, r7 ;#0x0040 - f64c: 76 40 78 00 mov.b #120, r6 ;#0x0078 - f650: 80 3c jmp $+258 ;abs 0xf752 - f652: 76 90 73 00 cmp.b #115, r6 ;#0x0073 - f656: 5b 20 jnz $+184 ;abs 0xf70e - f658: 1f 44 40 00 mov 64(r4), r15 ;0x0040(r4) - f65c: 0d 4f mov r15, r13 - f65e: 2d 53 incd r13 - f660: 84 4d 40 00 mov r13, 64(r4) ;0x0040(r4) - f664: 25 4f mov @r15, r5 - f666: 05 93 tst r5 - f668: 26 20 jnz $+78 ;abs 0xf6b6 - f66a: 05 44 mov r4, r5 - f66c: 35 50 11 00 add #17, r5 ;#0x0011 - f670: f5 40 28 00 mov.b #40, 0(r5) ;#0x0028, 0x0000(r5) - f674: 00 00 - f676: 0f 45 mov r5, r15 - f678: 1f 53 inc r15 - f67a: ff 40 6e 00 mov.b #110, 0(r15) ;#0x006e, 0x0000(r15) - f67e: 00 00 - f680: 0f 45 mov r5, r15 - f682: 2f 53 incd r15 - f684: ff 40 75 00 mov.b #117, 0(r15) ;#0x0075, 0x0000(r15) - f688: 00 00 - f68a: 0e 45 mov r5, r14 - f68c: 2e 52 add #4, r14 ;r2 As==10 - f68e: 0f 45 mov r5, r15 - f690: 3f 50 03 00 add #3, r15 ;#0x0003 - f694: ff 40 6c 00 mov.b #108, 0(r15) ;#0x006c, 0x0000(r15) - f698: 00 00 - f69a: 6f 4f mov.b @r15, r15 - f69c: ce 4f 00 00 mov.b r15, 0(r14) ;0x0000(r14) - f6a0: 0f 45 mov r5, r15 - f6a2: 3f 50 05 00 add #5, r15 ;#0x0005 - f6a6: ff 40 29 00 mov.b #41, 0(r15) ;#0x0029, 0x0000(r15) - f6aa: 00 00 - f6ac: 0f 45 mov r5, r15 - f6ae: 3f 50 06 00 add #6, r15 ;#0x0006 - f6b2: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) - f6b6: c4 93 0c 00 tst.b 12(r4) ;0x000c(r4) - f6ba: 21 38 jl $+68 ;abs 0xf6fe - f6bc: 5f 44 0c 00 mov.b 12(r4), r15 ;0x000c(r4) - f6c0: 8f 11 sxt r15 - f6c2: 0d 4f mov r15, r13 - f6c4: 0e 43 clr r14 - f6c6: 0f 45 mov r5, r15 - f6c8: b0 12 0e fa call #0xfa0e - f6cc: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - f6d0: 84 93 00 00 tst 0(r4) ;0x0000(r4) - f6d4: 10 24 jz $+34 ;abs 0xf6f6 - f6d6: 2f 44 mov @r4, r15 - f6d8: 4e 4f mov.b r15, r14 - f6da: 0f 45 mov r5, r15 - f6dc: 4d 4e mov.b r14, r13 - f6de: 4d 8f sub.b r15, r13 - f6e0: 4f 4d mov.b r13, r15 - f6e2: c4 4f 02 00 mov.b r15, 2(r4) ;0x0002(r4) - f6e6: d4 94 02 00 cmp.b 2(r4), 12(r4) ;0x0002(r4), 0x000c(r4) - f6ea: 0c 00 - f6ec: 0d 34 jge $+28 ;abs 0xf708 - f6ee: d4 44 0c 00 mov.b 12(r4), 2(r4) ;0x000c(r4), 0x0002(r4) - f6f2: 02 00 - f6f4: 09 3c jmp $+20 ;abs 0xf708 - f6f6: d4 44 0c 00 mov.b 12(r4), 2(r4) ;0x000c(r4), 0x0002(r4) - f6fa: 02 00 - f6fc: 05 3c jmp $+12 ;abs 0xf708 - f6fe: 0f 45 mov r5, r15 - f700: b0 12 48 fa call #0xfa48 - f704: c4 4f 02 00 mov.b r15, 2(r4) ;0x0002(r4) - f708: c4 43 10 00 mov.b #0, 16(r4) ;r3 As==00, 0x0010(r4) - f70c: 9f 3c jmp $+320 ;abs 0xf84c - f70e: 76 90 55 00 cmp.b #85, r6 ;#0x0055 - f712: 03 24 jz $+8 ;abs 0xf71a - f714: 76 90 75 00 cmp.b #117, r6 ;#0x0075 - f718: 08 20 jnz $+18 ;abs 0xf72a - f71a: 76 90 55 00 cmp.b #85, r6 ;#0x0055 - f71e: 01 20 jnz $+4 ;abs 0xf722 - f720: 57 d3 bis.b #1, r7 ;r3 As==01 - f722: f4 40 0a 00 mov.b #10, 6(r4) ;#0x000a, 0x0006(r4) - f726: 06 00 - f728: 14 3c jmp $+42 ;abs 0xf752 - f72a: 76 90 58 00 cmp.b #88, r6 ;#0x0058 - f72e: 03 24 jz $+8 ;abs 0xf736 - f730: 76 90 78 00 cmp.b #120, r6 ;#0x0078 - f734: 80 20 jnz $+258 ;abs 0xf836 - f736: f4 40 10 00 mov.b #16, 6(r4) ;#0x0010, 0x0006(r4) - f73a: 06 00 - f73c: 4f 47 mov.b r7, r15 - f73e: 3f f2 and #8, r15 ;r2 As==11 - f740: 08 24 jz $+18 ;abs 0xf752 - f742: 84 93 08 00 tst 8(r4) ;0x0008(r4) - f746: 03 20 jnz $+8 ;abs 0xf74e - f748: 84 93 0a 00 tst 10(r4) ;0x000a(r4) - f74c: 02 24 jz $+6 ;abs 0xf752 - f74e: 77 d0 40 00 bis.b #64, r7 ;#0x0040 - f752: c4 43 10 00 mov.b #0, 16(r4) ;r3 As==00, 0x0010(r4) - f756: d4 44 0c 00 mov.b 12(r4), 5(r4) ;0x000c(r4), 0x0005(r4) - f75a: 05 00 - f75c: c4 93 05 00 tst.b 5(r4) ;0x0005(r4) - f760: 02 38 jl $+6 ;abs 0xf766 - f762: 77 f0 df ff and.b #-33, r7 ;#0xffdf - f766: 05 44 mov r4, r5 - f768: 35 50 11 00 add #17, r5 ;#0x0011 - f76c: 35 50 28 00 add #40, r5 ;#0x0028 - f770: 84 93 08 00 tst 8(r4) ;0x0008(r4) - f774: 06 20 jnz $+14 ;abs 0xf782 - f776: 84 93 0a 00 tst 10(r4) ;0x000a(r4) - f77a: 03 20 jnz $+8 ;abs 0xf782 - f77c: c4 93 0c 00 tst.b 12(r4) ;0x000c(r4) - f780: 4d 24 jz $+156 ;abs 0xf81c - f782: 5c 44 06 00 mov.b 6(r4), r12 ;0x0006(r4) - f786: 0d 43 clr r13 - f788: c4 43 42 00 mov.b #0, 66(r4) ;r3 As==00, 0x0042(r4) - f78c: 1e 44 08 00 mov 8(r4), r14 ;0x0008(r4) - f790: 1f 44 0a 00 mov 10(r4), r15 ;0x000a(r4) - f794: 0e 8c sub r12, r14 - f796: 0f 7d subc r13, r15 - f798: 02 28 jnc $+6 ;abs 0xf79e - f79a: d4 43 42 00 mov.b #1, 66(r4) ;r3 As==01, 0x0042(r4) - f79e: 5e 44 06 00 mov.b 6(r4), r14 ;0x0006(r4) - f7a2: 0f 43 clr r15 - f7a4: 1c 44 08 00 mov 8(r4), r12 ;0x0008(r4) - f7a8: 1d 44 0a 00 mov 10(r4), r13 ;0x000a(r4) - f7ac: 0a 4e mov r14, r10 - f7ae: 0b 4f mov r15, r11 - f7b0: b0 12 72 fa call #0xfa72 - f7b4: 4b 4e mov.b r14, r11 - f7b6: 7b 90 0a 00 cmp.b #10, r11 ;#0x000a - f7ba: 03 2c jc $+8 ;abs 0xf7c2 - f7bc: 7b 50 30 00 add.b #48, r11 ;#0x0030 - f7c0: 07 3c jmp $+16 ;abs 0xf7d0 - f7c2: 7b 50 57 00 add.b #87, r11 ;#0x0057 - f7c6: 76 90 58 00 cmp.b #88, r6 ;#0x0058 - f7ca: 02 20 jnz $+6 ;abs 0xf7d0 - f7cc: 7b f0 df ff and.b #-33, r11 ;#0xffdf - f7d0: 35 53 add #-1, r5 ;r3 As==11 - f7d2: 4f 4b mov.b r11, r15 - f7d4: c5 4f 00 00 mov.b r15, 0(r5) ;0x0000(r5) - f7d8: 5e 44 06 00 mov.b 6(r4), r14 ;0x0006(r4) - f7dc: 0f 43 clr r15 - f7de: 1c 44 08 00 mov 8(r4), r12 ;0x0008(r4) - f7e2: 1d 44 0a 00 mov 10(r4), r13 ;0x000a(r4) - f7e6: 0a 4e mov r14, r10 - f7e8: 0b 4f mov r15, r11 - f7ea: b0 12 72 fa call #0xfa72 - f7ee: 0e 4c mov r12, r14 - f7f0: 0f 4d mov r13, r15 - f7f2: 84 4e 08 00 mov r14, 8(r4) ;0x0008(r4) - f7f6: 84 4f 0a 00 mov r15, 10(r4) ;0x000a(r4) - f7fa: c4 93 42 00 tst.b 66(r4) ;0x0042(r4) - f7fe: c1 23 jnz $-124 ;abs 0xf782 - f800: f4 92 06 00 cmp.b #8, 6(r4) ;r2 As==11, 0x0006(r4) - f804: 0b 20 jnz $+24 ;abs 0xf81c - f806: 4f 47 mov.b r7, r15 - f808: 3f f2 and #8, r15 ;r2 As==11 - f80a: 08 24 jz $+18 ;abs 0xf81c - f80c: 6f 45 mov.b @r5, r15 - f80e: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 - f812: 04 24 jz $+10 ;abs 0xf81c - f814: 35 53 add #-1, r5 ;r3 As==11 - f816: f5 40 30 00 mov.b #48, 0(r5) ;#0x0030, 0x0000(r5) - f81a: 00 00 - f81c: 0f 44 mov r4, r15 - f81e: 3f 50 11 00 add #17, r15 ;#0x0011 - f822: 3f 50 28 00 add #40, r15 ;#0x0028 - f826: 4e 4f mov.b r15, r14 - f828: 0f 45 mov r5, r15 - f82a: 4d 4e mov.b r14, r13 - f82c: 4d 8f sub.b r15, r13 - f82e: 4f 4d mov.b r13, r15 - f830: c4 4f 02 00 mov.b r15, 2(r4) ;0x0002(r4) - f834: 0b 3c jmp $+24 ;abs 0xf84c - f836: 46 93 tst.b r6 - f838: ac 24 jz $+346 ;abs 0xf992 - f83a: 05 44 mov r4, r5 - f83c: 35 50 11 00 add #17, r5 ;#0x0011 - f840: c5 46 00 00 mov.b r6, 0(r5) ;0x0000(r5) - f844: d4 43 02 00 mov.b #1, 2(r4) ;r3 As==01, 0x0002(r4) - f848: c4 43 10 00 mov.b #0, 16(r4) ;r3 As==00, 0x0010(r4) - f84c: d4 44 02 00 mov.b 2(r4), 3(r4) ;0x0002(r4), 0x0003(r4) - f850: 03 00 - f852: 5e 44 05 00 mov.b 5(r4), r14 ;0x0005(r4) - f856: 5f 44 02 00 mov.b 2(r4), r15 ;0x0002(r4) - f85a: 4d 4e mov.b r14, r13 - f85c: 4d 8f sub.b r15, r13 - f85e: 4f 4d mov.b r13, r15 - f860: c4 4f 04 00 mov.b r15, 4(r4) ;0x0004(r4) - f864: c4 93 04 00 tst.b 4(r4) ;0x0004(r4) - f868: 02 34 jge $+6 ;abs 0xf86e - f86a: c4 43 04 00 mov.b #0, 4(r4) ;r3 As==00, 0x0004(r4) - f86e: 5f 44 10 00 mov.b 16(r4), r15 ;0x0010(r4) - f872: 4f 93 tst.b r15 - f874: 03 24 jz $+8 ;abs 0xf87c - f876: d4 53 03 00 inc.b 3(r4) ;0x0003(r4) - f87a: 09 3c jmp $+20 ;abs 0xf88e - f87c: 4f 47 mov.b r7, r15 - f87e: 3f f0 40 00 and #64, r15 ;#0x0040 - f882: 05 24 jz $+12 ;abs 0xf88e - f884: 5f 44 03 00 mov.b 3(r4), r15 ;0x0003(r4) - f888: 6f 53 incd.b r15 - f88a: c4 4f 03 00 mov.b r15, 3(r4) ;0x0003(r4) - f88e: 5e 44 03 00 mov.b 3(r4), r14 ;0x0003(r4) - f892: 5f 44 04 00 mov.b 4(r4), r15 ;0x0004(r4) - f896: 4f 5e add.b r14, r15 - f898: c4 4f 03 00 mov.b r15, 3(r4) ;0x0003(r4) - f89c: 4f 47 mov.b r7, r15 - f89e: 3f f0 30 00 and #48, r15 ;#0x0030 - f8a2: 11 20 jnz $+36 ;abs 0xf8c6 - f8a4: 5e 44 0d 00 mov.b 13(r4), r14 ;0x000d(r4) - f8a8: 8e 11 sxt r14 - f8aa: 5f 44 03 00 mov.b 3(r4), r15 ;0x0003(r4) - f8ae: 8f 11 sxt r15 - f8b0: 0b 4e mov r14, r11 - f8b2: 0b 8f sub r15, r11 - f8b4: 1b 93 cmp #1, r11 ;r3 As==01 - f8b6: 07 38 jl $+16 ;abs 0xf8c6 - f8b8: 4e 4b mov.b r11, r14 - f8ba: 7f 40 20 00 mov.b #32, r15 ;#0x0020 - f8be: b0 12 ba f2 call #0xf2ba - f8c2: 0f 93 tst r15 - f8c4: 68 38 jl $+210 ;abs 0xf996 - f8c6: 5f 44 10 00 mov.b 16(r4), r15 ;0x0010(r4) - f8ca: 4f 93 tst.b r15 - f8cc: 09 24 jz $+20 ;abs 0xf8e0 - f8ce: 1e 43 mov #1, r14 ;r3 As==01 - f8d0: 0f 44 mov r4, r15 - f8d2: 3f 50 10 00 add #16, r15 ;#0x0010 - f8d6: b0 12 76 f2 call #0xf276 - f8da: 0f 93 tst r15 - f8dc: 12 34 jge $+38 ;abs 0xf902 - f8de: 64 3c jmp $+202 ;abs 0xf9a8 - f8e0: 4f 47 mov.b r7, r15 - f8e2: 3f f0 40 00 and #64, r15 ;#0x0040 - f8e6: 0d 24 jz $+28 ;abs 0xf902 - f8e8: f4 40 30 00 mov.b #48, 57(r4) ;#0x0030, 0x0039(r4) - f8ec: 39 00 - f8ee: c4 46 3a 00 mov.b r6, 58(r4) ;0x003a(r4) - f8f2: 0f 44 mov r4, r15 - f8f4: 3f 50 39 00 add #57, r15 ;#0x0039 - f8f8: 2e 43 mov #2, r14 ;r3 As==10 - f8fa: b0 12 76 f2 call #0xf276 - f8fe: 0f 93 tst r15 - f900: 4c 38 jl $+154 ;abs 0xf99a - f902: 4f 47 mov.b r7, r15 - f904: 3f f0 30 00 and #48, r15 ;#0x0030 - f908: 3f 90 20 00 cmp #32, r15 ;#0x0020 - f90c: 11 20 jnz $+36 ;abs 0xf930 - f90e: 5e 44 0d 00 mov.b 13(r4), r14 ;0x000d(r4) - f912: 8e 11 sxt r14 - f914: 5f 44 03 00 mov.b 3(r4), r15 ;0x0003(r4) - f918: 8f 11 sxt r15 - f91a: 0b 4e mov r14, r11 - f91c: 0b 8f sub r15, r11 - f91e: 1b 93 cmp #1, r11 ;r3 As==01 - f920: 07 38 jl $+16 ;abs 0xf930 - f922: 4e 4b mov.b r11, r14 - f924: 7f 40 30 00 mov.b #48, r15 ;#0x0030 - f928: b0 12 ba f2 call #0xf2ba - f92c: 0f 93 tst r15 - f92e: 37 38 jl $+112 ;abs 0xf99e - f930: 5e 44 04 00 mov.b 4(r4), r14 ;0x0004(r4) - f934: 7f 40 30 00 mov.b #48, r15 ;#0x0030 - f938: b0 12 ba f2 call #0xf2ba - f93c: 0f 93 tst r15 - f93e: 31 38 jl $+100 ;abs 0xf9a2 - f940: 5f 44 02 00 mov.b 2(r4), r15 ;0x0002(r4) - f944: 8f 11 sxt r15 - f946: 0e 4f mov r15, r14 - f948: 0f 45 mov r5, r15 - f94a: b0 12 76 f2 call #0xf276 - f94e: 0f 93 tst r15 - f950: 2a 38 jl $+86 ;abs 0xf9a6 - f952: 4f 47 mov.b r7, r15 - f954: 3f f0 10 00 and #16, r15 ;#0x0010 - f958: 02 20 jnz $+6 ;abs 0xf95e - f95a: 30 40 3a f3 br #0xf33a - f95e: 5e 44 0d 00 mov.b 13(r4), r14 ;0x000d(r4) - f962: 8e 11 sxt r14 - f964: 5f 44 03 00 mov.b 3(r4), r15 ;0x0003(r4) - f968: 8f 11 sxt r15 - f96a: 0b 4e mov r14, r11 - f96c: 0b 8f sub r15, r11 - f96e: 1b 93 cmp #1, r11 ;r3 As==01 - f970: 02 34 jge $+6 ;abs 0xf976 - f972: 30 40 3e f3 br #0xf33e - f976: 4e 4b mov.b r11, r14 - f978: 7f 40 20 00 mov.b #32, r15 ;#0x0020 - f97c: b0 12 ba f2 call #0xf2ba - f980: 0f 93 tst r15 - f982: 02 38 jl $+6 ;abs 0xf988 - f984: 30 40 42 f3 br #0xf342 - f988: 0f 3c jmp $+32 ;abs 0xf9a8 - f98a: 03 43 nop - f98c: 0d 3c jmp $+28 ;abs 0xf9a8 - f98e: 03 43 nop - f990: 0b 3c jmp $+24 ;abs 0xf9a8 - f992: 03 43 nop - f994: 09 3c jmp $+20 ;abs 0xf9a8 - f996: 03 43 nop - f998: 07 3c jmp $+16 ;abs 0xf9a8 - f99a: 03 43 nop - f99c: 05 3c jmp $+12 ;abs 0xf9a8 - f99e: 03 43 nop - f9a0: 03 3c jmp $+8 ;abs 0xf9a8 - f9a2: 03 43 nop - f9a4: 01 3c jmp $+4 ;abs 0xf9a8 - f9a6: 03 43 nop - f9a8: 1f 42 02 02 mov &0x0202,r15 - f9ac: 31 50 46 00 add #70, r1 ;#0x0046 - f9b0: 34 41 pop r4 - f9b2: 35 41 pop r5 - f9b4: 36 41 pop r6 - f9b6: 37 41 pop r7 - f9b8: 38 41 pop r8 - f9ba: 39 41 pop r9 - f9bc: 3a 41 pop r10 - f9be: 3b 41 pop r11 - f9c0: 30 41 ret - -0000f9c2 : - f9c2: 04 12 push r4 - f9c4: 21 82 sub #4, r1 ;r2 As==10 - f9c6: 04 41 mov r1, r4 - f9c8: 84 4f 02 00 mov r15, 2(r4) ;0x0002(r4) - f9cc: 84 43 00 00 mov #0, 0(r4) ;r3 As==00, 0x0000(r4) - f9d0: 1f 44 02 00 mov 2(r4), r15 ;0x0002(r4) - f9d4: 6f 4f mov.b @r15, r15 - f9d6: 4f 93 tst.b r15 - f9d8: 0d 24 jz $+28 ;abs 0xf9f4 - f9da: 1f 44 02 00 mov 2(r4), r15 ;0x0002(r4) - f9de: 6f 4f mov.b @r15, r15 - f9e0: 8f 11 sxt r15 - f9e2: 94 53 02 00 inc 2(r4) ;0x0002(r4) - f9e6: b0 12 0e f2 call #0xf20e - f9ea: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - f9ee: 84 93 00 00 tst 0(r4) ;0x0000(r4) - f9f2: ee 37 jge $-34 ;abs 0xf9d0 - f9f4: 84 93 00 00 tst 0(r4) ;0x0000(r4) - f9f8: 05 38 jl $+12 ;abs 0xfa04 - f9fa: 3f 40 0a 00 mov #10, r15 ;#0x000a - f9fe: b0 12 0e f2 call #0xf20e - fa02: 01 3c jmp $+4 ;abs 0xfa06 - fa04: 2f 44 mov @r4, r15 - fa06: 21 52 add #4, r1 ;r2 As==10 - fa08: 34 41 pop r4 - fa0a: 30 41 ret - -0000fa0c <_unexpected_>: - fa0c: 00 13 reti - -0000fa0e : - fa0e: 0b 12 push r11 - fa10: 04 12 push r4 - fa12: 21 83 decd r1 - fa14: 04 41 mov r1, r4 - fa16: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - fa1a: 0f 4d mov r13, r15 - fa1c: 4d 4e mov.b r14, r13 - fa1e: 0f 93 tst r15 - fa20: 0e 24 jz $+30 ;abs 0xfa3e - fa22: 2b 44 mov @r4, r11 - fa24: 6c 4b mov.b @r11, r12 - fa26: 4e 43 clr.b r14 - fa28: 4c 9d cmp.b r13, r12 - fa2a: 01 20 jnz $+4 ;abs 0xfa2e - fa2c: 5e 43 mov.b #1, r14 ;r3 As==01 - fa2e: 1b 53 inc r11 - fa30: 4e 93 tst.b r14 - fa32: 03 24 jz $+8 ;abs 0xfa3a - fa34: 0f 4b mov r11, r15 - fa36: 3f 53 add #-1, r15 ;r3 As==11 - fa38: 03 3c jmp $+8 ;abs 0xfa40 - fa3a: 3f 53 add #-1, r15 ;r3 As==11 - fa3c: f3 23 jnz $-24 ;abs 0xfa24 - fa3e: 0f 43 clr r15 - fa40: 21 53 incd r1 - fa42: 34 41 pop r4 - fa44: 3b 41 pop r11 - fa46: 30 41 ret - -0000fa48 : - fa48: 0b 12 push r11 - fa4a: 04 12 push r4 - fa4c: 21 83 decd r1 - fa4e: 04 41 mov r1, r4 - fa50: 84 4f 00 00 mov r15, 0(r4) ;0x0000(r4) - fa54: 2b 44 mov @r4, r11 - fa56: 01 3c jmp $+4 ;abs 0xfa5a - fa58: 1b 53 inc r11 - fa5a: 6f 4b mov.b @r11, r15 - fa5c: 4f 93 tst.b r15 - fa5e: fc 23 jnz $-6 ;abs 0xfa58 - fa60: 0e 4b mov r11, r14 - fa62: 2f 44 mov @r4, r15 - fa64: 0d 4e mov r14, r13 - fa66: 0d 8f sub r15, r13 - fa68: 0f 4d mov r13, r15 - fa6a: 21 53 incd r1 - fa6c: 34 41 pop r4 - fa6e: 3b 41 pop r11 - fa70: 30 41 ret - -0000fa72 <__udivmodsi4>: -#define r_tmp r8 - - .global __udivmodsi4 - .func __udivmodsi4 -__udivmodsi4: - xor r_remh, r_remh ; clear reminder and carry - fa72: 0f ef xor r15, r15 - xor r_reml, r_reml - fa74: 0e ee xor r14, r14 - mov #33, r_cnt - fa76: 39 40 21 00 mov #33, r9 ;#0x0021 - fa7a: 0a 3c jmp $+22 ;abs 0xfa90 - jmp .L__udivmodsi4_ep -.L__udivmodsi4_loop: - rrc r_tmp ; restore carry bit - fa7c: 08 10 rrc r8 - rlc r_reml - fa7e: 0e 6e rlc r14 - rlc r_remh - fa80: 0f 6f rlc r15 - - cmp r_arg2h, r_remh ; is reminder < divisor ? - fa82: 0f 9b cmp r11, r15 - fa84: 05 28 jnc $+12 ;abs 0xfa90 - jlo .L__udivmodsi4_ep ; yes, skip correction - fa86: 02 20 jnz $+6 ;abs 0xfa8c - jne +4 - ; they equal. check LSBytes - cmp r_arg2l, r_reml - fa88: 0e 9a cmp r10, r14 - fa8a: 02 28 jnc $+6 ;abs 0xfa90 - jlo .L__udivmodsi4_ep ; is reminder still < divisor ? - - sub r_arg2l, r_reml ; adjust reminder - fa8c: 0e 8a sub r10, r14 - subc r_arg2h, r_remh - fa8e: 0f 7b subc r11, r15 - -.L__udivmodsi4_ep: - rlc r_arg1l - fa90: 0c 6c rlc r12 - rlc r_arg1h - fa92: 0d 6d rlc r13 - rlc r_tmp - fa94: 08 68 rlc r8 - dec r_cnt ; this clobbers C bit. - fa96: 19 83 dec r9 - fa98: f1 23 jnz $-28 ;abs 0xfa7c - jnz .L__udivmodsi4_loop - ret - fa9a: 30 41 ret - -Disassembly of section .vectors: - -0000ffe0 : - ffe0: 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 0.0.0.0.0.0.0.0. - fff0: 30 f0 b0 f1 30 f0 30 f0 30 f0 30 f0 30 f0 00 f0 0...0.0.0.0.0...

trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c (nonexistent) @@ -1,16 +0,0 @@ -#include "hardware.h" - -int main(void) { - - WDTCTL = WDTPW | WDTHOLD; // Disable watchdog timer - - P3DIR = 0x0f; - P4DIR = 0x00; - - while(1){ - P3OUT = P4IN; - } - - return 0; -} -

trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile (nonexistent) @@ -1,52 +0,0 @@ -# makfile configuration -NAME = leds -OBJECTS = main.o -CPU = msp430x1121 - -CFLAGS = -mmcu=${CPU} -mforce-hwmul -O0 -Wall -g - -#switch the compiler (for the internal make rules) -CC = msp430-gcc - - -.PHONY: all FORCE clean download download-jtag download-bsl dist - -#all should be the first target. it's built when make is runwithout args -all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst - -#confgigure the next line if you want to use the serial download -download: download-uart -#download: download-jtag -#download: download-bsl - -#additional rules for files -${NAME}.elf: ${OBJECTS} - ${CC} -mmcu=${CPU} -o $@ ${OBJECTS} - -${NAME}.a43: ${NAME}.elf - msp430-objcopy -O ihex $^ $@ - -${NAME}.lst: ${NAME}.elf - msp430-objdump -dSt $^ >$@ - -download-jtag: all - msp430-jtag -e ${NAME}.elf - -download-bsl: all - msp430-bsl -e ${NAME}.elf - -download-uart: all - openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf - -clean: - rm -f ${NAME} ${NAME}.a43 ${NAME}.lst *.o - -#backup archive -dist: - tar czf dist.tgz *.c *.h *.txt makefile - -#dummy target as dependecy if something has to be build everytime -FORCE: - -#project dependencies -main.o: main.c hardware.h

trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h =================================================================== --- trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h (revision 155) +++ trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h (nonexistent) @@ -1,35 +0,0 @@ -#ifndef MAIN_H -#define MAIN_H - -#define __msp430_have_port3 -#define __MSP430_HAS_PORT3__ -#define __msp430_have_port4 -#define __MSP430_HAS_PORT4__ - -#include -#include -#include - -#ifndef P3DIR -#define P3IN_ 0x0018 /* Port 3 Input */ -const_sfrb(P3IN, P3IN_); -#define P3OUT_ 0x0019 /* Port 3 Output */ -sfrb(P3OUT, P3OUT_); -#define P3DIR_ 0x001A /* Port 3 Direction */ -sfrb(P3DIR, P3DIR_); -#define P3SEL_ 0x001B /* Port 3 Selection */ -sfrb(P3SEL, P3SEL_); -#endif - -#ifndef P4DIR -#define P4IN_ 0x001C /* Port 4 Input */ -const_sfrb(P4IN, P4IN_); -#define P4OUT_ 0x001D /* Port 4 Output */ -sfrb(P4OUT, P4OUT_); -#define P4DIR_ 0x001E /* Port 4 Direction */ -sfrb(P4DIR, P4DIR_); -#define P4SEL_ 0x001F /* Port 4 Selection */ -sfrb(P4SEL, P4SEL_); -#endif - -#endif // MAIN_H

trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property

powered by: WebSVN 2.1.0

Browse

Tools

Subversion Repositories openmsp430

Compare Revisions

Rev 155 → Rev 156