URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430
- from Rev 161 to Rev 162
- ↔ Reverse comparison
Rev 161 → Rev 162
/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/tb_openMSP430_fpga.v
72,7 → 72,6
// UART |
wire PMOD1_P1; |
reg PMOD1_P4; |
reg PMOD1_P8; |
|
// Core debug signals |
wire [8*32-1:0] i_state; |
156,7 → 155,6
SW1 = 1'b0; |
UART_RXD = 1'b1; // UART |
PMOD1_P4 = 1'b1; |
PMOD1_P8 = 1'b0; |
end |
|
// |
318,7 → 316,7
.PMOD1_P3 (), |
.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX |
.PMOD1_P7 (), |
.PMOD1_P8 (PMOD1_P8), // Serial Debug Interface enable |
.PMOD1_P8 (), |
.PMOD1_P9 (), |
.PMOD1_P10 (), |
|
trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/run
Property changes :
Added: svn:ignore
## -0,0 +1,4 ##
+pmem.*
+*.vcd
+simv
+stimulus.v
Index: trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.f
===================================================================
--- trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.f (revision 161)
+++ trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.f (revision 162)
@@ -84,6 +84,7 @@
../../../rtl/verilog/openmsp430/omsp_dbg.v
../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
+../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v
../../../rtl/verilog/openmsp430/omsp_watchdog.v
../../../rtl/verilog/openmsp430/omsp_multiplier.v
../../../rtl/verilog/openmsp430/omsp_sync_reset.v
Index: trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/leds.v
===================================================================
--- trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/leds.v (revision 161)
+++ trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/leds.v (revision 162)
@@ -13,11 +13,11 @@
stimulus_done = 0;
repeat(100) @(posedge CLK_40MHz);
- PMOD1_P8 = 1;
+ // PMOD1_P8 = 1;
repeat(500) @(posedge CLK_40MHz);
- PMOD1_P8 = 0;
+ // PMOD1_P8 = 0;
repeat(100) @(posedge CLK_40MHz);
- PMOD1_P8 = 1;
+ // PMOD1_P8 = 1;
repeat(500) @(posedge CLK_40MHz);
/trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.prj
29,6 → 29,7
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v |
verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v |
trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx
Property changes :
Added: svn:ignore
## -0,0 +1 ##
+WORK