URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430
- from Rev 183 to Rev 184
- ↔ Reverse comparison
Rev 183 → Rev 184
/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v
37,7 → 37,7
// FPGA Specific modules |
//============================================================================= |
|
`include "../../../rtl/verilog/openMSP430_fpga.v" |
`include "../../../rtl/verilog/OpenMSP430_fpga.v" |
`include "../../../rtl/verilog/io_mux.v" |
`include "../../../rtl/verilog/driver_7segment.v" |
`include "../../../rtl/verilog/ram16x512.v" // altera DE1 specific modules |
/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf
28,7 → 28,7
set_global_assignment -name TOP_LEVEL_ENTITY main |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:43:20 OCTOBER 13, 2009" |
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" |
set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1" |
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA |
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 |
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 |
492,7 → 492,6
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_OE_N |
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_UB_N |
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_LB_N |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" |
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" |
503,4 → 502,14
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" |
set_global_assignment -name VERILOG_FILE openMSP430_fpga_top.v |
set_global_assignment -name CDF_FILE Chain1.cdf |
set_global_assignment -name SEARCH_PATH "..\\..\\rtl\\verilog\\openmsp430/ ..\\..\\rtl\\verilog\\openmsp430\\periph/" |
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\openmsp430/ |
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\openmsp430\\periph/ |
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 |
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" |
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |