OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430
    from Rev 26 to Rev 27
    ↔ Reverse comparison
  •

Rev 26 → Rev 27

/trunk/fpga/diligent_s3board/bench/verilog/msp_debug.v File deleted
trunk/fpga/diligent_s3board/bench/verilog/msp_debug.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/bench/verilog/registers.v =================================================================== --- trunk/fpga/diligent_s3board/bench/verilog/registers.v (revision 26) +++ trunk/fpga/diligent_s3board/bench/verilog/registers.v (nonexistent) @@ -1,157 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: registers.v -// -// *Module Description: -// openMSP430 testbench -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- - -// CPU registers -//====================== - -wire [15:0] r0 = dut.openMSP430_0.execution_unit_0.register_file_0.r0; -wire [15:0] r1 = dut.openMSP430_0.execution_unit_0.register_file_0.r1; -wire [15:0] r2 = dut.openMSP430_0.execution_unit_0.register_file_0.r2; -wire [15:0] r3 = dut.openMSP430_0.execution_unit_0.register_file_0.r3; -wire [15:0] r4 = dut.openMSP430_0.execution_unit_0.register_file_0.r4; -wire [15:0] r5 = dut.openMSP430_0.execution_unit_0.register_file_0.r5; -wire [15:0] r6 = dut.openMSP430_0.execution_unit_0.register_file_0.r6; -wire [15:0] r7 = dut.openMSP430_0.execution_unit_0.register_file_0.r7; -wire [15:0] r8 = dut.openMSP430_0.execution_unit_0.register_file_0.r8; -wire [15:0] r9 = dut.openMSP430_0.execution_unit_0.register_file_0.r9; -wire [15:0] r10 = dut.openMSP430_0.execution_unit_0.register_file_0.r10; -wire [15:0] r11 = dut.openMSP430_0.execution_unit_0.register_file_0.r11; -wire [15:0] r12 = dut.openMSP430_0.execution_unit_0.register_file_0.r12; -wire [15:0] r13 = dut.openMSP430_0.execution_unit_0.register_file_0.r13; -wire [15:0] r14 = dut.openMSP430_0.execution_unit_0.register_file_0.r14; -wire [15:0] r15 = dut.openMSP430_0.execution_unit_0.register_file_0.r15; - - -// RAM cells -//====================== - -wire [15:0] mem200 = {dut.ram_8x512_hi_0.inst.mem[0], dut.ram_8x512_lo_0.inst.mem[0]}; -wire [15:0] mem202 = {dut.ram_8x512_hi_0.inst.mem[1], dut.ram_8x512_lo_0.inst.mem[1]}; -wire [15:0] mem204 = {dut.ram_8x512_hi_0.inst.mem[2], dut.ram_8x512_lo_0.inst.mem[2]}; -wire [15:0] mem206 = {dut.ram_8x512_hi_0.inst.mem[3], dut.ram_8x512_lo_0.inst.mem[3]}; -wire [15:0] mem208 = {dut.ram_8x512_hi_0.inst.mem[4], dut.ram_8x512_lo_0.inst.mem[4]}; -wire [15:0] mem20A = {dut.ram_8x512_hi_0.inst.mem[5], dut.ram_8x512_lo_0.inst.mem[5]}; -wire [15:0] mem20C = {dut.ram_8x512_hi_0.inst.mem[6], dut.ram_8x512_lo_0.inst.mem[6]}; -wire [15:0] mem20E = {dut.ram_8x512_hi_0.inst.mem[7], dut.ram_8x512_lo_0.inst.mem[7]}; -wire [15:0] mem210 = {dut.ram_8x512_hi_0.inst.mem[8], dut.ram_8x512_lo_0.inst.mem[8]}; -wire [15:0] mem212 = {dut.ram_8x512_hi_0.inst.mem[9], dut.ram_8x512_lo_0.inst.mem[9]}; -wire [15:0] mem214 = {dut.ram_8x512_hi_0.inst.mem[10], dut.ram_8x512_lo_0.inst.mem[10]}; -wire [15:0] mem216 = {dut.ram_8x512_hi_0.inst.mem[11], dut.ram_8x512_lo_0.inst.mem[11]}; -wire [15:0] mem218 = {dut.ram_8x512_hi_0.inst.mem[12], dut.ram_8x512_lo_0.inst.mem[12]}; -wire [15:0] mem21A = {dut.ram_8x512_hi_0.inst.mem[13], dut.ram_8x512_lo_0.inst.mem[13]}; -wire [15:0] mem21C = {dut.ram_8x512_hi_0.inst.mem[14], dut.ram_8x512_lo_0.inst.mem[14]}; -wire [15:0] mem21E = {dut.ram_8x512_hi_0.inst.mem[15], dut.ram_8x512_lo_0.inst.mem[15]}; -wire [15:0] mem220 = {dut.ram_8x512_hi_0.inst.mem[16], dut.ram_8x512_lo_0.inst.mem[16]}; -wire [15:0] mem222 = {dut.ram_8x512_hi_0.inst.mem[17], dut.ram_8x512_lo_0.inst.mem[17]}; -wire [15:0] mem224 = {dut.ram_8x512_hi_0.inst.mem[18], dut.ram_8x512_lo_0.inst.mem[18]}; -wire [15:0] mem226 = {dut.ram_8x512_hi_0.inst.mem[19], dut.ram_8x512_lo_0.inst.mem[19]}; -wire [15:0] mem228 = {dut.ram_8x512_hi_0.inst.mem[20], dut.ram_8x512_lo_0.inst.mem[20]}; -wire [15:0] mem22A = {dut.ram_8x512_hi_0.inst.mem[21], dut.ram_8x512_lo_0.inst.mem[21]}; -wire [15:0] mem22C = {dut.ram_8x512_hi_0.inst.mem[22], dut.ram_8x512_lo_0.inst.mem[22]}; -wire [15:0] mem22E = {dut.ram_8x512_hi_0.inst.mem[23], dut.ram_8x512_lo_0.inst.mem[23]}; -wire [15:0] mem230 = {dut.ram_8x512_hi_0.inst.mem[24], dut.ram_8x512_lo_0.inst.mem[24]}; -wire [15:0] mem232 = {dut.ram_8x512_hi_0.inst.mem[25], dut.ram_8x512_lo_0.inst.mem[25]}; -wire [15:0] mem234 = {dut.ram_8x512_hi_0.inst.mem[26], dut.ram_8x512_lo_0.inst.mem[26]}; -wire [15:0] mem236 = {dut.ram_8x512_hi_0.inst.mem[27], dut.ram_8x512_lo_0.inst.mem[27]}; -wire [15:0] mem238 = {dut.ram_8x512_hi_0.inst.mem[28], dut.ram_8x512_lo_0.inst.mem[28]}; -wire [15:0] mem23A = {dut.ram_8x512_hi_0.inst.mem[29], dut.ram_8x512_lo_0.inst.mem[29]}; -wire [15:0] mem23C = {dut.ram_8x512_hi_0.inst.mem[30], dut.ram_8x512_lo_0.inst.mem[30]}; -wire [15:0] mem23E = {dut.ram_8x512_hi_0.inst.mem[31], dut.ram_8x512_lo_0.inst.mem[31]}; -wire [15:0] mem240 = {dut.ram_8x512_hi_0.inst.mem[32], dut.ram_8x512_lo_0.inst.mem[32]}; -wire [15:0] mem242 = {dut.ram_8x512_hi_0.inst.mem[33], dut.ram_8x512_lo_0.inst.mem[33]}; -wire [15:0] mem244 = {dut.ram_8x512_hi_0.inst.mem[34], dut.ram_8x512_lo_0.inst.mem[34]}; -wire [15:0] mem246 = {dut.ram_8x512_hi_0.inst.mem[35], dut.ram_8x512_lo_0.inst.mem[35]}; -wire [15:0] mem248 = {dut.ram_8x512_hi_0.inst.mem[36], dut.ram_8x512_lo_0.inst.mem[36]}; -wire [15:0] mem24A = {dut.ram_8x512_hi_0.inst.mem[37], dut.ram_8x512_lo_0.inst.mem[37]}; -wire [15:0] mem24C = {dut.ram_8x512_hi_0.inst.mem[38], dut.ram_8x512_lo_0.inst.mem[38]}; -wire [15:0] mem24E = {dut.ram_8x512_hi_0.inst.mem[39], dut.ram_8x512_lo_0.inst.mem[39]}; -wire [15:0] mem250 = {dut.ram_8x512_hi_0.inst.mem[40], dut.ram_8x512_lo_0.inst.mem[40]}; -wire [15:0] mem252 = {dut.ram_8x512_hi_0.inst.mem[41], dut.ram_8x512_lo_0.inst.mem[41]}; -wire [15:0] mem254 = {dut.ram_8x512_hi_0.inst.mem[42], dut.ram_8x512_lo_0.inst.mem[42]}; -wire [15:0] mem256 = {dut.ram_8x512_hi_0.inst.mem[43], dut.ram_8x512_lo_0.inst.mem[43]}; -wire [15:0] mem258 = {dut.ram_8x512_hi_0.inst.mem[44], dut.ram_8x512_lo_0.inst.mem[44]}; -wire [15:0] mem25A = {dut.ram_8x512_hi_0.inst.mem[45], dut.ram_8x512_lo_0.inst.mem[45]}; -wire [15:0] mem25C = {dut.ram_8x512_hi_0.inst.mem[46], dut.ram_8x512_lo_0.inst.mem[46]}; -wire [15:0] mem25E = {dut.ram_8x512_hi_0.inst.mem[47], dut.ram_8x512_lo_0.inst.mem[47]}; -wire [15:0] mem260 = {dut.ram_8x512_hi_0.inst.mem[48], dut.ram_8x512_lo_0.inst.mem[48]}; -wire [15:0] mem262 = {dut.ram_8x512_hi_0.inst.mem[49], dut.ram_8x512_lo_0.inst.mem[49]}; -wire [15:0] mem264 = {dut.ram_8x512_hi_0.inst.mem[50], dut.ram_8x512_lo_0.inst.mem[50]}; -wire [15:0] mem266 = {dut.ram_8x512_hi_0.inst.mem[51], dut.ram_8x512_lo_0.inst.mem[51]}; -wire [15:0] mem268 = {dut.ram_8x512_hi_0.inst.mem[52], dut.ram_8x512_lo_0.inst.mem[52]}; -wire [15:0] mem26A = {dut.ram_8x512_hi_0.inst.mem[53], dut.ram_8x512_lo_0.inst.mem[53]}; -wire [15:0] mem26C = {dut.ram_8x512_hi_0.inst.mem[54], dut.ram_8x512_lo_0.inst.mem[54]}; -wire [15:0] mem26E = {dut.ram_8x512_hi_0.inst.mem[55], dut.ram_8x512_lo_0.inst.mem[55]}; -wire [15:0] mem270 = {dut.ram_8x512_hi_0.inst.mem[56], dut.ram_8x512_lo_0.inst.mem[56]}; -wire [15:0] mem272 = {dut.ram_8x512_hi_0.inst.mem[57], dut.ram_8x512_lo_0.inst.mem[57]}; -wire [15:0] mem274 = {dut.ram_8x512_hi_0.inst.mem[58], dut.ram_8x512_lo_0.inst.mem[58]}; -wire [15:0] mem276 = {dut.ram_8x512_hi_0.inst.mem[59], dut.ram_8x512_lo_0.inst.mem[59]}; -wire [15:0] mem278 = {dut.ram_8x512_hi_0.inst.mem[60], dut.ram_8x512_lo_0.inst.mem[60]}; -wire [15:0] mem27A = {dut.ram_8x512_hi_0.inst.mem[61], dut.ram_8x512_lo_0.inst.mem[61]}; -wire [15:0] mem27C = {dut.ram_8x512_hi_0.inst.mem[62], dut.ram_8x512_lo_0.inst.mem[62]}; -wire [15:0] mem27E = {dut.ram_8x512_hi_0.inst.mem[63], dut.ram_8x512_lo_0.inst.mem[63]}; -wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]}; - - -// ROM cells -//====================== -reg [15:0] rom_mem [2047:0]; - -// Interrupt vectors -wire [15:0] irq_vect_15 = rom_mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector -wire [15:0] irq_vect_14 = rom_mem[(1<<(`ROM_MSB+1))-2]; // NMI -wire [15:0] irq_vect_13 = rom_mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13 -wire [15:0] irq_vect_12 = rom_mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12 -wire [15:0] irq_vect_11 = rom_mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11 -wire [15:0] irq_vect_10 = rom_mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10 -wire [15:0] irq_vect_09 = rom_mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9 -wire [15:0] irq_vect_08 = rom_mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8 -wire [15:0] irq_vect_07 = rom_mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7 -wire [15:0] irq_vect_06 = rom_mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6 -wire [15:0] irq_vect_05 = rom_mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5 -wire [15:0] irq_vect_04 = rom_mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4 -wire [15:0] irq_vect_03 = rom_mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3 -wire [15:0] irq_vect_02 = rom_mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2 -wire [15:0] irq_vect_01 = rom_mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1 -wire [15:0] irq_vect_00 = rom_mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0 - - -// CPU internals -//====================== - -wire mclk = dut.openMSP430_0.mclk; -wire puc = dut.openMSP430_0.puc;
trunk/fpga/diligent_s3board/bench/verilog/registers.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v =================================================================== --- trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v (revision 26) +++ trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v (nonexistent) @@ -1,385 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: tb_openMSP430_fpga.v -// -// *Module Description: -// openMSP430 FPGA testbench -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module tb_openMSP430_fpga; - -// -// Wire & Register definition -//------------------------------ - -// Clock & Reset -reg CLK_50MHz; -reg RESET; - -// Slide Switches -reg SW7; -reg SW6; -reg SW5; -reg SW4; -reg SW3; -reg SW2; -reg SW1; -reg SW0; - -// Push Button Switches -reg BTN2; -reg BTN1; -reg BTN0; - -// LEDs -wire LED7; -wire LED6; -wire LED5; -wire LED4; -wire LED3; -wire LED2; -wire LED1; -wire LED0; - -// Four-Sigit, Seven-Segment LED Display -wire SEG_A; -wire SEG_B; -wire SEG_C; -wire SEG_D; -wire SEG_E; -wire SEG_F; -wire SEG_G; -wire SEG_DP; -wire SEG_AN0; -wire SEG_AN1; -wire SEG_AN2; -wire SEG_AN3; - -// UART -reg UART_RXD; -wire UART_TXD; - -// Core debug signals -wire [8*32-1:0] i_state; -wire [8*32-1:0] e_state; -wire [31:0] inst_cycle; -wire [8*32-1:0] inst_full; -wire [31:0] inst_number; -wire [15:0] inst_pc; -wire [8*32-1:0] inst_short; - -// Testbench variables -integer i; -integer error; -reg stimulus_done; - - -// -// Include files -//------------------------------ - -// CPU & Memory registers -`include "registers.v" - -// Verilog stimulus -`include "stimulus.v" - -// -// Initialize ROM -//------------------------------ - -initial - begin - // Read memory file - $readmemh("./rom.mem", rom_mem); - - // Update Xilinx memory banks - for (i=0; i<2048; i=i+1) - begin - dut.rom_8x2k_hi_0.inst.mem[i] = rom_mem[i][15:8]; - dut.rom_8x2k_lo_0.inst.mem[i] = rom_mem[i][7:0]; - end - end - -// -// Generate Clock & Reset -//------------------------------ -initial - begin - CLK_50MHz = 1'b0; - forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz - end - -initial - begin - RESET = 1'b0; - #100 RESET = 1'b1; - #600 RESET = 1'b0; - end - -// -// Global initialization -//------------------------------ -initial - begin - error = 0; - stimulus_done = 1; - SW7 = 1'b0; // Slide Switches - SW6 = 1'b0; - SW5 = 1'b0; - SW4 = 1'b0; - SW3 = 1'b0; - SW2 = 1'b0; - SW1 = 1'b0; - SW0 = 1'b0; - BTN2 = 1'b0; // Push Button Switches - BTN1 = 1'b0; - BTN0 = 1'b0; - UART_RXD = 1'b0; // UART - end - -// -// openMSP430 FPGA Instance -//---------------------------------- - -openMSP430_fpga dut ( - -// Clock Sources - .CLK_50MHz (CLK_50MHz), - .CLK_SOCKET (1'b0), - -// Slide Switches - .SW7 (SW7), - .SW6 (SW6), - .SW5 (SW5), - .SW4 (SW4), - .SW3 (SW3), - .SW2 (SW2), - .SW1 (SW1), - .SW0 (SW0), - -// Push Button Switches - .BTN3 (RESET), - .BTN2 (BTN2), - .BTN1 (BTN1), - .BTN0 (BTN0), - -// LEDs - .LED7 (LED7), - .LED6 (LED6), - .LED5 (LED5), - .LED4 (LED4), - .LED3 (LED3), - .LED2 (LED2), - .LED1 (LED1), - .LED0 (LED0), - -// Four-Sigit, Seven-Segment LED Display - .SEG_A (SEG_A), - .SEG_B (SEG_B), - .SEG_C (SEG_C), - .SEG_D (SEG_D), - .SEG_E (SEG_E), - .SEG_F (SEG_F), - .SEG_G (SEG_G), - .SEG_DP (SEG_DP), - .SEG_AN0 (SEG_AN0), - .SEG_AN1 (SEG_AN1), - .SEG_AN2 (SEG_AN2), - .SEG_AN3 (SEG_AN3), - -// RS-232 Port - .UART_RXD (UART_RXD), - .UART_TXD (UART_TXD), - .UART_RXD_A (1'b0), - .UART_TXD_A (UART_TXD_A), - -// PS/2 Mouse/Keyboard Port - .PS2_D (PS2_D), - .PS2_C (PS2_C), - -// Fast, Asynchronous SRAM - .SRAM_A17 (SRAM_A17), // Address Bus Connections - .SRAM_A16 (SRAM_A16), - .SRAM_A15 (SRAM_A15), - .SRAM_A14 (SRAM_A14), - .SRAM_A13 (SRAM_A13), - .SRAM_A12 (SRAM_A12), - .SRAM_A11 (SRAM_A11), - .SRAM_A10 (SRAM_A10), - .SRAM_A9 (SRAM_A9), - .SRAM_A8 (SRAM_A8), - .SRAM_A7 (SRAM_A7), - .SRAM_A6 (SRAM_A6), - .SRAM_A5 (SRAM_A5), - .SRAM_A4 (SRAM_A4), - .SRAM_A3 (SRAM_A3), - .SRAM_A2 (SRAM_A2), - .SRAM_A1 (SRAM_A1), - .SRAM_A0 (SRAM_A0), - .SRAM_OE (SRAM_OE), // Write enable and output enable control signals - .SRAM_WE (SRAM_WE), - .SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables - .SRAM0_IO14 (SRAM0_IO14), - .SRAM0_IO13 (SRAM0_IO13), - .SRAM0_IO12 (SRAM0_IO12), - .SRAM0_IO11 (SRAM0_IO11), - .SRAM0_IO10 (SRAM0_IO10), - .SRAM0_IO9 (SRAM0_IO9), - .SRAM0_IO8 (SRAM0_IO8), - .SRAM0_IO7 (SRAM0_IO7), - .SRAM0_IO6 (SRAM0_IO6), - .SRAM0_IO5 (SRAM0_IO5), - .SRAM0_IO4 (SRAM0_IO4), - .SRAM0_IO3 (SRAM0_IO3), - .SRAM0_IO2 (SRAM0_IO2), - .SRAM0_IO1 (SRAM0_IO1), - .SRAM0_IO0 (SRAM0_IO0), - .SRAM0_CE1 (SRAM0_CE1), - .SRAM0_UB1 (SRAM0_UB1), - .SRAM0_LB1 (SRAM0_LB1), - .SRAM1_IO15 (SRAM1_IO15), - .SRAM1_IO14 (SRAM1_IO14), - .SRAM1_IO13 (SRAM1_IO13), - .SRAM1_IO12 (SRAM1_IO12), - .SRAM1_IO11 (SRAM1_IO11), - .SRAM1_IO10 (SRAM1_IO10), - .SRAM1_IO9 (SRAM1_IO9), - .SRAM1_IO8 (SRAM1_IO8), - .SRAM1_IO7 (SRAM1_IO7), - .SRAM1_IO6 (SRAM1_IO6), - .SRAM1_IO5 (SRAM1_IO5), - .SRAM1_IO4 (SRAM1_IO4), - .SRAM1_IO3 (SRAM1_IO3), - .SRAM1_IO2 (SRAM1_IO2), - .SRAM1_IO1 (SRAM1_IO1), - .SRAM1_IO0 (SRAM1_IO0), - .SRAM1_CE2 (SRAM1_CE2), - .SRAM1_UB2 (SRAM1_UB2), - .SRAM1_LB2 (SRAM1_LB2), - -// VGA Port - .VGA_R (VGA_R), - .VGA_G (VGA_G), - .VGA_B (VGA_B), - .VGA_HS (VGA_HS), - .VGA_VS (VGA_VS) -); - - -// -// Debug utility signals -//---------------------------------------- -msp_debug msp_debug_0 ( - -// OUTPUTs - .e_state (e_state), // Execution state - .i_state (i_state), // Instruction fetch state - .inst_cycle (inst_cycle), // Cycle number within current instruction - .inst_full (inst_full), // Currently executed instruction (full version) - .inst_number (inst_number), // Instruction number since last system reset - .inst_pc (inst_pc), // Instruction Program counter - .inst_short (inst_short), // Currently executed instruction (short version) - -// INPUTs - .mclk (mclk), // Main system clock - .puc (puc) // Main system reset -); - -// -// Generate Waveform -//---------------------------------------- -initial - begin - `ifdef VPD_FILE - $vcdplusfile("tb_openMSP430_fpga.vpd"); - $vcdpluson(); - `else - $dumpfile("tb_openMSP430_fpga.vcd"); - $dumpvars(0, tb_openMSP430_fpga); - `endif - end - -// -// End of simulation -//---------------------------------------- - -initial // Timeout - begin - #500000; - $display(" ==============================================="); - $display("| SIMULATION FAILED |"); - $display("| (simulation Timeout) |"); - $display(" ==============================================="); - $finish; - end - -initial // Normal end of test - begin - @(inst_pc===16'hffff) - $display(" ==============================================="); - if (error!=0) - begin - $display("| SIMULATION FAILED |"); - $display("| (some verilog stimulus checks failed) |"); - end - else if (~stimulus_done) - begin - $display("| SIMULATION FAILED |"); - $display("| (the verilog stimulus didn't complete) |"); - end - else - begin - $display("| SIMULATION PASSED |"); - end - $display(" ==============================================="); - $finish; - end - - -// -// Tasks Definition -//------------------------------ - - task tb_error; - input [65*8:0] error_string; - begin - $display("ERROR: %s %t", error_string, $time); - error = error+1; - end - endtask - - -endmodule
trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/bench/verilog/glbl.v =================================================================== --- trunk/fpga/diligent_s3board/bench/verilog/glbl.v (revision 26) +++ trunk/fpga/diligent_s3board/bench/verilog/glbl.v (nonexistent) @@ -1,58 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11 2005/03/15 02:06:36 nandinip Exp $ - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - - wire GSR; - wire GTS; - wire PRLD; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule
trunk/fpga/diligent_s3board/bench/verilog/glbl.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v (nonexistent) @@ -1,251 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: driver_7segment.v -// -// *Module Description: -// Driver for the four-digit, seven-segment LED display. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" - -module driver_7segment ( - -// OUTPUTs - per_dout, // Peripheral data output - seg_a, // Segment A control - seg_b, // Segment B control - seg_c, // Segment C control - seg_d, // Segment D control - seg_e, // Segment E control - seg_f, // Segment F control - seg_g, // Segment G control - seg_dp, // Segment DP control - seg_an0, // Anode 0 control - seg_an1, // Anode 1 control - seg_an2, // Anode 2 control - seg_an3, // Anode 3 control - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output -output seg_a; // Segment A control -output seg_b; // Segment B control -output seg_c; // Segment C control -output seg_d; // Segment D control -output seg_e; // Segment E control -output seg_f; // Segment F control -output seg_g; // Segment G control -output seg_dp; // Segment DP control -output seg_an0; // Anode 0 control -output seg_an1; // Anode 1 control -output seg_an2; // Anode 2 control -output seg_an3; // Anode 3 control - -// INPUTs -//========= -input mclk; // Main system clock -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter DIGIT0 = 9'h090; -parameter DIGIT1 = 9'h091; -parameter DIGIT2 = 9'h092; -parameter DIGIT3 = 9'h093; - - -// Register one-hot decoder -parameter DIGIT0_D = (256'h1 << (DIGIT0 /2)); -parameter DIGIT1_D = (256'h1 << (DIGIT1 /2)); -parameter DIGIT2_D = (256'h1 << (DIGIT2 /2)); -parameter DIGIT3_D = (256'h1 << (DIGIT3 /2)); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [255:0] reg_dec; -always @(per_addr) - case (per_addr) - (DIGIT0 /2): reg_dec = DIGIT0_D; - (DIGIT1 /2): reg_dec = DIGIT1_D; - (DIGIT2 /2): reg_dec = DIGIT2_D; - (DIGIT3 /2): reg_dec = DIGIT3_D; - default : reg_dec = {256{1'b0}}; - endcase - -// Read/Write probes -wire reg_lo_write = per_wen[0] & per_en; -wire reg_hi_write = per_wen[1] & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; -wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; -wire [255:0] reg_rd = reg_dec & {256{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// DIGIT0 Register -//----------------- -reg [7:0] digit0; - -wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0/2] : reg_lo_wr[DIGIT0/2]; -wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) digit0 <= 8'h00; - else if (digit0_wr) digit0 <= digit0_nxt; - - -// DIGIT1 Register -//----------------- -reg [7:0] digit1; - -wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1/2] : reg_lo_wr[DIGIT1/2]; -wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) digit1 <= 8'h00; - else if (digit1_wr) digit1 <= digit1_nxt; - - -// DIGIT2 Register -//----------------- -reg [7:0] digit2; - -wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2/2] : reg_lo_wr[DIGIT2/2]; -wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) digit2 <= 8'h00; - else if (digit2_wr) digit2 <= digit2_nxt; - - -// DIGIT3 Register -//----------------- -reg [7:0] digit3; - -wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3/2] : reg_lo_wr[DIGIT3/2]; -wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) digit3 <= 8'h00; - else if (digit3_wr) digit3 <= digit3_nxt; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0/2]}}) << (8 & {4{DIGIT0[0]}}); -wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1/2]}}) << (8 & {4{DIGIT1[0]}}); -wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2/2]}}) << (8 & {4{DIGIT2[0]}}); -wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3/2]}}) << (8 & {4{DIGIT3[0]}}); - -wire [15:0] per_dout = digit0_rd | - digit1_rd | - digit2_rd | - digit3_rd; - - -//============================================================================ -// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER -//============================================================================ - -// Anode selection -//------------------ - -// Free running counter -reg [23:0] anode_cnt; -always @ (posedge mclk or posedge puc) -if (puc) anode_cnt <= 24'h00_0000; -else anode_cnt <= anode_cnt+24'h00_0001; - -// Anode selection -wire [3:0] seg_an = (4'h1 << anode_cnt[17:16]); -wire seg_an0 = ~seg_an[0]; -wire seg_an1 = ~seg_an[1]; -wire seg_an2 = ~seg_an[2]; -wire seg_an3 = ~seg_an[3]; - - -// Segment selection -//---------------------------- - -wire [7:0] digit = seg_an[0] ? digit0 : - seg_an[1] ? digit1 : - seg_an[2] ? digit2 : - digit3; - -wire seg_a = ~digit[7]; -wire seg_b = ~digit[6]; -wire seg_c = ~digit[5]; -wire seg_d = ~digit[4]; -wire seg_e = ~digit[3]; -wire seg_f = ~digit[2]; -wire seg_g = ~digit[1]; -wire seg_dp = ~digit[0]; - - -endmodule // driver_7segment - - - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/mem_backbone.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/mem_backbone.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/mem_backbone.v (nonexistent) @@ -1,246 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: mem_backbone.v -// -// *Module Description: -// Memory interface backbone (decoder + arbiter) -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module mem_backbone ( - -// OUTPUTs - dbg_mem_din, // Debug unit Memory data input - eu_mdb_in, // Execution Unit Memory data bus input - fe_mdb_in, // Frontend Memory data bus input - fe_rom_wait, // Frontend wait for ROM - per_addr, // Peripheral address - per_din, // Peripheral data input - per_wen, // Peripheral write enable (high active) - per_en, // Peripheral enable (high active) - ram_addr, // RAM address - ram_cen, // RAM chip enable (low active) - ram_din, // RAM data input - ram_wen, // RAM write enable (low active) - rom_addr, // ROM address - rom_cen, // ROM chip enable (low active) - rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE-- - rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF-- - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_addr, // Debug address for rd/wr access - dbg_mem_dout, // Debug unit data output - dbg_mem_en, // Debug unit memory enable - dbg_mem_wr, // Debug unit memory write - eu_mab, // Execution Unit Memory address bus - eu_mb_en, // Execution Unit Memory bus enable - eu_mb_wr, // Execution Unit Memory bus write transfer - eu_mdb_out, // Execution Unit Memory data bus output - fe_mab, // Frontend Memory address bus - fe_mb_en, // Frontend Memory bus enable - mclk, // Main system clock - per_dout, // Peripheral data output - puc, // Main system reset - ram_dout, // RAM data output - rom_dout // ROM data output -); - -// OUTPUTs -//========= -output [15:0] dbg_mem_din; // Debug unit Memory data input -output [15:0] eu_mdb_in; // Execution Unit Memory data bus input -output [15:0] fe_mdb_in; // Frontend Memory data bus input -output fe_rom_wait; // Frontend wait for ROM -output [7:0] per_addr; // Peripheral address -output [15:0] per_din; // Peripheral data input -output [1:0] per_wen; // Peripheral write enable (high active) -output per_en; // Peripheral enable (high active) -output [`RAM_MSB:0] ram_addr; // RAM address -output ram_cen; // RAM chip enable (low active) -output [15:0] ram_din; // RAM data input -output [1:0] ram_wen; // RAM write enable (low active) -output [`ROM_MSB:0] rom_addr; // ROM address -output rom_cen; // ROM chip enable (low active) -output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE-- -output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF-- - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_addr; // Debug address for rd/wr access -input [15:0] dbg_mem_dout; // Debug unit data output -input dbg_mem_en; // Debug unit memory enable -input [1:0] dbg_mem_wr; // Debug unit memory write -input [14:0] eu_mab; // Execution Unit Memory address bus -input eu_mb_en; // Execution Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer -input [15:0] eu_mdb_out; // Execution Unit Memory data bus output -input [14:0] fe_mab; // Frontend Memory address bus -input fe_mb_en; // Frontend Memory bus enable -input mclk; // Main system clock -input [15:0] per_dout; // Peripheral data output -input puc; // Main system reset -input [15:0] ram_dout; // RAM data output -input [15:0] rom_dout; // ROM data output - - -//============================================================================= -// 1) DECODER -//============================================================================= - -// RAM Interface -//------------------ - -// Execution unit access -wire eu_ram_cen = ~(eu_mb_en & (eu_mab>=(`RAM_BASE>>1)) & - (eu_mab<((`RAM_BASE+`RAM_SIZE)>>1))); -wire [15:0] eu_ram_addr = eu_mab-(`RAM_BASE>>1); - -// Debug interface access -wire dbg_ram_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`RAM_BASE>>1)) & - (dbg_mem_addr[15:1]<((`RAM_BASE+`RAM_SIZE)>>1))); -wire [15:0] dbg_ram_addr = dbg_mem_addr[15:1]-(`RAM_BASE>>1); - - -// RAM Interface -wire [`RAM_MSB:0] ram_addr = ~dbg_ram_cen ? dbg_ram_addr[`RAM_MSB:0] : eu_ram_addr[`RAM_MSB:0]; -wire ram_cen = dbg_ram_cen & eu_ram_cen; -wire [1:0] ram_wen = ~(dbg_mem_wr | eu_mb_wr); -wire [15:0] ram_din = ~dbg_ram_cen ? dbg_mem_dout : eu_mdb_out; - - -// ROM Interface -//------------------ -parameter ROM_OFFSET = (16'hFFFF-`ROM_SIZE+1); - -// Execution unit access (only read access are accepted) -wire eu_rom_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(ROM_OFFSET>>1))); -wire [15:0] eu_rom_addr = eu_mab-(ROM_OFFSET>>1); - -// Front-end access -wire fe_rom_cen = ~(fe_mb_en & (fe_mab>=(ROM_OFFSET>>1))); -wire [15:0] fe_rom_addr = fe_mab-(ROM_OFFSET>>1); - -// Debug interface access -wire dbg_rom_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(ROM_OFFSET>>1))); -wire [15:0] dbg_rom_addr = dbg_mem_addr[15:1]-(ROM_OFFSET>>1); - - -// ROM Interface (Execution unit has priority) -wire [`ROM_MSB:0] rom_addr = ~dbg_rom_cen ? dbg_rom_addr[`ROM_MSB:0] : - ~eu_rom_cen ? eu_rom_addr[`ROM_MSB:0] : fe_rom_addr[`ROM_MSB:0]; -wire rom_cen = fe_rom_cen & eu_rom_cen & dbg_rom_cen; -wire [1:0] rom_wen_dbg = ~dbg_mem_wr; -wire [15:0] rom_din_dbg = dbg_mem_dout; - -wire fe_rom_wait = (~fe_rom_cen & ~eu_rom_cen); - - -// Peripherals -//-------------------- -wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00); -wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00); - -wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0]; -wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out; -wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr; -wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en; - -reg [15:0] per_dout_val; -always @ (posedge mclk or posedge puc) - if (puc) per_dout_val <= 16'h0000; - else per_dout_val <= per_dout; - - -// Frontend data Mux -//--------------------------------- -// Whenever the frontend doesn't access the ROM, backup the data - -// Detect whenever the data should be backuped and restored -reg fe_rom_cen_dly; -always @(posedge mclk or posedge puc) - if (puc) fe_rom_cen_dly <= 1'b0; - else fe_rom_cen_dly <= fe_rom_cen; - -wire fe_rom_save = ( fe_rom_cen & ~fe_rom_cen_dly) & ~dbg_halt_st; -wire fe_rom_restore = (~fe_rom_cen & fe_rom_cen_dly) | dbg_halt_st; - -reg [15:0] rom_dout_bckup; -always @(posedge mclk or posedge puc) - if (puc) rom_dout_bckup <= 16'h0000; - else if (fe_rom_save) rom_dout_bckup <= rom_dout; - -// Mux between the ROM data and the backup -reg rom_dout_bckup_sel; -always @(posedge mclk or posedge puc) - if (puc) rom_dout_bckup_sel <= 1'b0; - else if (fe_rom_save) rom_dout_bckup_sel <= 1'b1; - else if (fe_rom_restore) rom_dout_bckup_sel <= 1'b0; - -assign fe_mdb_in = rom_dout_bckup_sel ? rom_dout_bckup : rom_dout; - - -// Execution-Unit data Mux -//--------------------------------- - -// Select between peripherals, RAM and ROM -reg [1:0] eu_mdb_in_sel; -always @(posedge mclk or posedge puc) - if (puc) eu_mdb_in_sel <= 2'b00; - else eu_mdb_in_sel <= {~eu_rom_cen, per_en}; - -// Mux -assign eu_mdb_in = eu_mdb_in_sel[1] ? rom_dout : - eu_mdb_in_sel[0] ? per_dout_val : ram_dout; - -// Debug interface data Mux -//--------------------------------- - -// Select between peripherals, RAM and ROM -reg [1:0] dbg_mem_din_sel; -always @(posedge mclk or posedge puc) - if (puc) dbg_mem_din_sel <= 2'b00; - else dbg_mem_din_sel <= {~dbg_rom_cen, dbg_per_en}; - -// Mux -assign dbg_mem_din = dbg_mem_din_sel[1] ? rom_dout : - dbg_mem_din_sel[0] ? per_dout_val : ram_dout; - - -endmodule // mem_backbone - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/mem_backbone.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/execution_unit.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/execution_unit.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/execution_unit.v (nonexistent) @@ -1,366 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: execution_unit.v -// -// *Module Description: -// openMSP430 Execution unit -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module execution_unit ( - -// OUTPUTs - cpuoff, // Turns off the CPU - dbg_reg_din, // Debug unit CPU register data input - gie, // General interrupt enable - mab, // Memory address bus - mb_en, // Memory bus enable - mb_wr, // Memory bus write transfer - mdb_out, // Memory data bus output - oscoff, // Turns off LFXT1 clock input - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - scg1, // System clock generator 1. Turns off the SMCLK - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_dout, // Debug unit data output - dbg_reg_wr, // Debug unit CPU register write - e_state, // Execution state - exec_done, // Execution completed - inst_ad, // Decoded Inst: destination addressing mode - inst_as, // Decoded Inst: source addressing mode - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_dest, // Decoded Inst: destination (one hot) - inst_dext, // Decoded Inst: destination extended instruction word - inst_irq_rst, // Decoded Inst: reset interrupt - inst_jmp, // Decoded Inst: Conditional jump - inst_sext, // Decoded Inst: source extended instruction word - inst_so, // Decoded Inst: Single-operand arithmetic - inst_src, // Decoded Inst: source (one hot) - inst_type, // Decoded Instruction type - mclk, // Main system clock - mdb_in, // Memory data bus input - pc, // Program counter - pc_nxt, // Next PC value (for CALL & IRQ) - puc // Main system reset -); - -// OUTPUTs -//========= -output cpuoff; // Turns off the CPU -output [15:0] dbg_reg_din; // Debug unit CPU register data input -output gie; // General interrupt enable -output [15:0] mab; // Memory address bus -output mb_en; // Memory bus enable -output [1:0] mb_wr; // Memory bus write transfer -output [15:0] mdb_out; // Memory data bus output -output oscoff; // Turns off LFXT1 clock input -output [15:0] pc_sw; // Program counter software value -output pc_sw_wr; // Program counter software write -output scg1; // System clock generator 1. Turns off the SMCLK - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_dout; // Debug unit data output -input dbg_reg_wr; // Debug unit CPU register write -input [3:0] e_state; // Execution state -input exec_done; // Execution completed -input [7:0] inst_ad; // Decoded Inst: destination addressing mode -input [7:0] inst_as; // Decoded Inst: source addressing mode -input [11:0] inst_alu; // ALU control signals -input inst_bw; // Decoded Inst: byte width -input [15:0] inst_dest; // Decoded Inst: destination (one hot) -input [15:0] inst_dext; // Decoded Inst: destination extended instruction word -input inst_irq_rst; // Decoded Inst: reset interrupt -input [7:0] inst_jmp; // Decoded Inst: Conditional jump -input [15:0] inst_sext; // Decoded Inst: source extended instruction word -input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic -input [15:0] inst_src; // Decoded Inst: source (one hot) -input [2:0] inst_type; // Decoded Instruction type -input mclk; // Main system clock -input [15:0] mdb_in; // Memory data bus input -input [15:0] pc; // Program counter -input [15:0] pc_nxt; // Next PC value (for CALL & IRQ) -input puc; // Main system reset - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -wire [15:0] alu_out; -wire [15:0] alu_out_add; -wire [3:0] alu_stat; -wire [3:0] alu_stat_wr; -wire [15:0] op_dst; -wire [15:0] op_src; -wire [15:0] reg_dest; -wire [15:0] reg_src; -wire [15:0] mdb_in_bw; -wire [15:0] mdb_in_val; -wire [3:0] status; - - -//============================================================================= -// 2) REGISTER FILE -//============================================================================= - -wire reg_dest_wr = ((e_state==`E_EXEC) & ( - (inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) | - (inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) | - inst_type[`INST_JMP])) | dbg_reg_wr; - -wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) | - ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])); - -wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI]; - -wire reg_sr_clr = (e_state==`E_IRQ_2); - -wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) | - ((e_state==`E_DST_WR) & inst_so[`RETI]); - -wire reg_incr = (exec_done & inst_as[`INDIR_I]) | - ((e_state==`E_SRC_RD) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & inst_so[`RETI]); - -assign dbg_reg_din = reg_dest; - - -register_file register_file_0 ( - -// OUTPUTs - .cpuoff (cpuoff), // Turns off the CPU - .gie (gie), // General interrupt enable - .oscoff (oscoff), // Turns off LFXT1 clock input - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .reg_dest (reg_dest), // Selected register destination content - .reg_src (reg_src), // Selected register source content - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - .status (status), // R2 Status {V,N,Z,C} - -// INPUTs - .alu_stat (alu_stat), // ALU Status {V,N,Z,C} - .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Register destination selection - .inst_src (inst_src), // Register source selection - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .puc (puc), // Main system reset - .reg_dest_val (alu_out), // Selected register destination value - .reg_dest_wr (reg_dest_wr), // Write selected register destination - .reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction - .reg_sp_val (alu_out_add), // Stack Pointer next value - .reg_sp_wr (reg_sp_wr), // Stack Pointer write - .reg_sr_clr (reg_sr_clr), // Status register clear for interrupts - .reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction - .reg_incr (reg_incr) // Increment source register -); - - -//============================================================================= -// 3) SOURCE OPERAND MUXING -//============================================================================= -// inst_as[`DIR] : Register direct. -> Source is in register -// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset -// inst_as[`INDIR] : Register indirect. -// inst_as[`INDIR_I]: Register indirect autoincrement. -// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x). -// inst_as[`IMM] : Immediate (operand is next word in the instruction stream). -// inst_as[`ABS] : Absolute (operand is in memory at address x). -// inst_as[`CONST] : Constant. - -wire src_reg_src_sel = (e_state==`E_IRQ_0) | - (e_state==`E_IRQ_2) | - ((e_state==`E_SRC_RD) & ~inst_as[`ABS]) | - ((e_state==`E_SRC_WR) & ~inst_as[`ABS]) | - ((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]); - -wire src_reg_dest_sel = (e_state==`E_IRQ_1) | - (e_state==`E_IRQ_3) | - ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])); - -wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] | - inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])); - -wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) | - ((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] | - inst_so[`RETI])); - -wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] | - inst_as[`CONST] | inst_so[`RETI])); - - -assign op_src = src_reg_src_sel ? reg_src : - src_reg_dest_sel ? reg_dest : - src_mdb_in_val_sel ? mdb_in_val : - src_inst_dext_sel ? inst_dext : - src_inst_sext_sel ? inst_sext : 16'h0000; - - -//============================================================================= -// 4) DESTINATION OPERAND MUXING -//============================================================================= -// inst_ad[`DIR] : Register direct. -// inst_ad[`IDX] : Register indexed. -// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x). -// inst_ad[`ABS] : Absolute (operand is in memory at address x). - - -wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])) | - ((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] | - inst_as[`ABS])); - -wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) | - ((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] | - inst_type[`INST_SO]) & ~inst_so[`RETI]); - -wire dst_fffe_sel = (e_state==`E_IRQ_0) | - (e_state==`E_IRQ_1) | - (e_state==`E_IRQ_3) | - ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]); - -wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) | - ((e_state==`E_DST_WR) & ~inst_ad[`ABS]) | - ((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] | - inst_type[`INST_SO]) & ~inst_so[`RETI]); - - -assign op_dst = dbg_halt_st ? dbg_mem_dout : - dst_inst_sext_sel ? inst_sext : - dst_mdb_in_bw_sel ? mdb_in_bw : - dst_reg_dest_sel ? reg_dest : - dst_fffe_sel ? 16'hfffe : 16'h0000; - - -//============================================================================= -// 5) ALU -//============================================================================= - -wire exec_cycle = (e_state==`E_EXEC); - -alu alu_0 ( - -// OUTPUTs - .alu_out (alu_out), // ALU output value - .alu_out_add (alu_out_add), // ALU adder output value - .alu_stat (alu_stat), // ALU Status {V,N,Z,C} - .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .exec_cycle (exec_cycle), // Instruction execution cycle - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_so (inst_so), // Single-operand arithmetic - .op_dst (op_dst), // Destination operand - .op_src (op_src), // Source operand - .status (status) // R2 Status {V,N,Z,C} -); - - -//============================================================================= -// 6) MEMORY INTERFACE -//============================================================================= - -// Detect memory read/write access -assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | - ((e_state==`E_IRQ_3) & ~inst_irq_rst) | - ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | - (e_state==`E_SRC_WR) | - ((e_state==`E_EXEC) & inst_so[`RETI]) | - (e_state==`E_DST_RD) | - (e_state==`E_DST_WR); - -wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 : - ~inst_bw ? 2'b11 : - alu_out_add[0] ? 2'b10 : 2'b01; -assign mb_wr = ({2{(e_state==`E_IRQ_1)}} | - {2{(e_state==`E_IRQ_3)}} | - {2{(e_state==`E_DST_WR)}} | - {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk; - -// Memory address bus -assign mab = alu_out_add[15:0]; - -// Memory data bus output -reg [15:0] mdb_out_nxt; -always @(posedge mclk or posedge puc) - if (puc) mdb_out_nxt <= 16'h0000; - else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt; - else if ((e_state==`E_EXEC & ~inst_so[`CALL]) | - (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out; - -assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt; - -// Format memory data bus input depending on BW -reg mab_lsb; -always @(posedge mclk or posedge puc) - if (puc) mab_lsb <= 1'b0; - else if (mb_en) mab_lsb <= alu_out_add[0]; - -assign mdb_in_bw = ~inst_bw ? mdb_in : - mab_lsb ? {2{mdb_in[15:8]}} : mdb_in; - -// Memory data bus input buffer (buffer after a source read) -reg mdb_in_buf_en; -always @(posedge mclk or posedge puc) - if (puc) mdb_in_buf_en <= 1'b0; - else mdb_in_buf_en <= (e_state==`E_SRC_RD); - -reg mdb_in_buf_valid; -always @(posedge mclk or posedge puc) - if (puc) mdb_in_buf_valid <= 1'b0; - else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0; - else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1; - -reg [15:0] mdb_in_buf; -always @(posedge mclk or posedge puc) - if (puc) mdb_in_buf <= 16'h0000; - else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw; - -assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw; - - -endmodule // execution_unit -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/execution_unit.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v (nonexistent) @@ -1,181 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: template_periph_16b.v -// -// *Module Description: -// 16 bit peripheral template. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module template_periph_16b ( - -// OUTPUTs - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter CNTRL1 = 9'h190; -parameter CNTRL2 = 9'h192; -parameter CNTRL3 = 9'h194; -parameter CNTRL4 = 9'h196; - - -// Register one-hot decoder -parameter CNTRL1_D = (512'h1 << CNTRL1); -parameter CNTRL2_D = (512'h1 << CNTRL2); -parameter CNTRL3_D = (512'h1 << CNTRL3); -parameter CNTRL4_D = (512'h1 << CNTRL4); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [511:0] reg_dec; -always @(per_addr) - case ({per_addr,1'b0}) - CNTRL1 : reg_dec = CNTRL1_D; - CNTRL2 : reg_dec = CNTRL2_D; - CNTRL3 : reg_dec = CNTRL3_D; - CNTRL4 : reg_dec = CNTRL4_D; - default: reg_dec = {512{1'b0}}; - endcase - -// Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [511:0] reg_wr = reg_dec & {512{reg_write}}; -wire [511:0] reg_rd = reg_dec & {512{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// CNTRL1 Register -//----------------- -reg [15:0] cntrl1; - -wire cntrl1_wr = reg_wr[CNTRL1]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl1 <= 16'h0000; - else if (cntrl1_wr) cntrl1 <= per_din; - - -// CNTRL2 Register -//----------------- -reg [15:0] cntrl2; - -wire cntrl2_wr = reg_wr[CNTRL2]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl2 <= 16'h0000; - else if (cntrl2_wr) cntrl2 <= per_din; - - -// CNTRL3 Register -//----------------- -reg [15:0] cntrl3; - -wire cntrl3_wr = reg_wr[CNTRL3]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl3 <= 16'h0000; - else if (cntrl3_wr) cntrl3 <= per_din; - - -// CNTRL4 Register -//----------------- -reg [15:0] cntrl4; - -wire cntrl4_wr = reg_wr[CNTRL4]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl4 <= 16'h0000; - else if (cntrl4_wr) cntrl4 <= per_din; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}}; -wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}}; -wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}}; -wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}}; - -wire [15:0] per_dout = cntrl1_rd | - cntrl2_rd | - cntrl3_rd | - cntrl4_rd; - - -endmodule // template_periph_16b - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v (nonexistent) @@ -1,189 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: template_periph_8b.v -// -// *Module Description: -// 8 bit peripheral template. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module template_periph_8b ( - -// OUTPUTs - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc // Main system reset -); - -// OUTPUTs -//========= -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter CNTRL1 = 9'h090; -parameter CNTRL2 = 9'h091; -parameter CNTRL3 = 9'h092; -parameter CNTRL4 = 9'h093; - - -// Register one-hot decoder -parameter CNTRL1_D = (256'h1 << (CNTRL1 /2)); -parameter CNTRL2_D = (256'h1 << (CNTRL2 /2)); -parameter CNTRL3_D = (256'h1 << (CNTRL3 /2)); -parameter CNTRL4_D = (256'h1 << (CNTRL4 /2)); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [255:0] reg_dec; -always @(per_addr) - case (per_addr) - (CNTRL1 /2): reg_dec = CNTRL1_D; - (CNTRL2 /2): reg_dec = CNTRL2_D; - (CNTRL3 /2): reg_dec = CNTRL3_D; - (CNTRL4 /2): reg_dec = CNTRL4_D; - default : reg_dec = {256{1'b0}}; - endcase - -// Read/Write probes -wire reg_lo_write = per_wen[0] & per_en; -wire reg_hi_write = per_wen[1] & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; -wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; -wire [255:0] reg_rd = reg_dec & {256{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// CNTRL1 Register -//----------------- -reg [7:0] cntrl1; - -wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1/2] : reg_lo_wr[CNTRL1/2]; -wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl1 <= 8'h00; - else if (cntrl1_wr) cntrl1 <= cntrl1_nxt; - - -// CNTRL2 Register -//----------------- -reg [7:0] cntrl2; - -wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2/2] : reg_lo_wr[CNTRL2/2]; -wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl2 <= 8'h00; - else if (cntrl2_wr) cntrl2 <= cntrl2_nxt; - - -// CNTRL3 Register -//----------------- -reg [7:0] cntrl3; - -wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3/2] : reg_lo_wr[CNTRL3/2]; -wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl3 <= 8'h00; - else if (cntrl3_wr) cntrl3 <= cntrl3_nxt; - - -// CNTRL4 Register -//----------------- -reg [7:0] cntrl4; - -wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4/2] : reg_lo_wr[CNTRL4/2]; -wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) cntrl4 <= 8'h00; - else if (cntrl4_wr) cntrl4 <= cntrl4_nxt; - - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] cntrl1_rd = (cntrl1 & {8{reg_rd[CNTRL1/2]}}) << (8 & {4{CNTRL1[0]}}); -wire [15:0] cntrl2_rd = (cntrl2 & {8{reg_rd[CNTRL2/2]}}) << (8 & {4{CNTRL2[0]}}); -wire [15:0] cntrl3_rd = (cntrl3 & {8{reg_rd[CNTRL3/2]}}) << (8 & {4{CNTRL3[0]}}); -wire [15:0] cntrl4_rd = (cntrl4 & {8{reg_rd[CNTRL4/2]}}) << (8 & {4{CNTRL4[0]}}); - -wire [15:0] per_dout = cntrl1_rd | - cntrl2_rd | - cntrl3_rd | - cntrl4_rd; - - -endmodule // template_periph_8b - - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/gpio.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/gpio.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/gpio.v (nonexistent) @@ -1,778 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: gpio.v -// -// *Module Description: -// Digital I/O interface -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module gpio ( - -// OUTPUTs - irq_port1, // Port 1 interrupt - irq_port2, // Port 2 interrupt - p1_dout, // Port 1 data output - p1_dout_en, // Port 1 data output enable - p1_sel, // Port 1 function select - p2_dout, // Port 2 data output - p2_dout_en, // Port 2 data output enable - p2_sel, // Port 2 function select - p3_dout, // Port 3 data output - p3_dout_en, // Port 3 data output enable - p3_sel, // Port 3 function select - p4_dout, // Port 4 data output - p4_dout_en, // Port 4 data output enable - p4_sel, // Port 4 function select - p5_dout, // Port 5 data output - p5_dout_en, // Port 5 data output enable - p5_sel, // Port 5 function select - p6_dout, // Port 6 data output - p6_dout_en, // Port 6 data output enable - p6_sel, // Port 6 function select - per_dout, // Peripheral data output - -// INPUTs - mclk, // Main system clock - p1_din, // Port 1 data input - p2_din, // Port 2 data input - p3_din, // Port 3 data input - p4_din, // Port 4 data input - p5_din, // Port 5 data input - p6_din, // Port 6 data input - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc // Main system reset -); - -// PARAMETERs -//============ -parameter P1_EN = 1'b1; // Enable Port 1 -parameter P2_EN = 1'b1; // Enable Port 2 -parameter P3_EN = 1'b0; // Enable Port 3 -parameter P4_EN = 1'b0; // Enable Port 4 -parameter P5_EN = 1'b0; // Enable Port 5 -parameter P6_EN = 1'b0; // Enable Port 6 - - -// OUTPUTs -//========= -output irq_port1; // Port 1 interrupt -output irq_port2; // Port 2 interrupt -output [7:0] p1_dout; // Port 1 data output -output [7:0] p1_dout_en; // Port 1 data output enable -output [7:0] p1_sel; // Port 1 function select -output [7:0] p2_dout; // Port 2 data output -output [7:0] p2_dout_en; // Port 2 data output enable -output [7:0] p2_sel; // Port 2 function select -output [7:0] p3_dout; // Port 3 data output -output [7:0] p3_dout_en; // Port 3 data output enable -output [7:0] p3_sel; // Port 3 function select -output [7:0] p4_dout; // Port 4 data output -output [7:0] p4_dout_en; // Port 4 data output enable -output [7:0] p4_sel; // Port 4 function select -output [7:0] p5_dout; // Port 5 data output -output [7:0] p5_dout_en; // Port 5 data output enable -output [7:0] p5_sel; // Port 5 function select -output [7:0] p6_dout; // Port 6 data output -output [7:0] p6_dout_en; // Port 6 data output enable -output [7:0] p6_sel; // Port 6 function select -output [15:0] per_dout; // Peripheral data output - -// INPUTs -//========= -input mclk; // Main system clock -input [7:0] p1_din; // Port 1 data input -input [7:0] p2_din; // Port 2 data input -input [7:0] p3_din; // Port 3 data input -input [7:0] p4_din; // Port 4 data input -input [7:0] p5_din; // Port 5 data input -input [7:0] p6_din; // Port 6 data input -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Masks -parameter P1_EN_MSK = {8{P1_EN[0]}}; -parameter P2_EN_MSK = {8{P2_EN[0]}}; -parameter P3_EN_MSK = {8{P3_EN[0]}}; -parameter P4_EN_MSK = {8{P4_EN[0]}}; -parameter P5_EN_MSK = {8{P5_EN[0]}}; -parameter P6_EN_MSK = {8{P6_EN[0]}}; - -// Register addresses -parameter P1IN = 9'h020; // Port 1 -parameter P1OUT = 9'h021; -parameter P1DIR = 9'h022; -parameter P1IFG = 9'h023; -parameter P1IES = 9'h024; -parameter P1IE = 9'h025; -parameter P1SEL = 9'h026; -parameter P2IN = 9'h028; // Port 2 -parameter P2OUT = 9'h029; -parameter P2DIR = 9'h02A; -parameter P2IFG = 9'h02B; -parameter P2IES = 9'h02C; -parameter P2IE = 9'h02D; -parameter P2SEL = 9'h02E; -parameter P3IN = 9'h018; // Port 3 -parameter P3OUT = 9'h019; -parameter P3DIR = 9'h01A; -parameter P3SEL = 9'h01B; -parameter P4IN = 9'h01C; // Port 4 -parameter P4OUT = 9'h01D; -parameter P4DIR = 9'h01E; -parameter P4SEL = 9'h01F; -parameter P5IN = 9'h030; // Port 5 -parameter P5OUT = 9'h031; -parameter P5DIR = 9'h032; -parameter P5SEL = 9'h033; -parameter P6IN = 9'h034; // Port 6 -parameter P6OUT = 9'h035; -parameter P6DIR = 9'h036; -parameter P6SEL = 9'h037; - - -// Register one-hot decoder -parameter P1IN_D = (256'h1 << (P1IN /2)); // Port 1 -parameter P1OUT_D = (256'h1 << (P1OUT /2)); -parameter P1DIR_D = (256'h1 << (P1DIR /2)); -parameter P1IFG_D = (256'h1 << (P1IFG /2)); -parameter P1IES_D = (256'h1 << (P1IES /2)); -parameter P1IE_D = (256'h1 << (P1IE /2)); -parameter P1SEL_D = (256'h1 << (P1SEL /2)); -parameter P2IN_D = (256'h1 << (P2IN /2)); // Port 2 -parameter P2OUT_D = (256'h1 << (P2OUT /2)); -parameter P2DIR_D = (256'h1 << (P2DIR /2)); -parameter P2IFG_D = (256'h1 << (P2IFG /2)); -parameter P2IES_D = (256'h1 << (P2IES /2)); -parameter P2IE_D = (256'h1 << (P2IE /2)); -parameter P2SEL_D = (256'h1 << (P2SEL /2)); -parameter P3IN_D = (256'h1 << (P3IN /2)); // Port 3 -parameter P3OUT_D = (256'h1 << (P3OUT /2)); -parameter P3DIR_D = (256'h1 << (P3DIR /2)); -parameter P3SEL_D = (256'h1 << (P3SEL /2)); -parameter P4IN_D = (256'h1 << (P4IN /2)); // Port 4 -parameter P4OUT_D = (256'h1 << (P4OUT /2)); -parameter P4DIR_D = (256'h1 << (P4DIR /2)); -parameter P4SEL_D = (256'h1 << (P4SEL /2)); -parameter P5IN_D = (256'h1 << (P5IN /2)); // Port 5 -parameter P5OUT_D = (256'h1 << (P5OUT /2)); -parameter P5DIR_D = (256'h1 << (P5DIR /2)); -parameter P5SEL_D = (256'h1 << (P5SEL /2)); -parameter P6IN_D = (256'h1 << (P6IN /2)); // Port 6 -parameter P6OUT_D = (256'h1 << (P6OUT /2)); -parameter P6DIR_D = (256'h1 << (P6DIR /2)); -parameter P6SEL_D = (256'h1 << (P6SEL /2)); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [255:0] reg_dec; -always @(per_addr) - case (per_addr) - (P1IN /2): reg_dec = P1IN_D & {256{P1_EN[0]}}; - (P1OUT /2): reg_dec = P1OUT_D & {256{P1_EN[0]}}; - (P1DIR /2): reg_dec = P1DIR_D & {256{P1_EN[0]}}; - (P1IFG /2): reg_dec = P1IFG_D & {256{P1_EN[0]}}; - (P1IES /2): reg_dec = P1IES_D & {256{P1_EN[0]}}; - (P1IE /2): reg_dec = P1IE_D & {256{P1_EN[0]}}; - (P1SEL /2): reg_dec = P1SEL_D & {256{P1_EN[0]}}; - (P2IN /2): reg_dec = P2IN_D & {256{P2_EN[0]}}; - (P2OUT /2): reg_dec = P2OUT_D & {256{P2_EN[0]}}; - (P2DIR /2): reg_dec = P2DIR_D & {256{P2_EN[0]}}; - (P2IFG /2): reg_dec = P2IFG_D & {256{P2_EN[0]}}; - (P2IES /2): reg_dec = P2IES_D & {256{P2_EN[0]}}; - (P2IE /2): reg_dec = P2IE_D & {256{P2_EN[0]}}; - (P2SEL /2): reg_dec = P2SEL_D & {256{P2_EN[0]}}; - (P3IN /2): reg_dec = P3IN_D & {256{P3_EN[0]}}; - (P3OUT /2): reg_dec = P3OUT_D & {256{P3_EN[0]}}; - (P3DIR /2): reg_dec = P3DIR_D & {256{P3_EN[0]}}; - (P3SEL /2): reg_dec = P3SEL_D & {256{P3_EN[0]}}; - (P4IN /2): reg_dec = P4IN_D & {256{P4_EN[0]}}; - (P4OUT /2): reg_dec = P4OUT_D & {256{P4_EN[0]}}; - (P4DIR /2): reg_dec = P4DIR_D & {256{P4_EN[0]}}; - (P4SEL /2): reg_dec = P4SEL_D & {256{P4_EN[0]}}; - (P5IN /2): reg_dec = P5IN_D & {256{P5_EN[0]}}; - (P5OUT /2): reg_dec = P5OUT_D & {256{P5_EN[0]}}; - (P5DIR /2): reg_dec = P5DIR_D & {256{P5_EN[0]}}; - (P5SEL /2): reg_dec = P5SEL_D & {256{P5_EN[0]}}; - (P6IN /2): reg_dec = P6IN_D & {256{P6_EN[0]}}; - (P6OUT /2): reg_dec = P6OUT_D & {256{P6_EN[0]}}; - (P6DIR /2): reg_dec = P6DIR_D & {256{P6_EN[0]}}; - (P6SEL /2): reg_dec = P6SEL_D & {256{P6_EN[0]}}; - default : reg_dec = {256{1'b0}}; - endcase - -// Read/Write probes -wire reg_lo_write = per_wen[0] & per_en; -wire reg_hi_write = per_wen[1] & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; -wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; -wire [255:0] reg_rd = reg_dec & {256{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// P1IN Register -//--------------- -reg [7:0] p1in; - -always @ (posedge mclk or posedge puc) - if (puc) p1in <= 8'h00; - else p1in <= p1_din & P1_EN_MSK; - - -// P1OUT Register -//---------------- -reg [7:0] p1out; - -wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT/2] : reg_lo_wr[P1OUT/2]; -wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p1out <= 8'h00; - else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK; - -assign p1_dout = p1out; - - -// P1DIR Register -//---------------- -reg [7:0] p1dir; - -wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR/2] : reg_lo_wr[P1DIR/2]; -wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p1dir <= 8'h00; - else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK; - -assign p1_dout_en = p1dir; - - -// P1IFG Register -//---------------- -reg [7:0] p1ifg; - -wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG/2] : reg_lo_wr[P1IFG/2]; -wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0]; -wire [7:0] p1ifg_set; - -always @ (posedge mclk or posedge puc) - if (puc) p1ifg <= 8'h00; - else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK; - else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK; - -// P1IES Register -//---------------- -reg [7:0] p1ies; - -wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES/2] : reg_lo_wr[P1IES/2]; -wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p1ies <= 8'h00; - else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK; - - -// P1IE Register -//---------------- -reg [7:0] p1ie; - -wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE/2] : reg_lo_wr[P1IE/2]; -wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p1ie <= 8'h00; - else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK; - - -// P1SEL Register -//---------------- -reg [7:0] p1sel; - -wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL/2] : reg_lo_wr[P1SEL/2]; -wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p1sel <= 8'h00; - else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK; - -assign p1_sel = p1sel; - - -// P2IN Register -//--------------- -reg [7:0] p2in; - -always @ (posedge mclk or posedge puc) - if (puc) p2in <= 8'h00; - else p2in <= p2_din & P2_EN_MSK; - - -// P2OUT Register -//---------------- -reg [7:0] p2out; - -wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT/2] : reg_lo_wr[P2OUT/2]; -wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p2out <= 8'h00; - else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK; - -assign p2_dout = p2out; - - -// P2DIR Register -//---------------- -reg [7:0] p2dir; - -wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR/2] : reg_lo_wr[P2DIR/2]; -wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p2dir <= 8'h00; - else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK; - -assign p2_dout_en = p2dir; - - -// P2IFG Register -//---------------- -reg [7:0] p2ifg; - -wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG/2] : reg_lo_wr[P2IFG/2]; -wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0]; -wire [7:0] p2ifg_set; - -always @ (posedge mclk or posedge puc) - if (puc) p2ifg <= 8'h00; - else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK; - else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK; - - -// P2IES Register -//---------------- -reg [7:0] p2ies; - -wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES/2] : reg_lo_wr[P2IES/2]; -wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p2ies <= 8'h00; - else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK; - - -// P2IE Register -//---------------- -reg [7:0] p2ie; - -wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE/2] : reg_lo_wr[P2IE/2]; -wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p2ie <= 8'h00; - else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK; - - -// P2SEL Register -//---------------- -reg [7:0] p2sel; - -wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL/2] : reg_lo_wr[P2SEL/2]; -wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p2sel <= 8'h00; - else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK; - -assign p2_sel = p2sel; - - -// P3IN Register -//--------------- -reg [7:0] p3in; - -always @ (posedge mclk or posedge puc) - if (puc) p3in <= 8'h00; - else p3in <= p3_din & P3_EN_MSK; - - -// P3OUT Register -//---------------- -reg [7:0] p3out; - -wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT/2] : reg_lo_wr[P3OUT/2]; -wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p3out <= 8'h00; - else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK; - -assign p3_dout = p3out; - - -// P3DIR Register -//---------------- -reg [7:0] p3dir; - -wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR/2] : reg_lo_wr[P3DIR/2]; -wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p3dir <= 8'h00; - else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK; - -assign p3_dout_en = p3dir; - - -// P3SEL Register -//---------------- -reg [7:0] p3sel; - -wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL/2] : reg_lo_wr[P3SEL/2]; -wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p3sel <= 8'h00; - else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK; - -assign p3_sel = p3sel; - - -// P4IN Register -//--------------- -reg [7:0] p4in; - -always @ (posedge mclk or posedge puc) - if (puc) p4in <= 8'h00; - else p4in <= p4_din & P4_EN_MSK; - - -// P4OUT Register -//---------------- -reg [7:0] p4out; - -wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT/2] : reg_lo_wr[P4OUT/2]; -wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p4out <= 8'h00; - else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK; - -assign p4_dout = p4out; - - -// P4DIR Register -//---------------- -reg [7:0] p4dir; - -wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR/2] : reg_lo_wr[P4DIR/2]; -wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p4dir <= 8'h00; - else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK; - -assign p4_dout_en = p4dir; - - -// P4SEL Register -//---------------- -reg [7:0] p4sel; - -wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL/2] : reg_lo_wr[P4SEL/2]; -wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p4sel <= 8'h00; - else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK; - -assign p4_sel = p4sel; - - -// P5IN Register -//--------------- -reg [7:0] p5in; - -always @ (posedge mclk or posedge puc) - if (puc) p5in <= 8'h00; - else p5in <= p5_din & P5_EN_MSK; - - -// P5OUT Register -//---------------- -reg [7:0] p5out; - -wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT/2] : reg_lo_wr[P5OUT/2]; -wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p5out <= 8'h00; - else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK; - -assign p5_dout = p5out; - - -// P5DIR Register -//---------------- -reg [7:0] p5dir; - -wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR/2] : reg_lo_wr[P5DIR/2]; -wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p5dir <= 8'h00; - else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK; - -assign p5_dout_en = p5dir; - - -// P5SEL Register -//---------------- -reg [7:0] p5sel; - -wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL/2] : reg_lo_wr[P5SEL/2]; -wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p5sel <= 8'h00; - else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK; - -assign p5_sel = p5sel; - - -// P6IN Register -//--------------- -reg [7:0] p6in; - -always @ (posedge mclk or posedge puc) - if (puc) p6in <= 8'h00; - else p6in <= p6_din & P6_EN_MSK; - - -// P6OUT Register -//---------------- -reg [7:0] p6out; - -wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT/2] : reg_lo_wr[P6OUT/2]; -wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p6out <= 8'h00; - else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK; - -assign p6_dout = p6out; - - -// P6DIR Register -//---------------- -reg [7:0] p6dir; - -wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR/2] : reg_lo_wr[P6DIR/2]; -wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p6dir <= 8'h00; - else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK; - -assign p6_dout_en = p6dir; - - -// P6SEL Register -//---------------- -reg [7:0] p6sel; - -wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL/2] : reg_lo_wr[P6SEL/2]; -wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) p6sel <= 8'h00; - else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK; - -assign p6_sel = p6sel; - - - -//============================================================================ -// 4) INTERRUPT GENERATION -//============================================================================ - -// Port 1 interrupt -//------------------ - -// Delay input -reg [7:0] p1in_dly; -always @ (posedge mclk or posedge puc) - if (puc) p1in_dly <= 8'h00; - else p1in_dly <= p1in & P1_EN_MSK; - -// Edge detection -wire [7:0] p1in_re = p1in & ~p1in_dly; -wire [7:0] p1in_fe = ~p1in & p1in_dly; - -// Set interrupt flag -assign p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7], - p1ies[6] ? p1in_fe[6] : p1in_re[6], - p1ies[5] ? p1in_fe[5] : p1in_re[5], - p1ies[4] ? p1in_fe[4] : p1in_re[4], - p1ies[3] ? p1in_fe[3] : p1in_re[3], - p1ies[2] ? p1in_fe[2] : p1in_re[2], - p1ies[1] ? p1in_fe[1] : p1in_re[1], - p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK; - -// Generate CPU interrupt -assign irq_port1 = |(p1ie & p1ifg) & P1_EN[0]; - - -// Port 1 interrupt -//------------------ - -// Delay input -reg [7:0] p2in_dly; -always @ (posedge mclk or posedge puc) - if (puc) p2in_dly <= 8'h00; - else p2in_dly <= p2in & P2_EN_MSK; - -// Edge detection -wire [7:0] p2in_re = p2in & ~p2in_dly; -wire [7:0] p2in_fe = ~p2in & p2in_dly; - -// Set interrupt flag -assign p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7], - p2ies[6] ? p2in_fe[6] : p2in_re[6], - p2ies[5] ? p2in_fe[5] : p2in_re[5], - p2ies[4] ? p2in_fe[4] : p2in_re[4], - p2ies[3] ? p2in_fe[3] : p2in_re[3], - p2ies[2] ? p2in_fe[2] : p2in_re[2], - p2ies[1] ? p2in_fe[1] : p2in_re[1], - p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK; - -// Generate CPU interrupt -assign irq_port2 = |(p2ie & p2ifg) & P2_EN[0]; - - -//============================================================================ -// 5) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] p1in_rd = (p1in & {8{reg_rd[P1IN/2]}}) << (8 & {4{P1IN[0]}}); -wire [15:0] p1out_rd = (p1out & {8{reg_rd[P1OUT/2]}}) << (8 & {4{P1OUT[0]}}); -wire [15:0] p1dir_rd = (p1dir & {8{reg_rd[P1DIR/2]}}) << (8 & {4{P1DIR[0]}}); -wire [15:0] p1ifg_rd = (p1ifg & {8{reg_rd[P1IFG/2]}}) << (8 & {4{P1IFG[0]}}); -wire [15:0] p1ies_rd = (p1ies & {8{reg_rd[P1IES/2]}}) << (8 & {4{P1IES[0]}}); -wire [15:0] p1ie_rd = (p1ie & {8{reg_rd[P1IE/2]}}) << (8 & {4{P1IE[0]}}); -wire [15:0] p1sel_rd = (p1sel & {8{reg_rd[P1SEL/2]}}) << (8 & {4{P1SEL[0]}}); -wire [15:0] p2in_rd = (p2in & {8{reg_rd[P2IN/2]}}) << (8 & {4{P2IN[0]}}); -wire [15:0] p2out_rd = (p2out & {8{reg_rd[P2OUT/2]}}) << (8 & {4{P2OUT[0]}}); -wire [15:0] p2dir_rd = (p2dir & {8{reg_rd[P2DIR/2]}}) << (8 & {4{P2DIR[0]}}); -wire [15:0] p2ifg_rd = (p2ifg & {8{reg_rd[P2IFG/2]}}) << (8 & {4{P2IFG[0]}}); -wire [15:0] p2ies_rd = (p2ies & {8{reg_rd[P2IES/2]}}) << (8 & {4{P2IES[0]}}); -wire [15:0] p2ie_rd = (p2ie & {8{reg_rd[P2IE/2]}}) << (8 & {4{P2IE[0]}}); -wire [15:0] p2sel_rd = (p2sel & {8{reg_rd[P2SEL/2]}}) << (8 & {4{P2SEL[0]}}); -wire [15:0] p3in_rd = (p3in & {8{reg_rd[P3IN/2]}}) << (8 & {4{P3IN[0]}}); -wire [15:0] p3out_rd = (p3out & {8{reg_rd[P3OUT/2]}}) << (8 & {4{P3OUT[0]}}); -wire [15:0] p3dir_rd = (p3dir & {8{reg_rd[P3DIR/2]}}) << (8 & {4{P3DIR[0]}}); -wire [15:0] p3sel_rd = (p3sel & {8{reg_rd[P3SEL/2]}}) << (8 & {4{P3SEL[0]}}); -wire [15:0] p4in_rd = (p4in & {8{reg_rd[P4IN/2]}}) << (8 & {4{P4IN[0]}}); -wire [15:0] p4out_rd = (p4out & {8{reg_rd[P4OUT/2]}}) << (8 & {4{P4OUT[0]}}); -wire [15:0] p4dir_rd = (p4dir & {8{reg_rd[P4DIR/2]}}) << (8 & {4{P4DIR[0]}}); -wire [15:0] p4sel_rd = (p4sel & {8{reg_rd[P4SEL/2]}}) << (8 & {4{P4SEL[0]}}); -wire [15:0] p5in_rd = (p5in & {8{reg_rd[P5IN/2]}}) << (8 & {4{P5IN[0]}}); -wire [15:0] p5out_rd = (p5out & {8{reg_rd[P5OUT/2]}}) << (8 & {4{P5OUT[0]}}); -wire [15:0] p5dir_rd = (p5dir & {8{reg_rd[P5DIR/2]}}) << (8 & {4{P5DIR[0]}}); -wire [15:0] p5sel_rd = (p5sel & {8{reg_rd[P5SEL/2]}}) << (8 & {4{P5SEL[0]}}); -wire [15:0] p6in_rd = (p6in & {8{reg_rd[P6IN/2]}}) << (8 & {4{P6IN[0]}}); -wire [15:0] p6out_rd = (p6out & {8{reg_rd[P6OUT/2]}}) << (8 & {4{P6OUT[0]}}); -wire [15:0] p6dir_rd = (p6dir & {8{reg_rd[P6DIR/2]}}) << (8 & {4{P6DIR[0]}}); -wire [15:0] p6sel_rd = (p6sel & {8{reg_rd[P6SEL/2]}}) << (8 & {4{P6SEL[0]}}); - -wire [15:0] per_dout = p1in_rd | - p1out_rd | - p1dir_rd | - p1ifg_rd | - p1ies_rd | - p1ie_rd | - p1sel_rd | - p2in_rd | - p2out_rd | - p2dir_rd | - p2ifg_rd | - p2ies_rd | - p2ie_rd | - p2sel_rd | - p3in_rd | - p3out_rd | - p3dir_rd | - p3sel_rd | - p4in_rd | - p4out_rd | - p4dir_rd | - p4sel_rd | - p5in_rd | - p5out_rd | - p5dir_rd | - p5sel_rd | - p6in_rd | - p6out_rd | - p6dir_rd | - p6sel_rd; - -endmodule // gpio - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/gpio.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/timerA.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/timerA.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/timerA.v (nonexistent) @@ -1,694 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: timerA.v -// -// *Module Description: -// Timer A top-level -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module timerA ( - -// OUTPUTs - irq_ta0, // Timer A interrupt: TACCR0 - irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2 - per_dout, // Peripheral data output - ta_out0, // Timer A output 0 - ta_out0_en, // Timer A output 0 enable - ta_out1, // Timer A output 1 - ta_out1_en, // Timer A output 1 enable - ta_out2, // Timer A output 2 - ta_out2_en, // Timer A output 2 enable - -// INPUTs - aclk_en, // ACLK enable (from CPU) - dbg_freeze, // Freeze Timer A counter - inclk, // INCLK external timer clock (SLOW) - irq_ta0_acc, // Interrupt request TACCR0 accepted - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc, // Main system reset - smclk_en, // SMCLK enable (from CPU) - ta_cci0a, // Timer A capture 0 input A - ta_cci0b, // Timer A capture 0 input B - ta_cci1a, // Timer A capture 1 input A - ta_cci1b, // Timer A capture 1 input B - ta_cci2a, // Timer A capture 2 input A - ta_cci2b, // Timer A capture 2 input B - taclk // TACLK external timer clock (SLOW) -); - -// OUTPUTs -//========= -output irq_ta0; // Timer A interrupt: TACCR0 -output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2 -output [15:0] per_dout; // Peripheral data output -output ta_out0; // Timer A output 0 -output ta_out0_en; // Timer A output 0 enable -output ta_out1; // Timer A output 1 -output ta_out1_en; // Timer A output 1 enable -output ta_out2; // Timer A output 2 -output ta_out2_en; // Timer A output 2 enable - -// INPUTs -//========= -input aclk_en; // ACLK enable (from CPU) -input dbg_freeze; // Freeze Timer A counter -input inclk; // INCLK external timer clock (SLOW) -input irq_ta0_acc; // Interrupt request TACCR0 accepted -input mclk; // Main system clock -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset -input smclk_en; // SMCLK enable (from CPU) -input ta_cci0a; // Timer A capture 0 input A -input ta_cci0b; // Timer A capture 0 input B -input ta_cci1a; // Timer A capture 1 input A -input ta_cci1b; // Timer A capture 1 input B -input ta_cci2a; // Timer A capture 2 input A -input ta_cci2b; // Timer A capture 2 input B -input taclk; // TACLK external timer clock (SLOW) - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter TACTL = 9'h160; -parameter TAR = 9'h170; -parameter TACCTL0 = 9'h162; -parameter TACCR0 = 9'h172; -parameter TACCTL1 = 9'h164; -parameter TACCR1 = 9'h174; -parameter TACCTL2 = 9'h166; -parameter TACCR2 = 9'h176; -parameter TAIV = 9'h12E; - - -// Register one-hot decoder -parameter TACTL_D = (512'h1 << TACTL); -parameter TAR_D = (512'h1 << TAR); -parameter TACCTL0_D = (512'h1 << TACCTL0); -parameter TACCR0_D = (512'h1 << TACCR0); -parameter TACCTL1_D = (512'h1 << TACCTL1); -parameter TACCR1_D = (512'h1 << TACCR1); -parameter TACCTL2_D = (512'h1 << TACCTL2); -parameter TACCR2_D = (512'h1 << TACCR2); -parameter TAIV_D = (512'h1 << TAIV); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [511:0] reg_dec; -always @(per_addr) - case ({per_addr,1'b0}) - TACTL : reg_dec = TACTL_D; - TAR : reg_dec = TAR_D; - TACCTL0: reg_dec = TACCTL0_D; - TACCR0 : reg_dec = TACCR0_D; - TACCTL1: reg_dec = TACCTL1_D; - TACCR1 : reg_dec = TACCR1_D; - TACCTL2: reg_dec = TACCTL2_D; - TACCR2 : reg_dec = TACCR2_D; - TAIV : reg_dec = TAIV_D; - default: reg_dec = {512{1'b0}}; - endcase - -// Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [511:0] reg_wr = reg_dec & {512{reg_write}}; -wire [511:0] reg_rd = reg_dec & {512{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// TACTL Register -//----------------- -reg [9:0] tactl; - -wire tactl_wr = reg_wr[TACTL]; -wire taclr = tactl_wr & per_din[`TACLR]; -wire taifg_set; -wire taifg_clr; - -always @ (posedge mclk or posedge puc) - if (puc) tactl <= 10'h000; - else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; - else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; - - -// TAR Register -//----------------- -reg [15:0] tar; - -wire tar_wr = reg_wr[TAR]; - -wire tar_clk; -wire tar_clr; -wire tar_inc; -wire tar_dec; -wire [15:0] tar_add = tar_inc ? 16'h0001 : - tar_dec ? 16'hffff : 16'h0000; -wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add); - -always @ (posedge mclk or posedge puc) - if (puc) tar <= 16'h0000; - else if (tar_wr) tar <= per_din; - else if (taclr) tar <= 16'h0000; - else if (tar_clk & ~dbg_freeze) tar <= tar_nxt; - - -// TACCTL0 Register -//------------------ -reg [15:0] tacctl0; - -wire tacctl0_wr = reg_wr[TACCTL0]; -wire ccifg0_set; -wire cov0_set; - -always @ (posedge mclk or posedge puc) - if (puc) tacctl0 <= 16'h0000; - else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; - else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; - -wire cci0; -reg scci0; -wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0}; - - -// TACCR0 Register -//------------------ -reg [15:0] taccr0; - -wire taccr0_wr = reg_wr[TACCR0]; -wire cci0_cap; - -always @ (posedge mclk or posedge puc) - if (puc) taccr0 <= 16'h0000; - else if (taccr0_wr) taccr0 <= per_din; - else if (cci0_cap) taccr0 <= tar; - - -// TACCTL1 Register -//------------------ -reg [15:0] tacctl1; - -wire tacctl1_wr = reg_wr[TACCTL1]; -wire ccifg1_set; -wire ccifg1_clr; -wire cov1_set; - -always @ (posedge mclk or posedge puc) - if (puc) tacctl1 <= 16'h0000; - else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; - else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; - -wire cci1; -reg scci1; -wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0}; - - -// TACCR1 Register -//------------------ -reg [15:0] taccr1; - -wire taccr1_wr = reg_wr[TACCR1]; -wire cci1_cap; - -always @ (posedge mclk or posedge puc) - if (puc) taccr1 <= 16'h0000; - else if (taccr1_wr) taccr1 <= per_din; - else if (cci1_cap) taccr1 <= tar; - - -// TACCTL2 Register -//------------------ -reg [15:0] tacctl2; - -wire tacctl2_wr = reg_wr[TACCTL2]; -wire ccifg2_set; -wire ccifg2_clr; -wire cov2_set; - -always @ (posedge mclk or posedge puc) - if (puc) tacctl2 <= 16'h0000; - else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; - else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; - -wire cci2; -reg scci2; -wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0}; - - -// TACCR2 Register -//------------------ -reg [15:0] taccr2; - -wire taccr2_wr = reg_wr[TACCR2]; -wire cci2_cap; - -always @ (posedge mclk or posedge puc) - if (puc) taccr2 <= 16'h0000; - else if (taccr2_wr) taccr2 <= per_din; - else if (cci2_cap) taccr2 <= tar; - - -// TAIV Register -//------------------ - -wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 : - (tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 : - (tactl[`TAIFG] & tactl[`TAIE]) ? 4'hA : - 4'h0; - -assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2); -assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4); -assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA); - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] tactl_rd = {6'h00, tactl} & {16{reg_rd[TACTL]}}; -wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}}; -wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}}; -wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}}; -wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}}; -wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}}; -wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}}; -wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}}; -wire [15:0] taiv_rd = {12'h000, taiv} & {16{reg_rd[TAIV]}}; - -wire [15:0] per_dout = tactl_rd | - tar_rd | - tacctl0_rd | - taccr0_rd | - tacctl1_rd | - taccr1_rd | - tacctl2_rd | - taccr2_rd | - taiv_rd; - - -//============================================================================ -// 5) Timer A counter control -//============================================================================ - -// Clock input synchronization (TACLK & INCLK) -//----------------------------------------------------------- -reg [2:0] taclk_s; - -always @ (posedge mclk or posedge puc) - if (puc) taclk_s <= 3'b000; - else taclk_s <= {taclk_s[1:0], taclk}; - -wire taclk_en = taclk_s[1] & ~taclk_s[2]; - - -reg [2:0] inclk_s; - -always @ (posedge mclk or posedge puc) - if (puc) inclk_s <= 3'b000; - else inclk_s <= {inclk_s[1:0], inclk}; - -wire inclk_en = inclk_s[1] & ~inclk_s[2]; - - -// Timer clock input mux -//----------------------------------------------------------- - -wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en : - (tactl[`TASSELx]==2'b01) ? aclk_en : - (tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en; - - -// Generate update pluse for the counter (<=> divided clock) -//----------------------------------------------------------- -reg [2:0] clk_div; - -assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 : - (tactl[`TAIDx]==2'b01) ? clk_div[0] : - (tactl[`TAIDx]==2'b10) ? &clk_div[1:0] : - &clk_div[2:0]); - -always @ (posedge mclk or posedge puc) - if (puc) clk_div <= 3'h0; - else if (tar_clk | taclr) clk_div <= 3'h0; - else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1; - - -// Time counter control signals -//----------------------------------------------------------- - -assign tar_clr = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0)) | - ((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000)); - -assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) | - ((tactl[`TAMCx]==2'b11) & ~tar_dec); - -reg tar_dir; -always @ (posedge mclk or posedge puc) - if (puc) tar_dir <= 1'b0; - else if (taclr) tar_dir <= 1'b0; - else if (tactl[`TAMCx]==2'b11) - begin - if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0; - else if (tar>=taccr0) tar_dir <= 1'b1; - end - else tar_dir <= 1'b0; - -assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0)); - - -//============================================================================ -// 6) Timer A comparator -//============================================================================ - -wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0); -wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1); -wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2); - - -//============================================================================ -// 7) Timer A capture logic -//============================================================================ - -// Input selection -//------------------ -assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a : - (tacctl0[`TACCISx]==2'b01) ? ta_cci0b : - (tacctl0[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a : - (tacctl1[`TACCISx]==2'b01) ? ta_cci1b : - (tacctl1[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a : - (tacctl2[`TACCISx]==2'b01) ? ta_cci2b : - (tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1; - -// Register CCIx for synchronization and edge detection -reg [2:0] cci_s; -always @ (posedge mclk or posedge puc) - if (puc) cci_s <= 3'h0; - else cci_s <= {cci2, cci1, cci0}; -reg [2:0] cci_ss; -always @ (posedge mclk or posedge puc) - if (puc) cci_ss <= 3'h0; - else cci_ss <= cci_s; -reg [2:0] cci_sss; -always @ (posedge mclk or posedge puc) - if (puc) cci_sss <= 3'h0; - else cci_sss <= cci_ss; - - -// Generate SCCIx -//------------------ - -always @ (posedge mclk or posedge puc) - if (puc) scci0 <= 1'b0; - else if (tar_clk & equ0) scci0 <= cci_ss[0]; - -always @ (posedge mclk or posedge puc) - if (puc) scci1 <= 1'b0; - else if (tar_clk & equ1) scci1 <= cci_ss[1]; - -always @ (posedge mclk or posedge puc) - if (puc) scci2 <= 1'b0; - else if (tar_clk & equ2) scci2 <= cci_ss[2]; - - -// Capture mode -//------------------ -wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 : - (tacctl0[`TACMx]==2'b01) ? ( cci_ss[0] & ~cci_sss[0]) : // Rising edge - (tacctl0[`TACMx]==2'b10) ? (~cci_ss[0] & cci_sss[0]) : // Falling edge - ( cci_ss[0] ^ cci_sss[0]); // Both edges - -wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 : - (tacctl1[`TACMx]==2'b01) ? ( cci_ss[1] & ~cci_sss[1]) : // Rising edge - (tacctl1[`TACMx]==2'b10) ? (~cci_ss[1] & cci_sss[1]) : // Falling edge - ( cci_ss[1] ^ cci_sss[1]); // Both edges - -wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 : - (tacctl2[`TACMx]==2'b01) ? ( cci_ss[2] & ~cci_sss[2]) : // Rising edge - (tacctl2[`TACMx]==2'b10) ? (~cci_ss[2] & cci_sss[2]) : // Falling edge - ( cci_ss[2] ^ cci_sss[2]); // Both edges - -// Event Synchronization -//----------------------- - -reg cci0_evt_s; -always @ (posedge mclk or posedge puc) - if (puc) cci0_evt_s <= 1'b0; - else if (tar_clk) cci0_evt_s <= 1'b0; - else if (cci0_evt) cci0_evt_s <= 1'b1; - -reg cci1_evt_s; -always @ (posedge mclk or posedge puc) - if (puc) cci1_evt_s <= 1'b0; - else if (tar_clk) cci1_evt_s <= 1'b0; - else if (cci1_evt) cci1_evt_s <= 1'b1; - -reg cci2_evt_s; -always @ (posedge mclk or posedge puc) - if (puc) cci2_evt_s <= 1'b0; - else if (tar_clk) cci2_evt_s <= 1'b0; - else if (cci2_evt) cci2_evt_s <= 1'b1; - -reg cci0_sync; -always @ (posedge mclk or posedge puc) - if (puc) cci0_sync <= 1'b0; - else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s); - -reg cci1_sync; -always @ (posedge mclk or posedge puc) - if (puc) cci1_sync <= 1'b0; - else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s); - -reg cci2_sync; -always @ (posedge mclk or posedge puc) - if (puc) cci2_sync <= 1'b0; - else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s); - - -// Generate final capture command -//----------------------------------- - -assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt; -assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt; -assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt; - - -// Generate capture overflow flag -//----------------------------------- - -reg cap0_taken; -wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc) - if (puc) cap0_taken <= 1'b0; - else if (cci0_cap) cap0_taken <= 1'b1; - else if (cap0_taken_clr) cap0_taken <= 1'b0; - -reg cap1_taken; -wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc) - if (puc) cap1_taken <= 1'b0; - else if (cci1_cap) cap1_taken <= 1'b1; - else if (cap1_taken_clr) cap1_taken <= 1'b0; - -reg cap2_taken; -wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]); -always @ (posedge mclk or posedge puc) - if (puc) cap2_taken <= 1'b0; - else if (cci2_cap) cap2_taken <= 1'b1; - else if (cap2_taken_clr) cap2_taken <= 1'b0; - - -assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0]; -assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1]; -assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2]; - - -//============================================================================ -// 8) Timer A output unit -//============================================================================ - -// Output unit 0 -//------------------- -reg ta_out0; - -wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output -wire ta_out0_mode1 = equ0 ? 1'b1 : ta_out0; // Set -wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset - equ0 ? 1'b0 : ta_out0; -wire ta_out0_mode3 = equ0 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out0; -wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle -wire ta_out0_mode5 = equ0 ? 1'b0 : ta_out0; // Reset -wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set - equ0 ? 1'b1 : ta_out0; -wire ta_out0_mode7 = equ0 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out0; - -wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 : - (tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 : - (tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 : - (tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 : - (tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 : - (tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 : - (tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 : - ta_out0_mode7; - -always @ (posedge mclk or posedge puc) - if (puc) ta_out0 <= 1'b0; - else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0; - else if (tar_clk) ta_out0 <= ta_out0_nxt; - -assign ta_out0_en = ~tacctl0[`TACAP]; - - -// Output unit 1 -//------------------- -reg ta_out1; - -wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output -wire ta_out1_mode1 = equ1 ? 1'b1 : ta_out1; // Set -wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset - equ0 ? 1'b0 : ta_out1; -wire ta_out1_mode3 = equ1 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out1; -wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle -wire ta_out1_mode5 = equ1 ? 1'b0 : ta_out1; // Reset -wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set - equ0 ? 1'b1 : ta_out1; -wire ta_out1_mode7 = equ1 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out1; - -wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 : - (tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 : - (tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 : - (tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 : - (tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 : - (tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 : - (tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 : - ta_out1_mode7; - -always @ (posedge mclk or posedge puc) - if (puc) ta_out1 <= 1'b0; - else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0; - else if (tar_clk) ta_out1 <= ta_out1_nxt; - -assign ta_out1_en = ~tacctl1[`TACAP]; - - -// Output unit 2 -//------------------- -reg ta_out2; - -wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output -wire ta_out2_mode1 = equ2 ? 1'b1 : ta_out2; // Set -wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset - equ0 ? 1'b0 : ta_out2; -wire ta_out2_mode3 = equ2 ? 1'b1 : // Set/Reset - equ0 ? 1'b0 : ta_out2; -wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle -wire ta_out2_mode5 = equ2 ? 1'b0 : ta_out2; // Reset -wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set - equ0 ? 1'b1 : ta_out2; -wire ta_out2_mode7 = equ2 ? 1'b0 : // Reset/Set - equ0 ? 1'b1 : ta_out2; - -wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 : - (tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 : - (tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 : - (tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 : - (tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 : - (tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 : - (tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 : - ta_out2_mode7; - -always @ (posedge mclk or posedge puc) - if (puc) ta_out2 <= 1'b0; - else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0; - else if (tar_clk) ta_out2 <= ta_out2_nxt; - -assign ta_out2_en = ~tacctl2[`TACAP]; - - -//============================================================================ -// 9) Timer A interrupt generation -//============================================================================ - - -assign taifg_set = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0)) | - ((tactl[`TAMCx]==2'b10) & (tar==16'hffff)) | - ((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec)); - -assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ0)); -assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ1)); -assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ2)); - - -wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]); - -wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) | - (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) | - (tacctl2[`TACCIFG] & tacctl2[`TACCIE]); - - -endmodule // timerA - - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/periph/timerA.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/register_file.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/register_file.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/register_file.v (nonexistent) @@ -1,347 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: register_file.v -// -// *Module Description: -// openMSP430 Register files -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module register_file ( - -// OUTPUTs - cpuoff, // Turns off the CPU - gie, // General interrupt enable - oscoff, // Turns off LFXT1 clock input - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - reg_dest, // Selected register destination content - reg_src, // Selected register source content - scg1, // System clock generator 1. Turns off the SMCLK - status, // R2 Status {V,N,Z,C} - -// INPUTs - alu_stat, // ALU Status {V,N,Z,C} - alu_stat_wr, // ALU Status write {V,N,Z,C} - inst_bw, // Decoded Inst: byte width - inst_dest, // Register destination selection - inst_src, // Register source selection - mclk, // Main system clock - pc, // Program counter - puc, // Main system reset - reg_dest_val, // Selected register destination value - reg_dest_wr, // Write selected register destination - reg_pc_call, // Trigger PC update for a CALL instruction - reg_sp_val, // Stack Pointer next value - reg_sp_wr, // Stack Pointer write - reg_sr_wr, // Status register update for RETI instruction - reg_sr_clr, // Status register clear for interrupts - reg_incr // Increment source register -); - -// OUTPUTs -//========= -output cpuoff; // Turns off the CPU -output gie; // General interrupt enable -output oscoff; // Turns off LFXT1 clock input -output [15:0] pc_sw; // Program counter software value -output pc_sw_wr; // Program counter software write -output [15:0] reg_dest; // Selected register destination content -output [15:0] reg_src; // Selected register source content -output scg1; // System clock generator 1. Turns off the SMCLK -output [3:0] status; // R2 Status {V,N,Z,C} - -// INPUTs -//========= -input [3:0] alu_stat; // ALU Status {V,N,Z,C} -input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} -input inst_bw; // Decoded Inst: byte width -input [15:0] inst_dest; // Register destination selection -input [15:0] inst_src; // Register source selection -input mclk; // Main system clock -input [15:0] pc; // Program counter -input puc; // Main system reset -input [15:0] reg_dest_val; // Selected register destination value -input reg_dest_wr; // Write selected register destination -input reg_pc_call; // Trigger PC update for a CALL instruction -input [15:0] reg_sp_val; // Stack Pointer next value -input reg_sp_wr; // Stack Pointer write -input reg_sr_wr; // Status register update for RETI instruction -input reg_sr_clr; // Status register clear for interrupts -input reg_incr; // Increment source register - - -//============================================================================= -// 1) AUTOINCREMENT UNIT -//============================================================================= - -wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002; -wire [15:0] reg_incr_val = reg_src+incr_op; - -wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val; - - -//============================================================================= -// 2) SPECIAL REGISTERS (R1/R2/R3) -//============================================================================= - -// Source input selection mask (for interrupt support) -//----------------------------------------------------- - -wire [15:0] inst_src_in = reg_sr_clr ? 16'h0004 : inst_src; - - -// R0: Program counter -//--------------------- - -wire [15:0] r0 = pc; - -wire [15:0] pc_sw = reg_dest_val_in; -wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call; - - -// R1: Stack pointer -//------------------- -reg [15:0] r1; -wire r1_wr = inst_dest[1] & reg_dest_wr; -wire r1_inc = inst_src_in[1] & reg_incr; - -always @(posedge mclk or posedge puc) - if (puc) r1 <= 16'h0000; - else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe; - else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe; - else if (r1_inc) r1 <= reg_incr_val & 16'hfffe; - - -// R2: Status register -//--------------------- -reg [15:0] r2; -wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr; - -wire r2_c = alu_stat_wr[0] ? alu_stat[0] : - r2_wr ? reg_dest_val_in[0] : r2[0]; // C - -wire r2_z = alu_stat_wr[1] ? alu_stat[1] : - r2_wr ? reg_dest_val_in[1] : r2[1]; // Z - -wire r2_n = alu_stat_wr[2] ? alu_stat[2] : - r2_wr ? reg_dest_val_in[2] : r2[2]; // N - -wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3]; - -wire r2_v = alu_stat_wr[3] ? alu_stat[3] : - r2_wr ? reg_dest_val_in[8] : r2[8]; // V - - -always @(posedge mclk or posedge puc) - if (puc) r2 <= 16'h0000; - else if (reg_sr_clr) r2 <= 16'h0000; - else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c}; - -assign status = {r2[8], r2[2:0]}; -assign gie = r2[3]; -assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr); -assign oscoff = r2[5]; -assign scg1 = r2[7]; - - -// R3: Constant generator -//------------------------ -reg [15:0] r3; -wire r3_wr = inst_dest[3] & reg_dest_wr; -wire r3_inc = inst_src_in[3] & reg_incr; - -always @(posedge mclk or posedge puc) - if (puc) r3 <= 16'h0000; - else if (r3_wr) r3 <= reg_dest_val_in; - else if (r3_inc) r3 <= reg_incr_val; - - -//============================================================================= -// 4) GENERAL PURPOSE REGISTERS (R4...R15) -//============================================================================= - -// R4 -reg [15:0] r4; -wire r4_wr = inst_dest[4] & reg_dest_wr; -wire r4_inc = inst_src_in[4] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r4 <= 16'h0000; - else if (r4_wr) r4 <= reg_dest_val_in; - else if (r4_inc) r4 <= reg_incr_val; - -// R5 -reg [15:0] r5; -wire r5_wr = inst_dest[5] & reg_dest_wr; -wire r5_inc = inst_src_in[5] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r5 <= 16'h0000; - else if (r5_wr) r5 <= reg_dest_val_in; - else if (r5_inc) r5 <= reg_incr_val; - -// R6 -reg [15:0] r6; -wire r6_wr = inst_dest[6] & reg_dest_wr; -wire r6_inc = inst_src_in[6] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r6 <= 16'h0000; - else if (r6_wr) r6 <= reg_dest_val_in; - else if (r6_inc) r6 <= reg_incr_val; - -// R7 -reg [15:0] r7; -wire r7_wr = inst_dest[7] & reg_dest_wr; -wire r7_inc = inst_src_in[7] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r7 <= 16'h0000; - else if (r7_wr) r7 <= reg_dest_val_in; - else if (r7_inc) r7 <= reg_incr_val; - -// R8 -reg [15:0] r8; -wire r8_wr = inst_dest[8] & reg_dest_wr; -wire r8_inc = inst_src_in[8] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r8 <= 16'h0000; - else if (r8_wr) r8 <= reg_dest_val_in; - else if (r8_inc) r8 <= reg_incr_val; - -// R9 -reg [15:0] r9; -wire r9_wr = inst_dest[9] & reg_dest_wr; -wire r9_inc = inst_src_in[9] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r9 <= 16'h0000; - else if (r9_wr) r9 <= reg_dest_val_in; - else if (r9_inc) r9 <= reg_incr_val; - -// R10 -reg [15:0] r10; -wire r10_wr = inst_dest[10] & reg_dest_wr; -wire r10_inc = inst_src_in[10] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r10 <= 16'h0000; - else if (r10_wr) r10 <= reg_dest_val_in; - else if (r10_inc) r10 <= reg_incr_val; - -// R11 -reg [15:0] r11; -wire r11_wr = inst_dest[11] & reg_dest_wr; -wire r11_inc = inst_src_in[11] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r11 <= 16'h0000; - else if (r11_wr) r11 <= reg_dest_val_in; - else if (r11_inc) r11 <= reg_incr_val; - -// R12 -reg [15:0] r12; -wire r12_wr = inst_dest[12] & reg_dest_wr; -wire r12_inc = inst_src_in[12] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r12 <= 16'h0000; - else if (r12_wr) r12 <= reg_dest_val_in; - else if (r12_inc) r12 <= reg_incr_val; - -// R13 -reg [15:0] r13; -wire r13_wr = inst_dest[13] & reg_dest_wr; -wire r13_inc = inst_src_in[13] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r13 <= 16'h0000; - else if (r13_wr) r13 <= reg_dest_val_in; - else if (r13_inc) r13 <= reg_incr_val; - -// R14 -reg [15:0] r14; -wire r14_wr = inst_dest[14] & reg_dest_wr; -wire r14_inc = inst_src_in[14] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r14 <= 16'h0000; - else if (r14_wr) r14 <= reg_dest_val_in; - else if (r14_inc) r14 <= reg_incr_val; - -// R15 -reg [15:0] r15; -wire r15_wr = inst_dest[15] & reg_dest_wr; -wire r15_inc = inst_src_in[15] & reg_incr; -always @(posedge mclk or posedge puc) - if (puc) r15 <= 16'h0000; - else if (r15_wr) r15 <= reg_dest_val_in; - else if (r15_inc) r15 <= reg_incr_val; - - -//============================================================================= -// 5) READ MUX -//============================================================================= - -assign reg_src = (r0 & {16{inst_src_in[0]}}) | - (r1 & {16{inst_src_in[1]}}) | - (r2 & {16{inst_src_in[2]}}) | - (r3 & {16{inst_src_in[3]}}) | - (r4 & {16{inst_src_in[4]}}) | - (r5 & {16{inst_src_in[5]}}) | - (r6 & {16{inst_src_in[6]}}) | - (r7 & {16{inst_src_in[7]}}) | - (r8 & {16{inst_src_in[8]}}) | - (r9 & {16{inst_src_in[9]}}) | - (r10 & {16{inst_src_in[10]}}) | - (r11 & {16{inst_src_in[11]}}) | - (r12 & {16{inst_src_in[12]}}) | - (r13 & {16{inst_src_in[13]}}) | - (r14 & {16{inst_src_in[14]}}) | - (r15 & {16{inst_src_in[15]}}); - -assign reg_dest = (r0 & {16{inst_dest[0]}}) | - (r1 & {16{inst_dest[1]}}) | - (r2 & {16{inst_dest[2]}}) | - (r3 & {16{inst_dest[3]}}) | - (r4 & {16{inst_dest[4]}}) | - (r5 & {16{inst_dest[5]}}) | - (r6 & {16{inst_dest[6]}}) | - (r7 & {16{inst_dest[7]}}) | - (r8 & {16{inst_dest[8]}}) | - (r9 & {16{inst_dest[9]}}) | - (r10 & {16{inst_dest[10]}}) | - (r11 & {16{inst_dest[11]}}) | - (r12 & {16{inst_dest[12]}}) | - (r13 & {16{inst_dest[13]}}) | - (r14 & {16{inst_dest[14]}}) | - (r15 & {16{inst_dest[15]}}); - - -endmodule // register_file - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/register_file.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v (nonexistent) @@ -1,296 +0,0 @@ -`ifdef OPENMSP430_DEFINES -`else -`define OPENMSP430_DEFINES -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_defines.v -// -// *Module Description: -// openMSP430 Configuration file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- - -//---------------------------------------------------------------------------- -// SYSTEM CONFIGURATION -//---------------------------------------------------------------------------- - -// ROM Size: -// 9 -> 1kB -// 10 -> 2kB -// 11 -> 4kB -// 12 -> 8kB -// 13 -> 16kB -`define ROM_AWIDTH 11 - -// RAM Size: -// 6 -> 128 B -// 7 -> 256 B -// 8 -> 512 B -// 9 -> 1 kB -// 10 -> 2 kB -`define RAM_AWIDTH 9 - -//---------------------------------------------------------------------------- -// REMOTE DEBUGGING INTERFACE CONFIGURATION -//---------------------------------------------------------------------------- - -// Include Debug interface -`define DBG_EN - -// Debug interface selection -// `define DBG_UART -> Enable UART (8N1) debug interface -// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET -// -`define DBG_UART -//`define DBG_JTAG - -// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) -// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 -// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 -// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 -// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 -// -`define DBG_HWBRK_0 -//`define DBG_HWBRK_1 -//`define DBG_HWBRK_2 -//`define DBG_HWBRK_3 - - -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// -//==========================================================================// -//==========================================================================// -//==========================================================================// -//==========================================================================// - -// ROM and RAM sizes -`define ROM_SIZE (2 << `ROM_AWIDTH) -`define RAM_SIZE (2 << `RAM_AWIDTH) - -// RAM Base Adresses -`define RAM_BASE 16'h0200 // RAM base address - -// ROM & RAM most significant address bit (for 16 bit words) -`define ROM_MSB `ROM_AWIDTH-1 -`define RAM_MSB `RAM_AWIDTH-1 - - -// Instructions type -`define INST_SO 0 -`define INST_JMP 1 -`define INST_TO 2 - -// Single-operand arithmetic -`define RRC 0 -`define SWPB 1 -`define RRA 2 -`define SXT 3 -`define PUSH 4 -`define CALL 5 -`define RETI 6 -`define IRQ 7 - -// Conditional jump -`define JNE 0 -`define JEQ 1 -`define JNC 2 -`define JC 3 -`define JN 4 -`define JGE 5 -`define JL 6 -`define JMP 7 - -// Two-operand arithmetic -`define MOV 0 -`define ADD 1 -`define ADDC 2 -`define SUBC 3 -`define SUB 4 -`define CMP 5 -`define DADD 6 -`define BIT 7 -`define BIC 8 -`define BIS 9 -`define XOR 10 -`define AND 11 - -// Addressing modes -`define DIR 0 -`define IDX 1 -`define INDIR 2 -`define INDIR_I 3 -`define SYMB 4 -`define IMM 5 -`define ABS 6 -`define CONST 7 - -// Execution state machine -`define E_IRQ_0 4'h0 -`define E_IRQ_1 4'h1 -`define E_IRQ_2 4'h2 -`define E_IRQ_3 4'h3 -`define E_IRQ_4 4'h4 -`define E_SRC_AD 4'h5 -`define E_SRC_RD 4'h6 -`define E_SRC_WR 4'h7 -`define E_DST_AD 4'h8 -`define E_DST_RD 4'h9 -`define E_DST_WR 4'hA -`define E_EXEC 4'hB -`define E_JUMP 4'hC -`define E_IDLE 4'hD - -// ALU control signals -`define ALU_SRC_INV 0 -`define ALU_INC 1 -`define ALU_INC_C 2 -`define ALU_ADD 3 -`define ALU_AND 4 -`define ALU_OR 5 -`define ALU_XOR 6 -`define ALU_DADD 7 -`define ALU_STAT_7 8 -`define ALU_STAT_F 9 -`define ALU_SHIFT 10 -`define EXEC_NO_WR 11 - -// Debug interface -`define DBG_UART_WR 18 -`define DBG_UART_BW 17 -`define DBG_UART_ADDR 16:11 - -// Debug interface CPU_CTL register -`define HALT 0 -`define RUN 1 -`define ISTEP 2 -`define SW_BRK_EN 3 -`define FRZ_BRK_EN 4 -`define RST_BRK_EN 5 -`define CPU_RST 6 - -// Debug interface CPU_STAT register -`define HALT_RUN 0 -`define PUC_PND 1 -`define SWBRK_PND 3 -`define HWBRK0_PND 4 -`define HWBRK1_PND 5 - -// Debug interface BRKx_CTL register -`define BRK_MODE_RD 0 -`define BRK_MODE_WR 1 -`define BRK_MODE 1:0 -`define BRK_EN 2 -`define BRK_I_EN 3 -`define BRK_RANGE 4 - -// Basic clock module: BCSCTL1 Control Register -`define DIVAx 5:4 - -// Basic clock module: BCSCTL2 Control Register -`define SELS 3 -`define DIVSx 2:1 - -// Timer A: TACTL Control Register -`define TASSELx 9:8 -`define TAIDx 7:6 -`define TAMCx 5:4 -`define TACLR 2 -`define TAIE 1 -`define TAIFG 0 - -// Timer A: TACCTLx Capture/Compare Control Register -`define TACMx 15:14 -`define TACCISx 13:12 -`define TASCS 11 -`define TASCCI 10 -`define TACAP 8 -`define TAOUTMODx 7:5 -`define TACCIE 4 -`define TACCI 3 -`define TAOUT 2 -`define TACOV 1 -`define TACCIFG 0 - -// -// DEBUG INTERFACE EXTRA CONFIGURATION -//====================================== - -// Debug interface: Software breakpoint opcode -`define DBG_SWBRK_OP 16'h4343 - -// Debug interface ID -`define DBG_ID 24'h4D5350 - -// Debug UART interface auto data synchronization -// If the following define is commented out, then -// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly -// defined. -`define DBG_UART_AUTO_SYNC - -// Debug UART interface data rate -// In order to properly setup the UART debug interface, you -// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and -// the chosen BAUD rate from the UART interface. -// -//`define DBG_UART_BAUD 9600 -//`define DBG_UART_BAUD 19200 -//`define DBG_UART_BAUD 38400 -//`define DBG_UART_BAUD 57600 -//`define DBG_UART_BAUD 115200 -//`define DBG_UART_BAUD 230400 -//`define DBG_UART_BAUD 460800 -//`define DBG_UART_BAUD 576000 -//`define DBG_UART_BAUD 921600 -`define DBG_UART_BAUD 2000000 -`define DBG_DCO_FREQ 20000000 -`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) - -// Check configuration -`ifdef DBG_EN - `ifdef DBG_UART - `ifdef DBG_JTAG -CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED - `endif - `else - `ifdef DBG_JTAG -CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET - `else -CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED - `endif - `endif -`endif - - -`endif \ No newline at end of file
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/timescale.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/timescale.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/timescale.v (nonexistent) @@ -1 +0,0 @@ -`timescale 1ns / 100ps
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/timescale.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_uart.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_uart.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_uart.v (nonexistent) @@ -1,273 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: dbg_uart.v -// -// *Module Description: -// Debug UART communication interface (8N1, Half-duplex) -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module dbg_uart ( - -// OUTPUTs - dbg_addr, // Debug register address - dbg_din, // Debug register data input - dbg_rd, // Debug register data read - dbg_uart_txd, // Debug interface: UART TXD - dbg_wr, // Debug register data write - -// INPUTs - dbg_dout, // Debug register data output - dbg_rd_rdy, // Debug register data is ready for read - dbg_uart_rxd, // Debug interface: UART RXD - mclk, // Main system clock - mem_burst, // Burst on going - mem_burst_end, // End TX/RX burst - mem_burst_rd, // Start TX burst - mem_burst_wr, // Start RX burst - mem_bw, // Burst byte width - por // Power on reset -); - -// OUTPUTs -//========= -output [5:0] dbg_addr; // Debug register address -output [15:0] dbg_din; // Debug register data input -output dbg_rd; // Debug register data read -output dbg_uart_txd; // Debug interface: UART TXD -output dbg_wr; // Debug register data write - -// INPUTs -//========= -input [15:0] dbg_dout; // Debug register data output -input dbg_rd_rdy; // Debug register data is ready for read -input dbg_uart_rxd; // Debug interface: UART RXD -input mclk; // Main system clock -input mem_burst; // Burst on going -input mem_burst_end; // End TX/RX burst -input mem_burst_rd; // Start TX burst -input mem_burst_wr; // Start RX burst -input mem_bw; // Burst byte width -input por; // Power on reset - - -//============================================================================= -// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING -//============================================================================= - -// Synchronize RXD input & buffer -//-------------------------------- -reg [3:0] rxd_sync; -always @ (posedge mclk or posedge por) - if (por) rxd_sync <= 4'h0; - else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd}; - -// Majority decision -//------------------------ -reg rxd_maj; - -wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} + - {1'b0, rxd_sync[2]} + - {1'b0, rxd_sync[3]}; -wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10); - -always @ (posedge mclk or posedge por) - if (por) rxd_maj <= 1'b0; - else rxd_maj <= rxd_maj_nxt; - -wire rxd_s = rxd_maj; -wire rxd_fe = rxd_maj & ~rxd_maj_nxt; -wire rxd_re = ~rxd_maj & rxd_maj_nxt; - - -//============================================================================= -// 2) UART STATE MACHINE -//============================================================================= - -// Receive state -//------------------------ -reg [2:0] uart_state; -reg [2:0] uart_state_nxt; - -wire sync_done; -wire xfer_done; -reg [19:0] xfer_buf; - -// State machine definition -parameter RX_SYNC = 3'h0; -parameter RX_CMD = 3'h1; -parameter RX_DATA1 = 3'h2; -parameter RX_DATA2 = 3'h3; -parameter TX_DATA1 = 3'h4; -parameter TX_DATA2 = 3'h5; - -// State transition -always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw) - case (uart_state) - RX_SYNC : uart_state_nxt = RX_CMD; - RX_CMD : uart_state_nxt = mem_burst_wr ? - (mem_bw ? RX_DATA2 : RX_DATA1) : - mem_burst_rd ? - (mem_bw ? TX_DATA2 : TX_DATA1) : - (xfer_buf[`DBG_UART_WR] ? - (xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) : - (xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1)); - RX_DATA1 : uart_state_nxt = RX_DATA2; - RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? - (mem_bw ? RX_DATA2 : RX_DATA1) : - RX_CMD; - TX_DATA1 : uart_state_nxt = TX_DATA2; - TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? - (mem_bw ? TX_DATA2 : TX_DATA1) : - RX_CMD; - default : uart_state_nxt = RX_CMD; - endcase - -// State machine -always @(posedge mclk or posedge por) - if (por) uart_state <= RX_SYNC; - else if (xfer_done | sync_done | - mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt; - -// Utility signals -wire cmd_valid = (uart_state==RX_CMD) & xfer_done; -wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2); - - -//============================================================================= -// 3) UART SYNCHRONIZATION -//============================================================================= -// After POR, the host needs to fist send a synchronization character (0x80) -// If this feature doesn't work properly, it is possible to disable it by -// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file. - -reg sync_busy; -always @ (posedge mclk or posedge por) - if (por) sync_busy <= 1'b0; - else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1; - else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0; - -assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy; - -`ifdef DBG_UART_AUTO_SYNC - -reg [14:0] sync_cnt; -always @ (posedge mclk or posedge por) - if (por) sync_cnt <= 15'h7ff8; - else if (sync_busy) sync_cnt <= sync_cnt+15'h0001; - -wire [11:0] bit_cnt_max = sync_cnt[14:3]; -`else -wire [11:0] bit_cnt_max = `DBG_UART_CNT; -`endif - - -//============================================================================= -// 4) UART RECEIVE / TRANSMIT -//============================================================================= - -// Transfer counter -//------------------------ -reg [3:0] xfer_bit; -reg [11:0] xfer_cnt; - -wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1)); -wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC)); -wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000); -assign xfer_done = (xfer_bit==4'hb); - -always @ (posedge mclk or posedge por) - if (por) xfer_bit <= 4'h0; - else if (txd_start | rxd_start) xfer_bit <= 4'h1; - else if (xfer_done) xfer_bit <= 4'h0; - else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1; - -always @ (posedge mclk or posedge por) - if (por) xfer_cnt <= 12'h000; - else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]}; - else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max; - else xfer_cnt <= xfer_cnt+12'hfff; - - -// Receive/Transmit buffer -//------------------------- -wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]}; - -always @ (posedge mclk or posedge por) - if (por) xfer_buf <= 18'h00000; - else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0}; - else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt; - - -// Generate TXD output -//------------------------ -reg dbg_uart_txd; - -always @ (posedge mclk or posedge por) - if (por) dbg_uart_txd <= 1'b1; - else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0]; - - -//============================================================================= -// 5) INTERFACE TO DEBUG REGISTERS -//============================================================================= - -reg [5:0] dbg_addr; - always @ (posedge mclk or posedge por) - if (por) dbg_addr <= 6'h00; - else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR]; - -reg dbg_bw; -always @ (posedge mclk or posedge por) - if (por) dbg_bw <= 1'b0; - else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW]; - -wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw; - -wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} : - {xfer_buf[18:11], xfer_buf[8:1]}; -wire dbg_wr = (xfer_done & (uart_state==RX_DATA2)); -wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) : - (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd; - - - -endmodule // dbg_uart - - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_uart.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430.v (nonexistent) @@ -1,439 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430.v -// -// *Module Description: -// openMSP430 Top level file -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module openMSP430 ( - -// OUTPUTs - aclk_en, // ACLK enable - dbg_freeze, // Freeze peripherals - dbg_uart_txd, // Debug interface: UART TXD - irq_acc, // Interrupt request accepted (one-hot signal) - mclk, // Main system clock - per_addr, // Peripheral address - per_din, // Peripheral data input - per_wen, // Peripheral write enable (high active) - per_en, // Peripheral enable (high active) - puc, // Main system reset - ram_addr, // RAM address - ram_cen, // RAM chip enable (low active) - ram_din, // RAM data input - ram_wen, // RAM write enable (low active) - rom_addr, // ROM address - rom_cen, // ROM chip enable (low active) - rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE-- - rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF-- - smclk_en, // SMCLK enable - -// INPUTs - dbg_uart_rxd, // Debug interface: UART RXD - dco_clk, // Fast oscillator (fast clock) - irq, // Maskable interrupts - lfxt_clk, // Low frequency oscillator (typ 32kHz) - nmi, // Non-maskable interrupt (asynchronous) - per_dout, // Peripheral data output - ram_dout, // RAM data output - reset_n, // Reset Pin (low active) - rom_dout // ROM data output -); - -// OUTPUTs -//========= -output aclk_en; // ACLK enable -output dbg_freeze; // Freeze peripherals -output dbg_uart_txd; // Debug interface: UART TXD -output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) -output mclk; // Main system clock -output [7:0] per_addr; // Peripheral address -output [15:0] per_din; // Peripheral data input -output [1:0] per_wen; // Peripheral write enable (high active) -output per_en; // Peripheral enable (high active) -output puc; // Main system reset -output [`RAM_MSB:0] ram_addr; // RAM address -output ram_cen; // RAM chip enable (low active) -output [15:0] ram_din; // RAM data input -output [1:0] ram_wen; // RAM write enable (low active) -output [`ROM_MSB:0] rom_addr; // ROM address -output rom_cen; // ROM chip enable (low active) -output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE-- -output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF-- -output smclk_en; // SMCLK enable - - -// INPUTs -//========= -input dbg_uart_rxd; // Debug interface: UART RXD -input dco_clk; // Fast oscillator (fast clock) -input [13:0] irq; // Maskable interrupts -input lfxt_clk; // Low frequency oscillator (typ 32kHz) -input nmi; // Non-maskable interrupt (asynchronous) -input [15:0] per_dout; // Peripheral data output -input [15:0] ram_dout; // RAM data output -input reset_n; // Reset Pin (active low) -input [15:0] rom_dout; // ROM data output - - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -wire [7:0] inst_ad; -wire [7:0] inst_as; -wire [11:0] inst_alu; -wire inst_bw; -wire [15:0] inst_dest; -wire [15:0] inst_dext; -wire [15:0] inst_sext; -wire [7:0] inst_so; -wire [15:0] inst_src; -wire [2:0] inst_type; -wire [3:0] e_state; -wire exec_done; - -wire [15:0] eu_mab; -wire [15:0] eu_mdb_in; -wire [15:0] eu_mdb_out; -wire [1:0] eu_mb_wr; -wire [15:0] fe_mab; -wire [15:0] fe_mdb_in; - -wire [15:0] pc_sw; -wire [7:0] inst_jmp; -wire [15:0] pc; -wire [15:0] pc_nxt; - -wire [15:0] dbg_mem_addr; -wire [15:0] dbg_mem_dout; -wire [15:0] dbg_mem_din; -wire [15:0] dbg_reg_din; -wire [1:0] dbg_mem_wr; - -wire [15:0] per_dout_or; -wire [15:0] per_dout_sfr; -wire [15:0] per_dout_wdog; -wire [15:0] per_dout_clk; - - -//============================================================================= -// 2) GLOBAL CLOCK & RESET MANAGEMENT -//============================================================================= - -clock_module clock_module_0 ( - -// OUTPUTs - .aclk_en (aclk_en), // ACLK enablex - .mclk (mclk), // Main system clock - .per_dout (per_dout_clk), // Peripheral data output - .por (por), // Power-on reset - .puc (puc), // Main system reset - .smclk_en (smclk_en), // SMCLK enable - -// INPUTs - .dbg_reset (dbg_reset), // Reset CPU from debug interface - .dco_clk (dco_clk), // Fast oscillator (fast clock) - .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz) - .oscoff (oscoff), // Turns off LFXT1 clock input - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .reset_n (reset_n), // Reset Pin (low active) - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - .wdt_reset (wdt_reset) // Watchdog-timer reset -); - - -//============================================================================= -// 3) FRONTEND (<=> FETCH & DECODE) -//============================================================================= - -frontend frontend_0 ( - -// OUTPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .decode (decode), // Frontend decode instruction - .e_state (e_state), // Execution state - .exec_done (exec_done), // Execution completed - .inst_ad (inst_ad), // Decoded Inst: destination addressing mode - .inst_as (inst_as), // Decoded Inst: source addressing mode - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Decoded Inst: destination (one hot) - .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word - .inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_sext (inst_sext), // Decoded Inst: source extended instruction word - .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic - .inst_src (inst_src), // Decoded Inst: source (one hot) - .inst_type (inst_type), // Decoded Instruction type - .irq_acc (irq_acc), // Interrupt request accepted - .mab (fe_mab), // Frontend Memory address bus - .mb_en (fe_mb_en), // Frontend Memory bus enable - .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted - .pc (pc), // Program counter - .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) - -// INPUTs - .cpuoff (cpuoff), // Turns off the CPU - .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command - .dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access - .fe_rom_wait (fe_rom_wait), // Frontend wait for ROM - .gie (gie), // General interrupt enable - .irq (irq), // Maskable interrupts - .mclk (mclk), // Main system clock - .mdb_in (fe_mdb_in), // Frontend Memory data bus input - .nmi_evt (nmi_evt), // Non-maskable interrupt event - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .puc (puc), // Main system reset - .wdt_irq (wdt_irq) // Watchdog-timer interrupt -); - - -//============================================================================= -// 4) EXECUTION UNIT -//============================================================================= - -execution_unit execution_unit_0 ( - -// OUTPUTs - .cpuoff (cpuoff), // Turns off the CPU - .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input - .mab (eu_mab), // Memory address bus - .mb_en (eu_mb_en), // Memory bus enable - .mb_wr (eu_mb_wr), // Memory bus write transfer - .mdb_out (eu_mdb_out), // Memory data bus output - .oscoff (oscoff), // Turns off LFXT1 clock input - .pc_sw (pc_sw), // Program counter software value - .pc_sw_wr (pc_sw_wr), // Program counter software write - .scg1 (scg1), // System clock generator 1. Turns off the SMCLK - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write - .e_state (e_state), // Execution state - .exec_done (exec_done), // Execution completed - .gie (gie), // General interrupt enable - .inst_ad (inst_ad), // Decoded Inst: destination addressing mode - .inst_as (inst_as), // Decoded Inst: source addressing mode - .inst_alu (inst_alu), // ALU control signals - .inst_bw (inst_bw), // Decoded Inst: byte width - .inst_dest (inst_dest), // Decoded Inst: destination (one hot) - .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word - .inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt - .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump - .inst_sext (inst_sext), // Decoded Inst: source extended instruction word - .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic - .inst_src (inst_src), // Decoded Inst: source (one hot) - .inst_type (inst_type), // Decoded Instruction type - .mclk (mclk), // Main system clock - .mdb_in (eu_mdb_in), // Memory data bus input - .pc (pc), // Program counter - .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) - .puc (puc) // Main system reset -); - - -//============================================================================= -// 5) MEMORY BACKBONE -//============================================================================= - -mem_backbone mem_backbone_0 ( - -// OUTPUTs - .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input - .eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input - .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input - .fe_rom_wait (fe_rom_wait), // Frontend wait for ROM - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_wen (per_wen), // Peripheral write enable (high active) - .per_en (per_en), // Peripheral enable (high active) - .ram_addr (ram_addr), // RAM address - .ram_cen (ram_cen), // RAM chip enable (low active) - .ram_din (ram_din), // RAM data input - .ram_wen (ram_wen), // RAM write enable (low active) - .rom_addr (rom_addr), // ROM address - .rom_cen (rom_cen), // ROM chip enable (low active) - .rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE-- - .rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF-- - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_mem_en (dbg_mem_en), // Debug unit memory enable - .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write - .eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer - .eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output - .fe_mab (fe_mab[15:1]), // Frontend Memory address bus - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .per_dout (per_dout_or), // Peripheral data output - .puc (puc), // Main system reset - .ram_dout (ram_dout), // RAM data output - .rom_dout (rom_dout) // ROM data output -); - - -//============================================================================= -// 6) SPECIAL FUNCTION REGISTERS -//============================================================================= - -sfr sfr_0 ( - -// OUTPUTs - .nmie (nmie), // Non-maskable interrupt enable - .per_dout (per_dout_sfr), // Peripheral data output - .wdt_irq (wdt_irq), // Watchdog-timer interrupt - .wdt_reset (wdt_reset), // Watchdog-timer reset - .wdtie (wdtie), // Watchdog-timer interrupt enable - -// INPUTs - .mclk (mclk), // Main system clock - .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .por (por), // Power-on reset - .puc (puc), // Main system reset - .wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag - .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag - .wdtpw_error (wdtpw_error), // Watchdog-timer password error - .wdttmsel (wdttmsel) // Watchdog-timer mode select -); - - -//============================================================================= -// 7) WATCHDOG TIMER -//============================================================================= - -watchdog watchdog_0 ( - -// OUTPUTs - .nmi_evt (nmi_evt), // NMI Event - .per_dout (per_dout_wdog), // Peripheral data output - .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag - .wdtpw_error (wdtpw_error), // Watchdog-timer password error - .wdttmsel (wdttmsel), // Watchdog-timer mode select - -// INPUTs - .aclk_en (aclk_en), // ACLK enable - .dbg_freeze (dbg_freeze), // Freeze Watchdog counter - .mclk (mclk), // Main system clock - .nmi (nmi), // Non-maskable interrupt (asynchronous) - .nmie (nmie), // Non-maskable interrupt enable - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .puc (puc), // Main system reset - .smclk_en (smclk_en), // SMCLK enable - .wdtie (wdtie) // Watchdog-timer interrupt enable -); - - -//============================================================================= -// 8) PERIPHERALS' OUTPUT BUS -//============================================================================= - -assign per_dout_or = per_dout | - per_dout_clk | - per_dout_sfr | - per_dout_wdog; - - -//============================================================================= -// 9) DEBUG INTERFACE -//============================================================================= - -`ifdef DBG_EN -dbg dbg_0 ( - -// OUTPUTs - .dbg_freeze (dbg_freeze), // Freeze peripherals - .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command - .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access - .dbg_mem_dout (dbg_mem_dout), // Debug unit data output - .dbg_mem_en (dbg_mem_en), // Debug unit memory enable - .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write - .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write - .dbg_reset (dbg_reset), // Reset CPU from debug interface - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - -// INPUTs - .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU - .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input - .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD - .decode (decode), // Frontend decode instruction - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .por (por), // Power on reset - .puc (puc) // Main system reset -); - -`else -assign dbg_freeze = 1'b0; -assign dbg_halt_cmd = 1'b0; -assign dbg_mem_addr = 16'h0000; -assign dbg_mem_dout = 16'h0000; -assign dbg_mem_en = 1'b0; -assign dbg_mem_wr = 2'b00; -assign dbg_reg_wr = 1'b0; -assign dbg_reset = 1'b0; -assign dbg_uart_txd = 1'b0; -`endif - - -endmodule // openMSP430 -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_hwbrk.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_hwbrk.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_hwbrk.v (nonexistent) @@ -1,275 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: dbg_hwbrk.v -// -// *Module Description: -// Hardware Breakpoint / Watchpoint module -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module dbg_hwbrk ( - -// OUTPUTs - brk_halt, // Hardware breakpoint command - brk_pnd, // Hardware break/watch-point pending - brk_dout, // Hardware break/watch-point register data input - -// INPUTs - brk_reg_rd, // Hardware break/watch-point register read select - brk_reg_wr, // Hardware break/watch-point register write select - dbg_din, // Debug register data input - eu_mab, // Execution-Unit Memory address bus - eu_mb_en, // Execution-Unit Memory bus enable - eu_mb_wr, // Execution-Unit Memory bus write transfer - eu_mdb_in, // Memory data bus input - eu_mdb_out, // Memory data bus output - exec_done, // Execution completed - fe_mb_en, // Frontend Memory bus enable - mclk, // Main system clock - pc, // Program counter - por // Power on reset -); - -// OUTPUTs -//========= -output brk_halt; // Hardware breakpoint command -output brk_pnd; // Hardware break/watch-point pending -output [15:0] brk_dout; // Hardware break/watch-point register data input - -// INPUTs -//========= -input [3:0] brk_reg_rd; // Hardware break/watch-point register read select -input [3:0] brk_reg_wr; // Hardware break/watch-point register write select -input [15:0] dbg_din; // Debug register data input -input [15:0] eu_mab; // Execution-Unit Memory address bus -input eu_mb_en; // Execution-Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer -input [15:0] eu_mdb_in; // Memory data bus input -input [15:0] eu_mdb_out; // Memory data bus output -input exec_done; // Execution completed -input fe_mb_en; // Frontend Memory bus enable -input mclk; // Main system clock -input [15:0] pc; // Program counter -input por; // Power on reset - - -//============================================================================= -// 1) WIRE & PARAMETER DECLARATION -//============================================================================= - -wire range_wr_set; -wire range_rd_set; -wire addr1_wr_set; -wire addr1_rd_set; -wire addr0_wr_set; -wire addr0_rd_set; - - -parameter BRK_CTL = 0, - BRK_STAT = 1, - BRK_ADDR0 = 2, - BRK_ADDR1 = 3; - - -//============================================================================= -// 2) CONFIGURATION REGISTERS -//============================================================================= - -// BRK_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE -// -// ACCESS_MODE: - 00 : Disabled -// - 01 : Detect read access -// - 10 : Detect write access -// - 11 : Detect read/write access -// NOTE: '10' & '11' modes are not supported on the instruction flow -// -// BREAK_EN: - 0 : Watchmode enable -// - 1 : Break enable -// -// INST_EN: - 0 : Checks are done on the execution unit (data flow) -// - 1 : Checks are done on the frontend (instruction flow) -// -// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1 -// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range -// -//----------------------------------------------------------------------------- -reg [4:0] brk_ctl; - -wire brk_ctl_wr = brk_reg_wr[BRK_CTL]; - -always @ (posedge mclk or posedge por) - if (por) brk_ctl <= 5'h00; - else if (brk_ctl_wr) brk_ctl <= dbg_din[4:0]; - -wire [7:0] brk_ctl_full = {3'b000, brk_ctl}; - - -// BRK_STAT Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD -//----------------------------------------------------------------------------- -reg [5:0] brk_stat; - -wire brk_stat_wr = brk_reg_wr[BRK_STAT]; -wire [5:0] brk_stat_set = {range_wr_set, range_rd_set, - addr1_wr_set, addr1_rd_set, - addr0_wr_set, addr0_rd_set}; -wire [5:0] brk_stat_clr = ~dbg_din[5:0]; - -always @ (posedge mclk or posedge por) - if (por) brk_stat <= 6'h00; - else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set); - else brk_stat <= (brk_stat | brk_stat_set); - -wire [7:0] brk_stat_full = {2'b00, brk_stat}; -wire brk_pnd = |brk_stat; - - -// BRK_ADDR0 Register -//----------------------------------------------------------------------------- -reg [15:0] brk_addr0; - -wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0]; - -always @ (posedge mclk or posedge por) - if (por) brk_addr0 <= 16'h0000; - else if (brk_addr0_wr) brk_addr0 <= dbg_din; - - -// BRK_ADDR1/DATA0 Register -//----------------------------------------------------------------------------- -reg [15:0] brk_addr1; - -wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1]; - -always @ (posedge mclk or posedge por) - if (por) brk_addr1 <= 16'h0000; - else if (brk_addr1_wr) brk_addr1 <= dbg_din; - - -//============================================================================ -// 3) DATA OUTPUT GENERATION -//============================================================================ - -wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}}; -wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}}; -wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}}; -wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}}; - -wire [15:0] brk_dout = brk_ctl_rd | - brk_stat_rd | - brk_addr0_rd | - brk_addr1_rd; - - -//============================================================================ -// 4) BREAKPOINT / WATCHPOINT GENERATION -//============================================================================ - -// Comparators -//--------------------------- -// Note: here the comparison logic is instanciated several times in order -// to improve the timings, at the cost of a bit more area. - -wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE]; -wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE]; -wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & brk_ctl[`BRK_RANGE]; - -reg fe_mb_en_buf; -always @ (posedge mclk or posedge por) - if (por) fe_mb_en_buf <= 1'b0; - else fe_mb_en_buf <= fe_mb_en; - -wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; -wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; -wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & brk_ctl[`BRK_RANGE]; - - -// Detect accesses -//--------------------------- - -// Detect Instruction read access -wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN]; -wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN]; -wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN]; - -// Detect Execution-Unit write access -wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; -wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; -wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; - -// Detect DATA read access -// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read -// before being written back. In that case, the read flag should not be set. -// In general, We should here make sure no write access occures during the -// same instruction cycle before setting the read flag. -reg [2:0] d_rd_trig; -always @ (posedge mclk or posedge por) - if (por) d_rd_trig <= 3'h0; - else if (exec_done) d_rd_trig <= 3'h0; - else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, - equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, - equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr}; - -wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr; -wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr; -wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr; - - -// Set flags -assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd); -assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr; -assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd); -assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr; -assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd); -assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr; - - -// Break CPU -assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set; - - -endmodule // dbg_hwbrk - - - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg_hwbrk.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/sfr.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/sfr.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/sfr.v (nonexistent) @@ -1,202 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: sfr.v -// -// *Module Description: -// Processor Special function register -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module sfr ( - -// OUTPUTs - nmie, // Non-maskable interrupt enable - per_dout, // Peripheral data output - wdt_irq, // Watchdog-timer interrupt - wdt_reset, // Watchdog-timer reset - wdtie, // Watchdog-timer interrupt enable - -// INPUTs - mclk, // Main system clock - nmi_acc, // Non-Maskable interrupt request accepted - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - por, // Power-on reset - puc, // Main system reset - wdtifg_clr, // Clear Watchdog-timer interrupt flag - wdtifg_set, // Set Watchdog-timer interrupt flag - wdtpw_error, // Watchdog-timer password error - wdttmsel // Watchdog-timer mode select -); - -// OUTPUTs -//========= -output nmie; // Non-maskable interrupt enable -output [15:0] per_dout; // Peripheral data output -output wdt_irq; // Watchdog-timer interrupt -output wdt_reset; // Watchdog-timer reset -output wdtie; // Watchdog-timer interrupt enable - -// INPUTs -//========= -input mclk; // Main system clock -input nmi_acc; // Non-Maskable interrupt request accepted -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input por; // Power-on reset -input puc; // Main system reset -input wdtifg_clr; // Clear Watchdog-timer interrupt flag -input wdtifg_set; // Set Watchdog-timer interrupt flag -input wdtpw_error; // Watchdog-timer password error -input wdttmsel; // Watchdog-timer mode select - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter IE1 = 9'h000; -parameter IFG1 = 9'h002; - -// Register one-hot decoder -parameter IE1_D = (256'h1 << (IE1 /2)); -parameter IFG1_D = (256'h1 << (IFG1 /2)); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [255:0] reg_dec; -always @(per_addr) - case (per_addr) - (IE1 /2): reg_dec = IE1_D; - (IFG1 /2): reg_dec = IFG1_D; - default : reg_dec = {256{1'b0}}; - endcase - -// Read/Write probes -wire reg_lo_write = per_wen[0] & per_en; -wire reg_hi_write = per_wen[1] & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; -wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; -wire [255:0] reg_rd = reg_dec & {256{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// IE1 Register -//-------------- -wire [7:0] ie1; -wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2]; -wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0]; - -reg nmie; -always @ (posedge mclk or posedge puc) - if (puc) nmie <= 1'b0; - else if (nmi_acc) nmie <= 1'b0; - else if (ie1_wr) nmie <= ie1_nxt[4]; - -reg wdtie; -always @ (posedge mclk or posedge puc) - if (puc) wdtie <= 1'b0; - else if (ie1_wr) wdtie <= ie1_nxt[0]; - -assign ie1 = {3'b000, nmie, 3'b000, wdtie}; - - -// IFG1 Register -//--------------- -wire [7:0] ifg1; -wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2]; -wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0]; - -reg nmiifg; -always @ (posedge mclk or posedge puc) - if (puc) nmiifg <= 1'b0; - else if (nmi_acc) nmiifg <= 1'b1; - else if (ifg1_wr) nmiifg <= ifg1_nxt[4]; - -reg wdtifg; -always @ (posedge mclk or posedge por) - if (por) wdtifg <= 1'b0; - else if (wdtifg_set) wdtifg <= 1'b1; - else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0; - else if (ifg1_wr) wdtifg <= ifg1_nxt[0]; - -assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg}; - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}}); -wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}}); - -wire [15:0] per_dout = ie1_rd | - ifg1_rd; - - -//============================================================================= -// 5) WATCHDOG INTERRUPT & RESET -//============================================================================= - -// Watchdog interrupt generation -//--------------------------------- -wire wdt_irq = wdttmsel & wdtifg & wdtie; - - -// Watchdog reset generation -//----------------------------- -reg wdt_reset; - -always @ (posedge mclk or posedge por) - if (por) wdt_reset <= 1'b0; - else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel); - - -endmodule // sfr
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/sfr.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg.v (nonexistent) @@ -1,796 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: dbg.v -// -// *Module Description: -// Debug interface -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module dbg ( - -// OUTPUTs - dbg_freeze, // Freeze peripherals - dbg_halt_cmd, // Halt CPU command - dbg_mem_addr, // Debug address for rd/wr access - dbg_mem_dout, // Debug unit data output - dbg_mem_en, // Debug unit memory enable - dbg_mem_wr, // Debug unit memory write - dbg_reg_wr, // Debug unit CPU register write - dbg_reset, // Reset CPU from debug interface - dbg_uart_txd, // Debug interface: UART TXD - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - dbg_mem_din, // Debug unit Memory data input - dbg_reg_din, // Debug unit CPU register data input - dbg_uart_rxd, // Debug interface: UART RXD - decode, // Frontend decode instruction - eu_mab, // Execution-Unit Memory address bus - eu_mb_en, // Execution-Unit Memory bus enable - eu_mb_wr, // Execution-Unit Memory bus write transfer - eu_mdb_in, // Memory data bus input - eu_mdb_out, // Memory data bus output - exec_done, // Execution completed - fe_mb_en, // Frontend Memory bus enable - fe_mdb_in, // Frontend Memory data bus input - mclk, // Main system clock - pc, // Program counter - por, // Power on reset - puc // Main system reset -); - -// OUTPUTs -//========= -output dbg_freeze; // Freeze peripherals -output dbg_halt_cmd; // Halt CPU command -output [15:0] dbg_mem_addr; // Debug address for rd/wr access -output [15:0] dbg_mem_dout; // Debug unit data output -output dbg_mem_en; // Debug unit memory enable -output [1:0] dbg_mem_wr; // Debug unit memory write -output dbg_reg_wr; // Debug unit CPU register write -output dbg_reset; // Reset CPU from debug interface -output dbg_uart_txd; // Debug interface: UART TXD - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input [15:0] dbg_mem_din; // Debug unit Memory data input -input [15:0] dbg_reg_din; // Debug unit CPU register data input -input dbg_uart_rxd; // Debug interface: UART RXD -input decode; // Frontend decode instruction -input [15:0] eu_mab; // Execution-Unit Memory address bus -input eu_mb_en; // Execution-Unit Memory bus enable -input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer -input [15:0] eu_mdb_in; // Memory data bus input -input [15:0] eu_mdb_out; // Memory data bus output -input exec_done; // Execution completed -input fe_mb_en; // Frontend Memory bus enable -input [15:0] fe_mdb_in; // Frontend Memory data bus input -input mclk; // Main system clock -input [15:0] pc; // Program counter -input por; // Power on reset -input puc; // Main system reset - - -//============================================================================= -// 1) WIRE & PARAMETER DECLARATION -//============================================================================= - -// Diverse wires and registers -wire [5:0] dbg_addr; -wire [15:0] dbg_din; -wire dbg_wr; -reg mem_burst; -wire dbg_reg_rd; -wire dbg_mem_rd; -reg dbg_mem_rd_dly; -wire dbg_swbrk; -wire dbg_rd; -reg dbg_rd_rdy; -wire mem_burst_rd; -wire mem_burst_wr; -wire brk0_halt; -wire brk0_pnd; -wire [15:0] brk0_dout; -wire brk1_halt; -wire brk1_pnd; -wire [15:0] brk1_dout; -wire brk2_halt; -wire brk2_pnd; -wire [15:0] brk2_dout; -wire brk3_halt; -wire brk3_pnd; -wire [15:0] brk3_dout; - -// Register addresses -parameter CPU_ID_LO = 6'h00; -parameter CPU_ID_HI = 6'h01; -parameter CPU_CTL = 6'h02; -parameter CPU_STAT = 6'h03; -parameter MEM_CTL = 6'h04; -parameter MEM_ADDR = 6'h05; -parameter MEM_DATA = 6'h06; -parameter MEM_CNT = 6'h07; -`ifdef DBG_HWBRK_0 -parameter BRK0_CTL = 6'h08; -parameter BRK0_STAT = 6'h09; -parameter BRK0_ADDR0 = 6'h0A; -parameter BRK0_ADDR1 = 6'h0B; -`endif -`ifdef DBG_HWBRK_1 -parameter BRK1_CTL = 6'h0C; -parameter BRK1_STAT = 6'h0D; -parameter BRK1_ADDR0 = 6'h0E; -parameter BRK1_ADDR1 = 6'h0F; -`endif -`ifdef DBG_HWBRK_2 -parameter BRK2_CTL = 6'h10; -parameter BRK2_STAT = 6'h11; -parameter BRK2_ADDR0 = 6'h12; -parameter BRK2_ADDR1 = 6'h13; -`endif -`ifdef DBG_HWBRK_3 -parameter BRK3_CTL = 6'h14; -parameter BRK3_STAT = 6'h15; -parameter BRK3_ADDR0 = 6'h16; -parameter BRK3_ADDR1 = 6'h17; -`endif - -// Register one-hot decoder -parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO); -parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI); -parameter CPU_CTL_D = (64'h1 << CPU_CTL); -parameter CPU_STAT_D = (64'h1 << CPU_STAT); -parameter MEM_CTL_D = (64'h1 << MEM_CTL); -parameter MEM_ADDR_D = (64'h1 << MEM_ADDR); -parameter MEM_DATA_D = (64'h1 << MEM_DATA); -parameter MEM_CNT_D = (64'h1 << MEM_CNT); -`ifdef DBG_HWBRK_0 -parameter BRK0_CTL_D = (64'h1 << BRK0_CTL); -parameter BRK0_STAT_D = (64'h1 << BRK0_STAT); -parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0); -parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1); -`endif -`ifdef DBG_HWBRK_1 -parameter BRK1_CTL_D = (64'h1 << BRK1_CTL); -parameter BRK1_STAT_D = (64'h1 << BRK1_STAT); -parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0); -parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1); -`endif -`ifdef DBG_HWBRK_2 -parameter BRK2_CTL_D = (64'h1 << BRK2_CTL); -parameter BRK2_STAT_D = (64'h1 << BRK2_STAT); -parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0); -parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1); -`endif -`ifdef DBG_HWBRK_3 -parameter BRK3_CTL_D = (64'h1 << BRK3_CTL); -parameter BRK3_STAT_D = (64'h1 << BRK3_STAT); -parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0); -parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1); -`endif - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Select Data register during a burst -wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr; - -// Register address decode -reg [63:0] reg_dec; -always @(dbg_addr_in) - case (dbg_addr_in) - CPU_ID_LO : reg_dec = CPU_ID_LO_D; - CPU_ID_HI : reg_dec = CPU_ID_HI_D; - CPU_CTL : reg_dec = CPU_CTL_D; - CPU_STAT : reg_dec = CPU_STAT_D; - MEM_CTL : reg_dec = MEM_CTL_D; - MEM_ADDR : reg_dec = MEM_ADDR_D; - MEM_DATA : reg_dec = MEM_DATA_D; - MEM_CNT : reg_dec = MEM_CNT_D; -`ifdef DBG_HWBRK_0 - BRK0_CTL : reg_dec = BRK0_CTL_D; - BRK0_STAT : reg_dec = BRK0_STAT_D; - BRK0_ADDR0: reg_dec = BRK0_ADDR0_D; - BRK0_ADDR1: reg_dec = BRK0_ADDR1_D; -`endif -`ifdef DBG_HWBRK_1 - BRK1_CTL : reg_dec = BRK1_CTL_D; - BRK1_STAT : reg_dec = BRK1_STAT_D; - BRK1_ADDR0: reg_dec = BRK1_ADDR0_D; - BRK1_ADDR1: reg_dec = BRK1_ADDR1_D; -`endif -`ifdef DBG_HWBRK_2 - BRK2_CTL : reg_dec = BRK2_CTL_D; - BRK2_STAT : reg_dec = BRK2_STAT_D; - BRK2_ADDR0: reg_dec = BRK2_ADDR0_D; - BRK2_ADDR1: reg_dec = BRK2_ADDR1_D; -`endif -`ifdef DBG_HWBRK_3 - BRK3_CTL : reg_dec = BRK3_CTL_D; - BRK3_STAT : reg_dec = BRK3_STAT_D; - BRK3_ADDR0: reg_dec = BRK3_ADDR0_D; - BRK3_ADDR1: reg_dec = BRK3_ADDR1_D; -`endif - default: reg_dec = {64{1'b0}}; - endcase - -// Read/Write probes -wire reg_write = dbg_wr; -wire reg_read = 1'b1; - -// Read/Write vectors -wire [511:0] reg_wr = reg_dec & {64{reg_write}}; -wire [511:0] reg_rd = reg_dec & {64{reg_read}}; - - -//============================================================================= -// 3) REGISTER: CORE INTERFACE -//============================================================================= - -// CPU_ID Register -//----------------- - -wire [3:0] cpu_id_rom = `ROM_AWIDTH; -wire [3:0] cpu_id_ram = `RAM_AWIDTH; -wire [31:0] cpu_id = {`DBG_ID, cpu_id_rom, cpu_id_ram}; - - -// CPU_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT -//----------------------------------------------------------------------------- -reg [6:3] cpu_ctl; - -wire cpu_ctl_wr = reg_wr[CPU_CTL]; - -always @ (posedge mclk or posedge por) - if (por) cpu_ctl <= 4'h0; - else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3]; - -wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000}; - -wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st; -wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st; -wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st; - - -// CPU_STAT Register -//------------------------------------------------------------------------------------ -// 7 6 5 4 3 2 1 0 -// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN -//------------------------------------------------------------------------------------ -reg [3:2] cpu_stat; - -wire cpu_stat_wr = reg_wr[CPU_STAT]; -wire [3:2] cpu_stat_set = {dbg_swbrk, puc}; -wire [3:2] cpu_stat_clr = ~dbg_din[3:2]; - -always @ (posedge mclk or posedge por) - if (por) cpu_stat <= 2'b00; - else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set); - else cpu_stat <= (cpu_stat | cpu_stat_set); - -wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd, - cpu_stat, 1'b0, dbg_halt_st}; - - -//============================================================================= -// 4) REGISTER: MEMORY INTERFACE -//============================================================================= - -// MEM_CTL Register -//----------------------------------------------------------------------------- -// 7 6 5 4 3 2 1 0 -// Reserved B/W MEM/REG RD/WR START -// -// START : - 0 : Do nothing. -// - 1 : Initiate memory transfer. -// -// RD/WR : - 0 : Read access. -// - 1 : Write access. -// -// MEM/REG: - 0 : Memory access. -// - 1 : CPU Register access. -// -// B/W : - 0 : 16 bit access. -// - 1 : 8 bit access (not valid for CPU Registers). -// -//----------------------------------------------------------------------------- -reg [3:1] mem_ctl; - -wire mem_ctl_wr = reg_wr[MEM_CTL]; - -always @ (posedge mclk or posedge por) - if (por) mem_ctl <= 3'h0; - else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1]; - -wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0}; - -reg mem_start; -always @ (posedge mclk or posedge por) - if (por) mem_start <= 1'b0; - else mem_start <= mem_ctl_wr & dbg_din[0]; - -wire mem_bw = mem_ctl[3]; - -// MEM_DATA Register -//------------------ -reg [15:0] mem_data; -reg [15:0] mem_addr; -wire mem_access; - -wire mem_data_wr = reg_wr[MEM_DATA]; - -wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din : - mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} : - {8'h00, dbg_mem_din[7:0]}; - -always @ (posedge mclk or posedge por) - if (por) mem_data <= 16'h0000; - else if (mem_data_wr) mem_data <= dbg_din; - else if (dbg_reg_rd) mem_data <= dbg_reg_din; - else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw; - - -// MEM_ADDR Register -//------------------ -reg [15:0] mem_cnt; - -wire mem_addr_wr = reg_wr[MEM_ADDR]; -wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2])); -wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2])); - -wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 : - (dbg_mem_acc & ~mem_bw) ? 16'h0002 : - (dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000; - -always @ (posedge mclk or posedge por) - if (por) mem_addr <= 16'h0000; - else if (mem_addr_wr) mem_addr <= dbg_din; - else mem_addr <= mem_addr + mem_addr_inc; - -// MEM_CNT Register -//------------------ - -wire mem_cnt_wr = reg_wr[MEM_CNT]; - -wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 : - (dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000; - -always @ (posedge mclk or posedge por) - if (por) mem_cnt <= 16'h0000; - else if (mem_cnt_wr) mem_cnt <= dbg_din; - else mem_cnt <= mem_cnt + mem_cnt_dec; - - -//============================================================================= -// 5) BREAKPOINTS / WATCHPOINTS -//============================================================================= - -`ifdef DBG_HWBRK_0 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1], - reg_rd[BRK0_ADDR0], - reg_rd[BRK0_STAT], - reg_rd[BRK0_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1], - reg_wr[BRK0_ADDR0], - reg_wr[BRK0_STAT], - reg_wr[BRK0_CTL]}; - -dbg_hwbrk dbg_hwbr_0 ( - -// OUTPUTs - .brk_halt (brk0_halt), // Hardware breakpoint command - .brk_pnd (brk0_pnd), // Hardware break/watch-point pending - .brk_dout (brk0_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select - .dbg_din (dbg_din), // Debug register data input - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .por (por) // Power on reset -); - -`else -assign brk0_halt = 1'b0; -assign brk0_pnd = 1'b0; -assign brk0_dout = 16'h0000; -`endif - -`ifdef DBG_HWBRK_1 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1], - reg_rd[BRK1_ADDR0], - reg_rd[BRK1_STAT], - reg_rd[BRK1_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1], - reg_wr[BRK1_ADDR0], - reg_wr[BRK1_STAT], - reg_wr[BRK1_CTL]}; - -dbg_hwbrk dbg_hwbr_1 ( - -// OUTPUTs - .brk_halt (brk1_halt), // Hardware breakpoint command - .brk_pnd (brk1_pnd), // Hardware break/watch-point pending - .brk_dout (brk1_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select - .dbg_din (dbg_din), // Debug register data input - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .por (por) // Power on reset -); - -`else -assign brk1_halt = 1'b0; -assign brk1_pnd = 1'b0; -assign brk1_dout = 16'h0000; -`endif - - `ifdef DBG_HWBRK_2 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1], - reg_rd[BRK2_ADDR0], - reg_rd[BRK2_STAT], - reg_rd[BRK2_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1], - reg_wr[BRK2_ADDR0], - reg_wr[BRK2_STAT], - reg_wr[BRK2_CTL]}; - -dbg_hwbrk dbg_hwbr_2 ( - -// OUTPUTs - .brk_halt (brk2_halt), // Hardware breakpoint command - .brk_pnd (brk2_pnd), // Hardware break/watch-point pending - .brk_dout (brk2_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select - .dbg_din (dbg_din), // Debug register data input - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .por (por) // Power on reset -); - -`else -assign brk2_halt = 1'b0; -assign brk2_pnd = 1'b0; -assign brk2_dout = 16'h0000; -`endif - -`ifdef DBG_HWBRK_3 -// Hardware Breakpoint/Watchpoint Register read select -wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1], - reg_rd[BRK3_ADDR0], - reg_rd[BRK3_STAT], - reg_rd[BRK3_CTL]}; - -// Hardware Breakpoint/Watchpoint Register write select -wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1], - reg_wr[BRK3_ADDR0], - reg_wr[BRK3_STAT], - reg_wr[BRK3_CTL]}; - -dbg_hwbrk dbg_hwbr_3 ( - -// OUTPUTs - .brk_halt (brk3_halt), // Hardware breakpoint command - .brk_pnd (brk3_pnd), // Hardware break/watch-point pending - .brk_dout (brk3_dout), // Hardware break/watch-point register data input - -// INPUTs - .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select - .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select - .dbg_din (dbg_din), // Debug register data input - .eu_mab (eu_mab), // Execution-Unit Memory address bus - .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable - .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer - .eu_mdb_in (eu_mdb_in), // Memory data bus input - .eu_mdb_out (eu_mdb_out), // Memory data bus output - .exec_done (exec_done), // Execution completed - .fe_mb_en (fe_mb_en), // Frontend Memory bus enable - .mclk (mclk), // Main system clock - .pc (pc), // Program counter - .por (por) // Power on reset -); - -`else -assign brk3_halt = 1'b0; -assign brk3_pnd = 1'b0; -assign brk3_dout = 16'h0000; -`endif - - -//============================================================================ -// 6) DATA OUTPUT GENERATION -//============================================================================ - -wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}}; -wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}}; -wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}}; -wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}}; -wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}}; -wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}}; -wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}}; -wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}}; - -wire [15:0] dbg_dout = cpu_id_lo_rd | - cpu_id_hi_rd | - cpu_ctl_rd | - cpu_stat_rd | - mem_ctl_rd | - mem_data_rd | - mem_addr_rd | - mem_cnt_rd | - brk0_dout | - brk1_dout | - brk2_dout | - brk3_dout; - -// Tell UART/JTAG interface that the data is ready to be read -always @ (posedge mclk or posedge por) - if (por) dbg_rd_rdy <= 1'b0; - else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly); - else dbg_rd_rdy <= dbg_rd; - - -//============================================================================ -// 7) CPU CONTROL -//============================================================================ - -// Reset CPU -//-------------------------- -wire dbg_reset = cpu_ctl[`CPU_RST]; - - -// Break after reset -//-------------------------- -wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc; - - -// Freeze peripherals -//-------------------------- -wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN]; - - -// Software break -//-------------------------- -assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode & cpu_ctl[`SW_BRK_EN]; - - -// Single step -//-------------------------- -reg [1:0] inc_step; -always @(posedge mclk or posedge por) - if (por) inc_step <= 2'b00; - else if (istep) inc_step <= 2'b11; - else inc_step <= {inc_step[0], 1'b0}; - - -// Run / Halt -//-------------------------- -reg halt_flag; - -wire mem_halt_cpu; -wire mem_run_cpu; - -wire halt_flag_clr = run_cpu | mem_run_cpu; -wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu | - brk0_halt | brk1_halt | brk2_halt | brk3_halt; - -always @(posedge mclk or posedge por) - if (por) halt_flag <= 1'b0; - else if (halt_flag_clr) halt_flag <= 1'b0; - else if (halt_flag_set) halt_flag <= 1'b1; - -wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1]; - - -//============================================================================ -// 8) MEMORY CONTROL -//============================================================================ - -// Control Memory bursts -//------------------------------ - -wire mem_burst_start = (mem_start & |mem_cnt); -wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt); - -// Detect when burst is on going -always @(posedge mclk or posedge por) - if (por) mem_burst <= 1'b0; - else if (mem_burst_start) mem_burst <= 1'b1; - else if (mem_burst_end) mem_burst <= 1'b0; - -// Control signals for UART/JTAG interface -assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]); -assign mem_burst_wr = (mem_burst_start & mem_ctl[1]); - -// Trigger CPU Register or memory access during a burst -reg mem_startb; -always @(posedge mclk or posedge por) - if (por) mem_startb <= 1'b0; - else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd; - -// Combine single and burst memory start of sequence -wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb); - - -// Memory access state machine -//------------------------------ -reg [1:0] mem_state; -reg [1:0] mem_state_nxt; - -// State machine definition -parameter M_IDLE = 2'h0; -parameter M_SET_BRK = 2'h1; -parameter M_ACCESS_BRK = 2'h2; -parameter M_ACCESS = 2'h3; - -// State transition -always @(mem_state or mem_seq_start or dbg_halt_st) - case (mem_state) - M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE : - dbg_halt_st ? M_ACCESS : M_SET_BRK; - M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK; - M_ACCESS_BRK : mem_state_nxt = M_IDLE; - M_ACCESS : mem_state_nxt = M_IDLE; - default : mem_state_nxt = M_IDLE; - endcase - -// State machine -always @(posedge mclk or posedge por) - if (por) mem_state <= M_IDLE; - else mem_state <= mem_state_nxt; - -// Utility signals -assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK); -assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE); -assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK); - - -// Interface to CPU Registers and Memory bacbkone -//------------------------------------------------ -assign dbg_mem_addr = mem_addr; -assign dbg_mem_dout = ~mem_bw ? mem_data : - mem_addr[0] ? {mem_data[7:0], 8'h00} : - {8'h00, mem_data[7:0]}; - -assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2]; -assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2]; - -assign dbg_mem_en = mem_access & ~mem_ctl[2]; -assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1]; - -wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 : - mem_addr[0] ? 2'b10 : 2'b01; -assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk; - - -// It takes one additional cycle to read from Memory as from registers -always @(posedge mclk or posedge por) - if (por) dbg_mem_rd_dly <= 1'b0; - else dbg_mem_rd_dly <= dbg_mem_rd; - - -//============================================================================= -// 9) UART COMMUNICATION -//============================================================================= -`ifdef DBG_UART -dbg_uart dbg_uart_0 ( - -// OUTPUTs - .dbg_addr (dbg_addr), // Debug register address - .dbg_din (dbg_din), // Debug register data input - .dbg_rd (dbg_rd), // Debug register data read - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - .dbg_wr (dbg_wr), // Debug register data write - -// INPUTs - .dbg_dout (dbg_dout), // Debug register data output - .dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD - .mclk (mclk), // Main system clock - .mem_burst (mem_burst), // Burst on going - .mem_burst_end(mem_burst_end), // End TX/RX burst - .mem_burst_rd (mem_burst_rd), // Start TX burst - .mem_burst_wr (mem_burst_wr), // Start RX burst - .mem_bw (mem_bw), // Burst byte width - .por (por) // Power on reset -); - -`else -assign dbg_addr = 6'h00; -assign dbg_din = 16'h0000; -assign dbg_rd = 1'b0; -assign dbg_uart_txd = 1'b0; -assign dbg_wr = 1'b0; -`endif - - -//============================================================================= -// 10) JTAG COMMUNICATION -//============================================================================= -`ifdef DBG_JTAG -JTAG INTERFACE IS NOT SUPPORTED YET -`else -`endif - -endmodule // dbg - - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/dbg.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/frontend.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/frontend.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/frontend.v (nonexistent) @@ -1,756 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: frontend.v -// -// *Module Description: -// openMSP430 Instruction fetch and decode unit -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module frontend ( - -// OUTPUTs - dbg_halt_st, // Halt/Run status from CPU - decode, // Frontend decode instruction - e_state, // Execution state - exec_done, // Execution completed - inst_ad, // Decoded Inst: destination addressing mode - inst_as, // Decoded Inst: source addressing mode - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_dest, // Decoded Inst: destination (one hot) - inst_dext, // Decoded Inst: destination extended instruction word - inst_irq_rst, // Decoded Inst: Reset interrupt - inst_jmp, // Decoded Inst: Conditional jump - inst_sext, // Decoded Inst: source extended instruction word - inst_so, // Decoded Inst: Single-operand arithmetic - inst_src, // Decoded Inst: source (one hot) - inst_type, // Decoded Instruction type - irq_acc, // Interrupt request accepted (one-hot signal) - mab, // Frontend Memory address bus - mb_en, // Frontend Memory bus enable - nmi_acc, // Non-Maskable interrupt request accepted - pc, // Program counter - pc_nxt, // Next PC value (for CALL & IRQ) - -// INPUTs - cpuoff, // Turns off the CPU - dbg_halt_cmd, // Halt CPU command - dbg_reg_sel, // Debug selected register for rd/wr access - fe_rom_wait, // Frontend wait for ROM - gie, // General interrupt enable - irq, // Maskable interrupts - mclk, // Main system clock - mdb_in, // Frontend Memory data bus input - nmi_evt, // Non-maskable interrupt event - pc_sw, // Program counter software value - pc_sw_wr, // Program counter software write - puc, // Main system reset - wdt_irq // Watchdog-timer interrupt -); - -// OUTPUTs -//========= -output dbg_halt_st; // Halt/Run status from CPU -output decode; // Frontend decode instruction -output [3:0] e_state; // Execution state -output exec_done; // Execution completed -output [7:0] inst_ad; // Decoded Inst: destination addressing mode -output [7:0] inst_as; // Decoded Inst: source addressing mode -output [11:0] inst_alu; // ALU control signals -output inst_bw; // Decoded Inst: byte width -output [15:0] inst_dest; // Decoded Inst: destination (one hot) -output [15:0] inst_dext; // Decoded Inst: destination extended instruction word -output inst_irq_rst; // Decoded Inst: Reset interrupt -output [7:0] inst_jmp; // Decoded Inst: Conditional jump -output [15:0] inst_sext; // Decoded Inst: source extended instruction word -output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic -output [15:0] inst_src; // Decoded Inst: source (one hot) -output [2:0] inst_type; // Decoded Instruction type -output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) -output [15:0] mab; // Frontend Memory address bus -output mb_en; // Frontend Memory bus enable -output nmi_acc; // Non-Maskable interrupt request accepted -output [15:0] pc; // Program counter -output [15:0] pc_nxt; // Next PC value (for CALL & IRQ) - -// INPUTs -//========= -input cpuoff; // Turns off the CPU -input dbg_halt_cmd; // Halt CPU command -input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access -input fe_rom_wait; // Frontend wait for ROM -input gie; // General interrupt enable -input [13:0] irq; // Maskable interrupts -input mclk; // Main system clock -input [15:0] mdb_in; // Frontend Memory data bus input -input nmi_evt; // Non-maskable interrupt event -input [15:0] pc_sw; // Program counter software value -input pc_sw_wr; // Program counter software write -input puc; // Main system reset -input wdt_irq; // Watchdog-timer interrupt - - -//============================================================================= -// 1) FRONTEND STATE MACHINE -//============================================================================= - -// The wire "conv" is used as state bits to calculate the next response -reg [2:0] i_state; -reg [2:0] i_state_nxt; - -reg [1:0] inst_sz; -wire [1:0] inst_sz_nxt; -wire irq_detect; -wire [2:0] inst_type_nxt; -wire is_const; -reg [15:0] sconst_nxt; -reg [3:0] e_state_nxt; - -// State machine definitons -parameter I_IRQ_FETCH = 3'h0; -parameter I_IRQ_DONE = 3'h1; -parameter I_DEC = 3'h2; // New instruction ready for decode -parameter I_EXT1 = 3'h3; // 1st Extension word -parameter I_EXT2 = 3'h4; // 2nd Extension word -parameter I_IDLE = 3'h5; // CPU is in IDLE mode - -// States Transitions -always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or - exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state) - case(i_state) - I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH : - (~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE; - I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE; - I_IRQ_DONE : i_state_nxt = I_DEC; - I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH : - (cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE : - dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE : - pc_sw_wr ? I_DEC : - ~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state - (inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed - I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH : - pc_sw_wr ? I_DEC : - (inst_sz!=2'b01) ? I_EXT2 : I_DEC; - I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC; - default : i_state_nxt = I_IRQ_FETCH; - endcase - -// State machine -always @(posedge mclk or posedge puc) - if (puc) i_state <= I_IRQ_FETCH; - else i_state <= i_state_nxt; - -// Utility signals -wire decode = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))) | irq_detect; -wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE); - -// Debug interface cpu status -reg dbg_halt_st; -always @(posedge mclk or posedge puc) - if (puc) dbg_halt_st <= 1'b0; - else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE); - - -//============================================================================= -// 2) INTERRUPT HANDLING -//============================================================================= - -// Detect nmi interrupt -reg inst_nmi; -always @(posedge mclk or posedge puc) - if (puc) inst_nmi <= 1'b0; - else if (nmi_evt) inst_nmi <= 1'b1; - else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0; - - -// Detect reset interrupt -reg inst_irq_rst; -always @(posedge mclk or posedge puc) - if (puc) inst_irq_rst <= 1'b1; - else if (exec_done) inst_irq_rst <= 1'b0; - -// Detect other interrupts -assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE)); - -// Select interrupt vector -reg [3:0] irq_num; -always @(posedge mclk or posedge puc) - if (puc) irq_num <= 4'hf; - else if (irq_detect) irq_num <= inst_nmi ? 4'he : - irq[13] ? 4'hd : - irq[12] ? 4'hc : - irq[11] ? 4'hb : - (irq[10] | wdt_irq) ? 4'ha : - irq[9] ? 4'h9 : - irq[8] ? 4'h8 : - irq[7] ? 4'h7 : - irq[6] ? 4'h6 : - irq[5] ? 4'h5 : - irq[4] ? 4'h4 : - irq[3] ? 4'h3 : - irq[2] ? 4'h2 : - irq[1] ? 4'h1 : - irq[0] ? 4'h0 : 4'hf; - -wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0}; - -// Interrupt request accepted -wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}}; -wire [13:0] irq_acc = irq_acc_all[13:0]; -wire nmi_acc = irq_acc_all[14]; - - -//============================================================================= -// 3) FETCH INSTRUCTION -//============================================================================= - -// -// 3.1) PROGRAM COUNTER & MEMORY INTERFACE -//----------------------------------------- - -// Program counter -reg [15:0] pc; - -// Detect if PC needs to be incremented -wire pc_inc = (~pc_sw_wr & fetch) & ~(i_state==I_IRQ_FETCH) & ~(i_state==I_IRQ_DONE); - -// Mux between software update and old PC -wire [15:0] pc_sel = pc_sw_wr ? pc_sw : - (i_state==I_IRQ_FETCH) ? irq_addr : - (i_state==I_IRQ_DONE) ? mdb_in : pc; - -// Compute next PC value -wire [15:0] pc_nxt = pc_sel + {14'h0000, pc_inc, 1'b0}; - -always @(posedge mclk or posedge puc) - if (puc) pc <= 16'h0000; - else pc <= pc_nxt; - -// Check if ROM has been busy in order to retry ROM access -reg rom_busy; -always @(posedge mclk or posedge puc) - if (puc) rom_busy <= 16'h0000; - else rom_busy <= fe_rom_wait; - -// Memory interface -wire [15:0] mab = pc_nxt; -wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | rom_busy | (dbg_halt_st & ~dbg_halt_cmd); - - -// -// 3.2) INSTRUCTION REGISTER -//-------------------------------- - -// Instruction register -wire [15:0] ir = mdb_in; - -// Detect if source extension word is required -wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]); - -// Detect if destination extension word is required -wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]); - -// For the Symbolic addressing mode, add -2 to the extension word in order -// to make up for the PC address -wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) | - ((i_state==I_EXT2) & inst_ad[`SYMB]) | - ((i_state==I_EXT1) & ~inst_as[`SYMB] & - ~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000; - -wire [15:0] ext_nxt = ir + ext_incr; - -// Store source extension word -reg [15:0] inst_sext; -always @(posedge mclk or posedge puc) - if (puc) inst_sext <= 16'h0000; - else if (decode & is_const) inst_sext <= sconst_nxt; - else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0}; - else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt; - -// Source extension word is ready -wire inst_sext_rdy = (i_state==I_EXT1) & is_sext; - - -// Store destination extension word -reg [15:0] inst_dext; -always @(posedge mclk or posedge puc) - if (puc) inst_dext <= 16'h0000; - else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt; - else if (i_state==I_EXT2) inst_dext <= ext_nxt; - -// Destination extension word is ready -wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2)); - - -//============================================================================= -// 4) DECODE INSTRUCTION -//============================================================================= - -// -// 4.1) OPCODE: INSTRUCTION TYPE -//---------------------------------------- -// Instructions type is encoded in a one hot fashion as following: -// -// 3'b001: Single-operand arithmetic -// 3'b010: Conditional jump -// 3'b100: Two-operand arithmetic - -reg [2:0] inst_type; -assign inst_type_nxt = {(ir[15:14]!=2'b00), - (ir[15:13]==3'b001), - (ir[15:13]==3'b000)} & {3{~irq_detect}}; - -always @(posedge mclk or posedge puc) - if (puc) inst_type <= 3'b000; - else if (decode) inst_type <= inst_type_nxt; - -// -// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC -//---------------------------------------- -// Instructions are encoded in a one hot fashion as following: -// -// 8'b00000001: RRC -// 8'b00000010: SWPB -// 8'b00000100: RRA -// 8'b00001000: SXT -// 8'b00010000: PUSH -// 8'b00100000: CALL -// 8'b01000000: RETI -// 8'b10000000: IRQ - -reg [7:0] inst_so; -wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/frontend.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/watchdog.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/watchdog.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/watchdog.v (nonexistent) @@ -1,220 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: watchdog.v -// -// *Module Description: -// Watchdog Timer -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module watchdog ( - -// OUTPUTs - nmi_evt, // NMI Event - per_dout, // Peripheral data output - wdtifg_set, // Set Watchdog-timer interrupt flag - wdtpw_error, // Watchdog-timer password error - wdttmsel, // Watchdog-timer mode select - -// INPUTs - aclk_en, // ACLK enable - dbg_freeze, // Freeze Watchdog counter - mclk, // Main system clock - nmi, // Non-maskable interrupt (asynchronous) - nmie, // Non-maskable interrupt enable - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - puc, // Main system reset - smclk_en, // SMCLK enable - wdtie // Watchdog timer interrupt enable -); - -// OUTPUTs -//========= -output nmi_evt; // NMI Event -output [15:0] per_dout; // Peripheral data output -output wdtifg_set; // Set Watchdog-timer interrupt flag -output wdtpw_error; // Watchdog-timer password error -output wdttmsel; // Watchdog-timer mode select - -// INPUTs -//========= -input aclk_en; // ACLK enable -input dbg_freeze; // Freeze Watchdog counter -input mclk; // Main system clock -input nmi; // Non-maskable interrupt (asynchronous) -input nmie; // Non-maskable interrupt enable -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input puc; // Main system reset -input smclk_en; // SMCLK enable -input wdtie; // Watchdog timer interrupt enable - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter WDTCTL = 9'h120; - - -// Register one-hot decoder -parameter WDTCTL_D = (512'h1 << WDTCTL); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [511:0] reg_dec; -always @(per_addr) - case ({per_addr,1'b0}) - WDTCTL : reg_dec = WDTCTL_D; - default: reg_dec = {512{1'b0}}; - endcase - -// Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [511:0] reg_wr = reg_dec & {512{reg_write}}; -wire [511:0] reg_rd = reg_dec & {512{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// WDTCTL Register -//----------------- -// WDTNMI & WDTSSEL are not implemented and therefore masked - -reg [7:0] wdtctl; - -wire wdtctl_wr = reg_wr[WDTCTL]; - -always @ (posedge mclk or posedge puc) - if (puc) wdtctl <= 8'h00; - else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7; - -wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a); -wire wdttmsel = wdtctl[4]; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// Data output mux -wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}}; - -wire [15:0] per_dout = wdtctl_rd; - - -//============================================================================= -// 4) NMI GENERATION -//============================================================================= - -// Synchronization state -reg [2:0] nmi_sync; -always @ (posedge mclk or posedge puc) - if (puc) nmi_sync <= 3'h0; - else nmi_sync <= {nmi_sync[1:0], nmi}; - -// Edge detection -wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie; -wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie; - -// NMI event -wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re; - - -//============================================================================= -// 5) WATCHDOG TIMER -//============================================================================= - -// Watchdog clock source selection -//--------------------------------- -wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en; - - -// Watchdog 16 bit counter -//-------------------------- -reg [15:0] wdtcnt; - -wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set; - -always @ (posedge mclk or posedge puc) - if (puc) wdtcnt <= 16'h0000; - else if (wdtcnt_clr) wdtcnt <= 16'h0000; - else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001; - - -// Interval selection mux -//-------------------------- -reg wdtqn; - -always @(wdtctl or wdtcnt) - case(wdtctl[1:0]) - 2'b00 : wdtqn = wdtcnt[15]; - 2'b01 : wdtqn = wdtcnt[13]; - 2'b10 : wdtqn = wdtcnt[9]; - default: wdtqn = wdtcnt[6]; - endcase - - -// Watchdog event detection -//----------------------------- -reg wdtqn_dly; - -always @ (posedge mclk or posedge puc) - if (puc) wdtqn_dly <= 1'b0; - else wdtqn_dly <= wdtqn; - -wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error; - - -endmodule // watchdog - - - - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/watchdog.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/clock_module.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/clock_module.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/clock_module.v (nonexistent) @@ -1,246 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: clock_module.v -// -// *Module Description: -// Basic clock module implementation. -// Since the openMSP430 mainly targets FPGA and hobby -// designers. The clock structure has been greatly -// symplified in order to ease integration. -// See online wiki for more info. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module clock_module ( - -// OUTPUTs - aclk_en, // ACLK enable - mclk, // Main system clock - per_dout, // Peripheral data output - por, // Power-on reset - puc, // Main system reset - smclk_en, // SMCLK enable - -// INPUTs - dbg_reset, // Reset CPU from debug interface - dco_clk, // Fast oscillator (fast clock) - lfxt_clk, // Low frequency oscillator (typ 32kHz) - oscoff, // Turns off LFXT1 clock input - per_addr, // Peripheral address - per_din, // Peripheral data input - per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) - reset_n, // Reset Pin (low active) - scg1, // System clock generator 1. Turns off the SMCLK - wdt_reset // Watchdog-timer reset -); - -// OUTPUTs -//========= -output aclk_en; // ACLK enable -output mclk; // Main system clock -output [15:0] per_dout; // Peripheral data output -output por; // Power-on reset -output puc; // Main system reset -output smclk_en; // SMCLK enable - -// INPUTs -//========= -input dbg_reset; // Reset CPU from debug interface -input dco_clk; // Fast oscillator (fast clock) -input lfxt_clk; // Low frequency oscillator (typ 32kHz) -input oscoff; // Turns off LFXT1 clock input -input [7:0] per_addr; // Peripheral address -input [15:0] per_din; // Peripheral data input -input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) -input reset_n; // Reset Pin (low active) -input scg1; // System clock generator 1. Turns off the SMCLK -input wdt_reset; // Watchdog-timer reset - - -//============================================================================= -// 1) PARAMETER DECLARATION -//============================================================================= - -// Register addresses -parameter BCSCTL1 = 9'h057; -parameter BCSCTL2 = 9'h058; - -// Register one-hot decoder -parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2)); -parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2)); - - -//============================================================================ -// 2) REGISTER DECODER -//============================================================================ - -// Register address decode -reg [255:0] reg_dec; -always @(per_addr) - case (per_addr) - (BCSCTL1 /2): reg_dec = BCSCTL1_D; - (BCSCTL2 /2): reg_dec = BCSCTL2_D; - default : reg_dec = {256{1'b0}}; - endcase - -// Read/Write probes -wire reg_lo_write = per_wen[0] & per_en; -wire reg_hi_write = per_wen[1] & per_en; -wire reg_read = ~|per_wen & per_en; - -// Read/Write vectors -wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; -wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; -wire [255:0] reg_rd = reg_dec & {256{reg_read}}; - - -//============================================================================ -// 3) REGISTERS -//============================================================================ - -// BCSCTL1 Register -//-------------- -reg [7:0] bcsctl1; -wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2]; -wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) bcsctl1 <= 8'h00; - else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits - - -// BCSCTL2 Register -//-------------- -reg [7:0] bcsctl2; -wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2]; -wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0]; - -always @ (posedge mclk or posedge puc) - if (puc) bcsctl2 <= 8'h00; - else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits - - -//============================================================================ -// 4) DATA OUTPUT GENERATION -//============================================================================ - -// Data output mux -wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}}); -wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}}); - -wire [15:0] per_dout = bcsctl1_rd | - bcsctl2_rd; - - -//============================================================================= -// 5) CLOCK GENERATION -//============================================================================= - -// Synchronize LFXT_CLK & edge detection -//--------------------------------------- -reg [2:0] lfxt_clk_s; - -always @ (posedge mclk or posedge puc) - if (puc) lfxt_clk_s <= 3'b000; - else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk}; - -wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]); - - -// Generate main system clock -//---------------------------- - -wire mclk = dco_clk; -wire mclk_n = !dco_clk; - - -// Generate ACLK -//---------------------------- - -reg [2:0] aclk_div; - -wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 : - (bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] : - (bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] : - &aclk_div[2:0]); - -always @ (posedge mclk or posedge puc) - if (puc) aclk_div <= 3'h0; - else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1; - - -// Generate SMCLK -//---------------------------- - -reg [2:0] smclk_div; - -wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1); - -wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 : - (bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] : - (bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] : - &smclk_div[2:0]); - -always @ (posedge mclk or posedge puc) - if (puc) smclk_div <= 3'h0; - else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1; - - -//============================================================================= -// 6) RESET GENERATION -//============================================================================= - -// Generate synchronized POR -wire por_reset = !reset_n; - -reg [1:0] por_s; -always @(posedge mclk_n or posedge por_reset) - if (por_reset) por_s <= 2'b11; - else por_s <= {por_s[0], 1'b0}; -wire por = por_s[1]; - -// Generate main system reset -wire puc_reset = por_reset | wdt_reset | dbg_reset; - -reg [1:0] puc_s; -always @(posedge mclk_n or posedge puc_reset) - if (puc_reset) puc_s <= 2'b11; - else puc_s <= {puc_s[0], 1'b0}; -wire puc = puc_s[1]; - - -endmodule // clock_module -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/clock_module.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/alu.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/alu.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/alu.v (nonexistent) @@ -1,248 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: alu.v -// -// *Module Description: -// openMSP430 ALU -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module alu ( - -// OUTPUTs - alu_out, // ALU output value - alu_out_add, // ALU adder output value - alu_stat, // ALU Status {V,N,Z,C} - alu_stat_wr, // ALU Status write {V,N,Z,C} - -// INPUTs - dbg_halt_st, // Halt/Run status from CPU - exec_cycle, // Instruction execution cycle - inst_alu, // ALU control signals - inst_bw, // Decoded Inst: byte width - inst_jmp, // Decoded Inst: Conditional jump - inst_so, // Single-operand arithmetic - op_dst, // Destination operand - op_src, // Source operand - status // R2 Status {V,N,Z,C} -); - -// OUTPUTs -//========= -output [15:0] alu_out; // ALU output value -output [15:0] alu_out_add; // ALU adder output value -output [3:0] alu_stat; // ALU Status {V,N,Z,C} -output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} - -// INPUTs -//========= -input dbg_halt_st; // Halt/Run status from CPU -input exec_cycle; // Instruction execution cycle -input [11:0] inst_alu; // ALU control signals -input inst_bw; // Decoded Inst: byte width -input [7:0] inst_jmp; // Decoded Inst: Conditional jump -input [7:0] inst_so; // Single-operand arithmetic -input [15:0] op_dst; // Destination operand -input [15:0] op_src; // Source operand -input [3:0] status; // R2 Status {V,N,Z,C} - - -//============================================================================= -// 1) FUNCTIONS -//============================================================================= - -function [4:0] bcd_add; - - input [3:0] X; - input [3:0] Y; - input C; - - reg [4:0] Z; - begin - Z = {1'b0,X}+{1'b0,Y}+C; - if (Z<10) bcd_add = Z; - else bcd_add = Z+6; - end - -endfunction - - -//============================================================================= -// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE -//============================================================================= -// SINGLE-OPERAND ARITHMETIC: -//----------------------------------------------------------------------------- -// Mnemonic S-Reg, Operation Status bits -// D-Reg, V N Z C -// -// RRC dst C->MSB->...LSB->C * * * * -// RRA dst MSB->MSB->...LSB->C 0 * * * -// SWPB dst Swap bytes - - - - -// SXT dst Bit7->Bit8...Bit15 0 * * * -// PUSH src SP-2->SP, src->@SP - - - - -// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - - -// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * * -// -//----------------------------------------------------------------------------- -// TWO-OPERAND ARITHMETIC: -//----------------------------------------------------------------------------- -// Mnemonic S-Reg, Operation Status bits -// D-Reg, V N Z C -// -// MOV src,dst src -> dst - - - - -// ADD src,dst src + dst -> dst * * * * -// ADDC src,dst src + dst + C -> dst * * * * -// SUB src,dst dst + ~src + 1 -> dst * * * * -// SUBC src,dst dst + ~src + C -> dst * * * * -// CMP src,dst dst + ~src + 1 * * * * -// DADD src,dst src + dst + C -> dst (decimaly) * * * * -// BIT src,dst src & dst 0 * * * -// BIC src,dst ~src & dst -> dst - - - - -// BIS src,dst src | dst -> dst - - - - -// XOR src,dst src ^ dst -> dst * * * * -// AND src,dst src & dst -> dst 0 * * * -// -//----------------------------------------------------------------------------- -// * the status bit is affected -// - the status bit is not affected -// 0 the status bit is cleared -// 1 the status bit is set -//----------------------------------------------------------------------------- - -// Invert source for substract and compare instructions. -wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]); -wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src; - - -// Mask the bit 8 for the Byte instructions for correct flags generation -wire op_bit8_msk = ~exec_cycle | ~inst_bw; -wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]}; -wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]}; - -// Clear the source operand (= jump offset) for conditional jumps -wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) | - (inst_jmp[`JGE] & (status[3]^status[2])) | - (inst_jmp[`JN] & ~status[2]) | - (inst_jmp[`JC] & ~status[0]) | - (inst_jmp[`JNC] & status[0]) | - (inst_jmp[`JEQ] & ~status[1]) | - (inst_jmp[`JNE] & status[1]); -wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}}; - -// Adder / AND / OR / XOR -wire [16:0] alu_add = op_src_in_jmp + op_dst_in; -wire [16:0] alu_and = op_src_in & op_dst_in; -wire [16:0] alu_or = op_src_in | op_dst_in; -wire [16:0] alu_xor = op_src_in ^ op_dst_in; - - -// Incrementer -wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) | - inst_alu[`ALU_INC]); -wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc}; - - - -// Decimal adder (DADD) -wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]); -wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]); -wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]); -wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]); -wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]}; - - -// Shifter for rotate instructions (RRC & RRA) -wire alu_shift_msb = inst_so[`RRC] ? status[0] : - inst_bw ? op_src[7] : op_src[15]; -wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8]; -wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]}; - - -// Swap bytes / Extend Sign -wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]}; -wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]}; - - -// Combine short paths toghether to simplify final ALU mux -wire alu_short_thro = ~(inst_alu[`ALU_AND] | - inst_alu[`ALU_OR] | - inst_alu[`ALU_XOR] | - inst_alu[`ALU_SHIFT] | - inst_so[`SWPB] | - inst_so[`SXT]); - -wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) | - ({16{inst_alu[`ALU_OR]}} & alu_or) | - ({16{inst_alu[`ALU_XOR]}} & alu_xor) | - ({16{inst_alu[`ALU_SHIFT]}} & alu_shift) | - ({16{inst_so[`SWPB]}} & alu_swpb) | - ({16{inst_so[`SXT]}} & alu_sxt) | - ({16{alu_short_thro}} & op_src_in); - - -// ALU output mux -wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st | - inst_alu[`ALU_ADD]) ? alu_add_inc : - inst_alu[`ALU_DADD] ? alu_dadd : alu_short; - -assign alu_out = alu_out_nxt[15:0]; -assign alu_out_add = alu_add[15:0]; - - -//----------------------------------------------------------------------------- -// STATUS FLAG GENERATION -//----------------------------------------------------------------------------- - -wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) : - (op_src_in[15] & op_dst_in[15]); - -wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) | - ( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) : - ((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) | - ( op_src_in[15] & op_dst_in[15] & ~alu_out[15])); - -wire N = inst_bw ? alu_out[7] : alu_out[15]; -wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0); -wire C = inst_bw ? alu_out[8] : alu_out_nxt[16]; - -assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} : - inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} : - inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C}; - -assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000; - - -endmodule // alu - -
trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/alu.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v (nonexistent) @@ -1,965 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_fpga.v -// -// *Module Description: -// openMSP430 FPGA Top-level for the Diligent -// Spartan-3 starter kit. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" -`include "openMSP430_defines.v" - -module openMSP430_fpga ( - -// Clock Sources - CLK_50MHz, - CLK_SOCKET, - -// Slide Switches - SW7, - SW6, - SW5, - SW4, - SW3, - SW2, - SW1, - SW0, - -// Push Button Switches - BTN3, - BTN2, - BTN1, - BTN0, - -// LEDs - LED7, - LED6, - LED5, - LED4, - LED3, - LED2, - LED1, - LED0, - -// Four-Sigit, Seven-Segment LED Display - SEG_A, - SEG_B, - SEG_C, - SEG_D, - SEG_E, - SEG_F, - SEG_G, - SEG_DP, - SEG_AN0, - SEG_AN1, - SEG_AN2, - SEG_AN3, - -// RS-232 Port - UART_RXD, - UART_TXD, - UART_RXD_A, - UART_TXD_A, - -// PS/2 Mouse/Keyboard Port - PS2_D, - PS2_C, - -// Fast, Asynchronous SRAM - SRAM_A17, // Address Bus Connections - SRAM_A16, - SRAM_A15, - SRAM_A14, - SRAM_A13, - SRAM_A12, - SRAM_A11, - SRAM_A10, - SRAM_A9, - SRAM_A8, - SRAM_A7, - SRAM_A6, - SRAM_A5, - SRAM_A4, - SRAM_A3, - SRAM_A2, - SRAM_A1, - SRAM_A0, - SRAM_OE, // Write enable and output enable control signals - SRAM_WE, - SRAM0_IO15, // SRAM Data signals, chip enables, and byte enables - SRAM0_IO14, - SRAM0_IO13, - SRAM0_IO12, - SRAM0_IO11, - SRAM0_IO10, - SRAM0_IO9, - SRAM0_IO8, - SRAM0_IO7, - SRAM0_IO6, - SRAM0_IO5, - SRAM0_IO4, - SRAM0_IO3, - SRAM0_IO2, - SRAM0_IO1, - SRAM0_IO0, - SRAM0_CE1, - SRAM0_UB1, - SRAM0_LB1, - SRAM1_IO15, - SRAM1_IO14, - SRAM1_IO13, - SRAM1_IO12, - SRAM1_IO11, - SRAM1_IO10, - SRAM1_IO9, - SRAM1_IO8, - SRAM1_IO7, - SRAM1_IO6, - SRAM1_IO5, - SRAM1_IO4, - SRAM1_IO3, - SRAM1_IO2, - SRAM1_IO1, - SRAM1_IO0, - SRAM1_CE2, - SRAM1_UB2, - SRAM1_LB2, - -// VGA Port - VGA_R, - VGA_G, - VGA_B, - VGA_HS, - VGA_VS -); - -// Clock Sources -input CLK_50MHz; -input CLK_SOCKET; - -// Slide Switches -input SW7; -input SW6; -input SW5; -input SW4; -input SW3; -input SW2; -input SW1; -input SW0; - -// Push Button Switches -input BTN3; -input BTN2; -input BTN1; -input BTN0; - -// LEDs -output LED7; -output LED6; -output LED5; -output LED4; -output LED3; -output LED2; -output LED1; -output LED0; - -// Four-Sigit, Seven-Segment LED Display -output SEG_A; -output SEG_B; -output SEG_C; -output SEG_D; -output SEG_E; -output SEG_F; -output SEG_G; -output SEG_DP; -output SEG_AN0; -output SEG_AN1; -output SEG_AN2; -output SEG_AN3; - -// RS-232 Port -input UART_RXD; -output UART_TXD; -input UART_RXD_A; -output UART_TXD_A; - -// PS/2 Mouse/Keyboard Port -inout PS2_D; -output PS2_C; - -// Fast, Asynchronous SRAM -output SRAM_A17; // Address Bus Connections -output SRAM_A16; -output SRAM_A15; -output SRAM_A14; -output SRAM_A13; -output SRAM_A12; -output SRAM_A11; -output SRAM_A10; -output SRAM_A9; -output SRAM_A8; -output SRAM_A7; -output SRAM_A6; -output SRAM_A5; -output SRAM_A4; -output SRAM_A3; -output SRAM_A2; -output SRAM_A1; -output SRAM_A0; -output SRAM_OE; // Write enable and output enable control signals -output SRAM_WE; -inout SRAM0_IO15; // SRAM Data signals, chip enables, and byte enables -inout SRAM0_IO14; -inout SRAM0_IO13; -inout SRAM0_IO12; -inout SRAM0_IO11; -inout SRAM0_IO10; -inout SRAM0_IO9; -inout SRAM0_IO8; -inout SRAM0_IO7; -inout SRAM0_IO6; -inout SRAM0_IO5; -inout SRAM0_IO4; -inout SRAM0_IO3; -inout SRAM0_IO2; -inout SRAM0_IO1; -inout SRAM0_IO0; -output SRAM0_CE1; -output SRAM0_UB1; -output SRAM0_LB1; -inout SRAM1_IO15; -inout SRAM1_IO14; -inout SRAM1_IO13; -inout SRAM1_IO12; -inout SRAM1_IO11; -inout SRAM1_IO10; -inout SRAM1_IO9; -inout SRAM1_IO8; -inout SRAM1_IO7; -inout SRAM1_IO6; -inout SRAM1_IO5; -inout SRAM1_IO4; -inout SRAM1_IO3; -inout SRAM1_IO2; -inout SRAM1_IO1; -inout SRAM1_IO0; -output SRAM1_CE2; -output SRAM1_UB2; -output SRAM1_LB2; - -// VGA Port -output VGA_R; -output VGA_G; -output VGA_B; -output VGA_HS; -output VGA_VS; - - -//============================================================================= -// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION -//============================================================================= - -// openMSP430 output buses -wire [7:0] per_addr; -wire [15:0] per_din; -wire [1:0] per_wen; -wire [`RAM_MSB:0] ram_addr; -wire [15:0] ram_din; -wire [1:0] ram_wen; -wire [`ROM_MSB:0] rom_addr; -wire [15:0] rom_din_dbg; -wire [1:0] rom_wen_dbg; -wire [13:0] irq_acc; - -// openMSP430 input buses -wire [13:0] irq_bus; -wire [15:0] per_dout; -wire [15:0] ram_dout; -wire [15:0] rom_dout; - -// GPIO -wire [7:0] p1_din; -wire [7:0] p1_dout; -wire [7:0] p1_dout_en; -wire [7:0] p1_sel; -wire [7:0] p2_din; -wire [7:0] p2_dout; -wire [7:0] p2_dout_en; -wire [7:0] p2_sel; -wire [7:0] p3_din; -wire [7:0] p3_dout; -wire [7:0] p3_dout_en; -wire [7:0] p3_sel; -wire [15:0] per_dout_dio; - -// Timer A -wire [15:0] per_dout_tA; - -// 7 segment driver -wire [15:0] per_dout_7seg; - -// Others -wire reset_pin; - - -//============================================================================= -// 2) CLOCK GENERATION -//============================================================================= - -// Input buffers -//------------------------ -IBUFG ibuf_clk_main (.O(clk_50M_in), .I(CLK_50MHz)); -IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET)); - - -// Digital Clock Manager -//------------------------ - -// Generate 20MHz clock from 50MHz on-board oscillator -//`define DCM_FX_MODE -`ifdef DCM_FX_MODE -DCM dcm_adv_clk_main ( - -// OUTPUTs - .CLK0 (), - .CLK90 (), - .CLK180 (), - .CLK270 (), - .CLK2X (), - .CLK2X180 (), - .CLKDV (), - .CLKFX (dcm_clk), - .CLKFX180 (), - .PSDONE (), - .STATUS (), - .LOCKED (dcm_locked), - -// INPUTs - .CLKIN (clk_50M_in), - .CLKFB (1'b0), - .PSINCDEC (1'b0), - .PSEN (1'b0), - .DSSEN (1'b0), - .RST (reset_pin), - .PSCLK (1'b0) -); - -// synopsys translate_off -defparam dcm_adv_clk_main.CLK_FEEDBACK = "NONE"; -defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5; -defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE"; -defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.0; -defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE"; -defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; -defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW"; -defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW"; -defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE"; -defparam dcm_adv_clk_main.FACTORY_JF = 16'hC080; -defparam dcm_adv_clk_main.PHASE_SHIFT = 0; -defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE"; - -defparam dcm_adv_clk_main.CLKFX_DIVIDE = 5; -defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 2; -// synopsys translate_on -`else -DCM dcm_adv_clk_main ( - -// OUTPUTs - .CLKDV (dcm_clk), - .CLKFX (), - .CLKFX180 (), - .CLK0 (CLK0_BUF), - .CLK2X (), - .CLK2X180 (), - .CLK90 (), - .CLK180 (), - .CLK270 (), - .LOCKED (dcm_locked), - .PSDONE (), - .STATUS (), - -// INPUTs - .CLKFB (CLKFB_IN), - .CLKIN (clk_50M_in), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .DSSEN (1'b0), - .PSCLK (1'b0), - .RST (reset_pin) -); -BUFG CLK0_BUFG_INST ( - .I(CLK0_BUF), - .O(CLKFB_IN) -); - -// synopsys translate_off -defparam dcm_adv_clk_main.CLK_FEEDBACK = "1X"; -defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5; -defparam dcm_adv_clk_main.CLKFX_DIVIDE = 1; -defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 4; -defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE"; -defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.000; -defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE"; -defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; -defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW"; -defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW"; -defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE"; -defparam dcm_adv_clk_main.FACTORY_JF = 16'h8080; -defparam dcm_adv_clk_main.PHASE_SHIFT = 0; -defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE"; -// synopsys translate_on -`endif - - -//wire dcm_locked = 1'b1; -//wire reset_n; - -//reg dcm_clk; -//always @(posedge clk_50M_in) -// if (~reset_n) dcm_clk <= 1'b0; -// else dcm_clk <= ~dcm_clk; - - -// Clock buffers -//------------------------ -BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk)); - - -//============================================================================= -// 3) RESET GENERATION & FPGA STARTUP -//============================================================================= - -// Reset input buffer -IBUF ibuf_reset_n (.O(reset_pin), .I(BTN3)); -wire reset_pin_n = ~reset_pin; - -// Release the reset only, if the DCM is locked -assign reset_n = reset_pin_n & dcm_locked; - -//Include the startup device -wire gsr_tb; -wire gts_tb; -STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb)); - - -//============================================================================= -// 4) OPENMSP430 -//============================================================================= - -openMSP430 openMSP430_0 ( - -// OUTPUTs - .aclk_en (aclk_en), // ACLK enable - .dbg_freeze (dbg_freeze), // Freeze peripherals - .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD - .irq_acc (irq_acc), // Interrupt request accepted (one-hot signal) - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_wen (per_wen), // Peripheral write enable (high active) - .per_en (per_en), // Peripheral enable (high active) - .puc (puc), // Main system reset - .ram_addr (ram_addr), // RAM address - .ram_cen (ram_cen), // RAM chip enable (low active) - .ram_din (ram_din), // RAM data input - .ram_wen (ram_wen), // RAM write enable (low active) - .rom_addr (rom_addr), // ROM address - .rom_cen (rom_cen), // ROM chip enable (low active) - .rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE-- - .rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF-- - .smclk_en (smclk_en), // SMCLK enable - -// INPUTs - .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD - .dco_clk (clk_sys), // Fast oscillator (fast clock) - .irq (irq_bus), // Maskable interrupts - .lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz) - .nmi (nmi), // Non-maskable interrupt (asynchronous) - .per_dout (per_dout), // Peripheral data output - .ram_dout (ram_dout), // RAM data output - .reset_n (reset_n), // Reset Pin (low active) - .rom_dout (rom_dout) // ROM data output -); - - -//============================================================================= -// 5) OPENMSP430 PERIPHERALS -//============================================================================= - -// -// Digital I/O -//------------------------------- - -gpio #(.P1_EN(1), - .P2_EN(1), - .P3_EN(1), - .P4_EN(0), - .P5_EN(0), - .P6_EN(0)) gpio_0 ( - -// OUTPUTs - .irq_port1 (irq_port1), // Port 1 interrupt - .irq_port2 (irq_port2), // Port 2 interrupt - .p1_dout (p1_dout), // Port 1 data output - .p1_dout_en (p1_dout_en), // Port 1 data output enable - .p1_sel (p1_sel), // Port 1 function select - .p2_dout (p2_dout), // Port 2 data output - .p2_dout_en (p2_dout_en), // Port 2 data output enable - .p2_sel (p2_sel), // Port 2 function select - .p3_dout (p3_dout), // Port 3 data output - .p3_dout_en (p3_dout_en), // Port 3 data output enable - .p3_sel (p3_sel), // Port 3 function select - .p4_dout (), // Port 4 data output - .p4_dout_en (), // Port 4 data output enable - .p4_sel (), // Port 4 function select - .p5_dout (), // Port 5 data output - .p5_dout_en (), // Port 5 data output enable - .p5_sel (), // Port 5 function select - .p6_dout (), // Port 6 data output - .p6_dout_en (), // Port 6 data output enable - .p6_sel (), // Port 6 function select - .per_dout (per_dout_dio), // Peripheral data output - -// INPUTs - .mclk (mclk), // Main system clock - .p1_din (p1_din), // Port 1 data input - .p2_din (p2_din), // Port 2 data input - .p3_din (p3_din), // Port 3 data input - .p4_din (8'h00), // Port 4 data input - .p5_din (8'h00), // Port 5 data input - .p6_din (8'h00), // Port 6 data input - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .puc (puc) // Main system reset -); - -// -// Timer A -//---------------------------------------------- - -timerA timerA_0 ( - -// OUTPUTs - .irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0 - .irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2 - .per_dout (per_dout_tA), // Peripheral data output - .ta_out0 (ta_out0), // Timer A output 0 - .ta_out0_en (ta_out0_en), // Timer A output 0 enable - .ta_out1 (ta_out1), // Timer A output 1 - .ta_out1_en (ta_out1_en), // Timer A output 1 enable - .ta_out2 (ta_out2), // Timer A output 2 - .ta_out2_en (ta_out2_en), // Timer A output 2 enable - -// INPUTs - .aclk_en (aclk_en), // ACLK enable (from CPU) - .dbg_freeze (dbg_freeze), // Freeze Timer A counter - .inclk (inclk), // INCLK external timer clock (SLOW) - .irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .puc (puc), // Main system reset - .smclk_en (smclk_en), // SMCLK enable (from CPU) - .ta_cci0a (ta_cci0a), // Timer A capture 0 input A - .ta_cci0b (ta_cci0b), // Timer A capture 0 input B - .ta_cci1a (ta_cci1a), // Timer A capture 1 input A - .ta_cci1b (1'b0), // Timer A capture 1 input B - .ta_cci2a (ta_cci2a), // Timer A capture 2 input A - .ta_cci2b (1'b0), // Timer A capture 2 input B - .taclk (taclk) // TACLK external timer clock (SLOW) -); - - -// -// Four-Digit, Seven-Segment LED Display driver -//---------------------------------------------- - -driver_7segment driver_7segment_0 ( - -// OUTPUTs - .per_dout (per_dout_7seg), // Peripheral data output - .seg_a (seg_a_), // Segment A control - .seg_b (seg_b_), // Segment B control - .seg_c (seg_c_), // Segment C control - .seg_d (seg_d_), // Segment D control - .seg_e (seg_e_), // Segment E control - .seg_f (seg_f_), // Segment F control - .seg_g (seg_g_), // Segment G control - .seg_dp (seg_dp_), // Segment DP control - .seg_an0 (seg_an0_), // Anode 0 control - .seg_an1 (seg_an1_), // Anode 1 control - .seg_an2 (seg_an2_), // Anode 2 control - .seg_an3 (seg_an3_), // Anode 3 control - -// INPUTs - .mclk (mclk), // Main system clock - .per_addr (per_addr), // Peripheral address - .per_din (per_din), // Peripheral data input - .per_en (per_en), // Peripheral enable (high active) - .per_wen (per_wen), // Peripheral write enable (high active) - .puc (puc) // Main system reset -); - - -// -// Combine peripheral data buses -//------------------------------- - -assign per_dout = per_dout_dio | - per_dout_tA | - per_dout_7seg; - -// -// Assign interrupts -//------------------------------- - -assign nmi = 1'b0; -assign irq_bus = {1'b0, // Vector 13 (0xFFFA) - 1'b0, // Vector 12 (0xFFF8) - 1'b0, // Vector 11 (0xFFF6) - 1'b0, // Vector 10 (0xFFF4) - Watchdog - - irq_ta0, // Vector 9 (0xFFF2) - irq_ta1, // Vector 8 (0xFFF0) - 1'b0, // Vector 7 (0xFFEE) - 1'b0, // Vector 6 (0xFFEC) - 1'b0, // Vector 5 (0xFFEA) - 1'b0, // Vector 4 (0xFFE8) - irq_port2, // Vector 3 (0xFFE6) - irq_port1, // Vector 2 (0xFFE4) - 1'b0, // Vector 1 (0xFFE2) - 1'b0}; // Vector 0 (0xFFE0) - -// -// GPIO Function selection -//-------------------------- - -// P1.0/TACLK I/O pin / Timer_A, clock signal TACLK input -// P1.1/TA0 I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output -// P1.2/TA1 I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output -// P1.3/TA2 I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output -// P1.4/SMCLK I/O pin / SMCLK signal output -// P1.5/TA0 I/O pin / Timer_A, compare: Out0 output -// P1.6/TA1 I/O pin / Timer_A, compare: Out1 output -// P1.7/TA2 I/O pin / Timer_A, compare: Out2 output -wire [7:0] p1_io_mux_b_unconnected; -wire [7:0] p1_io_dout; -wire [7:0] p1_io_dout_en; -wire [7:0] p1_io_din; - -io_mux #8 io_mux_p1 ( - .a_din (p1_din), - .a_dout (p1_dout), - .a_dout_en (p1_dout_en), - - .b_din ({p1_io_mux_b_unconnected[7], - p1_io_mux_b_unconnected[6], - p1_io_mux_b_unconnected[5], - p1_io_mux_b_unconnected[4], - ta_cci2a, - ta_cci1a, - ta_cci0a, - taclk - }), - .b_dout ({ta_out2, - ta_out1, - ta_out0, - (smclk_en & mclk), - ta_out2, - ta_out1, - ta_out0, - 1'b0 - }), - .b_dout_en ({ta_out2_en, - ta_out1_en, - ta_out0_en, - 1'b1, - ta_out2_en, - ta_out1_en, - ta_out0_en, - 1'b0 - }), - - .io_din (p1_io_din), - .io_dout (p1_io_dout), - .io_dout_en (p1_io_dout_en), - - .sel (p1_sel) -); - - - -// P2.0/ACLK I/O pin / ACLK output -// P2.1/INCLK I/O pin / Timer_A, clock signal at INCLK -// P2.2/TA0 I/O pin / Timer_A, capture: CCI0B input -// P2.3/TA1 I/O pin / Timer_A, compare: Out1 output -// P2.4/TA2 I/O pin / Timer_A, compare: Out2 output -wire [7:0] p2_io_mux_b_unconnected; -wire [7:0] p2_io_dout; -wire [7:0] p2_io_dout_en; -wire [7:0] p2_io_din; - -io_mux #8 io_mux_p2 ( - .a_din (p2_din), - .a_dout (p2_dout), - .a_dout_en (p2_dout_en), - - .b_din ({p2_io_mux_b_unconnected[7], - p2_io_mux_b_unconnected[6], - p2_io_mux_b_unconnected[5], - p2_io_mux_b_unconnected[4], - p2_io_mux_b_unconnected[3], - ta_cci0b, - inclk, - p2_io_mux_b_unconnected[0] - }), - .b_dout ({1'b0, - 1'b0, - 1'b0, - ta_out2, - ta_out1, - 1'b0, - 1'b0, - (aclk_en & mclk) - }), - .b_dout_en ({1'b0, - 1'b0, - 1'b0, - ta_out2_en, - ta_out1_en, - 1'b0, - 1'b0, - 1'b1 - }), - - .io_din (p2_io_din), - .io_dout (p2_io_dout), - .io_dout_en (p2_io_dout_en), - - .sel (p2_sel) -); - - -//============================================================================= -// 6) RAM / ROM -//============================================================================= - -// RAM -ram_8x512_hi ram_8x512_hi_0 ( - .addr (ram_addr), - .clk (clk_sys), - .din (ram_din[15:8]), - .dout (ram_dout[15:8]), - .en (ram_cen), - .we (ram_wen[1]) -); -ram_8x512_lo ram_8x512_lo_0 ( - .addr (ram_addr), - .clk (clk_sys), - .din (ram_din[7:0]), - .dout (ram_dout[7:0]), - .en (ram_cen), - .we (ram_wen[0]) -); - - -// ROM -rom_8x2k_hi rom_8x2k_hi_0 ( - .addr (rom_addr), - .clk (clk_sys), - .din (rom_din_dbg[15:8]), - .dout (rom_dout[15:8]), - .en (rom_cen), - .we (rom_wen_dbg[1]) -); - -rom_8x2k_lo rom_8x2k_lo_0 ( - .addr (rom_addr), - .clk (clk_sys), - .din (rom_din_dbg[7:0]), - .dout (rom_dout[7:0]), - .en (rom_cen), - .we (rom_wen_dbg[0]) -); - - - -//============================================================================= -// 7) I/O CELLS -//============================================================================= - - -// Slide Switches (Port 1 inputs) -//-------------------------------- -IBUF SW7_PIN (.O(p3_din[7]), .I(SW7)); -IBUF SW6_PIN (.O(p3_din[6]), .I(SW6)); -IBUF SW5_PIN (.O(p3_din[5]), .I(SW5)); -IBUF SW4_PIN (.O(p3_din[4]), .I(SW4)); -IBUF SW3_PIN (.O(p3_din[3]), .I(SW3)); -IBUF SW2_PIN (.O(p3_din[2]), .I(SW2)); -IBUF SW1_PIN (.O(p3_din[1]), .I(SW1)); -IBUF SW0_PIN (.O(p3_din[0]), .I(SW0)); - -// LEDs (Port 1 outputs) -//----------------------- -OBUF LED7_PIN (.I(p3_dout[7] & p3_dout_en[7]), .O(LED7)); -OBUF LED6_PIN (.I(p3_dout[6] & p3_dout_en[6]), .O(LED6)); -OBUF LED5_PIN (.I(p3_dout[5] & p3_dout_en[5]), .O(LED5)); -OBUF LED4_PIN (.I(p3_dout[4] & p3_dout_en[4]), .O(LED4)); -OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3)); -OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2)); -OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1)); -OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0)); - -// Push Button Switches -//---------------------- -IBUF BTN2_PIN (.O(), .I(BTN2)); -IBUF BTN1_PIN (.O(), .I(BTN1)); -IBUF BTN0_PIN (.O(), .I(BTN0)); - -// Four-Sigit, Seven-Segment LED Display -//--------------------------------------- -OBUF SEG_A_PIN (.I(seg_a_), .O(SEG_A)); -OBUF SEG_B_PIN (.I(seg_b_), .O(SEG_B)); -OBUF SEG_C_PIN (.I(seg_c_), .O(SEG_C)); -OBUF SEG_D_PIN (.I(seg_d_), .O(SEG_D)); -OBUF SEG_E_PIN (.I(seg_e_), .O(SEG_E)); -OBUF SEG_F_PIN (.I(seg_f_), .O(SEG_F)); -OBUF SEG_G_PIN (.I(seg_g_), .O(SEG_G)); -OBUF SEG_DP_PIN (.I(seg_dp_), .O(SEG_DP)); -OBUF SEG_AN0_PIN (.I(seg_an0_), .O(SEG_AN0)); -OBUF SEG_AN1_PIN (.I(seg_an1_), .O(SEG_AN1)); -OBUF SEG_AN2_PIN (.I(seg_an2_), .O(SEG_AN2)); -OBUF SEG_AN3_PIN (.I(seg_an3_), .O(SEG_AN3)); - -// RS-232 Port -//---------------------- -// P1.1 (TX) and P2.2 (RX) -assign p1_io_din = 8'h00; -assign p2_io_din[7:3] = 5'h00; -assign p2_io_din[1:0] = 2'h0; - -// Mux the RS-232 port between IO port and the debug interface. -// The mux is controlled with the SW0 switch -wire uart_txd_out = p3_din[0] ? dbg_uart_txd : p1_io_dout[1]; -wire uart_rxd_in; -assign p2_io_din[2] = p3_din[0] ? 1'b1 : uart_rxd_in; -assign dbg_uart_rxd = p3_din[0] ? uart_rxd_in : 1'b1; - -IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD)); -OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD)); - -IBUF UART_RXD_A_PIN (.O(), .I(UART_RXD_A)); -OBUF UART_TXD_A_PIN (.I(1'b0), .O(UART_TXD_A)); - - -// PS/2 Mouse/Keyboard Port -//-------------------------- -IOBUF PS2_D_PIN (.O(), .I(1'b0), .T(1'b1), .IO(PS2_D)); -OBUF PS2_C_PIN (.I(1'b0), .O(PS2_C)); - -// Fast, Asynchronous SRAM -//-------------------------- -OBUF SRAM_A17_PIN (.I(1'b0), .O(SRAM_A17)); -OBUF SRAM_A16_PIN (.I(1'b0), .O(SRAM_A16)); -OBUF SRAM_A15_PIN (.I(1'b0), .O(SRAM_A15)); -OBUF SRAM_A14_PIN (.I(1'b0), .O(SRAM_A14)); -OBUF SRAM_A13_PIN (.I(1'b0), .O(SRAM_A13)); -OBUF SRAM_A12_PIN (.I(1'b0), .O(SRAM_A12)); -OBUF SRAM_A11_PIN (.I(1'b0), .O(SRAM_A11)); -OBUF SRAM_A10_PIN (.I(1'b0), .O(SRAM_A10)); -OBUF SRAM_A9_PIN (.I(1'b0), .O(SRAM_A9)); -OBUF SRAM_A8_PIN (.I(1'b0), .O(SRAM_A8)); -OBUF SRAM_A7_PIN (.I(1'b0), .O(SRAM_A7)); -OBUF SRAM_A6_PIN (.I(1'b0), .O(SRAM_A6)); -OBUF SRAM_A5_PIN (.I(1'b0), .O(SRAM_A5)); -OBUF SRAM_A4_PIN (.I(1'b0), .O(SRAM_A4)); -OBUF SRAM_A3_PIN (.I(1'b0), .O(SRAM_A3)); -OBUF SRAM_A2_PIN (.I(1'b0), .O(SRAM_A2)); -OBUF SRAM_A1_PIN (.I(1'b0), .O(SRAM_A1)); -OBUF SRAM_A0_PIN (.I(1'b0), .O(SRAM_A0)); -OBUF SRAM_OE_PIN (.I(1'b1), .O(SRAM_OE)); -OBUF SRAM_WE_PIN (.I(1'b1), .O(SRAM_WE)); -IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO15)); -IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO14)); -IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO13)); -IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO12)); -IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO11)); -IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO10)); -IOBUF SRAM0_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO9)); -IOBUF SRAM0_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO8)); -IOBUF SRAM0_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO7)); -IOBUF SRAM0_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO6)); -IOBUF SRAM0_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO5)); -IOBUF SRAM0_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO4)); -IOBUF SRAM0_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO3)); -IOBUF SRAM0_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO2)); -IOBUF SRAM0_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO1)); -IOBUF SRAM0_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO0)); -OBUF SRAM0_CE1_PIN (.I(1'b1), .O(SRAM0_CE1)); -OBUF SRAM0_UB1_PIN (.I(1'b1), .O(SRAM0_UB1)); -OBUF SRAM0_LB1_PIN (.I(1'b1), .O(SRAM0_LB1)); -IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO15)); -IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO14)); -IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO13)); -IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO12)); -IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO11)); -IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO10)); -IOBUF SRAM1_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO9)); -IOBUF SRAM1_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO8)); -IOBUF SRAM1_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO7)); -IOBUF SRAM1_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO6)); -IOBUF SRAM1_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO5)); -IOBUF SRAM1_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO4)); -IOBUF SRAM1_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO3)); -IOBUF SRAM1_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO2)); -IOBUF SRAM1_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO1)); -IOBUF SRAM1_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO0)); -OBUF SRAM1_CE2_PIN (.I(1'b1), .O(SRAM1_CE2)); -OBUF SRAM1_UB2_PIN (.I(1'b1), .O(SRAM1_UB2)); -OBUF SRAM1_LB2_PIN (.I(1'b1), .O(SRAM1_LB2)); - -// VGA Port -//--------------------------------------- -OBUF VGA_R_PIN (.I(1'b0), .O(VGA_R)); -OBUF VGA_G_PIN (.I(1'b0), .O(VGA_G)); -OBUF VGA_B_PIN (.I(1'b0), .O(VGA_B)); -OBUF VGA_HS_PIN (.I(1'b0), .O(VGA_HS)); -OBUF VGA_VS_PIN (.I(1'b0), .O(VGA_VS)); - - -endmodule // openMSP430_fpga -
trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.ngc =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.ngc (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$g:x53=#Zl|bdaa:!3-522):'9+(>5?0163?56789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012346=6&9;871c:1p656a|;?=!9??;98JJUSS2mce0:4?>0081JHI\31?58EABU4;4<7LJKR=1=3>GCL[6?2:5NDEP?1;169B@AT;1780N5=4BT10?GS302H^_RGAFN18GIM>3JEFADZ[EE58GWCF\LN>7IG30?78@L:66<1OE1<15:FJ86823MC783;4DH>6:0=CA5<596JF<6<5?AOW494>7IA30?78@J:66<1OC1<15:FL86823ME783;4DN>6:0=CG5<596J@<6<5?AIW49497H@>;F18CKB63@20ECG[P^23<>OIA]ZT<<64IOKWTZ6502CEEY^P02:8MKOSXV:?46GAIUR\40>98:KMMQVX8>30ECG[SUCWA2=NF@^T<=94IOKW[5703@DBXR>=7:KMMQY7;>1BBDZP0558MKOSW9?<7D@FT^253>OIA]U;;:5FNHV\4=11BBDZP1558MKOSW8?<7D@FT^353>OIA]U:;:5FNHV\5=1B69JJLRX9J=0ECG[_0F4?LHN\V;N;6GAIU]2B2=NF@^T>=94IOKW[7703@DBXR<=7:KMMQY5;>1BBDZP2558MKOSW;?<7D@FT^053>OIA]U9;:5FNHV\6=11BBDZP3558MKOSW:?<7D@FT^153>OIA]U8;:5FNHV\7=178;HLJPZ5F?2CEEYQH6=:1E=;=4N050?K7?;2D:5?5A229M655H5?:1E>5=4N3;1?K543G9;?6@<539M07=I=:1E98=4N4;1?K053G=97C6=;O;4?KCS_FX@=6A>;Q68TDTSi2ZBBRLZSHF[f>VNFVH^_COBE89QEHD6>VY2:6]@USAF1>UU^HF87^]]4:VZT@g<]ZOYSLBFARa8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J2:UFf>QUA]OTJD\\T`9TVLRBWDEOI^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf>1jhi|'0(58eabu 8#37ljkr)33-2=flmx#>$94aefq,6/03hno~%:&7:cg`w.2!>1jhi|'6(58eabu >#<7ljkr):*3>gcl{"2%:5ndep?4;g50?:8eabu48:5;6okds>2:2=flmx7>394aefq86803hno~1:17:cg`w:26>1jhi|36?58eabu4>4<7ljkr=:=3>gcl{622?74bminahuwW!.Wimkm|%EHZL*Lick}aumq$46)9:1h`f84dhl+4,016:fjj919?2ndyy&?)69gkpr/9 =0hb{{(3+4?air|!9";6j`uu*7-2=cg|~#9$94dnww,3/03me~x%9&7:flqq:76>1ocxz31?58`jss4;4<7iazt=1=3>bh}}6?2:5kotv?1;11a}!Pcf-qkhY?p;aTdd agn08s`{GHy3<7MNwf78E>1<6sZ;26k<53;306=c>n38>=h9tnc795>he>3>0(o=5b09~W4>=n;086<==8d;e>736m>1X;l4i4;29564?m0l1>8?j9:Q23ml>6=4>:0yP5<<7e8d9607b?2|_m;4?:082>77|[831j?4<:011<`?a2;?:i:5+ae84f>Pe<38py:m51:w4`?64c==38:wEom;[35>6}02?0?6p*n9;d6?!d52jo0ek=50;9jgc<722en47>5$`69b5=ii:0;76aj7;29 d2=n91em>4>;:mf2?6=,h>1j=5aa281?>ib=3:1(l:5f19me6<432en87>5$`69b5=ii:0?76aj3;29 d2=n91em>4:;:mf6?6=,h>1j=5aa285?>ib93:1(l:5f19me6<032co;7>5$`69`c=ii:0;76gk6;29 d2=lo1em>4>;:kg1?6=,h>1hk5aa281?>oc<3:1(l:5dg9me6<432co?7>5$`69`c=ii:0?76gk2;29 d2=lo1em>4:;:kg5?6=,h>1hk5aa285?>oc83:1(l:5dg9me6<032cm;7>5;h`:>5<#i=0h?6`n3;28?le6290/m94l3:lb7?7<3`i;6=4+a58`7>hf;3807dli:18'e15<#i=0h?6`n3;68?ldc290/m94l3:lb7?3<3`hh6=4+a58`7>hf;3<07dlm:18'e15<#i=0h?6`n3;:8?ld?290/m94l3:lb7??<3`h<6=4+a58`7>hf;3k07ool:182>5<7sAki7)o6:`a8kd7=831vn?k50;394?6|@hh0(l752d9l6a<722wi=94?:383>5}Oik1/m4489:k1b?6=3fk;6=44}c36>5<5290;wEom;%c:>2?>{e9:0;6??50;2xLdd<,h31m85+3881?!5f2;1/?o4=;%1`>7=#;m097)=j:39'7c<53->;6?5+4081?!252;1/8>4=;%67>7=#<<097):9:39'02<53->36?5+4881?!2f2;1/8o4=;%6`>7=#4=;%77>7=#=<097);9:39'12<53-?36?5+5881?!3f2;1/9o4=;%7`>7=#=m097);j:39'1c<53-<;6?5+6081?!052;1/:>4=;%47>7=#><097)89:39'22<53-<36?5+6881?!0f2;1/:o4=;%4`>7=#>m097)8j:39'2c<53-=;6?5+7081?!152;1/;>4=;%57>7=#?<097)99:39'32<53-=36?5+3181?!562;1/??4=;%10>7=#;=097)=::39'73<53-9<6?5+b18bb>"403;0(l951:k2e?6=3`;i6=44i883>>o6k3:17d?k:188m4c=831b=k4?::k14?6=3`8h6=44i3394?=n03:17b5;h`94?=h::0;66gl:188k72=831bh7>5;n06>5<:4?::k24?6=3`kn6=44o3:94?=n980;66a=9;29?l752900c?o50;9j67<722cj47>5;|q4a?6=;r79i7d><5891>?5rsb694?4|Vk301<=59:&be?>>3tyhh7>52z\`5>;6;3;97)on:868yved2909wSm?;<30>47<,hk15:5rsb`94?4|Vkl01<=5119'ed<>02wxol4?:3y]f`=:9:0m7)on:8`8yve>2909wSlk;<30>`=#ih02o6s|c983>7}Yjj16=>4k;%cb>l0q~m::181[d?34;86l5+a`8;4>{tk;0;6?uQb69>565<5sWim70?<:058 dg=0;1vh>50;0xZa1<5891><5+a`8;7>{tll0;6?uQd79>56<582.jm76;;|qg`?6=:rTo963>3;3e?!gf21?0q~jl:181[b334;86"fi3237p}k9;296~Xc927:?7?m;%cb>=g7}Ym>16=>4=9:&be?>c3tyni7>52z\f2>;6;3837)on:9g8yvcc2909wSk:;<30>71<,hk14k5rsda94?4|Vl>01<=5279'ed<>82wxio4?:3y]a6=:9:0996*na;;2?xubi3:1>vPj2:?27?433-kj64<4}rg:>5<5sWo:70?<:318 dg=1:1vk=50;0xZc5<58>1>k5+a`8:1>{tn>0;6?uQf69>50<5n2.jm779;|q:=?6=:r7:87o?;<30>7ed6<5891mh5r}o76>5<6sAki7p`:6;295~Nfj2we9:4?:0yKeg=zf<21<7?tH``8yk3>290:wEom;|l6e?6=9rBjn6sa5c83>4}Oik1vb8m50;3xLdd{Ica?xh2m3:1=vFnb:m1c<728qCmo5rn7294?7|@hh0qc8>:182Mge3td=>7>51zJbf>{i>:0;65<6sAki7p`96;295~Nfj2we::4?:0yKeg=zf?21<7?tH``8yk0>290:wEom;|l5e?6=9rBjn6sa6c83>4}Oik1vb;m50;3xLdd{Ica?xh1m3:1=vFnb:m2c<728qCmo5rn6294?7|@hh0qc9>:182Mge3td<>7>51zJbf>{i?:0;65<6sAki7psr}AB@<1==8?:nllr@A@x4xFGXrwKL \ No newline at end of file
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_readme.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_readme.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_readme.txt (nonexistent) @@ -1,43 +0,0 @@ -The following files were generated for 'ram_8x512_hi' in directory -/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/: - -ram_8x512_hi.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -ram_8x512_hi.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -ram_8x512_hi.sym: - Please see the core data sheet. - -ram_8x512_hi.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -ram_8x512_hi.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -ram_8x512_hi.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -ram_8x512_hi_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -ram_8x512_hi_readme.txt: - Text file indicating the files generated and how they are used. - -ram_8x512_hi_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.log =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.log (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.log (nonexistent) @@ -1,39 +0,0 @@ -Welcome to Xilinx CORE Generator. -Opened project file -/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coreg -en/coregen.cgp. -Customizing IP... - WARNING! Program tries to unlock a connection without having acquired - a lock first, which indicates a programming error. - There will be no further warnings about this issue. -libxcb: WARNING! Program tries to lock an already locked connection, - which indicates a programming error. - There will be no further warnings about this issue. -Finished Customizing. -Generating IP... - WARNING! Program tries to unlock a connection without having acquired - a lock first, which indicates a programming error. - There will be no further warnings about this issue. -libxcb: WARNING! Program tries to lock an already locked connection, - which indicates a programming error. - There will be no further warnings about this issue. -Generating Implementation files. -Generating ISE symbol file... -Generating NGC file. -Finished Generating. -Successfully generated rom_8x2k_hi. -Customizing IP... -Finished Customizing. -Generating IP... - WARNING! Program tries to unlock a connection without having acquired - a lock first, which indicates a programming error. - There will be no further warnings about this issue. -libxcb: WARNING! Program tries to lock an already locked connection, - which indicates a programming error. - There will be no further warnings about this issue. -Generating Implementation files. -Generating ISE symbol file... -Generating NGC file. -Finished Generating. -Successfully generated rom_8x2k_lo. -Closed project file.
trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.log Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_xmdf.tcl =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_xmdf.tcl (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_xmdf.tcl (nonexistent) @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide ram_8x512_hi_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::ram_8x512_hi_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::ram_8x512_hi_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name ram_8x512_hi -} -# ::ram_8x512_hi_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::ram_8x512_hi_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_hi_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram_8x512_hi -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_flist.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_flist.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_flist.txt (nonexistent) @@ -1,9 +0,0 @@ -# Output products list for -rom_8x2k_hi.asy -rom_8x2k_hi.ngc -rom_8x2k_hi.sym -rom_8x2k_hi.v -rom_8x2k_hi.veo -rom_8x2k_hi.xco -rom_8x2k_hi_flist.txt -rom_8x2k_hi_xmdf.tcl
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.ngc =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.ngc (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$g:x53=#Zl|bdaa:!3-522):'9+(>5?0163?56789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012346=6&9;871c:1p656a|;?=!9??;98JJUSS2mce0:4?>0081JHI\31?58EABU4;4<7LJKR=1=3>GCL[6?2:5NDEP?1;169B@AT;1780N5=4BT10?GS302H^_RGAFN18GIM>3JEFADZ[EE58GWCF\LN>7IG30?78@L:66<1OE1<15:FJ86823MC783;4DH>6:0=CA5<596JF<6<5?AOW494>7IA30?78@J:66<1OC1<15:FL86823ME783;4DN>6:0=CG5<596J@<6<5?AIW49497H@>;F18CKB63@20ECG[P^23<>OIA]ZT<<64IOKWTZ6502CEEY^P02:8MKOSXV:?46GAIUR\40>98:KMMQVX8>30ECG[SUCWA2=NF@^T<=94IOKW[5703@DBXR>=7:KMMQY7;>1BBDZP0558MKOSW9?<7D@FT^253>OIA]U;;:5FNHV\4=11BBDZP1558MKOSW8?<7D@FT^353>OIA]U:;:5FNHV\5=1B69JJLRX9J=0ECG[_0F4?LHN\V;N;6GAIU]2B2=NF@^T>=94IOKW[7703@DBXR<=7:KMMQY5;>1BBDZP2558MKOSW;?<7D@FT^053>OIA]U9;:5FNHV\6=11BBDZP3558MKOSW:?<7D@FT^153>OIA]U8;:5FNHV\7=178;HLJPZ5F?2CEEYQH6=:1E=;=4N050?K7?;2D:5?5A229M655H5?:1E>5=4N3;1?K543G9;?6@<539M07=I=:1E98=4N4;1?K053G=97C6=;O;4?KCS_FX@=6A>;Q68TDTSi2ZBBRLZSHF[f>VNFVH^_COBE89QEHD6>VY2:6]@USAF1>UU^HF87^]]4:VZT@g<]ZOYSLBFARa8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J2:UFf>QUA]OTJD\\T`9TVLRBWDEOI^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf>1jhi|'0(58eabu 8#37ljkr)33-2=flmx#>$94aefq,6/03hno~%:&7:cg`w.2!>1jhi|'6(58eabu >#<7ljkr):*3>gcl{"2%:5ndep?4;g50?:8eabu48:5;6okds>2:2=flmx7>394aefq86803hno~1:17:cg`w:26>1jhi|36?58eabu4>4<7ljkr=:=3>gcl{622?74bminahuwW!.Wimkm|%EHZL*Lick}aumq$46)9:1h`f84dhl+4,016:fjj919?2ndyy&?)69gkpr/9 =0hb{{(3+4?air|!9";6j`uu*7-2=cg|~#9$94dnww,3/03me~x%9&7:flqq:76>1ocxz31?58`jss4;4<7iazt=1=3>bh}}6?2:5kotv?1;11a}!Pcf-qkhY?p;aT`b agn08s`{GHy3<7MNwf78E>1<6sZ;26k<53;306=c>n38>>9=tnc795>he>3>0(o=5b09~W4>=n;086<==8d;e>735<:1X;l4i4;29564?m0l1>8<;4:Q26=4>:0yP5<<7e8d96043;2|_m;4?:082>77|[831j?4<:011<`?a2;?98>5+ae84f>Pe<38py:m51:w4`?64c==38:wEom;[35>6}02?0?6p*n9;d6?!d52jo0ek=50;9jgc<722en47>5$`69b5=ii:0;76aj7;29 d2=n91em>4>;:mf2?6=,h>1j=5aa281?>ib=3:1(l:5f19me6<432en87>5$`69b5=ii:0?76aj3;29 d2=n91em>4:;:mf6?6=,h>1j=5aa285?>ib93:1(l:5f19me6<032co;7>5$`69`c=ii:0;76gk6;29 d2=lo1em>4>;:kg1?6=,h>1hk5aa281?>oc<3:1(l:5dg9me6<432co?7>5$`69`c=ii:0?76gk2;29 d2=lo1em>4:;:kg5?6=,h>1hk5aa285?>oc83:1(l:5dg9me6<032cm;7>5;h`:>5<#i=0h?6`n3;28?le6290/m94l3:lb7?7<3`i;6=4+a58`7>hf;3807dli:18'e15<#i=0h?6`n3;68?ldc290/m94l3:lb7?3<3`hh6=4+a58`7>hf;3<07dlm:18'e15<#i=0h?6`n3;:8?ld?290/m94l3:lb7??<3`h<6=4+a58`7>hf;3k07ool:182>5<7sAki7)o6:`a8kd7=831vn?k50;394?6|@hh0(l752d9l6a<722wi=94?:383>5}Oik1/m4489:k1b?6=3fk;6=44}c36>5<5290;wEom;%c:>2?>{e9:0;6??50;2xLdd<,h31m85+3881?!5f2;1/?o4=;%1`>7=#;m097)=j:39'7c<53->;6?5+4081?!252;1/8>4=;%67>7=#<<097):9:39'02<53->36?5+4881?!2f2;1/8o4=;%6`>7=#4=;%77>7=#=<097);9:39'12<53-?36?5+5881?!3f2;1/9o4=;%7`>7=#=m097);j:39'1c<53-<;6?5+6081?!052;1/:>4=;%47>7=#><097)89:39'22<53-<36?5+6881?!0f2;1/:o4=;%4`>7=#>m097)8j:39'2c<53-=;6?5+7081?!152;1/;>4=;%57>7=#?<097)99:39'32<53-=36?5+3181?!562;1/??4=;%10>7=#;=097)=::39'73<53-9<6?5+b18bb>"403;0(l951:k2e?6=3`;i6=44i883>>o6k3:17d?k:188m4c=831b=k4?::k14?6=3`8h6=44i3394?=n03:17b5;h`94?=h::0;66gl:188k72=831bh7>5;n06>5<:4?::k24?6=3`kn6=44o3:94?=n980;66a=9;29?l752900c?o50;9j67<722cj47>5;|q4a?6=;r79i7d><5891>?5rsb694?4|Vk301<=59:&be?>>3tyhh7>52z\`5>;6;3;97)on:868yved2909wSm?;<30>47<,hk15:5rsb`94?4|Vkl01<=5119'ed<>02wxol4?:3y]f`=:9:0m7)on:8`8yve>2909wSlk;<30>`=#ih02o6s|c983>7}Yjj16=>4k;%cb>l0q~m::181[d?34;86l5+a`8;4>{tk;0;6?uQb69>565<5sWim70?<:058 dg=0;1vh>50;0xZa1<5891><5+a`8;7>{tll0;6?uQd79>56<582.jm76;;|qg`?6=:rTo963>3;3e?!gf21?0q~jl:181[b334;86"fi3237p}k9;296~Xc927:?7?m;%cb>=g7}Ym>16=>4=9:&be?>c3tyni7>52z\f2>;6;3837)on:9g8yvcc2909wSk:;<30>71<,hk14k5rsda94?4|Vl>01<=5279'ed<>82wxio4?:3y]a6=:9:0996*na;;2?xubi3:1>vPj2:?27?433-kj64<4}rg:>5<5sWo:70?<:318 dg=1:1vk=50;0xZc5<58>1>k5+a`8:1>{tn>0;6?uQf69>50<5n2.jm779;|q:=?6=:r7:87o?;<30>7ed6<5891mh5r}o76>5<6sAki7p`:6;295~Nfj2we9:4?:0yKeg=zf<21<7?tH``8yk3>290:wEom;|l6e?6=9rBjn6sa5c83>4}Oik1vb8m50;3xLdd{Ica?xh2m3:1=vFnb:m1c<728qCmo5rn7294?7|@hh0qc8>:182Mge3td=>7>51zJbf>{i>:0;65<6sAki7p`96;295~Nfj2we::4?:0yKeg=zf?21<7?tH``8yk0>290:wEom;|l5e?6=9rBjn6sa6c83>4}Oik1vb;m50;3xLdd{Ica?xh1m3:1=vFnb:m2c<728qCmo5rn6294?7|@hh0qc9>:182Mge3td<>7>51zJbf>{i?:0;65<6sAki7psr}AB@<1=jj;;5;7i}ABA5{GHYqvLM \ No newline at end of file
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_readme.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_readme.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_readme.txt (nonexistent) @@ -1,43 +0,0 @@ -The following files were generated for 'ram_8x512_lo' in directory -/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/: - -ram_8x512_lo.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -ram_8x512_lo.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -ram_8x512_lo.sym: - Please see the core data sheet. - -ram_8x512_lo.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -ram_8x512_lo.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -ram_8x512_lo.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -ram_8x512_lo_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -ram_8x512_lo_readme.txt: - Text file indicating the files generated and how they are used. - -ram_8x512_lo_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.ngc =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.ngc (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$g0x53=#Zl|bdaa:!3-522):'9+(>5?0163?56789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012346=6&9i0?~665OTVSQQ1109:>LHW]]0jhi|38;2=3>GCL[6;255NDEP?55803HNO^1?17:CG@W:56>1JHI\33?58EABU4=4<7LJKR=7=3>GCL[6=2:5NDEP?3;115:FJ84823MC7>3;4DH>0:0=CA5>596JF<4<6?AO;>7?0HD28>79GMU:76<1OC1>15:FL84823ME7>3;4DN>0:0=CG5>596J@<4<6?AI;>7?0HB28>79GKU:76;1NB<5H3:EM@4=N02CEEY^P01:8MKOSXV::46GAIUR\47><8:KMMQVX8=20ECG[P^26<>OIA]ZT<;64IOKWTZ6012CEEY][AUG4?LHN\V:;;6GAIU]352=NF@^T;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D11BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D11BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1L8;HLJPZ5D?2CEEYQ2FDMIKK7:NLCLEFDj1Fmga}Vdppmjhd3DcecXjrrklj7=I8:1E===4N030?K75;2D:?>5A1518J4343G;=?6@>729M5=5H59:1E>?=4N310?K43;2D99>5A2718J7143G83>6@<3:L077=I<;1E9>5A5018J0353G<97C9=;O:1?K?03GO_[B\D1:M2?U2R^XLk0Y^K]_@NJEVe<]ZOYS[G\ICNF7>PDK01]EHYPTXRF6>QBj2]YEYKPFHPPPd=PZ@^NS@AKE0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFIc9[[FIUMVCEJB84Xe`\Ma`1jhi|33?58eabu4=4<7ljkr=7=3>gcl{6=2:5ndep?3;?69b`at;07827obdmdoptZp1W;&+Tdbfny"@KWC'Oldn~lz`r!33*45#=7iga<1<5?aoi484=7iga<3<5?aoi4:4=7iga<5<5?aoi4<4=7iga<7<;?aoi4>0;2;5kio>4:2=cg|~#<$94dnww,4/03me~x%<&7:flqq.4!>1ocxz'4(58`jss <#<7iazt)4*3>bh}}"<%:5kotv?4;169gkpr;<7=0hb{{<4<4?air|5<556j`uu>4>5803me~x1918:ggmc4iom80ic64nfaaqljck2xjaR6w500\ll7?3}g{#Rmh/scn[=~29;Uce#`ho39taxFGx0;0LMvi0;D90?7|[831in4<:011<`412;9<8ouab282?kd32=1/n<4nf:P5=<7e3496613j2Yb:?09?::l;R3;>`c=83;8>5k=6;0031b51;395c}T900no7=5120;a70=::=?n6*nb;5a?Sd52;q~;n4>;t5g>5=z,h:186ljf;295f<228lpDl74Z0497~0==3=1q)o8:dd8 g6=k11bii4?::k`=?6=3fo96=4+a38fe>hf93:07bk>:18'e75<#i;0nm6`n1;08?jba290/m?4ja:lb5?5<3fnn6=4+a38fe>hf93>07bjk:18'e75<#i;0nm6`n1;48?jbe290/m?4ja:lb5?1<3`n:6=4+a38g=>hf93:07dj?:18'e75<#i;0o56`n1;08?leb290/m?4k9:lb5?5<3`io6=4+a38g=>hf93>07dml:18'e75<#i;0o56`n1;48?lef290/m?4k9:lb5?1<3`l:6=44icf94?"f:3i=7co>:198mge=83.j>7m9;oc2>4=54ic;94?"f:3i=7co>:598mg>=83.j>7m9;oc2>0=:998fdg=83;1<7>tH`;8 d1=ih1d5k4?::a6`<7280;6=uGa89'e2<5m2e9h7>5;|`20?6=:3:13`8m6=44o8g94?=zj8?1<7<50;2xLd?<,h=1;45f2g83>>i>m3:17pl>3;2964<729qCm45+a68b7>"41380(>o52:&0f?4<,:i1>6*"39380(9<52:&77?4<,=>1>6*;5;08 10=:2.?;7<4$5:96>"31380(9o52:&7f?4<,=i1>6*;d;08 1c=:2.?j7<4$4296>"29380(8<52:&67?4<,<>1>6*:5;08 00=:2.>;7<4$4:96>"21380(8o52:&6f?4<,6*:d;08 0c=:2.>j7<4$7296>"19380(;<52:&57?4<,?>1>6*95;08 30=:2.=;7<4$7:96>"11380(;o52:&5f?4<,?i1>6*9d;08 3c=:2.=j7<4$6296>"09380(:<52:&47?4<,>>1>6*85;08 20=:2.<;7<4$6:96>"48380(>?52:&06?4<,:91>6*<4;08 63=:2.8:7<4$2596>"fm3ko7)=7:09'e0<63`;j6=44i0`94?=n13:17d?l:188m4b=831b=h4?::k2b?6=3`8;6=44i3a94?=n:80;66g7:188k7d=831b=:4?::kb>5<94?::kg>5<1;29?j4>2900e<<50;9l6d<722c9>7>5;hc5>5<7b<5891m;5212826>;6;3301<=5239~wf1=838pRoj4=01954=#i10356s|c483>7}Yjj16=>4>0:&b52z\af>;6;3l0(l65949~wf5=838pRoo4=019a>"f033=7p}l2;296~Xe127:?7j4$`:9=<=z{j;1<73;`8 d>=1k1voh50;0xZg0<5891m6*n8;;`?xuem3:1>vPm5:?27?><,h21;k5rsb;94?4|Vj301<=5169'e=vPk0:?27?473-k365<4}rf4>5<5sWim70?<:0d8 d>=0:1vi850;0xZfc<5891=h5+a98;0>{tl<0;6?uQce9>56<6l2.j476:;|qg0?6=:rTho63>3;3`?!g?21<0q~j<:181[ee34;86"f032j7p}j9;296~Xb927:?7<6;%c;>=d7}Yll16=>4=6:&bb3tyn97>52z\g`>;6;38>7)o7:9d8yvc32909wSjl;<30>72<,h215=5rsd194?4|Vmh01<=5229'e=<>92wxii4?:3y]aa=:9=09j6*n8;;1?xua93:1>vPi1:?21?4a3-k364:4}r;4>5<5s4;?64k4=0196f=z{021<73td>97>51zJb=>{i=?0;65<6sAk27p`:9;295~Nf12we9l4?:0yKe<=zf4}Oi01vb8h50;3xLd?{Ic:?xh193:1=vFn9:m27<728qCm45rn7194?7|@h30qc8;:182Mg>3td=97>51zJb=>{i>?0;65<6sAk27p`99;295~Nf12we:l4?:0yKe<=zf?h1<7?tH`;8yk0d290:wEo6;|l5`?6=9rBj56sa6d83>4}Oi01vb;h50;3xLd?{Ic:?xh093:1=vFn9:~yxFGKr3:65?l5`5f=xFGJr:vLM^t}AB \ No newline at end of file
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_xmdf.tcl =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_xmdf.tcl (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_xmdf.tcl (nonexistent) @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide ram_8x512_lo_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::ram_8x512_lo_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::ram_8x512_lo_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name ram_8x512_lo -} -# ::ram_8x512_lo_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::ram_8x512_lo_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_lo_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram_8x512_lo -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.xco =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.xco (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.xco (nonexistent) @@ -1,63 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.31 -# Date: Wed May 27 15:20:41 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s200 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ft256 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET component_name=rom_8x2k_hi -CSET depth=2048 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_Low -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=false -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_Low -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 9ba16db6 -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.veo =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.veo (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.veo (nonexistent) @@ -1,48 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -rom_8x2k_hi YourInstanceName ( - .addr(addr), // Bus [10 : 0] - .clk(clk), - .din(din), // Bus [7 : 0] - .dout(dout), // Bus [7 : 0] - .en(en), - .we(we)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file rom_8x2k_hi.v when simulating -// the core, rom_8x2k_hi. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_flist.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_flist.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_flist.txt (nonexistent) @@ -1,9 +0,0 @@ -# Output products list for -rom_8x2k_lo.asy -rom_8x2k_lo.ngc -rom_8x2k_lo.sym -rom_8x2k_lo.v -rom_8x2k_lo.veo -rom_8x2k_lo.xco -rom_8x2k_lo_flist.txt -rom_8x2k_lo_xmdf.tcl
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_readme.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_readme.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_readme.txt (nonexistent) @@ -1,43 +0,0 @@ -The following files were generated for 'rom_8x2k_hi' in directory -/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/: - -rom_8x2k_hi.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -rom_8x2k_hi.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -rom_8x2k_hi.sym: - Please see the core data sheet. - -rom_8x2k_hi.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -rom_8x2k_hi.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -rom_8x2k_hi.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -rom_8x2k_hi_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -rom_8x2k_hi_readme.txt: - Text file indicating the files generated and how they are used. - -rom_8x2k_hi_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.asy =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.asy (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.asy (nonexistent) @@ -1,27 +0,0 @@ -Version 4 -SymbolType BLOCK -RECTANGLE Normal 32 0 320 272 -PIN 0 48 LEFT 36 -PINATTR PinName addr[10:0] -PINATTR Polarity IN -LINE Wide 0 48 32 48 -PIN 0 80 LEFT 36 -PINATTR PinName din[7:0] -PINATTR Polarity IN -LINE Wide 0 80 32 80 -PIN 0 112 LEFT 36 -PINATTR PinName we -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 144 LEFT 36 -PINATTR PinName en -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 240 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 352 48 RIGHT 36 -PINATTR PinName dout[7:0] -PINATTR Polarity OUT -LINE Wide 320 48 352 48
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_flist.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_flist.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_flist.txt (nonexistent) @@ -1,9 +0,0 @@ -# Output products list for -ram_8x512_hi.asy -ram_8x512_hi.ngc -ram_8x512_hi.sym -ram_8x512_hi.v -ram_8x512_hi.veo -ram_8x512_hi.xco -ram_8x512_hi_flist.txt -ram_8x512_hi_xmdf.tcl
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.ngc =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.ngc (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$g0x53=#Zl|bdaa:!3-522):'9+(>5?0163?56789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012346=6&9i0?~665OTVSQQ1109:>LHW]]0jhi|38;2=3>GCL[6;255NDEP?55803HNO^1?17:CG@W:56>1JHI\33?58EABU4=4<7LJKR=7=3>GCL[6=2:5NDEP?3;115:FJ84823MC7>3;4DH>0:0=CA5>596JF<4<6?AO;>7?0HD28>79GMU:76<1OC1>15:FL84823ME7>3;4DN>0:0=CG5>596J@<4<6?AI;>7?0HB28>79GKU:76;1NB<5H3:EM@4=N02CEEY^P01:8MKOSXV::46GAIUR\47><8:KMMQVX8=20ECG[P^26<>OIA]ZT<;64IOKWTZ6012CEEY][AUG4?LHN\V:;;6GAIU]352=NF@^T;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D11BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D11BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1L8;HLJPZ5D?2CEEYQ2FDMIKK7:NLCLEFDj1Fmga}Vdppmjhd3DcecXjrrklj7=I8:1E===4N030?K75;2D:?>5A1518J4343G;=?6@>729M5=5H59:1E>?=4N310?K43;2D99>5A2718J7143G83>6@<3:L077=I<;1E9>5A5018J0353G<97C9=;O:1?K?03GO_[B\D1:M2?U2R^XLk0Y^K]_@NJEVe<]ZOYS[G\ICNF7>PDK01]EHYPTXRF6>QBj2]YEYKPFHPPPd=PZ@^NS@AKE0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFIc9[[FIUMVCEJB84Xe`\Ma`1jhi|33?58eabu4=4<7ljkr=7=3>gcl{6=2:5ndep?3;?69b`at;07827obdmdoptZp1W;&+Tdbfny"@KWC'Oldn~lz`r!33*45#=7iga<1<5?aoi484=7iga<3<5?aoi4:4=7iga<5<5?aoi4<4=7iga<7<;?aoi4>0;2;5kio>4:2=cg|~#<$94dnww,4/03me~x%<&7:flqq.4!>1ocxz'4(58`jss <#<7iazt)4*3>bh}}"<%:5kotv?4;169gkpr;<7=0hb{{<4<4?air|5<556j`uu>4>5803me~x1918:ggmc4iom80ic64nfaaqljck2xjaR6w500\hj7?3}g{#Rmh/scn[=~29;Ugc#`ho39taxFGx0;0LMvi0;D90?7|[831in4<:011<`412;9<7e349661f92Yb:?09?:o=;R3;>`c=83;8>5k=6;003d451;395c}T900no7=5120;a70=::=j=6*nb;5a?Sd52;q~;n4>;t5g>5=z,h:186ljf;295f<228lpDl74Z0497~0==3=1q)o8:dd8 g6=k11bii4?::k`=?6=3fo96=4+a38fe>hf93:07bk>:18'e75<#i;0nm6`n1;08?jba290/m?4ja:lb5?5<3fnn6=4+a38fe>hf93>07bjk:18'e75<#i;0nm6`n1;48?jbe290/m?4ja:lb5?1<3`n:6=4+a38g=>hf93:07dj?:18'e75<#i;0o56`n1;08?leb290/m?4k9:lb5?5<3`io6=4+a38g=>hf93>07dml:18'e75<#i;0o56`n1;48?lef290/m?4k9:lb5?1<3`l:6=44icf94?"f:3i=7co>:198mge=83.j>7m9;oc2>4=54ic;94?"f:3i=7co>:598mg>=83.j>7m9;oc2>0=:998fdg=83;1<7>tH`;8 d1=ih1d5k4?::a6`<7280;6=uGa89'e2<5m2e9h7>5;|`20?6=:3:13`8m6=44o8g94?=zj8?1<7<50;2xLd?<,h=1;45f2g83>>i>m3:17pl>3;2964<729qCm45+a68b7>"41380(>o52:&0f?4<,:i1>6*"39380(9<52:&77?4<,=>1>6*;5;08 10=:2.?;7<4$5:96>"31380(9o52:&7f?4<,=i1>6*;d;08 1c=:2.?j7<4$4296>"29380(8<52:&67?4<,<>1>6*:5;08 00=:2.>;7<4$4:96>"21380(8o52:&6f?4<,6*:d;08 0c=:2.>j7<4$7296>"19380(;<52:&57?4<,?>1>6*95;08 30=:2.=;7<4$7:96>"11380(;o52:&5f?4<,?i1>6*9d;08 3c=:2.=j7<4$6296>"09380(:<52:&47?4<,>>1>6*85;08 20=:2.<;7<4$6:96>"48380(>?52:&06?4<,:91>6*<4;08 63=:2.8:7<4$2596>"fm3ko7)=7:09'e0<63`;j6=44i0`94?=n13:17d?l:188m4b=831b=h4?::k2b?6=3`8;6=44i3a94?=n:80;66g7:188k7d=831b=:4?::kb>5<94?::kg>5<1;29?j4>2900e<<50;9l6d<722c9>7>5;hc5>5<7b<5891m;5212826>;6;3301<=5239~wf1=838pRoj4=01954=#i10356s|c483>7}Yjj16=>4>0:&b52z\af>;6;3l0(l65949~wf5=838pRoo4=019a>"f033=7p}l2;296~Xe127:?7j4$`:9=<=z{j;1<73;`8 d>=1k1voh50;0xZg0<5891m6*n8;;`?xuem3:1>vPm5:?27?><,h21;k5rsb;94?4|Vj301<=5169'e=vPk0:?27?473-k365<4}rf4>5<5sWim70?<:0d8 d>=0:1vi850;0xZfc<5891=h5+a98;0>{tl<0;6?uQce9>56<6l2.j476:;|qg0?6=:rTho63>3;3`?!g?21<0q~j<:181[ee34;86"f032j7p}j9;296~Xb927:?7<6;%c;>=d7}Yll16=>4=6:&bb3tyn97>52z\g`>;6;38>7)o7:9d8yvc32909wSjl;<30>72<,h215=5rsd194?4|Vmh01<=5229'e=<>92wxii4?:3y]aa=:9=09j6*n8;;1?xua93:1>vPi1:?21?4a3-k364:4}r;4>5<5s4;?64k4=0196f=z{021<73td>97>51zJb=>{i=?0;65<6sAk27p`:9;295~Nf12we9l4?:0yKe<=zf4}Oi01vb8h50;3xLd?{Ic:?xh193:1=vFn9:m27<728qCm45rn7194?7|@h30qc8;:182Mg>3td=97>51zJb=>{i>?0;65<6sAk27p`99;295~Nf12we:l4?:0yKe<=zf?h1<7?tH`;8yk0d290:wEo6;|l5`?6=9rBj56sa6d83>4}Oi01vb;h50;3xLd?{Ic:?xh093:1=vFn9:~yxFGKr3:6imk127:exFGJr:vLM^t}AB \ No newline at end of file
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.ngc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_xmdf.tcl =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_xmdf.tcl (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_xmdf.tcl (nonexistent) @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide rom_8x2k_hi_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::rom_8x2k_hi_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::rom_8x2k_hi_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name rom_8x2k_hi -} -# ::rom_8x2k_hi_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::rom_8x2k_hi_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_hi_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom_8x2k_hi -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.xco =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.xco (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.xco (nonexistent) @@ -1,63 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.31 -# Date: Wed May 27 15:21:33 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s200 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ft256 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET component_name=rom_8x2k_lo -CSET depth=2048 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_Low -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=false -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_Low -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 648b0470 -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.veo =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.veo (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.veo (nonexistent) @@ -1,48 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -rom_8x2k_lo YourInstanceName ( - .addr(addr), // Bus [10 : 0] - .clk(clk), - .din(din), // Bus [7 : 0] - .dout(dout), // Bus [7 : 0] - .en(en), - .we(we)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file rom_8x2k_lo.v when simulating -// the core, rom_8x2k_lo. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v (nonexistent) @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file rom_8x2k_hi.v when simulating -// the core, rom_8x2k_hi. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module rom_8x2k_hi( - addr, - clk, - din, - dout, - en, - we); - - -input [10 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(11), - .c_default_data("0"), - .c_depth(2048), - .c_enable_rlocs(0), - .c_has_default_data(1), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("mif_file_16_1"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(0), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(0), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of rom_8x2k_hi is "black_box" - -endmodule -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock (nonexistent)
trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl (nonexistent)
trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject (nonexistent)
trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_readme.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_readme.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_readme.txt (nonexistent) @@ -1,43 +0,0 @@ -The following files were generated for 'rom_8x2k_lo' in directory -/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/: - -rom_8x2k_lo.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -rom_8x2k_lo.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -rom_8x2k_lo.sym: - Please see the core data sheet. - -rom_8x2k_lo.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -rom_8x2k_lo.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -rom_8x2k_lo.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -rom_8x2k_lo_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -rom_8x2k_lo_readme.txt: - Text file indicating the files generated and how they are used. - -rom_8x2k_lo_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_readme.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.asy =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.asy (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.asy (nonexistent) @@ -1,27 +0,0 @@ -Version 4 -SymbolType BLOCK -RECTANGLE Normal 32 0 320 272 -PIN 0 48 LEFT 36 -PINATTR PinName addr[10:0] -PINATTR Polarity IN -LINE Wide 0 48 32 48 -PIN 0 80 LEFT 36 -PINATTR PinName din[7:0] -PINATTR Polarity IN -LINE Wide 0 80 32 80 -PIN 0 112 LEFT 36 -PINATTR PinName we -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 144 LEFT 36 -PINATTR PinName en -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 240 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 352 48 RIGHT 36 -PINATTR PinName dout[7:0] -PINATTR Polarity OUT -LINE Wide 320 48 352 48
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.veo =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.veo (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.veo (nonexistent) @@ -1,48 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -ram_8x512_hi YourInstanceName ( - .addr(addr), // Bus [8 : 0] - .clk(clk), - .din(din), // Bus [7 : 0] - .dout(dout), // Bus [7 : 0] - .en(en), - .we(we)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file ram_8x512_hi.v when simulating -// the core, ram_8x512_hi. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.xco =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.xco (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.xco (nonexistent) @@ -1,63 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.31 -# Date: Mon Apr 6 14:52:29 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s200 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ft256 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET component_name=ram_8x512_hi -CSET depth=512 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_Low -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=false -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_Low -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 14e27e11 -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_flist.txt =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_flist.txt (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_flist.txt (nonexistent) @@ -1,9 +0,0 @@ -# Output products list for -ram_8x512_lo.asy -ram_8x512_lo.ngc -ram_8x512_lo.sym -ram_8x512_lo.v -ram_8x512_lo.veo -ram_8x512_lo.xco -ram_8x512_lo_flist.txt -ram_8x512_lo_xmdf.tcl
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_flist.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym (nonexistent) @@ -1,40 +0,0 @@ -VERSION 5 -BEGIN SYMBOL rom_8x2k_hi -SYMBOLTYPE BLOCK -TIMESTAMP 2009 5 27 15 20 33 -SYMPIN 0 48 Input addr[10:0] -SYMPIN 0 80 Input din[7:0] -SYMPIN 0 112 Input we -SYMPIN 0 144 Input en -SYMPIN 0 240 Input clk -SYMPIN 352 48 Output dout[7:0] -RECTANGLE N 32 0 320 272 -BEGIN DISPLAY 36 48 PIN addr[10:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 48 32 48 -END LINE -BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 112 PIN we ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 112 32 112 -BEGIN DISPLAY 36 144 PIN en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 240 PIN clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 320 48 352 48 -END LINE -END SYMBOL
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.asy =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.asy (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.asy (nonexistent) @@ -1,27 +0,0 @@ -Version 4 -SymbolType BLOCK -RECTANGLE Normal 32 0 320 272 -PIN 0 48 LEFT 36 -PINATTR PinName addr[8:0] -PINATTR Polarity IN -LINE Wide 0 48 32 48 -PIN 0 80 LEFT 36 -PINATTR PinName din[7:0] -PINATTR Polarity IN -LINE Wide 0 80 32 80 -PIN 0 112 LEFT 36 -PINATTR PinName we -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 144 LEFT 36 -PINATTR PinName en -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 240 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 352 48 RIGHT 36 -PINATTR PinName dout[7:0] -PINATTR Polarity OUT -LINE Wide 320 48 352 48
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_xmdf.tcl =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_xmdf.tcl (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_xmdf.tcl (nonexistent) @@ -1,72 +0,0 @@ -# The package naming convention is _xmdf -package provide rom_8x2k_lo_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::rom_8x2k_lo_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::rom_8x2k_lo_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name rom_8x2k_lo -} -# ::rom_8x2k_lo_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::rom_8x2k_lo_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_lo_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom_8x2k_lo -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_xmdf.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v (nonexistent) @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file rom_8x2k_lo.v when simulating -// the core, rom_8x2k_lo. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module rom_8x2k_lo( - addr, - clk, - din, - dout, - en, - we); - - -input [10 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(11), - .c_default_data("0"), - .c_depth(2048), - .c_enable_rlocs(0), - .c_has_default_data(1), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("mif_file_16_1"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(0), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(0), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of rom_8x2k_lo is "black_box" - -endmodule -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.xco =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.xco (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.xco (nonexistent) @@ -1,63 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.31 -# Date: Mon Apr 6 14:53:15 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s200 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ft256 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET component_name=ram_8x512_lo -CSET depth=512 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_Low -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=false -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_Low -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 31e1c8c8 -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.xco Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.veo =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.veo (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.veo (nonexistent) @@ -1,48 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -ram_8x512_lo YourInstanceName ( - .addr(addr), // Bus [8 : 0] - .clk(clk), - .din(din), // Bus [7 : 0] - .dout(dout), // Bus [7 : 0] - .en(en), - .we(we)); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file ram_8x512_lo.v when simulating -// the core, ram_8x512_lo. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.veo Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.sym =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.sym (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.sym (nonexistent) @@ -1,40 +0,0 @@ -VERSION 5 -BEGIN SYMBOL rom_8x2k_lo -SYMBOLTYPE BLOCK -TIMESTAMP 2009 5 27 15 21 26 -SYMPIN 0 48 Input addr[10:0] -SYMPIN 0 80 Input din[7:0] -SYMPIN 0 112 Input we -SYMPIN 0 144 Input en -SYMPIN 0 240 Input clk -SYMPIN 352 48 Output dout[7:0] -RECTANGLE N 32 0 320 272 -BEGIN DISPLAY 36 48 PIN addr[10:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 48 32 48 -END LINE -BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 112 PIN we ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 112 32 112 -BEGIN DISPLAY 36 144 PIN en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 240 PIN clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 320 48 352 48 -END LINE -END SYMBOL
trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.sym Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v (nonexistent) @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file ram_8x512_hi.v when simulating -// the core, ram_8x512_hi. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module ram_8x512_hi( - addr, - clk, - din, - dout, - en, - we); - - -input [8 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(9), - .c_default_data("0"), - .c_depth(512), - .c_enable_rlocs(0), - .c_has_default_data(1), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("mif_file_16_1"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(0), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(0), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of ram_8x512_hi is "black_box" - -endmodule -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.asy =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.asy (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.asy (nonexistent) @@ -1,27 +0,0 @@ -Version 4 -SymbolType BLOCK -RECTANGLE Normal 32 0 320 272 -PIN 0 48 LEFT 36 -PINATTR PinName addr[8:0] -PINATTR Polarity IN -LINE Wide 0 48 32 48 -PIN 0 80 LEFT 36 -PINATTR PinName din[7:0] -PINATTR Polarity IN -LINE Wide 0 80 32 80 -PIN 0 112 LEFT 36 -PINATTR PinName we -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 144 LEFT 36 -PINATTR PinName en -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 240 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 352 48 RIGHT 36 -PINATTR PinName dout[7:0] -PINATTR Polarity OUT -LINE Wide 320 48 352 48
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.asy Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.sym =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.sym (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.sym (nonexistent) @@ -1,40 +0,0 @@ -VERSION 5 -BEGIN SYMBOL ram_8x512_hi -SYMBOLTYPE BLOCK -TIMESTAMP 2009 4 6 14 52 20 -SYMPIN 0 48 Input addr[8:0] -SYMPIN 0 80 Input din[7:0] -SYMPIN 0 112 Input we -SYMPIN 0 144 Input en -SYMPIN 0 240 Input clk -SYMPIN 352 48 Output dout[7:0] -RECTANGLE N 32 0 320 272 -BEGIN DISPLAY 36 48 PIN addr[8:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 48 32 48 -END LINE -BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 112 PIN we ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 112 32 112 -BEGIN DISPLAY 36 144 PIN en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 240 PIN clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 320 48 352 48 -END LINE -END SYMBOL
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.sym Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise (nonexistent)
trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v (nonexistent) @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file ram_8x512_lo.v when simulating -// the core, ram_8x512_lo. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module ram_8x512_lo( - addr, - clk, - din, - dout, - en, - we); - - -input [8 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(9), - .c_default_data("0"), - .c_depth(512), - .c_enable_rlocs(0), - .c_has_default_data(1), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("mif_file_16_1"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(0), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(0), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of ram_8x512_lo is "black_box" - -endmodule -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.sym =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.sym (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.sym (nonexistent) @@ -1,40 +0,0 @@ -VERSION 5 -BEGIN SYMBOL ram_8x512_lo -SYMBOLTYPE BLOCK -TIMESTAMP 2009 4 6 14 53 7 -SYMPIN 0 48 Input addr[8:0] -SYMPIN 0 80 Input din[7:0] -SYMPIN 0 112 Input we -SYMPIN 0 144 Input en -SYMPIN 0 240 Input clk -SYMPIN 352 48 Output dout[7:0] -RECTANGLE N 32 0 320 272 -BEGIN DISPLAY 36 48 PIN addr[8:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 48 32 48 -END LINE -BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 112 PIN we ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 112 32 112 -BEGIN DISPLAY 36 144 PIN en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 240 PIN clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 320 48 352 48 -END LINE -END SYMBOL
trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.sym Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp (nonexistent) @@ -1,20 +0,0 @@ -# Date: Mon Apr 6 14:50:01 2009 -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s200 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ft256 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp -
trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v =================================================================== --- trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v (revision 26) +++ trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v (nonexistent) @@ -1,112 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: io_mux.v -// -// *Module Description: -// I/O mux for port function selection. -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- -`include "timescale.v" - -module io_mux ( - -// Function A (typically GPIO) - a_din, - a_dout, - a_dout_en, - -// Function B (Timer A, ...) - b_din, - b_dout, - b_dout_en, - -// IO Cell - io_din, - io_dout, - io_dout_en, - -// Function selection (0=A, 1=B) - sel -); - -// PARAMETERs -//============ -parameter WIDTH = 8; - -// Function A (typically GPIO) -//=============================== -output [WIDTH-1:0] a_din; -input [WIDTH-1:0] a_dout; -input [WIDTH-1:0] a_dout_en; - -// Function B (Timer A, ...) -//=============================== -output [WIDTH-1:0] b_din; -input [WIDTH-1:0] b_dout; -input [WIDTH-1:0] b_dout_en; - -// IO Cell -//=============================== -input [WIDTH-1:0] io_din; -output [WIDTH-1:0] io_dout; -output [WIDTH-1:0] io_dout_en; - -// Function selection (0=A, 1=B) -//=============================== -input [WIDTH-1:0] sel; - - -//============================================================================= -// 1) I/O FUNCTION SELECTION MUX -//============================================================================= - -function [WIDTH-1:0] mux ( - input [WIDTH-1:0] A, - input [WIDTH-1:0] B, - input [WIDTH-1:0] SEL -); - integer i; - begin - mux = {WIDTH{1'b0}}; - for (i = 0; i < WIDTH; i = i + 1) - mux[i] = sel[i] ? B[i] : A[i]; - end -endfunction - - -assign a_din = mux( io_din, {WIDTH{1'b0}}, sel); -assign b_din = mux({WIDTH{1'b0}}, io_din, sel); -assign io_dout = mux( a_dout, b_dout, sel); -assign io_dout_en = mux( a_dout_en, b_dout_en, sel); - - -endmodule // io_mux
trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf =================================================================== --- trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf (revision 26) +++ trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf (nonexistent)
trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/doc/board_user_guide.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/doc/board_user_guide.pdf =================================================================== --- trunk/fpga/diligent_s3board/doc/board_user_guide.pdf (revision 26) +++ trunk/fpga/diligent_s3board/doc/board_user_guide.pdf (nonexistent)
trunk/fpga/diligent_s3board/doc/board_user_guide.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/doc/xapp462.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/fpga/diligent_s3board/doc/xapp462.pdf =================================================================== --- trunk/fpga/diligent_s3board/doc/xapp462.pdf (revision 26) +++ trunk/fpga/diligent_s3board/doc/xapp462.pdf (nonexistent)
trunk/fpga/diligent_s3board/doc/xapp462.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/run/run_disassemble =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/run/run_disassemble (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/run/run_disassemble (nonexistent) @@ -1 +0,0 @@ -msp430-objdump -D rom.elf
trunk/fpga/diligent_s3board/sim/rtl_sim/run/run_disassemble Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/run/run =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/run/run (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/run/run (nonexistent) @@ -1,4 +0,0 @@ -#!/bin/csh -f - -#../bin/msp430sim leds -../bin/msp430sim ta_uart
trunk/fpga/diligent_s3board/sim/rtl_sim/run/run Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/run =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/run (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/run (nonexistent)
trunk/fpga/diligent_s3board/sim/rtl_sim/run Property changes : Deleted: svn:ignore ## -1,4 +0,0 ## -rom.* -simv -stimulus.v -*.vcd Index: trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f (nonexistent) @@ -1,89 +0,0 @@ -//============================================================================= -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//----------------------------------------------------------------------------- -// -// File Name: submit.f -// -// Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//----------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//============================================================================= - -//============================================================================= -// Xilinx library -//============================================================================= -+libext+.v - --y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ --y /opt/Xilinx/10.1/ISE/verilog/src/simprims/ --y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib/ - - -//============================================================================= -// FPGA Specific modules -//============================================================================= - -+incdir+../../../rtl/verilog/ -../../../rtl/verilog/openMSP430_fpga.v -../../../rtl/verilog/io_mux.v -../../../rtl/verilog/driver_7segment.v -../../../rtl/verilog/coregen/ram_8x512_hi.v -../../../rtl/verilog/coregen/ram_8x512_lo.v -../../../rtl/verilog/coregen/rom_8x2k_hi.v -../../../rtl/verilog/coregen/rom_8x2k_lo.v - - -//============================================================================= -// openMSP430 -//============================================================================= - -+incdir+../../../rtl/verilog/openmsp430/ -../../../rtl/verilog/openmsp430/openMSP430.v -../../../rtl/verilog/openmsp430/frontend.v -../../../rtl/verilog/openmsp430/execution_unit.v -../../../rtl/verilog/openmsp430/register_file.v -../../../rtl/verilog/openmsp430/alu.v -../../../rtl/verilog/openmsp430/mem_backbone.v -../../../rtl/verilog/openmsp430/clock_module.v -../../../rtl/verilog/openmsp430/sfr.v -../../../rtl/verilog/openmsp430/dbg.v -../../../rtl/verilog/openmsp430/dbg_hwbrk.v -../../../rtl/verilog/openmsp430/dbg_uart.v -../../../rtl/verilog/openmsp430/watchdog.v -../../../rtl/verilog/openmsp430/periph/gpio.v -../../../rtl/verilog/openmsp430/periph/timerA.v - - -//============================================================================= -// Testbench related -//============================================================================= - -+incdir+../../../bench/verilog/ -../../../bench/verilog/tb_openMSP430_fpga.v -../../../bench/verilog/msp_debug.v -../../../bench/verilog/glbl.v -
trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/src/leds.v =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/src/leds.v (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/src/leds.v (nonexistent) @@ -1,21 +0,0 @@ -/*===========================================================================*/ -/* DIGITAL I/O */ -/*---------------------------------------------------------------------------*/ -/* Test the Digital I/O interface. */ -/*===========================================================================*/ - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); - repeat(5) @(posedge CLK_50MHz); - stimulus_done = 0; - - - - - - stimulus_done = 1; - end -
trunk/fpga/diligent_s3board/sim/rtl_sim/src/leds.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/src/ta_uart.v =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/src/ta_uart.v (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/src/ta_uart.v (nonexistent) @@ -1,92 +0,0 @@ -/*===========================================================================*/ -/* DIGITAL I/O */ -/*---------------------------------------------------------------------------*/ -/* Test the Digital I/O interface. */ -/*===========================================================================*/ - -reg [32*8-1:0] rx_chain; -integer rx_offset; - - -reg [7:0] rxbuf; -integer rxcnt; -`define BAUD 140 - -task uart_rx; - begin - @(negedge UART_TXD); - rxbuf = 0; - repeat(`BAUD*3/2) @(posedge mclk); - for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1) - begin - rxbuf = {UART_TXD, rxbuf[7:1]}; - repeat(`BAUD) @(posedge mclk); - end - end -endtask - -task uart_tx; - input [7:0] txbuf; - - reg [9:0] txbuf_full; - integer txcnt; - begin - UART_RXD = 1'b1; - txbuf_full = {1'b1, txbuf, 1'b0}; - repeat(`BAUD) @(posedge mclk); - for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1) - begin - UART_RXD = txbuf_full[txcnt]; -// txbuf_full = {txbuf_full[8:1], 1'b0}; - repeat(`BAUD) @(posedge mclk); - end - end -endtask - - - -initial - begin - $display(" ==============================================="); - $display("| START SIMULATION |"); - $display(" ==============================================="); - repeat(5) @(posedge CLK_50MHz); - stimulus_done = 0; - rx_chain = 0; - rx_offset = 0; - - while (rx_offset<1) - begin - uart_rx; - rx_chain = rx_chain | (rxbuf << (31*8-(8*rx_offset))); - rx_offset = rx_offset+1; - end - - repeat(50) @(posedge CLK_50MHz); - uart_tx("a"); - -// repeat(5000) @(posedge mclk); -// UART_RXD = 1; -// repeat(160) @(posedge mclk); -// UART_RXD = 0; -// repeat(160) @(posedge mclk); -// UART_RXD = 1; -// repeat(160) @(posedge mclk); -// UART_RXD = 0; -// repeat(160) @(posedge mclk); -// UART_RXD = 1; -// repeat(160) @(posedge mclk); -// UART_RXD = 0; -// repeat(160) @(posedge mclk); -// UART_RXD = 1; -// repeat(160) @(posedge mclk); -// UART_RXD = 0; -// repeat(160) @(posedge mclk); - - - stimulus_done = 1; - //repeat(1000) @(posedge mclk); - //$finish(); - - end -
trunk/fpga/diligent_s3board/sim/rtl_sim/src/ta_uart.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl (nonexistent) @@ -1,153 +0,0 @@ -#!/usr/bin/tclsh -#------------------------------------------------------------------------------ -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#------------------------------------------------------------------------------ -# -# File Name: ihex2mem.tcl -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#------------------------------------------------------------------------------ -# $Rev$ -# $LastChangedBy$ -# $LastChangedDate$ -#------------------------------------------------------------------------------ - -############################################################################### -# PARAMETER CHECK # -############################################################################### - -if {$argc != 6} { - puts "ERROR : wrong number of arguments" - puts "USAGE : ihex2mem.tcl -ihex -out -mem_size " - puts "Example : ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size 2048" - exit 1 -} - -# default values -set ihex empty.in -set out empty.out -set mem_size -1 - -# parse arguments -for {set i 0} {$i < $argc} {incr i} { - switch -exact -- [lindex $argv $i] { - -ihex {set ihex [lindex $argv [expr $i+1]]; incr i} - -out {set out [lindex $argv [expr $i+1]]; incr i} - -mem_size {set mem_size [lindex $argv [expr $i+1]]; incr i} - } -} - -# Make sure arugments were specified -if {[string eq $ihex empty.in]} { - puts "IHEX input file isn't specified" - exit 1 -} -if {[string eq $out empty.out]} { - puts "MEMH output file isn't specified" - exit 1 -} -if {[string eq $mem_size -1]} { - puts "Memory size isn't specified" - exit 1 -} - - -############################################################################### -# CONVERSION PROCEDURE # -############################################################################### - -#-----------------------------------------------------------------------------# -# OPEN FILES # -#-----------------------------------------------------------------------------# - -# IHEX Input -if [catch {open $ihex r} f_ihex] { - puts "ERROR Cannot open input file $ihex" - exit 1 -} - -# MEMH Output -if [catch {open $out w } f_out] { - puts "ERROR Cannot create output file $out" - exit 1 -} - - -#-----------------------------------------------------------------------------# -# CONVERSION # -#-----------------------------------------------------------------------------# - - -# Conversions procedure -proc hex2dec { val } { - set val [format "%u" 0x[string trimleft $val]] - return $val -} - - -# Initialize memory array (16 bit words) -set num_word [expr ($mem_size/2)-1] -for {set i 0} {$i <= $num_word} {incr i} { - set mem_arr($i) 0000 -} - - -# Calculate Address offset (offset=(0x10000-memory_size)) -set mem_offset [expr 65536-$mem_size] - - -# Process input file -while {[gets $f_ihex line] >= 0} { - - # Process line - set byte_count [hex2dec [string range $line 1 2]] - set start_addr [expr ([hex2dec [string range $line 3 6]] - $mem_offset)] - set rec_type [string range $line 7 8] - - if {$rec_type == 00} { - for {set i 0} {$i < $byte_count*2} {set i [expr $i+4]} { - set mem_msb [string range $line [expr $i+11] [expr $i+12]] - set mem_lsb [string range $line [expr $i+9] [expr $i+10]] - set addr [expr ($start_addr+$i/2)/2] - set mem_arr($addr) "$mem_msb$mem_lsb" - } - } -} -close $f_ihex - - -# Writing memory array to file -for {set i 0} {$i <= $num_word} {incr i} { - - if {![expr $i%16]} { - puts -nonewline $f_out "\n@[format "%04x" $i] " - } - puts -nonewline $f_out " [format "%02s" $mem_arr($i) ]" -} - -puts $f_out "\n" -close $f_out - -exit 0
trunk/fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim (nonexistent) @@ -1,115 +0,0 @@ -#!/bin/sh -#------------------------------------------------------------------------------ -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#------------------------------------------------------------------------------ -# -# File Name: msp430sim -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#------------------------------------------------------------------------------ -# $Rev$ -# $LastChangedBy$ -# $LastChangedDate$ -#------------------------------------------------------------------------------ - -############################################################################### -# Parameter Check # -############################################################################### -EXPECTED_ARGS=1 -if [ $# -ne $EXPECTED_ARGS ]; then - echo "ERROR : wrong number of arguments" - echo "USAGE : msp430sim " - echo "Example : msp430sim leds" - exit 1 -fi - - -############################################################################### -# Check if the required files exist # -############################################################################### -softdir=../../../software/$1; -elffile=../../../software/$1/$1.elf; -verfile=../src/$1.v; -submitfile=../src/submit.f; -incfile=../../../rtl/verilog/openmsp430/openMSP430_defines.v; - -if [ ! -e $softdir ]; then - echo "Software directory doesn't exist: $softdir" - exit 1 -fi -if [ ! -e $verfile ]; then - echo "Verilog stimulus file $verfile doesn't exist: $verfile" - exit 1 -fi -if [ ! -e $submitfile ]; then - echo "Verilog submit file $submitfile doesn't exist: $submitfile" - exit 1 -fi - - -############################################################################### -# Cleanup # -############################################################################### -echo "Cleanup..." -rm -rf rom.* -rm -rf stimulus.v - - -############################################################################### -# Run simulation # -############################################################################### -echo " =======================================================" -echo "| Start simulation: $1" -echo " =======================================================" - -# Make C program -cd $softdir -make -cd ../../sim/rtl_sim/run/ - -# Create links -ln -s $elffile rom.elf -ln -s $verfile stimulus.v - -# Make local copy of the openMSP403 configuration file and remove comments -cp $incfile ./rom.inc -sed -i "/^\/\// s,.*,," rom.inc - -# Get ROM size -romsize=`grep ROM_AWIDTH rom.inc | grep -v ROM_MSB | grep -v ROM_SIZE` -romsize=${romsize##* } -romsize=$((2<<$romsize)) - -# Create IHEX file from ELF -echo "Convert ELF file to IHEX format..." -msp430-objcopy -O ihex rom.elf rom.ihex - -# Generate ROM memory file -echo "Convert IHEX file to Verilog MEMH format..." -../bin/ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size $romsize - -# Start verilog simulation -echo "Start Verilog simulation..." -../bin/rtlsim.sh stimulus.v rom.mem $submitfile
trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh =================================================================== --- trunk/fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh (revision 26) +++ trunk/fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/sh -#------------------------------------------------------------------------------ -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#------------------------------------------------------------------------------ -# -# File Name: rtlsim.sh -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#------------------------------------------------------------------------------ -# $Rev$ -# $LastChangedBy$ -# $LastChangedDate$ -#------------------------------------------------------------------------------ - -############################################################################### -# Parameter Check # -############################################################################### -EXPECTED_ARGS=3 -if [ $# -ne $EXPECTED_ARGS ]; then - echo "ERROR : wrong number of arguments" - echo "USAGE : rtlsim.sh " - echo "Example : rtlsim.sh ./stimulus.v rom.mem ../src/submit.f" - exit 1 -fi - - -############################################################################### -# Check if the required files exist # -############################################################################### - -if [ ! -e $1 ]; then - echo "Verilog stimulus file $1 doesn't exist" - exit 1 -fi -if [ ! -e $2 ]; then - echo "ROM memory file $2 doesn't exist" - exit 1 -fi -if [ ! -e $3 ]; then - echo "Verilog submit file $3 doesn't exist" - exit 1 -fi - - -############################################################################### -# Start verilog simulation # -############################################################################### -rm -rf simv -iverilog -o simv -c $3 -./simv
trunk/fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj (nonexistent) @@ -1,66 +0,0 @@ -//---------------------------------------------------------------------------- -// Copyright (C) 2001 Authors -// -// This source file may be used and distributed without restriction provided -// that this copyright statement is not removed from the file and that any -// derivative work contains the original copyright notice and the associated -// disclaimer. -// -// This source file is free software; you can redistribute it and/or modify -// it under the terms of the GNU Lesser General Public License as published -// by the Free Software Foundation; either version 2.1 of the License, or -// (at your option) any later version. -// -// This source is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -// License for more details. -// -// You should have received a copy of the GNU Lesser General Public License -// along with this source; if not, write to the Free Software Foundation, -// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -// -//---------------------------------------------------------------------------- -// -// *File Name: openMSP430_fpga.prj -// -// *Author(s): -// - Olivier Girard, olgirard@gmail.com -// -//---------------------------------------------------------------------------- -// $Rev$ -// $LastChangedBy$ -// $LastChangedDate$ -//---------------------------------------------------------------------------- - -//============================================================================= -// FPGA Specific modules -//============================================================================= - -`include "../../../rtl/verilog/openMSP430_fpga.v" -`include "../../../rtl/verilog/io_mux.v" -`include "../../../rtl/verilog/driver_7segment.v" -`include "../../../rtl/verilog/coregen/ram_8x512_hi.v" -`include "../../../rtl/verilog/coregen/ram_8x512_lo.v" -`include "../../../rtl/verilog/coregen/rom_8x2k_hi.v" -`include "../../../rtl/verilog/coregen/rom_8x2k_lo.v" - - -//============================================================================= -// openMSP430 -//============================================================================= - -`include "../../../rtl/verilog/openmsp430/openMSP430.v" -`include "../../../rtl/verilog/openmsp430/frontend.v" -`include "../../../rtl/verilog/openmsp430/execution_unit.v" -`include "../../../rtl/verilog/openmsp430/register_file.v" -`include "../../../rtl/verilog/openmsp430/alu.v" -`include "../../../rtl/verilog/openmsp430/mem_backbone.v" -`include "../../../rtl/verilog/openmsp430/clock_module.v" -`include "../../../rtl/verilog/openmsp430/dbg.v" -`include "../../../rtl/verilog/openmsp430/dbg_hwbrk.v" -`include "../../../rtl/verilog/openmsp430/dbg_uart.v" -`include "../../../rtl/verilog/openmsp430/sfr.v" -`include "../../../rtl/verilog/openmsp430/watchdog.v" -`include "../../../rtl/verilog/openmsp430/periph/gpio.v" -`include "../../../rtl/verilog/openmsp430/periph/timerA.v"
trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat (nonexistent) @@ -1,47 +0,0 @@ -::############################################################################### -::# # -::# Xilinx RAM update script for WINDOWS # -::# # -::############################################################################### - -::############################################################################### -::# Specify Program to be loaded # -::############################################################################### - -set MSP430_PROGRAM=leds -::set MSP430_PROGRAM=ta_uart - - -::############################################################################### -::# Check if the required files exist # -::############################################################################### -set softdir=..\..\software\%MSP430_PROGRAM% -set elffile=..\..\software\%MSP430_PROGRAM%\%MSP430_PROGRAM%.elf - -IF EXIST %softdir% GOTO :DIR_OKAY -ECHO ERROR: Software directory doesn't exist: %softdir% -PAUSE -EXIT -:DIR_OKAY - -IF EXIST %elffile% GOTO :ELF_OKAY -ECHO ERROR: ELF file doesn't exist: %elffile% -PAUSE -EXIT -:ELF_OKAY - - -::############################################################################### -::# Update FPGA Bitstream # -::############################################################################### - - -DEL /f .\WORK\%MSP430_PROGRAM%.elf -DEL /f .\WORK\%MSP430_PROGRAM%.bit - -XCOPY %elffile% .\WORK\ - -cd .\WORK -data2mem -bm ..\memory.bmm -bd %MSP430_PROGRAM%.elf -bt openMSP430_fpga_top.bit -o b %MSP430_PROGRAM%.bit -cd ..\ -PAUSE \ No newline at end of file
trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.bat Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf (nonexistent) @@ -1,245 +0,0 @@ -#============================================================================= -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#----------------------------------------------------------------------------- -# -# File Name: openMSP430_fpga.ucf -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#----------------------------------------------------------------------------- -# $Rev$ -# $LastChangedBy$ -# $LastChangedDate$ -#============================================================================= - -#-----------------------------------------------------------------------------# -# Clock configuration & ROM Block Assignments # -#-----------------------------------------------------------------------------# - -# CLOCKS Definition -NET "CLK_50MHz" PERIOD = 20 nS LOW 10.0 nS; -#NET "dcm_clk" PERIOD = 50 nS LOW 25.0 nS; -#NET "clk_sys" PERIOD = 50 nS LOW 25.0 nS; -NET "dcm_clk" PERIOD = 40 nS LOW 20.0 nS; -NET "clk_sys" PERIOD = 40 nS LOW 20.0 nS; - - -# DCM Configuration -#INST dcm_adv_clk_main CLKFX_DIVIDE = 5; -#INST dcm_adv_clk_main CLKFX_MULTIPLY = 2; -#INST dcm_adv_clk_main CLK_FEEDBACK = NONE; -#INST dcm_adv_clk_main CLKDV_DIVIDE = 2.5; -#INST dcm_adv_clk_main CLKIN_DIVIDE_BY_2 = FALSE; -#INST dcm_adv_clk_main CLKIN_PERIOD = 20.000000; -#INST dcm_adv_clk_main CLKOUT_PHASE_SHIFT = NONE; -#INST dcm_adv_clk_main DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; -#INST dcm_adv_clk_main DFS_FREQUENCY_MODE = LOW; -#INST dcm_adv_clk_main DLL_FREQUENCY_MODE = LOW; -#INST dcm_adv_clk_main DUTY_CYCLE_CORRECTION = TRUE; -#INST dcm_adv_clk_main FACTORY_JF = C080; -#INST dcm_adv_clk_main PHASE_SHIFT = 0; -#INST dcm_adv_clk_main STARTUP_WAIT = FALSE; -INST dcm_adv_clk_main CLK_FEEDBACK = 1X; -INST dcm_adv_clk_main CLKDV_DIVIDE = 2.5; -INST dcm_adv_clk_main CLKFX_DIVIDE = 1; -INST dcm_adv_clk_main CLKFX_MULTIPLY = 4; -INST dcm_adv_clk_main CLKIN_DIVIDE_BY_2 = FALSE; -INST dcm_adv_clk_main CLKIN_PERIOD = 20.000; -INST dcm_adv_clk_main CLKOUT_PHASE_SHIFT = NONE; -INST dcm_adv_clk_main DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; -INST dcm_adv_clk_main DFS_FREQUENCY_MODE = LOW; -INST dcm_adv_clk_main DLL_FREQUENCY_MODE = LOW; -INST dcm_adv_clk_main DUTY_CYCLE_CORRECTION = TRUE; -INST dcm_adv_clk_main FACTORY_JF = 8080; -INST dcm_adv_clk_main PHASE_SHIFT = 0; -INST dcm_adv_clk_main STARTUP_WAIT = FALSE; - - -# ROM Block Assignments -INST "rom_8x2k_hi_0/B8" LOC = "RAMB16_X1Y2"; -INST "rom_8x2k_lo_0/B8" LOC = "RAMB16_X1Y1"; - -# RAM Block Assignments -INST "ram_8x512_hi_0/B8" LOC = "RAMB16_X1Y4"; -INST "ram_8x512_lo_0/B8" LOC = "RAMB16_X1Y3"; - - -#-----------------------------------------------------------------------------# -# Clock Sources # -#-----------------------------------------------------------------------------# - -NET "CLK_50MHz" LOC = "T9" | IOSTANDARD = LVCMOS33 ; // Input -NET "CLK_SOCKET" LOC = "D9" | IOSTANDARD = LVCMOS33 ; // Input - - -#-----------------------------------------------------------------------------# -# Switches and LEDs # -#-----------------------------------------------------------------------------# - -# Slide Switches -NET "SW7" LOC = "K13" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW6" LOC = "K14" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW5" LOC = "J13" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW4" LOC = "J14" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW3" LOC = "H13" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW2" LOC = "H14" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW1" LOC = "G12" | IOSTANDARD = LVCMOS33 ; // Input -NET "SW0" LOC = "F12" | IOSTANDARD = LVCMOS33 ; // Input - -# Push Button Switches -NET "BTN3" LOC = "L14" | IOSTANDARD = LVCMOS33 ; // Input -NET "BTN2" LOC = "L13" | IOSTANDARD = LVCMOS33 ; // Input -NET "BTN1" LOC = "M14" | IOSTANDARD = LVCMOS33 ; // Input -NET "BTN0" LOC = "M13" | IOSTANDARD = LVCMOS33 ; // Input - -# LEDs -NET "LED7" LOC = "P11" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED6" LOC = "P12" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED5" LOC = "N12" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED4" LOC = "P13" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED3" LOC = "N14" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED2" LOC = "L12" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED1" LOC = "P14" | IOSTANDARD = LVCMOS33 ; // Output -NET "LED0" LOC = "K12" | IOSTANDARD = LVCMOS33 ; // Output - - -#-----------------------------------------------------------------------------# -# Four-Sigit, Seven-Segment LED Display # -#-----------------------------------------------------------------------------# - -NET "SEG_A" LOC = "E14" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_B" LOC = "G13" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_C" LOC = "N15" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_D" LOC = "P15" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_E" LOC = "R16" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_F" LOC = "F13" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_G" LOC = "N16" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_DP" LOC = "P16" | IOSTANDARD = LVCMOS33 ; // Output - -NET "SEG_AN0" LOC = "D14" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_AN1" LOC = "G14" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_AN2" LOC = "F14" | IOSTANDARD = LVCMOS33 ; // Output -NET "SEG_AN3" LOC = "E13" | IOSTANDARD = LVCMOS33 ; // Output - - -#-----------------------------------------------------------------------------# -# RS-232 Port # -#-----------------------------------------------------------------------------# - -NET "UART_RXD" LOC = "T13" | IOSTANDARD = LVCMOS33 ; // Input -NET "UART_TXD" LOC = "R13" | IOSTANDARD = LVCMOS33 ; // Output - -NET "UART_RXD_A" LOC = "N10" | IOSTANDARD = LVCMOS33 ; // Input -NET "UART_TXD_A" LOC = "T14" | IOSTANDARD = LVCMOS33 ; // Output - - -#-----------------------------------------------------------------------------# -# PS/2 Mouse/Keyboard Port # -#-----------------------------------------------------------------------------# - -NET "PS2_D" LOC = "M15" | IOSTANDARD = LVCMOS33 ; // I/O -NET "PS2_C" LOC = "M16" | IOSTANDARD = LVCMOS33 ; // Output - - -#-----------------------------------------------------------------------------# -# Fast, Asynchronous SRAM # -#-----------------------------------------------------------------------------# - -# Address Bus Connections -NET "SRAM_A17" LOC = "L3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A16" LOC = "K5" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A15" LOC = "K3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A14" LOC = "J3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A13" LOC = "J4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A12" LOC = "H4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A11" LOC = "H3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A10" LOC = "G5" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A9" LOC = "E4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A8" LOC = "E3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A7" LOC = "F4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A6" LOC = "F3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A5" LOC = "G4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A4" LOC = "L4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A3" LOC = "M3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A2" LOC = "M4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A1" LOC = "N3" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_A0" LOC = "L5" | IOSTANDARD = LVCMOS33 ; // Output - - -# Write enable and output enable control signals -NET "SRAM_OE" LOC = "K4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM_WE" LOC = "G3" | IOSTANDARD = LVCMOS33 ; // Output - - -# SRAM Data signals, chip enables, and byte enables -NET "SRAM0_IO15" LOC = "R1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO14" LOC = "P1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO13" LOC = "L2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO12" LOC = "J2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO11" LOC = "H1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO10" LOC = "F2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO9" LOC = "P8" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO8" LOC = "D3" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO7" LOC = "B1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO6" LOC = "C1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO5" LOC = "C2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO4" LOC = "R5" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO3" LOC = "T5" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO2" LOC = "R6" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO1" LOC = "T8" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_IO0" LOC = "N7" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM0_CE1" LOC = "P7" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM0_UB1" LOC = "T4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM0_LB1" LOC = "P6" | IOSTANDARD = LVCMOS33 ; // Output - -NET "SRAM1_IO15" LOC = "N1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO14" LOC = "M1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO13" LOC = "K2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO12" LOC = "C3" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO11" LOC = "F5" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO10" LOC = "G1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO9" LOC = "E2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO8" LOC = "D2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO7" LOC = "D1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO6" LOC = "E1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO5" LOC = "G2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO4" LOC = "J1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO3" LOC = "K1" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO2" LOC = "M2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO1" LOC = "N2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_IO0" LOC = "P2" | IOSTANDARD = LVCMOS33 ; // I/O -NET "SRAM1_CE2" LOC = "N5" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM1_UB2" LOC = "R4" | IOSTANDARD = LVCMOS33 ; // Output -NET "SRAM1_LB2" LOC = "P5" | IOSTANDARD = LVCMOS33 ; // Output - - -#-----------------------------------------------------------------------------# -# VGA Port # -#-----------------------------------------------------------------------------# - -NET "VGA_R" LOC = "R12" | IOSTANDARD = LVCMOS33 ; // Output -NET "VGA_G" LOC = "T12" | IOSTANDARD = LVCMOS33 ; // Output -NET "VGA_B" LOC = "R11" | IOSTANDARD = LVCMOS33 ; // Output -NET "VGA_HS" LOC = "R9" | IOSTANDARD = LVCMOS33 ; // Output -NET "VGA_VS" LOC = "T10" | IOSTANDARD = LVCMOS33 ; // Output
trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Date Revision Author \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/memory.bmm =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/memory.bmm (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/memory.bmm (nonexistent) @@ -1,21 +0,0 @@ -ADDRESS_SPACE blockrom RAMB16 [0xf000:0xffff] - - BUS_BLOCK - - rom_8x2k_lo_0/B8 [7:0] LOC = X1Y1; - rom_8x2k_hi_0/B8 [15:8] LOC = X1Y2; - - END_BUS_BLOCK; - -END_ADDRESS_SPACE; - -ADDRESS_SPACE blockram RAMB16 [0x0200:0x11ff] - - BUS_BLOCK - - ram_8x512_lo_0/B8 [7:0] LOC = X1Y3; - ram_8x512_hi_0/B8 [15:8] LOC = X1Y4; - - END_BUS_BLOCK; - -END_ADDRESS_SPACE;
trunk/fpga/diligent_s3board/synthesis/xilinx/memory.bmm Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat (nonexistent) @@ -1,48 +0,0 @@ -::###################################################### -::# # -::# Xilinx Synthesis, Place & Route script for WINDOWS # -::# # -::###################################################### - -:: Cleanup -RMDIR /S /Q .\WORK -MKDIR WORK -cd ./WORK - -:: Copy the RAM & ROM ngc files -XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_hi.ngc . -XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_lo.ngc . -XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_hi.ngc . -XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_lo.ngc . - -:: Copy the Xilinx constraints file -XCOPY ..\openMSP430_fpga.ucf . - - -:: XFLOW -::--------------- - -xflow -p 3S200FT256-4 -implement high_effort.opt ^ - -config bitgen.opt ^ - -synth ..\xst_verilog.opt ^ - ..\openMSP430_fpga.prj - -:: MANUAL FLOW -::--------------- - -::xst -intstyle xflow -ifn ..\openMSP430_fpga.xst - -::ngdbuild -p xc3s200-4-ft256 -uc ..\openMSP430_fpga.ucf openMSP430_fpga - -::map -k 6 -detail -pr b openMSP430_fpga - -::par -ol med -w openMSP430_fpga.ncd openMSP430_fpga - -::trce -e -o openMSP430_fpga_err.twr openMSP430_fpga -::trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga - -::bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga - - -cd .. -PAUSE \ No newline at end of file
trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh (nonexistent) @@ -1,44 +0,0 @@ -#!/bin/sh -############################################################################### -# # -# Xilinx RAM update script for LINUX # -# # -############################################################################### - -############################################################################### -# Parameter Check # -############################################################################### -EXPECTED_ARGS=1 -if [ $# -ne $EXPECTED_ARGS ]; then - echo "ERROR : wrong number of arguments" - echo "USAGE : load_rom " - echo "Example : load_rom leds" - echo "Available tests:" - ls ../../software/ - exit 1 -fi - -############################################################################### -# Check if the required files exist # -############################################################################### -softdir=../../software/$1; -elffile=../../software/$1/$1.elf; - -if [ ! -e $softdir ]; then - echo "Software directory doesn't exist: $softdir" - exit 1 -fi - -############################################################################### -# Update FPGA Bitstream # -############################################################################### - - -rm -f ./WORK/$1.elf -rm -f ./WORK/$1.bit - -cp -f $elffile ./WORK/ - -cd ./WORK -data2mem -bm ../memory.bmm -bd $1.elf -bt openMSP430_fpga_top.bit -o b $1.bit -cd ../
trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom.sh Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/xst_verilog.opt =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/xst_verilog.opt (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/xst_verilog.opt (nonexistent) @@ -1,68 +0,0 @@ -FLOWTYPE = FPGA_SYNTHESIS; -######################################################### -## Filename: xst_verilog.opt -## -## Verilog Option File for XST targeted for speed -## This works for FPGA devices. -## -## Version: 11.1 -## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_verilog_speed.opt,v 1.14 2008/10/20 23:47:14 rvklair Exp $ -######################################################### -# -# Options for XST -# -# -Program xst --ifn _xst.scr; # input XST script file --ofn _xst.log; # output XST log file --intstyle xflow; # Message Reporting Style: ise, xflow, or silent -# -# The options listed under ParamFile are the XST Properties that can be set by the -# user. To turn on an option, uncomment by removing the '#' in front of the switch. -# -ParamFile: _xst.scr -"run"; -# -# Global Synthesis Options -# -"-ifn "; # Input/Project File Name -"-ifmt Verilog"; # Input Format -"-ofn "; # Output File Name -"-ofmt ngc"; # Output File Format -"-p "; # Target Device -"-verilog2001 YES"; # Enables the use of Verilog 2001 Constructs - # YES, NO - -"-vlgincdir ../../../rtl/verilog/openmsp430/"; - -#"-opt_mode SPEED"; # Optimization Criteria - # AREA or SPEED -#"-uc .xcf"; # Constraint File name -#"-case maintain"; # Specifies how to handle source name case - # upper, lower, maintain -#"-keep_hierarchy NO"; # Prevents optimization across module boundaries - # CPLD default YES, FPGA default NO -#"-write_timing_constraints NO"; # Write Timing Constraints - # YES, NO -#"-cross_clock_analysis NO"; # Cross Clock Option - # YES, NO -#"-iobuf YES"; # Add I/O Buffers to top level ports - # YES, NO -# -# The following are HDL Options -# -# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2 -# -#"-register_balancing NO"; # Register Balancing - # YES, NO, Forward, Backward -#"-move_first_stage YES"; # Move First Flip-Flop Stage - # YES, NO -#"-move_last_stage YES"; # Move Last Flip-Flop Stage - # YES, NO -End ParamFile -End Program xst -# -# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options -# - -
trunk/fpga/diligent_s3board/synthesis/xilinx/xst_verilog.opt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh (nonexistent) @@ -1,48 +0,0 @@ -#!/bin/tcsh -###################################################### -# # -# Xilinx Synthesis, Place & Route script for LINUX # -# # -###################################################### - -# Cleanup -rm -rf ./WORK -mkdir WORK -cd ./WORK - -# Create links for RAM & ROM ngc files -ln -s ../../../rtl/verilog/coregen/ram_8x512_hi.ngc . -ln -s ../../../rtl/verilog/coregen/ram_8x512_lo.ngc . -ln -s ../../../rtl/verilog/coregen/rom_8x2k_hi.ngc . -ln -s ../../../rtl/verilog/coregen/rom_8x2k_lo.ngc . - -# Create link to the Xilinx constraints file -ln -s ../openMSP430_fpga.ucf . - - -# XFLOW -#--------------- - -xflow -p 3S200FT256-4 -implement high_effort.opt \ - -config bitgen.opt \ - -synth ../xst_verilog.opt \ - ../openMSP430_fpga.prj - -# MANUAL FLOW -#--------------- - -#xst -intstyle xflow -ifn ../openMSP430_fpga.xst - -#ngdbuild -p xc3s200-4-ft256 -uc ../openMSP430_fpga.ucf openMSP430_fpga - -#map -k 6 -detail -pr b openMSP430_fpga - -#par -ol med -w openMSP430_fpga.ncd openMSP430_fpga - -#trce -e -o openMSP430_fpga_err.twr openMSP430_fpga -#trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga - -#bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga - - -cd ..
trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/fpga/diligent_s3board/synthesis/xilinx =================================================================== --- trunk/fpga/diligent_s3board/synthesis/xilinx (revision 26) +++ trunk/fpga/diligent_s3board/synthesis/xilinx (nonexistent)
trunk/fpga/diligent_s3board/synthesis/xilinx Property changes : Deleted: svn:ignore ## -1 +0,0 ## -WORK Index: trunk/fpga/diligent_s3board/software/ta_uart/README.txt =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/README.txt (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/README.txt (nonexistent) @@ -1,47 +0,0 @@ -what's this? ------------- -it's a simple example project for the MSP430 series MCU and the GCC port -of the mspgcc project. the project contains a makefile and uses assembler -and C sources. this time it is a software UART with Timer_A. - -this example shows the following features: - - Timer_A uart, full duplex - o same pins as BSL (P1.1 TX, P2.2 RX) - o it contains a reusable code - - - software FLL - the watch crystal is used as reference and the main clock - is adjusted to 1.536MHz on startup - - - use uprintf to print formated strings and do a printf - emulation that prints to the serial port. - - - the main loop is a simple line editor. when a return character - ('\r', usualy RETURN key) is received, it writes the received - characters from the buffer to the serial port. - connect a terminal at 9600,N,8,1 to try it out. - - - makefile - o compile and link - o include assembler files - o convert to intel hex format - o generate a listing with mixed C / assembly - -required hardware ------------------ - - - a MSP430F1121 or larger device (any from the F1x series) - connect pins P1.1 (TX) and P2.2 (RX) through level converters - to a terminal. you can also use a BSL hardware, the same pins - are used. - - - watch crystal 32.768kHz - - - optionaly a LED on P2.5 (470 Ohms series resistor to GND) - -disclaimer ----------- -this example is part of the mspgcc project http://mspgcc.sf.net -see license.txt for details. - -chris \ No newline at end of file
trunk/fpga/diligent_s3board/software/ta_uart/README.txt Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/swuart.h =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/swuart.h (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/swuart.h (nonexistent) @@ -1,6 +0,0 @@ -#ifndef SWUART_H -#define SWUART_H - -void serPutc(char); //send one character over timer_a uart -extern char rxdata; -#endif //SWUART_H
trunk/fpga/diligent_s3board/software/ta_uart/swuart.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/miniterm.py =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/miniterm.py (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/miniterm.py (nonexistent) @@ -1,135 +0,0 @@ -#!/usr/bin/env python -#very simple serial terminal -#http://pyserial.sf.net package required -#input characters are sent directly, received characters are displays as is -#baudrate and echo configuartion is done through globals: - -# - -import sys, os, serial, threading, getopt -#EXITCHARCTER = '\x1b' #ESC -EXITCHARCTER = '\x04' #ctrl+d - -#first choosea platform dependant way to read single characters from the console -if os.name == 'nt': #sys.platform == 'win32': - import msvcrt - def getkey(): - while 1: - if echo: - z = msvcrt.getche() - else: - z = msvcrt.getch() - if z == '\0' or z == '\xe0': #functions keys - msvcrt.getch() - else: - return z - -elif os.name == 'posix': - #XXX: Untested code derrived from the Python FAQ.... -# import termios, TERMIOS, sys, os - import termios, sys, os - fd = sys.stdin.fileno() - old = termios.tcgetattr(fd) - new = termios.tcgetattr(fd) - new[3] = new[3] & ~TERMIOS.ICANON & ~TERMIOS.ECHO - new[6][TERMIOS.VMIN] = 1 - new[6][TERMIOS.VTIME] = 0 - termios.tcsetattr(fd, TERMIOS.TCSANOW, new) - s = '' # We'll save the characters typed and add them to the pool. - def getkey(): - c = os.read(fd, 1) - if echo: sys.stdout.write(c) - return c - def clenaup_console(): - termios.tcsetattr(fd, TERMIOS.TCSAFLUSH, old) - sys.exitfunc = clenaup_console #terminal modes have to be restored on exit... - -else: - raise "Sorry no implementation for your platform (%s) available." % sys.platform - - -def reader(): - """loop forever and copy serial->console""" - while 1: - sys.stdout.write(s.read()) - -def writer(): - """loop forever and copy console->serial""" - while 1: - c = getkey() - if c == EXITCHARCTER: break #exit on esc - s.write(c) #send character - if convert_outgoing_cr and c == '\r': - s.write('\n') - if echo: sys.stdout.write('\n') - - -#print a short help message -def usage(): - print >>sys.stderr, """USAGE: %s [options] - Simple Terminal Programm for the serial port. - - options: - -p, --port=PORT: port, a number, defualt = 0 or a device name - -b, --baud=BAUD: baudrate, default 9600 - -r, --rtscts: enable RTS/CTS flow control (default off) - -x, --xonxoff: enable software flow control (default off) - -e, --echo: enable local echo (default off) - -c, --cr: disable CR -> CR+LF translation - - """ % sys.argv[0] - -if __name__ == '__main__': - #parse command line options - try: - opts, args = getopt.getopt(sys.argv[1:], - "hp:b:rxec", - ["help", "port=", "baud=", "rtscts", "xonxoff", "echo", "cr"]) - except getopt.GetoptError: - # print help information and exit: - usage() - sys.exit(2) - - port = 0 - baudrate = 9600 - echo = 0 - convert_outgoing_cr = 1 - rtscts = 0 - xonxoff = 0 - for o, a in opts: - if o in ("-h", "--help"): #help text - usage() - sys.exit() - elif o in ("-p", "--port"): #specified port - try: - port = int(a) - except ValueError: - port = a - elif o in ("-b", "--baud"): #specified baudrate - try: - baudrate = int(a) - except ValueError: - raise ValueError, "Baudrate must be a integer number" - elif o in ("-r", "--rtscts"): - rtscts = 1 - elif o in ("-x", "--xonxoff"): - xonxoff = 1 - elif o in ("-e", "--echo"): - echo = 1 - elif o in ("-c", "--cr"): - convert_outgoing_cr = 0 - - try: - s = serial.Serial(port, baudrate, rtscts=rtscts, xonxoff=xonxoff) - except: - print "could not open port" - sys.exit(1) - print "--- Miniterm --- type Ctrl-D to quit" - #start serial->console thread - r = threading.Thread(target=reader) - r.setDaemon(1) - r.start() - #enter console->serial loop - writer() - - print "\n--- exit ---"
trunk/fpga/diligent_s3board/software/ta_uart/miniterm.py Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/makefile =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/makefile (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/makefile (nonexistent) @@ -1,55 +0,0 @@ -# makfile configuration -NAME = ta_uart -OBJECTS = main.o swuart.o fll.o -CPU = msp430x1121 - -ASFLAGS = -mmcu=${CPU} -x assembler-with-cpp -D_GNU_ASSEMBLER_ -c -CFLAGS = -mmcu=${CPU} -O2 -Wall -g - -#switch the compiler (for the internal make rules) -CC = msp430-gcc -AS = msp430-gcc - -.PHONY: all FORCE clean download download-jtag download-bsl dist - -#all should be the first target. it's built when make is runwithout args -all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst - -#confgigure the next line if you want to use the serial download -download: download-uart -#download: download-jtag -#download: download-bsl - -#additional rules for files -${NAME}.elf: ${OBJECTS} - ${CC} -mmcu=${CPU} -o $@ ${OBJECTS} - -${NAME}.a43: ${NAME}.elf - msp430-objcopy -O ihex $^ $@ - -${NAME}.lst: ${NAME}.elf - msp430-objdump -dSt $^ > $@ - -download-jtag: all - msp430-jtag -e ${NAME}.elf - -download-bsl: all - msp430-bsl -e ${NAME}.elf - -download-uart: all - openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf - -clean: - rm -f ${NAME} ${NAME}.a43 ${NAME}.lst *.o - -#backup archive -dist: - tar czf dist.tgz *.c *.h *.txt makefile - -#dummy target as dependecy if something has to be build everytime -FORCE: - -#project dependencies -main.o: main.c hardware.h -fll.o: fll.s hardware.h -swuart.o: swuart.s hardware.h
trunk/fpga/diligent_s3board/software/ta_uart/makefile Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/fll.s =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/fll.s (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/fll.s (nonexistent) @@ -1,51 +0,0 @@ -#include "hardware.h" -.text -.global fllInit ; SW FLL to init DCO/SMCLK -frequency - .type fllInit, @function -fllInit: - mov.b #BCSCTL1_FLL, &BCSCTL1 ; Init basic clock control reg 1 - mov.b #BCSCTL2_FLL, &BCSCTL2 ; Init basic clock control reg 2 - mov #TACTL_FLL, &TACTL ; SMCLK is TA-clock / Timer stopped - bis #MC1, &TACTL ; Start timer: Continuos Mode - mov #CCTL2_FLL, &CCTL2 ; Init CCR2 and Clear capture flag - -.Lwait0:bit #CCIFG, &CCTL2 ; Test/Wait for capture flag - jz .Lwait0 ; May be used with INT / LPM0 later ? - mov &CCR2, r15 ; Store CCR2 init-value - bic #CCIFG, &CCTL2 ; Clear capture flag -.Lwait1:bit #CCIFG, &CCTL2 ; Test/Wait for capture flag - jz .Lwait1 ; May be used with INT / LPM0 later ? - bic #CCIFG, &CCTL2 ; Clear capture flag - mov.b &BCSCTL1, r14 ; Store current Rsel value - bic.b #0x0f8, r14 ; Mask for Rsel bits - mov.b &DCOCTL, r13 ; Store current DCO value - -.LfllUP:cmp.b #DCOCTL_MAX, r13 ; Needs Rsel to be increased ? - jne .LfllDN ; No - cmp.b #7, r14 ; Is max Rsel already selected ? - jge .LfllER ; Yes, Rsel can not be increased - inc.b &BCSCTL1 ; Increase Rsel - jmp .LfllRx ; Test DCO again - -.LfllDN:cmp.b #DCOCTL_MIN, r13 ; Needs Rsel to be decreased ? - jne .LfllCP ; No - cmp.b #0, r14 ; Is min Rsel already selected ? - jeq .LfllER ; Yes, Rsel can not be increased - dec.b &BCSCTL1 ; Decrease Rsel -.LfllRx:mov.b #60h, &DCOCTL ; Center DCO (may be optimized later ?) - jmp .Lwait0 ; Test DCO again -.LfllCP: - mov &CCR2, r12 ; Read captured value - sub r15, r12 ; Subtract last captured value - mov &CCR2, r15 ; Store CCR2 value for next pass - cmp #DCO_FSET, r12 ; DCO_FSET= SMCLK/(32768/4) - jl .LfllI ; - jeq .LfllOK ; -.LfllD: dec.b &DCOCTL ; Decrement value - jmp .Lwait0 ; -.LfllI: inc.b &DCOCTL ; Increment value - jmp .Lwait0 ; - -.LfllER: ; error, currently ingnored -.LfllOK:clr &CCTL2 ; stop CCR2 - ret ;
trunk/fpga/diligent_s3board/software/ta_uart/fll.s Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/fll.h =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/fll.h (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/fll.h (nonexistent) @@ -1,6 +0,0 @@ -#ifndef FLL_H -#define FLL_H - -void fllInit(void); //do an FLL loop to adjust system frequency - -#endif //FLL_H
trunk/fpga/diligent_s3board/software/ta_uart/fll.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/hardware.h =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/hardware.h (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/hardware.h (nonexistent) @@ -1,72 +0,0 @@ -#ifndef HARDWARE_H -#define HARDWARE_H - -#define __msp430_have_port3 -#define __MSP430_HAS_PORT3__ - -#include -#include -#include - - -//PINS -//PORT1 -#define TX BIT1 - -//PORT2 -#define RX BIT2 -#define LED BIT1 - -//Port Output Register 'P1OUT, P2OUT': -#define P1OUT_INIT TX //Init Output data of port1 -#define P2OUT_INIT 0 //Init Output data of port2 -#define P3OUT_INIT 0 //Init Output data of port3 - -//Port Direction Register 'P1DIR, P2DIR': -#define P1DIR_INIT TX //Init of Port1 Data-Direction Reg (Out=1 / Inp=0) -#define P2DIR_INIT ~RX //Init of Port2 Data-Direction Reg (Out=1 / Inp=0) -#define P3DIR_INIT 0xff //Init of Port3 Data-Direction Reg (Out=1 / Inp=0) - -//Selection of Port or Module -Function on the Pins 'P1SEL, P2SEL' -#define P1SEL_INIT 0 //P1-Modules: -#define P2SEL_INIT RX //P2-Modules: -#define P3SEL_INIT 0 //P3-Modules: - -//Interrupt capabilities of P1 and P2 -#define P1IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) -#define P2IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) -#define P1IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) -#define P2IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) - -#define IE_INIT 0 -#define WDTCTL_INIT WDTPW|WDTHOLD - -#define BCSCTL1_FLL XT2OFF|DIVA1|RSEL2|RSEL0 -#define BCSCTL2_FLL 0 -#define TACTL_FLL TASSEL_2|TACLR -#define CCTL2_FLL CM0|CCIS0|CAP - -#define TACTL_AFTER_FLL TASSEL_2|TACLR|ID_0 - -//#define BAUD 40 //9600 @3MHz div 8 -//#define BAUD 20 //19200 @3MHz div 8 -//#define BAUD 20 //9600 @1.5MHz div 8 -//#define BAUD 140 //9600 @1.5MHz div 8 - -//#define BAUD 2083 //9600 @20.0MHz div 1 -//#define BAUD 1042 //19200 @20.0MHz div 1 -//#define BAUD 521 //38400 @20.0MHz div 1 -//#define BAUD 347 //57600 @20.0MHz div 1 -#define BAUD 174 //115200 @20.0MHz div 1 -//#define BAUD 87 //230400 @20.0MHz div 1 - -//Selection of 'Digitally Controlled Oszillator' (desired frquency in HZ, 1..3 MHz) -#define DCO_FREQ 1536000 //3072000/2 makes 9600 a bit more precise - -//Automatic, do not edit -#define DCO_FSET (DCO_FREQ/8192) //DCO_FSET = DCO_FREQ / (32768/4) -#define DCOCTL_MAX 0xff // Used from FLL to check when Rsel must be changed -#define DCOCTL_MIN 0 // Used from FLL to check when Rsel must be changed - - -#endif //HARDWARE_H
trunk/fpga/diligent_s3board/software/ta_uart/hardware.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/main.c =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/main.c (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/main.c (nonexistent) @@ -1,106 +0,0 @@ -/* -see README.txt for details. - -chris -*/ -#include "hardware.h" -#include -#include -#include "swuart.h" -#include "fll.h" - -/** -Delay function. -*/ -void delay(unsigned int d) { - while(d--) { - nop(); - nop(); - } -} - -/** -Main function with init an an endless loop that is synced with the -interrupts trough the lowpower mode. -*/ -int main(void) { - int reading = 0; - int pos = 0; - char buf[40]; - int led = 0; - - WDTCTL = WDTCTL_INIT; //Init watchdog timer - - P1OUT = P1OUT_INIT; //Init output data of port1 - P1SEL = P1SEL_INIT; //Select port or module -function on port1 - P1DIR = P1DIR_INIT; //Init port direction register of port1 - P1IES = P1IES_INIT; //init port interrupts - P1IE = P1IE_INIT; - - P2OUT = P2OUT_INIT; //Init output data of port2 - P2SEL = P2SEL_INIT; //Select port or module -function on port2 - P2DIR = P2DIR_INIT; //Init port direction register of port2 - P2IES = P2IES_INIT; //init port interrupts - P2IE = P2IE_INIT; - - P3DIR = 0xff; - P3OUT = 0xff; //light LED during init - delay(65535); //Wait for watch crystal startup - delay(65535); -// fllInit(); //Init FLL to desired frequency using the 32k768 cystal as reference. - P3OUT = 0x00; //switch off LED - - TACTL = TACTL_AFTER_FLL; //setup timer (still stopped) - CCTL0 = CCIE|CAP|CM_2|CCIS_1|SCS; //select P2.2 with UART signal - CCTL1 = 0; // - CCTL2 = 0; // - TACTL |= MC1; //start timer - - eint(); //enable interrupts - - printf("\r\n====== openMSP430 in action ======\r\n"); //say hello - printf("\r\nSimple Line Editor Ready\r\n"); //say hello - - while (1) { //main loop, never ends... - printf("> "); //show prompt - reading = 1; - while (reading) { //loop and read characters - LPM0; //sync, wakeup by irq - - led++; // Some lighting... - if (led==9) { - led = 0; - } - P3OUT = (0x01 << led); - - switch (rxdata) { - //process RETURN key - case '\r': - //case '\n': - printf("\r\n"); //finish line - buf[pos++] = 0; //to use printf... - printf(":%s\r\n", buf); - reading = 0; //exit read loop - pos = 0; //reset buffer - break; - //backspace - case '\b': - if (pos > 0) { //is there a char to delete? - pos--; //remove it in buffer - putchar('\b'); //go back - putchar(' '); //erase on screen - putchar('\b'); //go back - } - break; - //other characters - default: - //only store characters if buffer has space - if (pos < sizeof(buf)) { - putchar(rxdata); //echo - buf[pos++] = rxdata; //store - } - } - } - } -} -
trunk/fpga/diligent_s3board/software/ta_uart/main.c Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart/swuart.s =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart/swuart.s (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart/swuart.s (nonexistent) @@ -1,78 +0,0 @@ -#include "hardware.h" - -;variables -.data - .comm rxdata,1,1 ;char var - .comm rxshift,1,1 ;char var - .comm rxbit,2,2 ;short var, aligned - -.text - -interrupt(TIMERA0_VECTOR) ;register interrupt vector -;interrupt handler to receive as Timer_A UART -.global ccr0 ;place a label afterwards so -ccr0: ;that it is used in the listing - add rxbit, r0 - jmp .Lrxstart ;start bit - jmp .Lrxdatabit ;D0 - jmp .Lrxdatabit ;D1 - jmp .Lrxdatabit ;D2 - jmp .Lrxdatabit ;D3 - jmp .Lrxdatabit ;D4 - jmp .Lrxdatabit ;D5 - jmp .Lrxdatabit ;D6 -; jmp .Lrxlastbit ;D7 that one is following anyway - -.Lrxlastbit: ;last bit, handle byte - bit #SCCI, &CCTL0 ;read last bit - rrc.b rxshift ;and save it - clr rxbit ;reset state - mov #CCIE|CAP|CM_2|CCIS_1|SCS, &CCTL0 ;restore capture mode - mov.b rxshift, rxdata ;copy received data - bic #CPUOFF|OSCOFF|SCG0|SCG1, 0(r1) ;exit all lowpower modes - ;here you might do other things too, like setting a flag - ;that the wakeup comes from the Timer_A UART. however - ;it should not take longer than one bit time, otherwise - ;charcetrs will be lost. - reti - -.Lrxstart: ;startbit, init - clr rxshift ;clear input buffer - add #(BAUD/2), &CCR0 ;startbit + 1.5 bits -> first bit - mov #CCIE|CCIS_1|SCS, &CCTL0;set compare mode, sample bits - jmp .Lrxex ;set state,... - -.Lrxdatabit: ;save databit - bit #SCCI, &CCTL0 ;measure databit - rrc.b rxshift ;rotate in databit - -.Lrxex: add #BAUD, &CCR0 ;one bit delay - incd rxbit ;setup next state - reti - -; void serPutc(char) -;use an other Capture/Compare than for receiving (full duplex). -;this one is without interrupts and OUTMOD, because only -;this way P1.1 can be used. P1.1 is prefered because the -;BSL is on that pin too. -.global putchar - .type putchar, @function -putchar: ;send a byte - mov #0, &CCTL1 ;select compare mode - mov #10, r13 ;ten bits: Start, 8 Data, Stop - rla r15 ;shift in start bit (0) - bis #0x0200, r15 ;set tenth bit (1), thats the stop bit - mov &TAR, &CCR1 ;set up start time -.Lt1lp: add #BAUD, &CCR1 ;set up for one bit - rrc r15 ;shift data trough carry - jc .Lt1 ;test carry bit -.Lt0: bic.b #TX, &P1OUT ;generate pulse - jmp .Ltc ; -.Lt1: bis.b #TX, &P1OUT ;just use the same amount of time as for a zero - jmp .Ltc ; -.Ltc: bit #CCIFG, &CCTL1 ;wait for compare - jz .Ltc ;loop until the bit is set - bic #CCIFG, &CCTL1 ;clear for next loop - dec r13 ;decrement bit counter - jnz .Lt1lp ;loop until all bits are transmitted - ret
trunk/fpga/diligent_s3board/software/ta_uart/swuart.s Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/ta_uart =================================================================== --- trunk/fpga/diligent_s3board/software/ta_uart (revision 26) +++ trunk/fpga/diligent_s3board/software/ta_uart (nonexistent)
trunk/fpga/diligent_s3board/software/ta_uart Property changes : Deleted: svn:ignore ## -1,3 +0,0 ## -*.a43 -*.elf -*.lst Index: trunk/fpga/diligent_s3board/software/leds/hardware.h =================================================================== --- trunk/fpga/diligent_s3board/software/leds/hardware.h (revision 26) +++ trunk/fpga/diligent_s3board/software/leds/hardware.h (nonexistent) @@ -1,13 +0,0 @@ -#ifndef MAIN_H -#define MAIN_H - -#define __msp430_have_port3 -#define __MSP430_HAS_PORT3__ - -#include -#include -#include - - - -#endif // MAIN_H
trunk/fpga/diligent_s3board/software/leds/hardware.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/leds/main.c =================================================================== --- trunk/fpga/diligent_s3board/software/leds/main.c (revision 26) +++ trunk/fpga/diligent_s3board/software/leds/main.c (nonexistent) @@ -1,71 +0,0 @@ -#include "hardware.h" -#include "7seg.h" - -/** -Delay function. -*/ -void delay(unsigned int c, unsigned int d) { - int i, j; - for (i = 0; i>(o&7)); - delay(0x0007, 0xffff); - } - } -} -
trunk/fpga/diligent_s3board/software/leds/main.c Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/leds/7seg.c =================================================================== --- trunk/fpga/diligent_s3board/software/leds/7seg.c (revision 26) +++ trunk/fpga/diligent_s3board/software/leds/7seg.c (nonexistent) @@ -1,195 +0,0 @@ -/* -********************************************************************************************************* -* -* Multiplexed LED Display Driver -* -* (c) Copyright 2004, modified by John Leung -* Reference: Jean J. Labrosse, Embedded Systems Building Blocks -* All Rights Reserved -* -* Filename : LED.C -* Programmer : John Leung -* Remarks : Modified for SaiWanHo project -* Date : 19th Nov 2004 -* Hardware : PCB 11OCT2004.001 -********************************************************************************************************* -* DESCRIPTION -* -* This module provides an interface to a multiplexed "8 segments x N digits" LED matrix. -* -* To use this driver: -* -* 1) You must define (LED.H): -* -* DISP_N_DIG The total number of segments to display, inc. dp status -* DISP_N_SS The total number of seven-segment digits (modules) -* DISP_PORT1_DIG The address of the DIGITS output port -* DISP_PORT_SEG The address of the SEGMENTS output port -* first_dig_msk The first digit mask for selecting the most significant digit -* -* 2) You must allocate a hardware timer which will interrupt the CPU at a rate of at least: -* -* DISP_N_DIG * 60 (Hz) -* -* The timer interrupt must vector to DispMuxISR (defined in LED_IA.ASM). You MUST write the -* code to clear the interrupt source. The interrupt source must be cleared either in DispMuxISR -* or in DispMuxHandler(). -* -* 3) Adapt DispInitPort(), DispOutSeg() and DispOutDig() for your environment. -********************************************************************************************************* -*/ -#include "7seg.h" - -/* -********************************************************************************************************* -* SEVEN-SEGMENT Digit table -********************************************************************************************************* -*/ - -INT8U * const DispSegTbl[] = { - (INT8U *) &DIGIT3, - (INT8U *) &DIGIT2, - (INT8U *) &DIGIT1, - (INT8U *) &DIGIT0 -}; - -/* -********************************************************************************************************* -* ASCII to SEVEN-SEGMENT conversion table -* a -* ------ -* f | | b -* | g | -* Note: The segments are mapped as follows: ------ -* e | | c -* a b c d e f g | d | -* -- -- -- -- -- -- -- -- ------ -* B7 B6 B5 B4 B3 B2 B1 B0 -********************************************************************************************************* -*/ - -const INT8U DispASCIItoSegTbl[] = {// ASCII to SEVEN-SEGMENT conversion table -0x00, // ' ' -0x00, // '!', No seven-segment conversion for exclamation point -0x44, // '"', Double quote -0x00, // '#', Pound sign -0x00, // '$', No seven-segment conversion for dollar sign -0x00, // '%', No seven-segment conversion for percent sign -0x00, // '&', No seven-segment conversion for ampersand -0x40, // ''', Single quote -0x9C, // '(', Same as '[' -0xF0, // ')', Same as ']' -0x00, // '*', No seven-segment conversion for asterix -0x00, // '+', No seven-segment conversion for plus sign -0x00, // ',', No seven-segment conversion for comma -0x02, // '-', Minus sign -0x00, // '.', No seven-segment conversion for period -0x00, // '/', No seven-segment conversion for slash -0xFC, // '0' -0x60, // '1' -0xDA, // '2' -0xF2, // '3' -0x66, // '4' -0xB6, // '5' -0xBE, // '6' -0xE0, // '7' -0xFE, // '8' -0xF6, // '9' -0x00, // ':', No seven-segment conversion for colon -0x00, // ';', No seven-segment conversion for semi-colon -0x00, // '<', No seven-segment conversion for less-than sign -0x12, // '=', Equal sign -0x00, // '>', No seven-segment conversion for greater-than sign -0xCA, //'?', Question mark -0x00, // '@', No seven-segment conversion for commercial at-sign -0xEE, // 'A' -0x3E, // 'B', Actually displayed as 'b' -0x9C, // 'C' -0x7A, // 'D', Actually displayed as 'd' -0x9E, // 'E' -0x8E, // 'F' -0xBC, // 'G', Actually displayed as 'g' -0x6E, // 'H' -0x60, // 'I', Same as '1' -0x78, // 'J' -0x00, // 'K', No seven-segment conversion -0x1C, // 'L' -0x6E, // 'M', No seven-segment conversion -0x2A, // 'N', Actually displayed as 'n' -0xFC, // 'O', Same as '0' -0xCE, // 'P' -0x00, // 'Q', No seven-segment conversion -0x0A, // 'R', Actually displayed as 'r' -0xB6, // 'S', Same as '5' -0x1E, // 'T', Actually displayed as 't' -0x7C, // 'U' -0x00, // 'V', No seven-segment conversion -0x00, // 'W', No seven-segment conversion -0x00, // 'X', No seven-segment conversion -0x76, // 'Y' -0x00, // 'Z', No seven-segment conversion -0x00, // '[' -0x00, // '\', No seven-segment conversion -0x00, // ']' -0x00, // '^', No seven-segment conversion -0x00, // '_', Underscore -0x00, // '`', No seven-segment conversion for reverse quote -0xFA, // 'a' -0x3E, // 'b' -0x1A, // 'c' -0x7A, // 'd' -0xDE, // 'e' -0x8E, // 'f', Actually displayed as 'F' -0xBC, // 'g' -0x2E, // 'h' -0x20, // 'i' -0x78, // 'j', Actually displayed as 'J' -0x00, // 'k', No seven-segment conversion -0x1C, // 'l', Actually displayed as 'L' -0x00, // 'm', No seven-segment conversion -0x2A, // 'n' -0x3A, // 'o' -0xCE, // 'p', Actually displayed as 'P' -0x00, // 'q', No seven-segment conversion -0x0A, // 'r' -0xB6, // 's', Actually displayed as 'S' -0x1E, // 't' -0x38, // 'u' -0x00, // 'v', No seven-segment conversion -0x00, // 'w', No seven-segment conversion -0x00, // 'x', No seven-segment conversion -0x76, // 'y', Actually displayed as 'Y' -0x00 // 'z', No seven-segment conversion -}; - -/* -********************************************************************************************************* -* DISPLAY ASCII STRING ON SEVEN-SEGMENT DISPLAY -* -* Description: This function is called to display an ASCII string on the seven-segment display. -* Arguments : dig is the position of the first digit where the string will appear: -* 0 for the first seven-segment digit. -* 1 for the second seven-segment digit. -* . . . . . . . -* . . . . . . . -* DISP_N_SS - 1 is the last seven-segment digit. -* s is the ASCII string to display -* Returns : none -* Notes : - Not all ASCII characters can be displayed on a seven-segment display. Consult the -* ASCII to seven-segment conversion table DispASCIItoSegTbl[]. -********************************************************************************************************* -*/ - -void DispStr (INT8U offset, INT8U *s) -{ - int dig = 0; - register INT8U* p; - register INT8U c; - while (dig < DIGIT_NR) { - p = DispSegTbl[dig]; - c = *(offset+s); - *p = DispASCIItoSegTbl[c - 0x20]; - dig++; - s++; - } -}
trunk/fpga/diligent_s3board/software/leds/7seg.c Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/leds/7seg.h =================================================================== --- trunk/fpga/diligent_s3board/software/leds/7seg.h (revision 26) +++ trunk/fpga/diligent_s3board/software/leds/7seg.h (nonexistent) @@ -1,72 +0,0 @@ -/* -********************************************************************************************************* -* -* Multiplexed LED Display Driver -* Reference: Jean J. Labrosse, Embedded Systems Building Blocks -* -* Filename : LED.C -* Programmer : John Leung (www.TechToys.com.hk) -* Remarks : Modified for PIC16-LEDSTK1 -* Date : First version 1.0 on 19th Nov 2004 -* Language : CCS C complier for PIC mid-range MCU, PCM version 3.170, under MPLAB IDE 7.01 -* Hardware : PCB 11OCT2004.001, MCU is Microchip's PIC16F877a -* History : Modified for PIC16-LEDSTK1 dated 12 Jan 2006 -********************************************************************************************************* -* DESCRIPTION -* -* This module provides an interface to a multiplexed "7-segments x N digits" LED matrix. -* -* To use this driver: -* -* 1) To use this module, the following parameters under define (LED.H): -* -* DISP_N_DIG The total number of segments to display, inc. dp status -* DISP_N_SS The total number of seven-segment digits, e.g "0" "1" "2" is 3-digit -* DISP_PORT1_DIG The address of the DIGITS output port -* DISP_PORT_SEG The address of the SEGMENTS output port -* first_dig_msk The first digit mask for selecting the most significant digit -* -* 2) Allocate a hardware timer which will interrupt the CPU at a rate of at least: -* -* DISP_N_DIG * 60 (Hz) -* -********************************************************************************************************* -*/ -#ifndef _7SEG_H -#define _7SEG_H - -/* -********************************************************************************************************* -* CONSTANTS -********************************************************************************************************* -*/ -#include -#include -#include - -typedef unsigned char INT8U; -typedef unsigned int INT16U; - - -// Four-Digit, Seven-Segment LED Display driver -#define DIGIT0_ 0x0090 -sfrb (DIGIT0,DIGIT0_); -#define DIGIT1_ 0x0091 -sfrb (DIGIT1,DIGIT1_); -#define DIGIT2_ 0x0092 -sfrb (DIGIT2,DIGIT2_); -#define DIGIT3_ 0x0093 -sfrb (DIGIT3,DIGIT3_); - -#define DIGIT_NR 4 /* Total number of seven-segment digits */ - -/* -********************************************************************************************************* -* FUNCTION PROTOTYPES -********************************************************************************************************* -*/ - -void DispStr(INT8U offset, INT8U *s); //API to display an ASCII string - - -#endif // _7SEG_H
trunk/fpga/diligent_s3board/software/leds/7seg.h Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/leds/makefile =================================================================== --- trunk/fpga/diligent_s3board/software/leds/makefile (revision 26) +++ trunk/fpga/diligent_s3board/software/leds/makefile (nonexistent) @@ -1,53 +0,0 @@ -# makfile configuration -NAME = leds -OBJECTS = main.o 7seg.o -CPU = msp430x1121 - -CFLAGS = -mmcu=${CPU} -O2 -Wall -g - -#switch the compiler (for the internal make rules) -CC = msp430-gcc - - -.PHONY: all FORCE clean download download-jtag download-bsl dist - -#all should be the first target. it's built when make is runwithout args -all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst - -#confgigure the next line if you want to use the serial download -download: download-uart -#download: download-jtag -#download: download-bsl - -#additional rules for files -${NAME}.elf: ${OBJECTS} - ${CC} -mmcu=${CPU} -o $@ ${OBJECTS} - -${NAME}.a43: ${NAME}.elf - msp430-objcopy -O ihex $^ $@ - -${NAME}.lst: ${NAME}.elf - msp430-objdump -dSt $^ >$@ - -download-jtag: all - msp430-jtag -e ${NAME}.elf - -download-bsl: all - msp430-bsl -e ${NAME}.elf - -download-uart: all - openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf - -clean: - rm -f ${NAME} ${NAME}.a43 ${NAME}.lst *.o - -#backup archive -dist: - tar czf dist.tgz *.c *.h *.txt makefile - -#dummy target as dependecy if something has to be build everytime -FORCE: - -#project dependencies -main.o: main.c hardware.h 7seg.h -7seg.o: 7seg.c 7seg.h
trunk/fpga/diligent_s3board/software/leds/makefile Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/diligent_s3board/software/leds =================================================================== --- trunk/fpga/diligent_s3board/software/leds (revision 26) +++ trunk/fpga/diligent_s3board/software/leds (nonexistent)
trunk/fpga/diligent_s3board/software/leds Property changes : Deleted: svn:ignore ## -1,3 +0,0 ## -*.a43 -*.elf -*.lst

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.