Subversion Repositories openmsp430

/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v

/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run

trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run Property changes : Added: svn:ignore ## -0,0 +1,4 ## +pmem.* +simv +stimulus.v +*.vcd Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl (nonexistent) @@ -1,186 +0,0 @@ -#!/usr/bin/tclsh -#------------------------------------------------------------------------------ -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#------------------------------------------------------------------------------ -# -# File Name: run_analysis.tcl -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#------------------------------------------------------------------------------ -# $Rev: 17 $ -# $LastChangedBy: olivier.girard $ -# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ -#------------------------------------------------------------------------------ -package require Tclx - -############################################################################### -# SET SOME GLOBAL VARIABLES # -############################################################################### - -# Set tools -set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify_pro.exe" -set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe" - -# Set the FPGA: architecture, model, package_syn package_libero, speed-grade -set fpgaConfig { ProASIC3L A3P1000L FBGA484 "484 FBGA" Std} - -# RTL Top Level module -set designTop "openMSP430_fpga" - -# RTL include files -set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \ - ../../../rtl/verilog/openmsp430/openMSP430_defines.v \ - ../../../rtl/verilog/openmsp430/openMSP430_undefines.v" - -############################################################################### -# CLEANUP # -############################################################################### -proc sleep {time} { - after [expr $time*1000] set end 1 - vwait end - } - - -# Cleanup -file delete -force ./WORK -file mkdir ./WORK -cd ./WORK - -# Copy RTL include files -foreach rtlFile $rtlIncludeFiles { - file copy $rtlFile . -} - -############################################################################### -# GENERATE SYNTHESIS SCRIPT # -############################################################################### - -# Copy Synplify tcl command files -if [catch {open "../synplify.tcl" r} f_synplify_tcl] { - puts "ERROR: Cannot open Synplify command file file ../synplify.tcl" - exit 1 -} - -set synplify_tcl [read $f_synplify_tcl] -close $f_synplify_tcl - -regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 0]]" synplify_tcl -regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 1]]" synplify_tcl -regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 2]]" synplify_tcl -regsub -all {} $synplify_tcl "[string toupper [lindex $fpgaConfig 4]]" synplify_tcl -regsub -all {} $synplify_tcl $designTop synplify_tcl - -set f_synplify_tcl [open "synplify.tcl" w] -puts $f_synplify_tcl $synplify_tcl -close $f_synplify_tcl - -############################################################################### -# GENERATE PLACE & ROUTE SCRIPT # -############################################################################### - -# Copy Libero Designer tcl command files -if [catch {open "../libero_designer.tcl" r} f_libero_designer_tcl] { - puts "ERROR: Cannot open Libero Designer command file file ../libero_designer.tcl" - exit 1 -} -set libero_designer_tcl [read $f_libero_designer_tcl] -close $f_libero_designer_tcl - -regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 0]" libero_designer_tcl -regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 1]" libero_designer_tcl -regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 3]" libero_designer_tcl -regsub -all {} $libero_designer_tcl "[lindex $fpgaConfig 4]" libero_designer_tcl - -set f_libero_designer_tcl [open "libero_designer.tcl" w] -puts $f_libero_designer_tcl $libero_designer_tcl -close $f_libero_designer_tcl - -############################################################################### -# RUN SYNTHESIS # -############################################################################### - -# Start synthesis -puts "START SYNTHESIS..." -flush stdout -sleep 10 -eval exec $SYNPLICITY synplify.tcl -sleep 30 - -# Wait until EDIF file is generated -while {!([file exists "./rev_1/design_files.edn"])} { - sleep 10 -} - -# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script -sleep 10 -eval exec taskkill /IM synplify.exe -sleep 20 - -puts "SYNTHESIS DONE..." -flush stdout - -############################################################################### -# RUN PLACE & ROUTE # -############################################################################### - -# Run place & route -puts "START PLACE & ROUTE..." -flush stdout -eval exec $LIBERO_DESIGNER script:libero_designer.tcl logfile:libero_designer.log -puts "PLACE & ROUTE DONE..." -flush stdout - -############################################################################### -# REPORT SUMMARY # -############################################################################### - -# Extract timing information -if [catch {open "report_timing_max.txt" r} f_timing] { - puts "ERROR: Cannot open timing file" - exit 1 -} -set timingFile [read $f_timing] -close $f_timing -regexp {SUMMARY(.*)END SUMMARY} $timingFile whole_match timing -puts $timing -puts "====================================================================================" - -# Extract size information -if [catch {open "report_status.txt" r} f_area] { - puts "ERROR: Cannot open status file: report_status.txt" - exit 1 -} -set areaFile [read $f_area] -close $f_area -regexp {(Compile report:.*?)Total:} $areaFile whole_match area1 -regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2 -puts $area1 -puts $area2 -puts "====================================================================================" - -cd ../ -sleep 3 - -exit 0

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc (nonexistent) @@ -1,54 +0,0 @@ -#------------------------------------------------------------------------------ -# Actel Physical design constraints file -#------------------------------------------------------------------------------ - -#----------------------# -# I/O constraints # -# ---------------------# - -# CLOCK & RESET -#------------------------------------------------ -set_io oscclk -pinname E4 -set_io porst_n -pinname V7 -set_io pbrst_n -pinname T9 - - -# GPIOA -#------------------------------------------------ -set_io din_x -pinname D5 ;# GPIOA_0 -set_io sclk_x -pinname D6 ;# GPIOA_1 -set_io sync_n_x -pinname D10 ;# GPIOA_2 -set_io din_y -pinname G10 ;# GPIOA_3 -set_io sclk_y -pinname G11 ;# GPIOA_4 -set_io sync_n_y -pinname E11 ;# GPIOA_5 - - -# UART INTERFACE -#------------------------------------------------ -set_io uart_rx -pinname D9 -set_io uart_tx -pinname G9 - - -# SWITCHES & LEDS -#------------------------------------------------ -set_io switch\[0\] -pinname D18 -set_io switch\[1\] -pinname D17 -set_io switch\[2\] -pinname E17 -set_io switch\[3\] -pinname F16 -set_io switch\[4\] -pinname D15 -set_io switch\[5\] -pinname G14 -set_io switch\[6\] -pinname E14 -set_io switch\[7\] -pinname F14 -set_io switch\[8\] -pinname G13 -set_io switch\[9\] -pinname D14 -set_io led\[0\] -pinname E10 -out_drive 12 -set_io led\[1\] -pinname F10 -out_drive 12 -set_io led\[2\] -pinname U8 -out_drive 12 -set_io led\[3\] -pinname W5 -out_drive 12 -set_io led\[4\] -pinname U7 -out_drive 12 -set_io led\[5\] -pinname V6 -out_drive 12 -set_io led\[6\] -pinname U5 -out_drive 12 -set_io led\[7\] -pinname U4 -out_drive 12 -set_io led\[8\] -pinname V4 -out_drive 12 -set_io led\[9\] -pinname V5 -out_drive 12 -

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.sdc =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.sdc (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.sdc (nonexistent) @@ -1,4 +0,0 @@ -# Design Constraints - -create_clock -period 40.0 -waveform {0.0 20.0} oscclk -

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.sdc Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v (revision 82) @@ -58,6 +58,7 @@ `include "../../../rtl/verilog/openmsp430/omsp_dbg.v" `include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v" `include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v" +`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v" `include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v" `include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"

/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/prepare_implementation.tcl

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/prepare_implementation.tcl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pdc =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pdc (nonexistent) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pdc (revision 82) @@ -0,0 +1,54 @@ +#------------------------------------------------------------------------------ +# Actel Physical design constraints file +#------------------------------------------------------------------------------ + +#----------------------# +# I/O constraints # +# ---------------------# + +# CLOCK & RESET +#------------------------------------------------ +set_io oscclk -pinname E4 +set_io porst_n -pinname V7 +set_io pbrst_n -pinname T9 + + +# GPIOA +#------------------------------------------------ +set_io din_x -pinname D5 ;# GPIOA_0 +set_io sclk_x -pinname D6 ;# GPIOA_1 +set_io sync_n_x -pinname D10 ;# GPIOA_2 +set_io din_y -pinname G10 ;# GPIOA_3 +set_io sync_n_y -pinname G11 ;# GPIOA_4 +set_io sclk_y -pinname E11 ;# GPIOA_5 + + +# UART INTERFACE +#------------------------------------------------ +set_io uart_rx -pinname D9 +set_io uart_tx -pinname G9 + + +# SWITCHES & LEDS +#------------------------------------------------ +#set_io switch\[0\] -pinname D18 +#set_io switch\[1\] -pinname D17 +#set_io switch\[2\] -pinname E17 +#set_io switch\[3\] -pinname F16 +#set_io switch\[4\] -pinname D15 +#set_io switch\[5\] -pinname G14 +#set_io switch\[6\] -pinname E14 +#set_io switch\[7\] -pinname F14 +#set_io switch\[8\] -pinname G13 +#set_io switch\[9\] -pinname D14 +set_io led\[0\] -pinname E10 +set_io led\[1\] -pinname F10 +set_io led\[2\] -pinname U8 +set_io led\[3\] -pinname W5 +set_io led\[4\] -pinname U7 +set_io led\[5\] -pinname V6 +set_io led\[6\] -pinname U5 +set_io led\[7\] -pinname U4 +set_io led\[8\] -pinname V4 +set_io led\[9\] -pinname V5 +

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pdc Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.post.sdc =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.post.sdc (nonexistent) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.post.sdc (revision 82) @@ -0,0 +1,7 @@ +# Design Constraints + +create_clock -name oscclk -period 20.0 -waveform [list 0.0 10.0] oscclk +create_clock -name dco_clk -period 62.5 -waveform [list 0.0 31.25] pll_0:GLA + +set_false_path -from {pbrst_n} +set_false_path -from {porst_n}

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.post.sdc Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/libero_designer.tcl =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/libero_designer.tcl (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/libero_designer.tcl (revision 82) @@ -1,29 +1,56 @@ -new_design -name "design_fpga" -family "" -path {.} -block "off" +new_design -name "libero_designer" -family "" -path {.} -block "off" set_device -die "" \ -package "" \ -speed "" -import_source -format "edif" -edif_flavor "GENERIC" {./rev_1/design_files.edn} \ - -format "sdc" -scenario "Primary" {../design_files.sdc} \ +import_source -format "edif" -edif_flavor "GENERIC" {../work_synplify/synplify.edn} \ + -format "sdc" -scenario "Primary" {../design_constraints.post.sdc} \ + -format "pdc" -abort_on_error "yes" {../design_constraints.pdc} \ -merge_physical "no" -merge_timing "yes" compile -pdc_abort_on_error "on" -pdc_eco_display_unmatched_objects "off" -pdc_eco_max_warnings 10000 \ -demote_globals "off" -demote_globals_max_fanout 12 -promote_globals "off" \ - -promote_globals_min_fanout 200 -promote_globals_max_limit 0 -localclock_max_shared_instances 12 \ + -promote_globals_min_fanout 200 -promote_globals_max_limit 0 -localclock_max_shared_instances 12 \ -localclock_buffer_tree_max_fanout 12 -combine_register "off" -delete_buffer_tree "off" \ -delete_buffer_tree_max_fanout 12 -report_high_fanout_nets_limit 10 -layout -timing_driven -placer_high_effort "on" -seq_opt "on" +layout -timing_driven -place_incremental "off" \ + -route_incremental "off" \ + -mindel_repair "on" \ + -placer_high_effort "on" \ + -seq_opt "on" -report -type "timer" -format "TEXT" -analysis "max" -print_summary "yes" \ - -use_slack_threshold "no" -print_paths "yes" -max_paths 5 -max_expanded_paths 1 \ - -include_user_sets "no" -include_pin_to_pin "yes" -select_clock_domains "no" \ - {./report_timing_max.txt} -report -type "status" \ - {./report_status.txt} +report -type "status" {./report_status.txt} +report -type "timer" -format "TEXT" -analysis "max" -print_summary "yes" \ + -use_slack_threshold "no" -print_paths "yes" -max_paths 5 \ + -max_expanded_paths 1 -include_user_sets "no" -include_pin_to_pin "yes" \ + -include_clock_domains "yes" -select_clock_domains "no" \ + "./report_timing_max.txt" +report -type "timing_violations" -format "TEXT" -analysis "max" -use_slack_threshold "yes" \ + -slack_threshold 0.00 -limit_max_paths "yes" -max_paths 100 \ + -max_expanded_paths 0 \ + "./report_timing_violations_max.txt" +report -type "bottleneck" -format "TEXT" -analysis "max" -slack_threshold 0.00 \ + -max_parallel_paths 1 -max_paths 100 -max_instances 10 \ + -cost_type "path_count" \ + "./report_bottleneck_max.txt" +report -type "datasheet" -format "TEXT" \ + "./reports_datasheet.txt" +report -type "constraints_coverage" "./reports_constraints_coverage.txt" +report -type "combinational_loops" "./reports_combinational_loops.txt" +report -type "pin" -listby "name" \ + "./reports_pin.txt" +report -type "flipflop" "./reports_flipflop.txt" +report -type "ccc_configuration" "./reports_ccc_configuration.txt" +report -type "globalnet" "./reports_globalnet.txt" +report -type "globalusage" "./reports_globalusage.txt" +export -format "log" -diagnostic "./libero_designer.log" +export -format "pdb " -feature "prog_fpga" "./fpga_bitstream.pdb" + +save_design "./libero_designer.adb"

/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pre.sdc

trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_constraints.pre.sdc Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/synplify.tcl =================================================================== --- trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/synplify.tcl (revision 81) +++ trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/synplify.tcl (revision 82) @@ -3,11 +3,11 @@ #add_file options add_file -verilog "../design_files.v" -add_file -constraint "../design_files.sdc" +add_file -constraint "../design_constraints.pre.sdc" -#implementation: "rev_1" -impl -add rev_1 -type fpga +#implementation: "synplify" +impl -add "synplify" -type fpga #device options set_option -technology @@ -19,11 +19,11 @@ #compilation/mapping options set_option -default_enum_encoding default set_option -resource_sharing 1 -set_option -use_fsm_explorer 0 +set_option -use_fsm_explorer 1 set_option -top_module #map options -set_option -frequency 30.000 +set_option -frequency 50.0 set_option -vendor_xcompatible_mode 0 set_option -vendor_xcompatible_mode 0 set_option -run_prop_extract 1 @@ -31,7 +31,7 @@ set_option -globalthreshold 50 set_option -maxfan_hard 0 set_option -disable_io_insertion 0 -set_option -retiming 0 +set_option -retiming 1 set_option -report_path 4000 set_option -opcond COMWC set_option -update_models_cp 0 @@ -50,7 +50,7 @@ #set result format/file last project -result_format "edif" -project -result_file "./rev_1/design_files.edn" +project -result_file "./synplify.edn" # #implementation attributes @@ -58,7 +58,7 @@ set_option -vlog_std v2001 set_option -dup 0 set_option -project_relative_includes 1 -impl -active "rev_1" +impl -active "synplify" # Run synthesis @@ -65,7 +65,7 @@ project -run synthesis # Save and quit -project -save rev_1.prj +project -save "./synplify.prj" + #exit 0 -

/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/spacewar.h

/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/makefile

/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar

trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar Property changes : Added: svn:ignore ## -0,0 +1,4 ## +*.o +*.a43 +*.elf +*.lst